1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */ 3 4 #include "qos.h" 5 6 #define MLX5_QOS_DEFAULT_DWRR_UID 0 7 8 bool mlx5_qos_is_supported(struct mlx5_core_dev *mdev) 9 { 10 if (!MLX5_CAP_GEN(mdev, qos)) 11 return false; 12 if (!MLX5_CAP_QOS(mdev, nic_sq_scheduling)) 13 return false; 14 if (!MLX5_CAP_QOS(mdev, nic_bw_share)) 15 return false; 16 if (!MLX5_CAP_QOS(mdev, nic_rate_limit)) 17 return false; 18 return true; 19 } 20 21 int mlx5_qos_max_leaf_nodes(struct mlx5_core_dev *mdev) 22 { 23 return 1 << MLX5_CAP_QOS(mdev, log_max_qos_nic_queue_group); 24 } 25 26 int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id, 27 u32 bw_share, u32 max_avg_bw, u32 *id) 28 { 29 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; 30 31 MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id); 32 MLX5_SET(scheduling_context, sched_ctx, element_type, 33 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP); 34 MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share); 35 MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw); 36 37 return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, 38 sched_ctx, id); 39 } 40 41 int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id, 42 u32 bw_share, u32 max_avg_bw, u32 *id) 43 { 44 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; 45 void *attr; 46 47 MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id); 48 MLX5_SET(scheduling_context, sched_ctx, element_type, 49 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); 50 MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share); 51 MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw); 52 53 attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); 54 MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); 55 56 return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, 57 sched_ctx, id); 58 } 59 60 int mlx5_qos_create_root_node(struct mlx5_core_dev *mdev, u32 *id) 61 { 62 return mlx5_qos_create_inner_node(mdev, MLX5_QOS_DEFAULT_DWRR_UID, 0, 0, id); 63 } 64 65 int mlx5_qos_update_node(struct mlx5_core_dev *mdev, u32 parent_id, 66 u32 bw_share, u32 max_avg_bw, u32 id) 67 { 68 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; 69 u32 bitmask = 0; 70 71 MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id); 72 MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share); 73 MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw); 74 75 bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE; 76 bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; 77 78 return mlx5_modify_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, 79 sched_ctx, id, bitmask); 80 } 81 82 int mlx5_qos_destroy_node(struct mlx5_core_dev *mdev, u32 id) 83 { 84 return mlx5_destroy_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, id); 85 } 86