1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/mlx5/port.h> 34 #include "mlx5_core.h" 35 36 /* calling with verbose false will not print error to log */ 37 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in, 38 void *data_out, int size_out, u16 reg_id, int arg, 39 int write, bool verbose) 40 { 41 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out; 42 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in; 43 int err = -ENOMEM; 44 u32 *out = NULL; 45 u32 *in = NULL; 46 void *data; 47 48 in = kvzalloc(inlen, GFP_KERNEL); 49 out = kvzalloc(outlen, GFP_KERNEL); 50 if (!in || !out) 51 goto out; 52 53 data = MLX5_ADDR_OF(access_register_in, in, register_data); 54 memcpy(data, data_in, size_in); 55 56 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG); 57 MLX5_SET(access_register_in, in, op_mod, !write); 58 MLX5_SET(access_register_in, in, argument, arg); 59 MLX5_SET(access_register_in, in, register_id, reg_id); 60 61 err = mlx5_cmd_do(dev, in, inlen, out, outlen); 62 if (verbose) 63 err = mlx5_cmd_check(dev, err, in, out); 64 if (err) 65 goto out; 66 67 data = MLX5_ADDR_OF(access_register_out, out, register_data); 68 memcpy(data_out, data, size_out); 69 70 out: 71 kvfree(out); 72 kvfree(in); 73 return err; 74 } 75 EXPORT_SYMBOL_GPL(mlx5_access_reg); 76 77 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 78 int size_in, void *data_out, int size_out, 79 u16 reg_id, int arg, int write) 80 { 81 return mlx5_access_reg(dev, data_in, size_in, data_out, size_out, 82 reg_id, arg, write, true); 83 } 84 EXPORT_SYMBOL_GPL(mlx5_core_access_reg); 85 86 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 87 u8 access_reg_group) 88 { 89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; 90 int sz = MLX5_ST_SZ_BYTES(pcam_reg); 91 92 MLX5_SET(pcam_reg, in, feature_group, feature_group); 93 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group); 94 95 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0); 96 } 97 98 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group, 99 u8 access_reg_group) 100 { 101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; 102 int sz = MLX5_ST_SZ_BYTES(mcam_reg); 103 104 MLX5_SET(mcam_reg, in, feature_group, feature_group); 105 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group); 106 107 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0); 108 } 109 110 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 111 u8 feature_group, u8 access_reg_group) 112 { 113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; 114 int sz = MLX5_ST_SZ_BYTES(qcam_reg); 115 116 MLX5_SET(qcam_reg, in, feature_group, feature_group); 117 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group); 118 119 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0); 120 } 121 122 struct mlx5_reg_pcap { 123 u8 rsvd0; 124 u8 port_num; 125 u8 rsvd1[2]; 126 __be32 caps_127_96; 127 __be32 caps_95_64; 128 __be32 caps_63_32; 129 __be32 caps_31_0; 130 }; 131 132 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps) 133 { 134 struct mlx5_reg_pcap in; 135 struct mlx5_reg_pcap out; 136 137 memset(&in, 0, sizeof(in)); 138 in.caps_127_96 = cpu_to_be32(caps); 139 in.port_num = port_num; 140 141 return mlx5_core_access_reg(dev, &in, sizeof(in), &out, 142 sizeof(out), MLX5_REG_PCAP, 0, 1); 143 } 144 EXPORT_SYMBOL_GPL(mlx5_set_port_caps); 145 146 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 147 int ptys_size, int proto_mask, u8 local_port) 148 { 149 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 150 151 MLX5_SET(ptys_reg, in, local_port, local_port); 152 MLX5_SET(ptys_reg, in, proto_mask, proto_mask); 153 return mlx5_core_access_reg(dev, in, sizeof(in), ptys, 154 ptys_size, MLX5_REG_PTYS, 0, 0); 155 } 156 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys); 157 158 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration) 159 { 160 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; 161 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; 162 163 MLX5_SET(mlcr_reg, in, local_port, 1); 164 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration); 165 return mlx5_core_access_reg(dev, in, sizeof(in), out, 166 sizeof(out), MLX5_REG_MLCR, 0, 1); 167 } 168 169 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, 170 u16 *proto_oper, u8 local_port) 171 { 172 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 173 int err; 174 175 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, 176 local_port); 177 if (err) 178 return err; 179 180 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper); 181 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper); 182 183 return 0; 184 } 185 EXPORT_SYMBOL(mlx5_query_ib_port_oper); 186 187 /* This function should be used after setting a port register only */ 188 void mlx5_toggle_port_link(struct mlx5_core_dev *dev) 189 { 190 enum mlx5_port_status ps; 191 192 mlx5_query_port_admin_status(dev, &ps); 193 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN); 194 if (ps == MLX5_PORT_UP) 195 mlx5_set_port_admin_status(dev, MLX5_PORT_UP); 196 } 197 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link); 198 199 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, 200 enum mlx5_port_status status) 201 { 202 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; 203 u32 out[MLX5_ST_SZ_DW(paos_reg)]; 204 205 MLX5_SET(paos_reg, in, local_port, 1); 206 MLX5_SET(paos_reg, in, admin_status, status); 207 MLX5_SET(paos_reg, in, ase, 1); 208 return mlx5_core_access_reg(dev, in, sizeof(in), out, 209 sizeof(out), MLX5_REG_PAOS, 0, 1); 210 } 211 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status); 212 213 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 214 enum mlx5_port_status *status) 215 { 216 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; 217 u32 out[MLX5_ST_SZ_DW(paos_reg)]; 218 int err; 219 220 MLX5_SET(paos_reg, in, local_port, 1); 221 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 222 sizeof(out), MLX5_REG_PAOS, 0, 0); 223 if (err) 224 return err; 225 *status = MLX5_GET(paos_reg, out, admin_status); 226 return 0; 227 } 228 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status); 229 230 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu, 231 u16 *max_mtu, u16 *oper_mtu, u8 port) 232 { 233 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0}; 234 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; 235 236 MLX5_SET(pmtu_reg, in, local_port, port); 237 mlx5_core_access_reg(dev, in, sizeof(in), out, 238 sizeof(out), MLX5_REG_PMTU, 0, 0); 239 240 if (max_mtu) 241 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu); 242 if (oper_mtu) 243 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu); 244 if (admin_mtu) 245 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu); 246 } 247 248 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port) 249 { 250 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0}; 251 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; 252 253 MLX5_SET(pmtu_reg, in, admin_mtu, mtu); 254 MLX5_SET(pmtu_reg, in, local_port, port); 255 return mlx5_core_access_reg(dev, in, sizeof(in), out, 256 sizeof(out), MLX5_REG_PMTU, 0, 1); 257 } 258 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu); 259 260 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, 261 u8 port) 262 { 263 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port); 264 } 265 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu); 266 267 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, 268 u8 port) 269 { 270 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port); 271 } 272 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu); 273 274 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num) 275 { 276 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0}; 277 u32 out[MLX5_ST_SZ_DW(pmlp_reg)]; 278 int err; 279 280 MLX5_SET(pmlp_reg, in, local_port, 1); 281 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 282 MLX5_REG_PMLP, 0, 0); 283 if (err) 284 return err; 285 286 *module_num = MLX5_GET(lane_2_module_mapping, 287 MLX5_ADDR_OF(pmlp_reg, out, lane0_module_mapping), 288 module); 289 290 return 0; 291 } 292 293 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num, 294 u8 *module_id) 295 { 296 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {}; 297 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; 298 int err, status; 299 u8 *ptr; 300 301 MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW); 302 MLX5_SET(mcia_reg, in, module, module_num); 303 MLX5_SET(mcia_reg, in, device_address, 0); 304 MLX5_SET(mcia_reg, in, page_number, 0); 305 MLX5_SET(mcia_reg, in, size, 1); 306 MLX5_SET(mcia_reg, in, l, 0); 307 308 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 309 sizeof(out), MLX5_REG_MCIA, 0, 0); 310 if (err) 311 return err; 312 313 status = MLX5_GET(mcia_reg, out, status); 314 if (status) { 315 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n", 316 status); 317 return -EIO; 318 } 319 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0); 320 321 *module_id = ptr[0]; 322 323 return 0; 324 } 325 326 static int mlx5_qsfp_eeprom_page(u16 offset) 327 { 328 if (offset < MLX5_EEPROM_PAGE_LENGTH) 329 /* Addresses between 0-255 - page 00 */ 330 return 0; 331 332 /* Addresses between 256 - 639 belongs to pages 01, 02 and 03 333 * For example, offset = 400 belongs to page 02: 334 * 1 + ((400 - 256)/128) = 2 335 */ 336 return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) / 337 MLX5_EEPROM_HIGH_PAGE_LENGTH); 338 } 339 340 static int mlx5_qsfp_eeprom_high_page_offset(int page_num) 341 { 342 if (!page_num) /* Page 0 always start from low page */ 343 return 0; 344 345 /* High page */ 346 return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH; 347 } 348 349 static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset) 350 { 351 *i2c_addr = MLX5_I2C_ADDR_LOW; 352 *page_num = mlx5_qsfp_eeprom_page(*offset); 353 *offset -= mlx5_qsfp_eeprom_high_page_offset(*page_num); 354 } 355 356 static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset) 357 { 358 *i2c_addr = MLX5_I2C_ADDR_LOW; 359 *page_num = 0; 360 361 if (*offset < MLX5_EEPROM_PAGE_LENGTH) 362 return; 363 364 *i2c_addr = MLX5_I2C_ADDR_HIGH; 365 *offset -= MLX5_EEPROM_PAGE_LENGTH; 366 } 367 368 static int mlx5_mcia_max_bytes(struct mlx5_core_dev *dev) 369 { 370 /* mcia supports either 12 dwords or 32 dwords */ 371 return (MLX5_CAP_MCAM_FEATURE(dev, mcia_32dwords) ? 32 : 12) * sizeof(u32); 372 } 373 374 static int mlx5_query_mcia(struct mlx5_core_dev *dev, 375 struct mlx5_module_eeprom_query_params *params, u8 *data) 376 { 377 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {}; 378 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; 379 int status, err; 380 void *ptr; 381 u16 size; 382 383 size = min_t(int, params->size, mlx5_mcia_max_bytes(dev)); 384 385 MLX5_SET(mcia_reg, in, l, 0); 386 MLX5_SET(mcia_reg, in, size, size); 387 MLX5_SET(mcia_reg, in, module, params->module_number); 388 MLX5_SET(mcia_reg, in, device_address, params->offset); 389 MLX5_SET(mcia_reg, in, page_number, params->page); 390 MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address); 391 392 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 393 sizeof(out), MLX5_REG_MCIA, 0, 0); 394 if (err) 395 return err; 396 397 status = MLX5_GET(mcia_reg, out, status); 398 if (status) { 399 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n", 400 status); 401 return -EIO; 402 } 403 404 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0); 405 memcpy(data, ptr, size); 406 407 return size; 408 } 409 410 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, 411 u16 offset, u16 size, u8 *data) 412 { 413 struct mlx5_module_eeprom_query_params query = {0}; 414 u8 module_id; 415 int err; 416 417 err = mlx5_query_module_num(dev, &query.module_number); 418 if (err) 419 return err; 420 421 err = mlx5_query_module_id(dev, query.module_number, &module_id); 422 if (err) 423 return err; 424 425 switch (module_id) { 426 case MLX5_MODULE_ID_SFP: 427 mlx5_sfp_eeprom_params_set(&query.i2c_address, &query.page, &offset); 428 break; 429 case MLX5_MODULE_ID_QSFP: 430 case MLX5_MODULE_ID_QSFP_PLUS: 431 case MLX5_MODULE_ID_QSFP28: 432 mlx5_qsfp_eeprom_params_set(&query.i2c_address, &query.page, &offset); 433 break; 434 default: 435 mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id); 436 return -EINVAL; 437 } 438 439 if (offset + size > MLX5_EEPROM_PAGE_LENGTH) 440 /* Cross pages read, read until offset 256 in low page */ 441 size = MLX5_EEPROM_PAGE_LENGTH - offset; 442 443 query.size = size; 444 query.offset = offset; 445 446 return mlx5_query_mcia(dev, &query, data); 447 } 448 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom); 449 450 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, 451 struct mlx5_module_eeprom_query_params *params, 452 u8 *data) 453 { 454 int err; 455 456 err = mlx5_query_module_num(dev, ¶ms->module_number); 457 if (err) 458 return err; 459 460 if (params->i2c_address != MLX5_I2C_ADDR_HIGH && 461 params->i2c_address != MLX5_I2C_ADDR_LOW) { 462 mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address); 463 return -EINVAL; 464 } 465 466 return mlx5_query_mcia(dev, params, data); 467 } 468 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page); 469 470 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, 471 int pvlc_size, u8 local_port) 472 { 473 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0}; 474 475 MLX5_SET(pvlc_reg, in, local_port, local_port); 476 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc, 477 pvlc_size, MLX5_REG_PVLC, 0, 0); 478 } 479 480 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 481 u8 *vl_hw_cap, u8 local_port) 482 { 483 u32 out[MLX5_ST_SZ_DW(pvlc_reg)]; 484 int err; 485 486 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port); 487 if (err) 488 return err; 489 490 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap); 491 492 return 0; 493 } 494 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap); 495 496 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 497 u8 port_num, void *out, size_t sz) 498 { 499 u32 *in; 500 int err; 501 502 in = kvzalloc(sz, GFP_KERNEL); 503 if (!in) { 504 err = -ENOMEM; 505 return err; 506 } 507 508 MLX5_SET(ppcnt_reg, in, local_port, port_num); 509 510 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP); 511 err = mlx5_core_access_reg(dev, in, sz, out, 512 sz, MLX5_REG_PPCNT, 0, 0); 513 514 kvfree(in); 515 return err; 516 } 517 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt); 518 519 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out, 520 u32 out_size) 521 { 522 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 523 524 MLX5_SET(pfcc_reg, in, local_port, 1); 525 526 return mlx5_core_access_reg(dev, in, sizeof(in), out, 527 out_size, MLX5_REG_PFCC, 0, 0); 528 } 529 530 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause) 531 { 532 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 533 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 534 535 MLX5_SET(pfcc_reg, in, local_port, 1); 536 MLX5_SET(pfcc_reg, in, pptx, tx_pause); 537 MLX5_SET(pfcc_reg, in, pprx, rx_pause); 538 539 return mlx5_core_access_reg(dev, in, sizeof(in), out, 540 sizeof(out), MLX5_REG_PFCC, 0, 1); 541 } 542 EXPORT_SYMBOL_GPL(mlx5_set_port_pause); 543 544 int mlx5_query_port_pause(struct mlx5_core_dev *dev, 545 u32 *rx_pause, u32 *tx_pause) 546 { 547 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 548 int err; 549 550 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 551 if (err) 552 return err; 553 554 if (rx_pause) 555 *rx_pause = MLX5_GET(pfcc_reg, out, pprx); 556 557 if (tx_pause) 558 *tx_pause = MLX5_GET(pfcc_reg, out, pptx); 559 560 return 0; 561 } 562 EXPORT_SYMBOL_GPL(mlx5_query_port_pause); 563 564 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, 565 u16 stall_critical_watermark, 566 u16 stall_minor_watermark) 567 { 568 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 569 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 570 571 MLX5_SET(pfcc_reg, in, local_port, 1); 572 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1); 573 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1); 574 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1); 575 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1); 576 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1); 577 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark, 578 stall_critical_watermark); 579 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark); 580 581 return mlx5_core_access_reg(dev, in, sizeof(in), out, 582 sizeof(out), MLX5_REG_PFCC, 0, 1); 583 } 584 585 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, 586 u16 *stall_critical_watermark, 587 u16 *stall_minor_watermark) 588 { 589 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 590 int err; 591 592 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 593 if (err) 594 return err; 595 596 if (stall_critical_watermark) 597 *stall_critical_watermark = MLX5_GET(pfcc_reg, out, 598 device_stall_critical_watermark); 599 600 if (stall_minor_watermark) 601 *stall_minor_watermark = MLX5_GET(pfcc_reg, out, 602 device_stall_minor_watermark); 603 604 return 0; 605 } 606 607 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx) 608 { 609 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; 610 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 611 612 MLX5_SET(pfcc_reg, in, local_port, 1); 613 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx); 614 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx); 615 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx); 616 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx); 617 618 return mlx5_core_access_reg(dev, in, sizeof(in), out, 619 sizeof(out), MLX5_REG_PFCC, 0, 1); 620 } 621 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc); 622 623 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx) 624 { 625 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; 626 int err; 627 628 err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); 629 if (err) 630 return err; 631 632 if (pfc_en_tx) 633 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx); 634 635 if (pfc_en_rx) 636 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx); 637 638 return 0; 639 } 640 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc); 641 642 int mlx5_max_tc(struct mlx5_core_dev *mdev) 643 { 644 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8; 645 646 return num_tc - 1; 647 } 648 649 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out) 650 { 651 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0}; 652 653 MLX5_SET(dcbx_param, in, port_number, 1); 654 655 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 656 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0); 657 } 658 659 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in) 660 { 661 u32 out[MLX5_ST_SZ_DW(dcbx_param)]; 662 663 MLX5_SET(dcbx_param, in, port_number, 1); 664 665 return mlx5_core_access_reg(mdev, in, sizeof(out), out, 666 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1); 667 } 668 669 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc) 670 { 671 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0}; 672 u32 out[MLX5_ST_SZ_DW(qtct_reg)]; 673 int err; 674 int i; 675 676 for (i = 0; i < 8; i++) { 677 if (prio_tc[i] > mlx5_max_tc(mdev)) 678 return -EINVAL; 679 680 MLX5_SET(qtct_reg, in, prio, i); 681 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]); 682 683 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 684 sizeof(out), MLX5_REG_QTCT, 0, 1); 685 if (err) 686 return err; 687 } 688 689 return 0; 690 } 691 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc); 692 693 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 694 u8 prio, u8 *tc) 695 { 696 u32 in[MLX5_ST_SZ_DW(qtct_reg)]; 697 u32 out[MLX5_ST_SZ_DW(qtct_reg)]; 698 int err; 699 700 memset(in, 0, sizeof(in)); 701 memset(out, 0, sizeof(out)); 702 703 MLX5_SET(qtct_reg, in, port_number, 1); 704 MLX5_SET(qtct_reg, in, prio, prio); 705 706 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 707 sizeof(out), MLX5_REG_QTCT, 0, 0); 708 if (!err) 709 *tc = MLX5_GET(qtct_reg, out, tclass); 710 711 return err; 712 } 713 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc); 714 715 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in, 716 int inlen) 717 { 718 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 719 720 if (!MLX5_CAP_GEN(mdev, ets)) 721 return -EOPNOTSUPP; 722 723 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out), 724 MLX5_REG_QETCR, 0, 1); 725 } 726 727 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out, 728 int outlen) 729 { 730 u32 in[MLX5_ST_SZ_DW(qetc_reg)]; 731 732 if (!MLX5_CAP_GEN(mdev, ets)) 733 return -EOPNOTSUPP; 734 735 memset(in, 0, sizeof(in)); 736 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen, 737 MLX5_REG_QETCR, 0, 0); 738 } 739 740 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group) 741 { 742 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 743 int i; 744 745 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 746 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1); 747 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]); 748 } 749 750 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 751 } 752 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group); 753 754 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 755 u8 tc, u8 *tc_group) 756 { 757 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 758 void *ets_tcn_conf; 759 int err; 760 761 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 762 if (err) 763 return err; 764 765 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, 766 tc_configuration[tc]); 767 768 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 769 group); 770 771 return 0; 772 } 773 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group); 774 775 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw) 776 { 777 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 778 int i; 779 780 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 781 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1); 782 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]); 783 } 784 785 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 786 } 787 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc); 788 789 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, 790 u8 tc, u8 *bw_pct) 791 { 792 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 793 void *ets_tcn_conf; 794 int err; 795 796 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 797 if (err) 798 return err; 799 800 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, 801 tc_configuration[tc]); 802 803 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 804 bw_allocation); 805 806 return 0; 807 } 808 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc); 809 810 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, 811 u8 *max_bw_value, 812 u8 *max_bw_units) 813 { 814 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0}; 815 void *ets_tcn_conf; 816 int i; 817 818 MLX5_SET(qetc_reg, in, port_number, 1); 819 820 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 821 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]); 822 823 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1); 824 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units, 825 max_bw_units[i]); 826 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value, 827 max_bw_value[i]); 828 } 829 830 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in)); 831 } 832 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit); 833 834 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, 835 u8 *max_bw_value, 836 u8 *max_bw_units) 837 { 838 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; 839 void *ets_tcn_conf; 840 int err; 841 int i; 842 843 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out)); 844 if (err) 845 return err; 846 847 for (i = 0; i <= mlx5_max_tc(mdev); i++) { 848 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]); 849 850 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 851 max_bw_value); 852 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf, 853 max_bw_units); 854 } 855 856 return 0; 857 } 858 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit); 859 860 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode) 861 { 862 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {}; 863 864 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL); 865 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1); 866 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode); 867 return mlx5_cmd_exec_in(mdev, set_wol_rol, in); 868 } 869 EXPORT_SYMBOL_GPL(mlx5_set_port_wol); 870 871 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode) 872 { 873 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {}; 874 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {}; 875 int err; 876 877 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL); 878 err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out); 879 if (!err) 880 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode); 881 882 return err; 883 } 884 EXPORT_SYMBOL_GPL(mlx5_query_port_wol); 885 886 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen) 887 { 888 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; 889 890 MLX5_SET(pcmr_reg, in, local_port, 1); 891 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 892 outlen, MLX5_REG_PCMR, 0, 0); 893 } 894 895 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen) 896 { 897 u32 out[MLX5_ST_SZ_DW(pcmr_reg)]; 898 899 return mlx5_core_access_reg(mdev, in, inlen, out, 900 sizeof(out), MLX5_REG_PCMR, 0, 1); 901 } 902 903 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable) 904 { 905 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; 906 int err; 907 908 err = mlx5_query_ports_check(mdev, in, sizeof(in)); 909 if (err) 910 return err; 911 MLX5_SET(pcmr_reg, in, local_port, 1); 912 MLX5_SET(pcmr_reg, in, fcs_chk, enable); 913 return mlx5_set_ports_check(mdev, in, sizeof(in)); 914 } 915 916 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, 917 bool *enabled) 918 { 919 u32 out[MLX5_ST_SZ_DW(pcmr_reg)]; 920 /* Default values for FW which do not support MLX5_REG_PCMR */ 921 *supported = false; 922 *enabled = true; 923 924 if (!MLX5_CAP_GEN(mdev, ports_check)) 925 return; 926 927 if (mlx5_query_ports_check(mdev, out, sizeof(out))) 928 return; 929 930 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap)); 931 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk)); 932 } 933 934 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size) 935 { 936 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 937 938 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps, 939 mtpps_size, MLX5_REG_MTPPS, 0, 0); 940 } 941 942 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size) 943 { 944 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 945 946 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out, 947 sizeof(out), MLX5_REG_MTPPS, 0, 1); 948 } 949 950 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode) 951 { 952 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 953 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 954 int err = 0; 955 956 MLX5_SET(mtppse_reg, in, pin, pin); 957 958 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 959 sizeof(out), MLX5_REG_MTPPSE, 0, 0); 960 if (err) 961 return err; 962 963 *arm = MLX5_GET(mtppse_reg, in, event_arm); 964 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode); 965 966 return err; 967 } 968 969 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode) 970 { 971 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 972 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0}; 973 974 MLX5_SET(mtppse_reg, in, pin, pin); 975 MLX5_SET(mtppse_reg, in, event_arm, arm); 976 MLX5_SET(mtppse_reg, in, event_generation_mode, mode); 977 978 return mlx5_core_access_reg(mdev, in, sizeof(in), out, 979 sizeof(out), MLX5_REG_MTPPSE, 0, 1); 980 } 981 982 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state) 983 { 984 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {}; 985 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {}; 986 int err; 987 988 MLX5_SET(qpts_reg, in, local_port, 1); 989 MLX5_SET(qpts_reg, in, trust_state, trust_state); 990 991 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 992 sizeof(out), MLX5_REG_QPTS, 0, 1); 993 return err; 994 } 995 996 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state) 997 { 998 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {}; 999 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {}; 1000 int err; 1001 1002 MLX5_SET(qpts_reg, in, local_port, 1); 1003 1004 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 1005 sizeof(out), MLX5_REG_QPTS, 0, 0); 1006 if (!err) 1007 *trust_state = MLX5_GET(qpts_reg, out, trust_state); 1008 1009 return err; 1010 } 1011 1012 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio) 1013 { 1014 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg); 1015 void *qpdpm_dscp; 1016 void *out; 1017 void *in; 1018 int err; 1019 1020 in = kzalloc(sz, GFP_KERNEL); 1021 out = kzalloc(sz, GFP_KERNEL); 1022 if (!in || !out) { 1023 err = -ENOMEM; 1024 goto out; 1025 } 1026 1027 MLX5_SET(qpdpm_reg, in, local_port, 1); 1028 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0); 1029 if (err) 1030 goto out; 1031 1032 memcpy(in, out, sz); 1033 MLX5_SET(qpdpm_reg, in, local_port, 1); 1034 1035 /* Update the corresponding dscp entry */ 1036 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]); 1037 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio); 1038 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1); 1039 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1); 1040 1041 out: 1042 kfree(in); 1043 kfree(out); 1044 return err; 1045 } 1046 1047 /* dscp2prio[i]: priority that dscp i mapped to */ 1048 #define MLX5E_SUPPORTED_DSCP 64 1049 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio) 1050 { 1051 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg); 1052 void *qpdpm_dscp; 1053 void *out; 1054 void *in; 1055 int err; 1056 int i; 1057 1058 in = kzalloc(sz, GFP_KERNEL); 1059 out = kzalloc(sz, GFP_KERNEL); 1060 if (!in || !out) { 1061 err = -ENOMEM; 1062 goto out; 1063 } 1064 1065 MLX5_SET(qpdpm_reg, in, local_port, 1); 1066 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0); 1067 if (err) 1068 goto out; 1069 1070 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) { 1071 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]); 1072 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio); 1073 } 1074 1075 out: 1076 kfree(in); 1077 kfree(out); 1078 return err; 1079 } 1080