1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <net/devlink.h> 54 #include "mlx5_core.h" 55 #include "lib/eq.h" 56 #include "fs_core.h" 57 #include "lib/mpfs.h" 58 #include "eswitch.h" 59 #include "lib/mlx5.h" 60 #include "fpga/core.h" 61 #include "fpga/ipsec.h" 62 #include "accel/ipsec.h" 63 #include "accel/tls.h" 64 #include "lib/clock.h" 65 #include "lib/vxlan.h" 66 #include "lib/devcom.h" 67 #include "diag/fw_tracer.h" 68 #include "ecpf.h" 69 70 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 71 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 MODULE_VERSION(DRIVER_VERSION); 74 75 unsigned int mlx5_core_debug_mask; 76 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 77 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 78 79 #define MLX5_DEFAULT_PROF 2 80 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 81 module_param_named(prof_sel, prof_sel, uint, 0444); 82 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 83 84 static u32 sw_owner_id[4]; 85 86 enum { 87 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 88 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 89 }; 90 91 static struct mlx5_profile profile[] = { 92 [0] = { 93 .mask = 0, 94 }, 95 [1] = { 96 .mask = MLX5_PROF_MASK_QP_SIZE, 97 .log_max_qp = 12, 98 }, 99 [2] = { 100 .mask = MLX5_PROF_MASK_QP_SIZE | 101 MLX5_PROF_MASK_MR_CACHE, 102 .log_max_qp = 18, 103 .mr_cache[0] = { 104 .size = 500, 105 .limit = 250 106 }, 107 .mr_cache[1] = { 108 .size = 500, 109 .limit = 250 110 }, 111 .mr_cache[2] = { 112 .size = 500, 113 .limit = 250 114 }, 115 .mr_cache[3] = { 116 .size = 500, 117 .limit = 250 118 }, 119 .mr_cache[4] = { 120 .size = 500, 121 .limit = 250 122 }, 123 .mr_cache[5] = { 124 .size = 500, 125 .limit = 250 126 }, 127 .mr_cache[6] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[7] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[8] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[9] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[10] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[11] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[12] = { 152 .size = 64, 153 .limit = 32 154 }, 155 .mr_cache[13] = { 156 .size = 32, 157 .limit = 16 158 }, 159 .mr_cache[14] = { 160 .size = 16, 161 .limit = 8 162 }, 163 .mr_cache[15] = { 164 .size = 8, 165 .limit = 4 166 }, 167 }, 168 }; 169 170 #define FW_INIT_TIMEOUT_MILI 2000 171 #define FW_INIT_WAIT_MS 2 172 #define FW_PRE_INIT_TIMEOUT_MILI 10000 173 174 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 175 { 176 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 177 int err = 0; 178 179 while (fw_initializing(dev)) { 180 if (time_after(jiffies, end)) { 181 err = -EBUSY; 182 break; 183 } 184 msleep(FW_INIT_WAIT_MS); 185 } 186 187 return err; 188 } 189 190 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 191 { 192 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 193 driver_version); 194 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 195 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 196 int remaining_size = driver_ver_sz; 197 char *string; 198 199 if (!MLX5_CAP_GEN(dev, driver_version)) 200 return; 201 202 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 203 204 strncpy(string, "Linux", remaining_size); 205 206 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 207 strncat(string, ",", remaining_size); 208 209 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 210 strncat(string, DRIVER_NAME, remaining_size); 211 212 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 213 strncat(string, ",", remaining_size); 214 215 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 216 strncat(string, DRIVER_VERSION, remaining_size); 217 218 /*Send the command*/ 219 MLX5_SET(set_driver_version_in, in, opcode, 220 MLX5_CMD_OP_SET_DRIVER_VERSION); 221 222 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 223 } 224 225 static int set_dma_caps(struct pci_dev *pdev) 226 { 227 int err; 228 229 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 230 if (err) { 231 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 232 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 233 if (err) { 234 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 235 return err; 236 } 237 } 238 239 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 240 if (err) { 241 dev_warn(&pdev->dev, 242 "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 243 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 244 if (err) { 245 dev_err(&pdev->dev, 246 "Can't set consistent PCI DMA mask, aborting\n"); 247 return err; 248 } 249 } 250 251 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 252 return err; 253 } 254 255 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 256 { 257 struct pci_dev *pdev = dev->pdev; 258 int err = 0; 259 260 mutex_lock(&dev->pci_status_mutex); 261 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 262 err = pci_enable_device(pdev); 263 if (!err) 264 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 265 } 266 mutex_unlock(&dev->pci_status_mutex); 267 268 return err; 269 } 270 271 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 272 { 273 struct pci_dev *pdev = dev->pdev; 274 275 mutex_lock(&dev->pci_status_mutex); 276 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 277 pci_disable_device(pdev); 278 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 279 } 280 mutex_unlock(&dev->pci_status_mutex); 281 } 282 283 static int request_bar(struct pci_dev *pdev) 284 { 285 int err = 0; 286 287 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 288 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 289 return -ENODEV; 290 } 291 292 err = pci_request_regions(pdev, DRIVER_NAME); 293 if (err) 294 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 295 296 return err; 297 } 298 299 static void release_bar(struct pci_dev *pdev) 300 { 301 pci_release_regions(pdev); 302 } 303 304 struct mlx5_reg_host_endianness { 305 u8 he; 306 u8 rsvd[15]; 307 }; 308 309 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 310 311 enum { 312 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 313 MLX5_DEV_CAP_FLAG_DCT, 314 }; 315 316 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 317 { 318 switch (size) { 319 case 128: 320 return 0; 321 case 256: 322 return 1; 323 case 512: 324 return 2; 325 case 1024: 326 return 3; 327 case 2048: 328 return 4; 329 case 4096: 330 return 5; 331 default: 332 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 333 return 0; 334 } 335 } 336 337 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 338 enum mlx5_cap_type cap_type, 339 enum mlx5_cap_mode cap_mode) 340 { 341 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 342 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 343 void *out, *hca_caps; 344 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 345 int err; 346 347 memset(in, 0, sizeof(in)); 348 out = kzalloc(out_sz, GFP_KERNEL); 349 if (!out) 350 return -ENOMEM; 351 352 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 353 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 354 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 355 if (err) { 356 mlx5_core_warn(dev, 357 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 358 cap_type, cap_mode, err); 359 goto query_ex; 360 } 361 362 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 363 364 switch (cap_mode) { 365 case HCA_CAP_OPMOD_GET_MAX: 366 memcpy(dev->caps.hca_max[cap_type], hca_caps, 367 MLX5_UN_SZ_BYTES(hca_cap_union)); 368 break; 369 case HCA_CAP_OPMOD_GET_CUR: 370 memcpy(dev->caps.hca_cur[cap_type], hca_caps, 371 MLX5_UN_SZ_BYTES(hca_cap_union)); 372 break; 373 default: 374 mlx5_core_warn(dev, 375 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 376 cap_type, cap_mode); 377 err = -EINVAL; 378 break; 379 } 380 query_ex: 381 kfree(out); 382 return err; 383 } 384 385 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 386 { 387 int ret; 388 389 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 390 if (ret) 391 return ret; 392 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 393 } 394 395 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 396 { 397 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 398 399 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 400 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 401 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 402 } 403 404 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 405 { 406 void *set_ctx; 407 void *set_hca_cap; 408 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 409 int req_endianness; 410 int err; 411 412 if (MLX5_CAP_GEN(dev, atomic)) { 413 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 414 if (err) 415 return err; 416 } else { 417 return 0; 418 } 419 420 req_endianness = 421 MLX5_CAP_ATOMIC(dev, 422 supported_atomic_req_8B_endianness_mode_1); 423 424 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 425 return 0; 426 427 set_ctx = kzalloc(set_sz, GFP_KERNEL); 428 if (!set_ctx) 429 return -ENOMEM; 430 431 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 432 433 /* Set requestor to host endianness */ 434 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 435 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 436 437 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 438 439 kfree(set_ctx); 440 return err; 441 } 442 443 static int handle_hca_cap_odp(struct mlx5_core_dev *dev) 444 { 445 void *set_hca_cap; 446 void *set_ctx; 447 int set_sz; 448 bool do_set = false; 449 int err; 450 451 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 452 !MLX5_CAP_GEN(dev, pg)) 453 return 0; 454 455 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 456 if (err) 457 return err; 458 459 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 460 set_ctx = kzalloc(set_sz, GFP_KERNEL); 461 if (!set_ctx) 462 return -ENOMEM; 463 464 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 465 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 466 MLX5_ST_SZ_BYTES(odp_cap)); 467 468 #define ODP_CAP_SET_MAX(dev, field) \ 469 do { \ 470 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 471 if (_res) { \ 472 do_set = true; \ 473 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 474 } \ 475 } while (0) 476 477 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 478 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 482 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 485 486 if (do_set) 487 err = set_caps(dev, set_ctx, set_sz, 488 MLX5_SET_HCA_CAP_OP_MOD_ODP); 489 490 kfree(set_ctx); 491 492 return err; 493 } 494 495 static int handle_hca_cap(struct mlx5_core_dev *dev) 496 { 497 void *set_ctx = NULL; 498 struct mlx5_profile *prof = dev->profile; 499 int err = -ENOMEM; 500 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 501 void *set_hca_cap; 502 503 set_ctx = kzalloc(set_sz, GFP_KERNEL); 504 if (!set_ctx) 505 goto query_ex; 506 507 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 508 if (err) 509 goto query_ex; 510 511 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 512 capability); 513 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 514 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 515 516 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 517 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 518 128); 519 /* we limit the size of the pkey table to 128 entries for now */ 520 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 521 to_fw_pkey_sz(dev, 128)); 522 523 /* Check log_max_qp from HCA caps to set in current profile */ 524 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 525 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 526 profile[prof_sel].log_max_qp, 527 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 528 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 529 } 530 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 531 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 532 prof->log_max_qp); 533 534 /* disable cmdif checksum */ 535 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 536 537 /* Enable 4K UAR only when HCA supports it and page size is bigger 538 * than 4K. 539 */ 540 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 541 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 542 543 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 544 545 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 546 MLX5_SET(cmd_hca_cap, 547 set_hca_cap, 548 cache_line_128byte, 549 cache_line_size() >= 128 ? 1 : 0); 550 551 if (MLX5_CAP_GEN_MAX(dev, dct)) 552 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 553 554 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 555 MLX5_SET(cmd_hca_cap, 556 set_hca_cap, 557 num_vhca_ports, 558 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 559 560 err = set_caps(dev, set_ctx, set_sz, 561 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 562 563 query_ex: 564 kfree(set_ctx); 565 return err; 566 } 567 568 static int set_hca_cap(struct mlx5_core_dev *dev) 569 { 570 int err; 571 572 err = handle_hca_cap(dev); 573 if (err) { 574 mlx5_core_err(dev, "handle_hca_cap failed\n"); 575 goto out; 576 } 577 578 err = handle_hca_cap_atomic(dev); 579 if (err) { 580 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 581 goto out; 582 } 583 584 err = handle_hca_cap_odp(dev); 585 if (err) { 586 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 587 goto out; 588 } 589 590 out: 591 return err; 592 } 593 594 static int set_hca_ctrl(struct mlx5_core_dev *dev) 595 { 596 struct mlx5_reg_host_endianness he_in; 597 struct mlx5_reg_host_endianness he_out; 598 int err; 599 600 if (!mlx5_core_is_pf(dev)) 601 return 0; 602 603 memset(&he_in, 0, sizeof(he_in)); 604 he_in.he = MLX5_SET_HOST_ENDIANNESS; 605 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 606 &he_out, sizeof(he_out), 607 MLX5_REG_HOST_ENDIANNESS, 0, 1); 608 return err; 609 } 610 611 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 612 { 613 int ret = 0; 614 615 /* Disable local_lb by default */ 616 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 617 ret = mlx5_nic_vport_update_local_lb(dev, false); 618 619 return ret; 620 } 621 622 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 623 { 624 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 625 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 626 627 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 628 MLX5_SET(enable_hca_in, in, function_id, func_id); 629 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 630 dev->caps.embedded_cpu); 631 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 632 } 633 634 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 635 { 636 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 637 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 638 639 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 640 MLX5_SET(disable_hca_in, in, function_id, func_id); 641 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 642 dev->caps.embedded_cpu); 643 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 644 } 645 646 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 647 struct ptp_system_timestamp *sts) 648 { 649 u32 timer_h, timer_h1, timer_l; 650 651 timer_h = ioread32be(&dev->iseg->internal_timer_h); 652 ptp_read_system_prets(sts); 653 timer_l = ioread32be(&dev->iseg->internal_timer_l); 654 ptp_read_system_postts(sts); 655 timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 656 if (timer_h != timer_h1) { 657 /* wrap around */ 658 ptp_read_system_prets(sts); 659 timer_l = ioread32be(&dev->iseg->internal_timer_l); 660 ptp_read_system_postts(sts); 661 } 662 663 return (u64)timer_l | (u64)timer_h1 << 32; 664 } 665 666 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 667 { 668 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 669 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 670 u32 sup_issi; 671 int err; 672 673 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 674 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 675 query_out, sizeof(query_out)); 676 if (err) { 677 u32 syndrome; 678 u8 status; 679 680 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 681 if (!status || syndrome == MLX5_DRIVER_SYND) { 682 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 683 err, status, syndrome); 684 return err; 685 } 686 687 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 688 dev->issi = 0; 689 return 0; 690 } 691 692 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 693 694 if (sup_issi & (1 << 1)) { 695 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 696 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 697 698 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 699 MLX5_SET(set_issi_in, set_in, current_issi, 1); 700 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 701 set_out, sizeof(set_out)); 702 if (err) { 703 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 704 err); 705 return err; 706 } 707 708 dev->issi = 1; 709 710 return 0; 711 } else if (sup_issi & (1 << 0) || !sup_issi) { 712 return 0; 713 } 714 715 return -EOPNOTSUPP; 716 } 717 718 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 719 const struct pci_device_id *id) 720 { 721 struct mlx5_priv *priv = &dev->priv; 722 int err = 0; 723 724 priv->pci_dev_data = id->driver_data; 725 726 pci_set_drvdata(dev->pdev, dev); 727 728 dev->bar_addr = pci_resource_start(pdev, 0); 729 priv->numa_node = dev_to_node(&dev->pdev->dev); 730 731 err = mlx5_pci_enable_device(dev); 732 if (err) { 733 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 734 return err; 735 } 736 737 err = request_bar(pdev); 738 if (err) { 739 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 740 goto err_disable; 741 } 742 743 pci_set_master(pdev); 744 745 err = set_dma_caps(pdev); 746 if (err) { 747 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 748 goto err_clr_master; 749 } 750 751 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 752 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 753 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 754 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 755 756 dev->iseg_base = dev->bar_addr; 757 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 758 if (!dev->iseg) { 759 err = -ENOMEM; 760 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 761 goto err_clr_master; 762 } 763 764 return 0; 765 766 err_clr_master: 767 pci_clear_master(dev->pdev); 768 release_bar(dev->pdev); 769 err_disable: 770 mlx5_pci_disable_device(dev); 771 return err; 772 } 773 774 static void mlx5_pci_close(struct mlx5_core_dev *dev) 775 { 776 iounmap(dev->iseg); 777 pci_clear_master(dev->pdev); 778 release_bar(dev->pdev); 779 mlx5_pci_disable_device(dev); 780 } 781 782 static int mlx5_init_once(struct mlx5_core_dev *dev) 783 { 784 int err; 785 786 dev->priv.devcom = mlx5_devcom_register_device(dev); 787 if (IS_ERR(dev->priv.devcom)) 788 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 789 dev->priv.devcom); 790 791 err = mlx5_query_board_id(dev); 792 if (err) { 793 mlx5_core_err(dev, "query board id failed\n"); 794 goto err_devcom; 795 } 796 797 err = mlx5_eq_table_init(dev); 798 if (err) { 799 mlx5_core_err(dev, "failed to initialize eq\n"); 800 goto err_devcom; 801 } 802 803 err = mlx5_events_init(dev); 804 if (err) { 805 mlx5_core_err(dev, "failed to initialize events\n"); 806 goto err_eq_cleanup; 807 } 808 809 err = mlx5_cq_debugfs_init(dev); 810 if (err) { 811 mlx5_core_err(dev, "failed to initialize cq debugfs\n"); 812 goto err_events_cleanup; 813 } 814 815 mlx5_init_qp_table(dev); 816 817 mlx5_init_mkey_table(dev); 818 819 mlx5_init_reserved_gids(dev); 820 821 mlx5_init_clock(dev); 822 823 dev->vxlan = mlx5_vxlan_create(dev); 824 825 err = mlx5_init_rl_table(dev); 826 if (err) { 827 mlx5_core_err(dev, "Failed to init rate limiting\n"); 828 goto err_tables_cleanup; 829 } 830 831 err = mlx5_mpfs_init(dev); 832 if (err) { 833 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 834 goto err_rl_cleanup; 835 } 836 837 err = mlx5_eswitch_init(dev); 838 if (err) { 839 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 840 goto err_mpfs_cleanup; 841 } 842 843 err = mlx5_sriov_init(dev); 844 if (err) { 845 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 846 goto err_eswitch_cleanup; 847 } 848 849 err = mlx5_fpga_init(dev); 850 if (err) { 851 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 852 goto err_sriov_cleanup; 853 } 854 855 dev->tracer = mlx5_fw_tracer_create(dev); 856 857 return 0; 858 859 err_sriov_cleanup: 860 mlx5_sriov_cleanup(dev); 861 err_eswitch_cleanup: 862 mlx5_eswitch_cleanup(dev->priv.eswitch); 863 err_mpfs_cleanup: 864 mlx5_mpfs_cleanup(dev); 865 err_rl_cleanup: 866 mlx5_cleanup_rl_table(dev); 867 err_tables_cleanup: 868 mlx5_vxlan_destroy(dev->vxlan); 869 mlx5_cleanup_mkey_table(dev); 870 mlx5_cleanup_qp_table(dev); 871 mlx5_cq_debugfs_cleanup(dev); 872 err_events_cleanup: 873 mlx5_events_cleanup(dev); 874 err_eq_cleanup: 875 mlx5_eq_table_cleanup(dev); 876 err_devcom: 877 mlx5_devcom_unregister_device(dev->priv.devcom); 878 879 return err; 880 } 881 882 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 883 { 884 mlx5_fw_tracer_destroy(dev->tracer); 885 mlx5_fpga_cleanup(dev); 886 mlx5_sriov_cleanup(dev); 887 mlx5_eswitch_cleanup(dev->priv.eswitch); 888 mlx5_mpfs_cleanup(dev); 889 mlx5_cleanup_rl_table(dev); 890 mlx5_vxlan_destroy(dev->vxlan); 891 mlx5_cleanup_clock(dev); 892 mlx5_cleanup_reserved_gids(dev); 893 mlx5_cleanup_mkey_table(dev); 894 mlx5_cleanup_qp_table(dev); 895 mlx5_cq_debugfs_cleanup(dev); 896 mlx5_events_cleanup(dev); 897 mlx5_eq_table_cleanup(dev); 898 mlx5_devcom_unregister_device(dev->priv.devcom); 899 } 900 901 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 902 { 903 int err; 904 905 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 906 fw_rev_min(dev), fw_rev_sub(dev)); 907 908 /* Only PFs hold the relevant PCIe information for this query */ 909 if (mlx5_core_is_pf(dev)) 910 pcie_print_link_status(dev->pdev); 911 912 /* wait for firmware to accept initialization segments configurations 913 */ 914 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); 915 if (err) { 916 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 917 FW_PRE_INIT_TIMEOUT_MILI); 918 return err; 919 } 920 921 err = mlx5_cmd_init(dev); 922 if (err) { 923 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 924 return err; 925 } 926 927 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 928 if (err) { 929 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 930 FW_INIT_TIMEOUT_MILI); 931 goto err_cmd_cleanup; 932 } 933 934 err = mlx5_core_enable_hca(dev, 0); 935 if (err) { 936 mlx5_core_err(dev, "enable hca failed\n"); 937 goto err_cmd_cleanup; 938 } 939 940 err = mlx5_core_set_issi(dev); 941 if (err) { 942 mlx5_core_err(dev, "failed to set issi\n"); 943 goto err_disable_hca; 944 } 945 946 err = mlx5_satisfy_startup_pages(dev, 1); 947 if (err) { 948 mlx5_core_err(dev, "failed to allocate boot pages\n"); 949 goto err_disable_hca; 950 } 951 952 err = set_hca_ctrl(dev); 953 if (err) { 954 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 955 goto reclaim_boot_pages; 956 } 957 958 err = set_hca_cap(dev); 959 if (err) { 960 mlx5_core_err(dev, "set_hca_cap failed\n"); 961 goto reclaim_boot_pages; 962 } 963 964 err = mlx5_satisfy_startup_pages(dev, 0); 965 if (err) { 966 mlx5_core_err(dev, "failed to allocate init pages\n"); 967 goto reclaim_boot_pages; 968 } 969 970 err = mlx5_cmd_init_hca(dev, sw_owner_id); 971 if (err) { 972 mlx5_core_err(dev, "init hca failed\n"); 973 goto reclaim_boot_pages; 974 } 975 976 mlx5_set_driver_version(dev); 977 978 mlx5_start_health_poll(dev); 979 980 err = mlx5_query_hca_caps(dev); 981 if (err) { 982 mlx5_core_err(dev, "query hca failed\n"); 983 goto stop_health; 984 } 985 986 return 0; 987 988 stop_health: 989 mlx5_stop_health_poll(dev, boot); 990 reclaim_boot_pages: 991 mlx5_reclaim_startup_pages(dev); 992 err_disable_hca: 993 mlx5_core_disable_hca(dev, 0); 994 err_cmd_cleanup: 995 mlx5_cmd_cleanup(dev); 996 997 return err; 998 } 999 1000 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1001 { 1002 int err; 1003 1004 mlx5_stop_health_poll(dev, boot); 1005 err = mlx5_cmd_teardown_hca(dev); 1006 if (err) { 1007 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1008 return err; 1009 } 1010 mlx5_reclaim_startup_pages(dev); 1011 mlx5_core_disable_hca(dev, 0); 1012 mlx5_cmd_cleanup(dev); 1013 1014 return 0; 1015 } 1016 1017 static int mlx5_load(struct mlx5_core_dev *dev) 1018 { 1019 int err; 1020 1021 dev->priv.uar = mlx5_get_uars_page(dev); 1022 if (IS_ERR(dev->priv.uar)) { 1023 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1024 err = PTR_ERR(dev->priv.uar); 1025 return err; 1026 } 1027 1028 mlx5_events_start(dev); 1029 mlx5_pagealloc_start(dev); 1030 1031 err = mlx5_eq_table_create(dev); 1032 if (err) { 1033 mlx5_core_err(dev, "Failed to create EQs\n"); 1034 goto err_eq_table; 1035 } 1036 1037 err = mlx5_fw_tracer_init(dev->tracer); 1038 if (err) { 1039 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1040 goto err_fw_tracer; 1041 } 1042 1043 err = mlx5_fpga_device_start(dev); 1044 if (err) { 1045 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1046 goto err_fpga_start; 1047 } 1048 1049 err = mlx5_accel_ipsec_init(dev); 1050 if (err) { 1051 mlx5_core_err(dev, "IPSec device start failed %d\n", err); 1052 goto err_ipsec_start; 1053 } 1054 1055 err = mlx5_accel_tls_init(dev); 1056 if (err) { 1057 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1058 goto err_tls_start; 1059 } 1060 1061 err = mlx5_init_fs(dev); 1062 if (err) { 1063 mlx5_core_err(dev, "Failed to init flow steering\n"); 1064 goto err_fs; 1065 } 1066 1067 err = mlx5_core_set_hca_defaults(dev); 1068 if (err) { 1069 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1070 goto err_sriov; 1071 } 1072 1073 err = mlx5_sriov_attach(dev); 1074 if (err) { 1075 mlx5_core_err(dev, "sriov init failed %d\n", err); 1076 goto err_sriov; 1077 } 1078 1079 err = mlx5_ec_init(dev); 1080 if (err) { 1081 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1082 goto err_ec; 1083 } 1084 1085 return 0; 1086 1087 err_ec: 1088 mlx5_sriov_detach(dev); 1089 err_sriov: 1090 mlx5_cleanup_fs(dev); 1091 err_fs: 1092 mlx5_accel_tls_cleanup(dev); 1093 err_tls_start: 1094 mlx5_accel_ipsec_cleanup(dev); 1095 err_ipsec_start: 1096 mlx5_fpga_device_stop(dev); 1097 err_fpga_start: 1098 mlx5_fw_tracer_cleanup(dev->tracer); 1099 err_fw_tracer: 1100 mlx5_eq_table_destroy(dev); 1101 err_eq_table: 1102 mlx5_pagealloc_stop(dev); 1103 mlx5_events_stop(dev); 1104 mlx5_put_uars_page(dev, dev->priv.uar); 1105 return err; 1106 } 1107 1108 static void mlx5_unload(struct mlx5_core_dev *dev) 1109 { 1110 mlx5_ec_cleanup(dev); 1111 mlx5_sriov_detach(dev); 1112 mlx5_cleanup_fs(dev); 1113 mlx5_accel_ipsec_cleanup(dev); 1114 mlx5_accel_tls_cleanup(dev); 1115 mlx5_fpga_device_stop(dev); 1116 mlx5_fw_tracer_cleanup(dev->tracer); 1117 mlx5_eq_table_destroy(dev); 1118 mlx5_pagealloc_stop(dev); 1119 mlx5_events_stop(dev); 1120 mlx5_put_uars_page(dev, dev->priv.uar); 1121 } 1122 1123 static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1124 { 1125 int err = 0; 1126 1127 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1128 mutex_lock(&dev->intf_state_mutex); 1129 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1130 mlx5_core_warn(dev, "interface is up, NOP\n"); 1131 goto out; 1132 } 1133 /* remove any previous indication of internal error */ 1134 dev->state = MLX5_DEVICE_STATE_UP; 1135 1136 err = mlx5_function_setup(dev, boot); 1137 if (err) 1138 goto out; 1139 1140 if (boot) { 1141 err = mlx5_init_once(dev); 1142 if (err) { 1143 mlx5_core_err(dev, "sw objs init failed\n"); 1144 goto function_teardown; 1145 } 1146 } 1147 1148 err = mlx5_load(dev); 1149 if (err) 1150 goto err_load; 1151 1152 if (mlx5_device_registered(dev)) { 1153 mlx5_attach_device(dev); 1154 } else { 1155 err = mlx5_register_device(dev); 1156 if (err) { 1157 mlx5_core_err(dev, "register device failed %d\n", err); 1158 goto err_reg_dev; 1159 } 1160 } 1161 1162 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1163 out: 1164 mutex_unlock(&dev->intf_state_mutex); 1165 1166 return err; 1167 1168 err_reg_dev: 1169 mlx5_unload(dev); 1170 err_load: 1171 if (boot) 1172 mlx5_cleanup_once(dev); 1173 function_teardown: 1174 mlx5_function_teardown(dev, boot); 1175 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1176 mutex_unlock(&dev->intf_state_mutex); 1177 1178 return err; 1179 } 1180 1181 static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1182 { 1183 int err = 0; 1184 1185 if (cleanup) 1186 mlx5_drain_health_recovery(dev); 1187 1188 mutex_lock(&dev->intf_state_mutex); 1189 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1190 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1191 __func__); 1192 if (cleanup) 1193 mlx5_cleanup_once(dev); 1194 goto out; 1195 } 1196 1197 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1198 1199 if (mlx5_device_registered(dev)) 1200 mlx5_detach_device(dev); 1201 1202 mlx5_unload(dev); 1203 1204 if (cleanup) 1205 mlx5_cleanup_once(dev); 1206 1207 mlx5_function_teardown(dev, cleanup); 1208 out: 1209 mutex_unlock(&dev->intf_state_mutex); 1210 return err; 1211 } 1212 1213 static const struct devlink_ops mlx5_devlink_ops = { 1214 #ifdef CONFIG_MLX5_ESWITCH 1215 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, 1216 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, 1217 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, 1218 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, 1219 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, 1220 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, 1221 #endif 1222 }; 1223 1224 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1225 { 1226 struct mlx5_priv *priv = &dev->priv; 1227 int err; 1228 1229 dev->profile = &profile[profile_idx]; 1230 1231 INIT_LIST_HEAD(&priv->ctx_list); 1232 spin_lock_init(&priv->ctx_lock); 1233 mutex_init(&dev->pci_status_mutex); 1234 mutex_init(&dev->intf_state_mutex); 1235 1236 mutex_init(&priv->bfregs.reg_head.lock); 1237 mutex_init(&priv->bfregs.wc_head.lock); 1238 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1239 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1240 1241 mutex_init(&priv->alloc_mutex); 1242 mutex_init(&priv->pgdir_mutex); 1243 INIT_LIST_HEAD(&priv->pgdir_list); 1244 spin_lock_init(&priv->mkey_lock); 1245 1246 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1247 mlx5_debugfs_root); 1248 if (!priv->dbg_root) { 1249 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 1250 return -ENOMEM; 1251 } 1252 1253 err = mlx5_health_init(dev); 1254 if (err) 1255 goto err_health_init; 1256 1257 err = mlx5_pagealloc_init(dev); 1258 if (err) 1259 goto err_pagealloc_init; 1260 1261 return 0; 1262 1263 err_pagealloc_init: 1264 mlx5_health_cleanup(dev); 1265 err_health_init: 1266 debugfs_remove(dev->priv.dbg_root); 1267 1268 return err; 1269 } 1270 1271 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1272 { 1273 mlx5_pagealloc_cleanup(dev); 1274 mlx5_health_cleanup(dev); 1275 debugfs_remove_recursive(dev->priv.dbg_root); 1276 } 1277 1278 #define MLX5_IB_MOD "mlx5_ib" 1279 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1280 { 1281 struct mlx5_core_dev *dev; 1282 struct devlink *devlink; 1283 int err; 1284 1285 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); 1286 if (!devlink) { 1287 dev_err(&pdev->dev, "kzalloc failed\n"); 1288 return -ENOMEM; 1289 } 1290 1291 dev = devlink_priv(devlink); 1292 dev->device = &pdev->dev; 1293 dev->pdev = pdev; 1294 1295 err = mlx5_mdev_init(dev, prof_sel); 1296 if (err) 1297 goto mdev_init_err; 1298 1299 err = mlx5_pci_init(dev, pdev, id); 1300 if (err) { 1301 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1302 err); 1303 goto pci_init_err; 1304 } 1305 1306 err = mlx5_load_one(dev, true); 1307 if (err) { 1308 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 1309 err); 1310 goto err_load_one; 1311 } 1312 1313 request_module_nowait(MLX5_IB_MOD); 1314 1315 err = devlink_register(devlink, &pdev->dev); 1316 if (err) 1317 goto clean_load; 1318 1319 pci_save_state(pdev); 1320 return 0; 1321 1322 clean_load: 1323 mlx5_unload_one(dev, true); 1324 1325 err_load_one: 1326 mlx5_pci_close(dev); 1327 pci_init_err: 1328 mlx5_mdev_uninit(dev); 1329 mdev_init_err: 1330 devlink_free(devlink); 1331 1332 return err; 1333 } 1334 1335 static void remove_one(struct pci_dev *pdev) 1336 { 1337 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1338 struct devlink *devlink = priv_to_devlink(dev); 1339 1340 devlink_unregister(devlink); 1341 mlx5_unregister_device(dev); 1342 1343 if (mlx5_unload_one(dev, true)) { 1344 mlx5_core_err(dev, "mlx5_unload_one failed\n"); 1345 mlx5_health_flush(dev); 1346 return; 1347 } 1348 1349 mlx5_pci_close(dev); 1350 mlx5_mdev_uninit(dev); 1351 devlink_free(devlink); 1352 } 1353 1354 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1355 pci_channel_state_t state) 1356 { 1357 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1358 1359 mlx5_core_info(dev, "%s was called\n", __func__); 1360 1361 mlx5_enter_error_state(dev, false); 1362 mlx5_unload_one(dev, false); 1363 /* In case of kernel call drain the health wq */ 1364 if (state) { 1365 mlx5_drain_health_wq(dev); 1366 mlx5_pci_disable_device(dev); 1367 } 1368 1369 return state == pci_channel_io_perm_failure ? 1370 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1371 } 1372 1373 /* wait for the device to show vital signs by waiting 1374 * for the health counter to start counting. 1375 */ 1376 static int wait_vital(struct pci_dev *pdev) 1377 { 1378 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1379 struct mlx5_core_health *health = &dev->priv.health; 1380 const int niter = 100; 1381 u32 last_count = 0; 1382 u32 count; 1383 int i; 1384 1385 for (i = 0; i < niter; i++) { 1386 count = ioread32be(health->health_counter); 1387 if (count && count != 0xffffffff) { 1388 if (last_count && last_count != count) { 1389 mlx5_core_info(dev, 1390 "wait vital counter value 0x%x after %d iterations\n", 1391 count, i); 1392 return 0; 1393 } 1394 last_count = count; 1395 } 1396 msleep(50); 1397 } 1398 1399 return -ETIMEDOUT; 1400 } 1401 1402 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1403 { 1404 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1405 int err; 1406 1407 mlx5_core_info(dev, "%s was called\n", __func__); 1408 1409 err = mlx5_pci_enable_device(dev); 1410 if (err) { 1411 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1412 __func__, err); 1413 return PCI_ERS_RESULT_DISCONNECT; 1414 } 1415 1416 pci_set_master(pdev); 1417 pci_restore_state(pdev); 1418 pci_save_state(pdev); 1419 1420 if (wait_vital(pdev)) { 1421 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1422 return PCI_ERS_RESULT_DISCONNECT; 1423 } 1424 1425 return PCI_ERS_RESULT_RECOVERED; 1426 } 1427 1428 static void mlx5_pci_resume(struct pci_dev *pdev) 1429 { 1430 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1431 int err; 1432 1433 mlx5_core_info(dev, "%s was called\n", __func__); 1434 1435 err = mlx5_load_one(dev, false); 1436 if (err) 1437 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1438 __func__, err); 1439 else 1440 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1441 } 1442 1443 static const struct pci_error_handlers mlx5_err_handler = { 1444 .error_detected = mlx5_pci_err_detected, 1445 .slot_reset = mlx5_pci_slot_reset, 1446 .resume = mlx5_pci_resume 1447 }; 1448 1449 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1450 { 1451 bool fast_teardown = false, force_teardown = false; 1452 int ret = 1; 1453 1454 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1455 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1456 1457 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1458 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1459 1460 if (!fast_teardown && !force_teardown) 1461 return -EOPNOTSUPP; 1462 1463 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1464 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1465 return -EAGAIN; 1466 } 1467 1468 /* Panic tear down fw command will stop the PCI bus communication 1469 * with the HCA, so the health polll is no longer needed. 1470 */ 1471 mlx5_drain_health_wq(dev); 1472 mlx5_stop_health_poll(dev, false); 1473 1474 ret = mlx5_cmd_fast_teardown_hca(dev); 1475 if (!ret) 1476 goto succeed; 1477 1478 ret = mlx5_cmd_force_teardown_hca(dev); 1479 if (!ret) 1480 goto succeed; 1481 1482 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1483 mlx5_start_health_poll(dev); 1484 return ret; 1485 1486 succeed: 1487 mlx5_enter_error_state(dev, true); 1488 1489 /* Some platforms requiring freeing the IRQ's in the shutdown 1490 * flow. If they aren't freed they can't be allocated after 1491 * kexec. There is no need to cleanup the mlx5_core software 1492 * contexts. 1493 */ 1494 mlx5_core_eq_free_irqs(dev); 1495 1496 return 0; 1497 } 1498 1499 static void shutdown(struct pci_dev *pdev) 1500 { 1501 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1502 int err; 1503 1504 mlx5_core_info(dev, "Shutdown was called\n"); 1505 err = mlx5_try_fast_unload(dev); 1506 if (err) 1507 mlx5_unload_one(dev, false); 1508 mlx5_pci_disable_device(dev); 1509 } 1510 1511 static const struct pci_device_id mlx5_core_pci_table[] = { 1512 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1513 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1514 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1515 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1516 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1517 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1518 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1519 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1520 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1521 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1522 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1523 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1524 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1525 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1526 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1527 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1528 { 0, } 1529 }; 1530 1531 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1532 1533 void mlx5_disable_device(struct mlx5_core_dev *dev) 1534 { 1535 mlx5_pci_err_detected(dev->pdev, 0); 1536 } 1537 1538 void mlx5_recover_device(struct mlx5_core_dev *dev) 1539 { 1540 mlx5_pci_disable_device(dev); 1541 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1542 mlx5_pci_resume(dev->pdev); 1543 } 1544 1545 static struct pci_driver mlx5_core_driver = { 1546 .name = DRIVER_NAME, 1547 .id_table = mlx5_core_pci_table, 1548 .probe = init_one, 1549 .remove = remove_one, 1550 .shutdown = shutdown, 1551 .err_handler = &mlx5_err_handler, 1552 .sriov_configure = mlx5_core_sriov_configure, 1553 }; 1554 1555 static void mlx5_core_verify_params(void) 1556 { 1557 if (prof_sel >= ARRAY_SIZE(profile)) { 1558 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1559 prof_sel, 1560 ARRAY_SIZE(profile) - 1, 1561 MLX5_DEFAULT_PROF); 1562 prof_sel = MLX5_DEFAULT_PROF; 1563 } 1564 } 1565 1566 static int __init init(void) 1567 { 1568 int err; 1569 1570 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1571 1572 mlx5_core_verify_params(); 1573 mlx5_fpga_ipsec_build_fs_cmds(); 1574 mlx5_register_debugfs(); 1575 1576 err = pci_register_driver(&mlx5_core_driver); 1577 if (err) 1578 goto err_debug; 1579 1580 #ifdef CONFIG_MLX5_CORE_EN 1581 mlx5e_init(); 1582 #endif 1583 1584 return 0; 1585 1586 err_debug: 1587 mlx5_unregister_debugfs(); 1588 return err; 1589 } 1590 1591 static void __exit cleanup(void) 1592 { 1593 #ifdef CONFIG_MLX5_CORE_EN 1594 mlx5e_cleanup(); 1595 #endif 1596 pci_unregister_driver(&mlx5_core_driver); 1597 mlx5_unregister_debugfs(); 1598 } 1599 1600 module_init(init); 1601 module_exit(cleanup); 1602