1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "fpga/core.h" 64 #include "fpga/ipsec.h" 65 #include "accel/ipsec.h" 66 #include "accel/tls.h" 67 #include "lib/clock.h" 68 #include "lib/vxlan.h" 69 #include "lib/geneve.h" 70 #include "lib/devcom.h" 71 #include "lib/pci_vsc.h" 72 #include "diag/fw_tracer.h" 73 #include "ecpf.h" 74 #include "lib/hv_vhca.h" 75 #include "diag/rsc_dump.h" 76 77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79 MODULE_LICENSE("Dual BSD/GPL"); 80 81 unsigned int mlx5_core_debug_mask; 82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84 85 #define MLX5_DEFAULT_PROF 2 86 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 87 module_param_named(prof_sel, prof_sel, uint, 0444); 88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 89 90 static u32 sw_owner_id[4]; 91 92 enum { 93 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 94 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 95 }; 96 97 static struct mlx5_profile profile[] = { 98 [0] = { 99 .mask = 0, 100 }, 101 [1] = { 102 .mask = MLX5_PROF_MASK_QP_SIZE, 103 .log_max_qp = 12, 104 }, 105 [2] = { 106 .mask = MLX5_PROF_MASK_QP_SIZE | 107 MLX5_PROF_MASK_MR_CACHE, 108 .log_max_qp = 18, 109 .mr_cache[0] = { 110 .size = 500, 111 .limit = 250 112 }, 113 .mr_cache[1] = { 114 .size = 500, 115 .limit = 250 116 }, 117 .mr_cache[2] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[3] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[4] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[5] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[6] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[7] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[8] = { 142 .size = 500, 143 .limit = 250 144 }, 145 .mr_cache[9] = { 146 .size = 500, 147 .limit = 250 148 }, 149 .mr_cache[10] = { 150 .size = 500, 151 .limit = 250 152 }, 153 .mr_cache[11] = { 154 .size = 500, 155 .limit = 250 156 }, 157 .mr_cache[12] = { 158 .size = 64, 159 .limit = 32 160 }, 161 .mr_cache[13] = { 162 .size = 32, 163 .limit = 16 164 }, 165 .mr_cache[14] = { 166 .size = 16, 167 .limit = 8 168 }, 169 .mr_cache[15] = { 170 .size = 8, 171 .limit = 4 172 }, 173 }, 174 }; 175 176 #define FW_INIT_TIMEOUT_MILI 2000 177 #define FW_INIT_WAIT_MS 2 178 #define FW_PRE_INIT_TIMEOUT_MILI 120000 179 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 180 181 static int fw_initializing(struct mlx5_core_dev *dev) 182 { 183 return ioread32be(&dev->iseg->initializing) >> 31; 184 } 185 186 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 187 u32 warn_time_mili) 188 { 189 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 191 int err = 0; 192 193 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 194 195 while (fw_initializing(dev)) { 196 if (time_after(jiffies, end)) { 197 err = -EBUSY; 198 break; 199 } 200 if (warn_time_mili && time_after(jiffies, warn)) { 201 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 202 jiffies_to_msecs(end - warn) / 1000); 203 warn = jiffies + msecs_to_jiffies(warn_time_mili); 204 } 205 msleep(FW_INIT_WAIT_MS); 206 } 207 208 return err; 209 } 210 211 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 212 { 213 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 214 driver_version); 215 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 216 int remaining_size = driver_ver_sz; 217 char *string; 218 219 if (!MLX5_CAP_GEN(dev, driver_version)) 220 return; 221 222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 223 224 strncpy(string, "Linux", remaining_size); 225 226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 227 strncat(string, ",", remaining_size); 228 229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 230 strncat(string, KBUILD_MODNAME, remaining_size); 231 232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 233 strncat(string, ",", remaining_size); 234 235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 236 237 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 238 (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff), 239 (u16)(LINUX_VERSION_CODE & 0xffff)); 240 241 /*Send the command*/ 242 MLX5_SET(set_driver_version_in, in, opcode, 243 MLX5_CMD_OP_SET_DRIVER_VERSION); 244 245 mlx5_cmd_exec_in(dev, set_driver_version, in); 246 } 247 248 static int set_dma_caps(struct pci_dev *pdev) 249 { 250 int err; 251 252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 253 if (err) { 254 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 255 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 256 if (err) { 257 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 258 return err; 259 } 260 } 261 262 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 263 if (err) { 264 dev_warn(&pdev->dev, 265 "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 266 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 267 if (err) { 268 dev_err(&pdev->dev, 269 "Can't set consistent PCI DMA mask, aborting\n"); 270 return err; 271 } 272 } 273 274 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 275 return err; 276 } 277 278 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 279 { 280 struct pci_dev *pdev = dev->pdev; 281 int err = 0; 282 283 mutex_lock(&dev->pci_status_mutex); 284 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 285 err = pci_enable_device(pdev); 286 if (!err) 287 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 288 } 289 mutex_unlock(&dev->pci_status_mutex); 290 291 return err; 292 } 293 294 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 295 { 296 struct pci_dev *pdev = dev->pdev; 297 298 mutex_lock(&dev->pci_status_mutex); 299 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 300 pci_disable_device(pdev); 301 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 302 } 303 mutex_unlock(&dev->pci_status_mutex); 304 } 305 306 static int request_bar(struct pci_dev *pdev) 307 { 308 int err = 0; 309 310 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 311 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 312 return -ENODEV; 313 } 314 315 err = pci_request_regions(pdev, KBUILD_MODNAME); 316 if (err) 317 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 318 319 return err; 320 } 321 322 static void release_bar(struct pci_dev *pdev) 323 { 324 pci_release_regions(pdev); 325 } 326 327 struct mlx5_reg_host_endianness { 328 u8 he; 329 u8 rsvd[15]; 330 }; 331 332 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 333 334 enum { 335 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 336 MLX5_DEV_CAP_FLAG_DCT, 337 }; 338 339 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 340 { 341 switch (size) { 342 case 128: 343 return 0; 344 case 256: 345 return 1; 346 case 512: 347 return 2; 348 case 1024: 349 return 3; 350 case 2048: 351 return 4; 352 case 4096: 353 return 5; 354 default: 355 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 356 return 0; 357 } 358 } 359 360 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 361 enum mlx5_cap_type cap_type, 362 enum mlx5_cap_mode cap_mode) 363 { 364 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 365 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 366 void *out, *hca_caps; 367 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 368 int err; 369 370 memset(in, 0, sizeof(in)); 371 out = kzalloc(out_sz, GFP_KERNEL); 372 if (!out) 373 return -ENOMEM; 374 375 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 376 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 377 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 378 if (err) { 379 mlx5_core_warn(dev, 380 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 381 cap_type, cap_mode, err); 382 goto query_ex; 383 } 384 385 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 386 387 switch (cap_mode) { 388 case HCA_CAP_OPMOD_GET_MAX: 389 memcpy(dev->caps.hca_max[cap_type], hca_caps, 390 MLX5_UN_SZ_BYTES(hca_cap_union)); 391 break; 392 case HCA_CAP_OPMOD_GET_CUR: 393 memcpy(dev->caps.hca_cur[cap_type], hca_caps, 394 MLX5_UN_SZ_BYTES(hca_cap_union)); 395 break; 396 default: 397 mlx5_core_warn(dev, 398 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 399 cap_type, cap_mode); 400 err = -EINVAL; 401 break; 402 } 403 query_ex: 404 kfree(out); 405 return err; 406 } 407 408 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 409 { 410 int ret; 411 412 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 413 if (ret) 414 return ret; 415 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 416 } 417 418 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 419 { 420 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 421 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 422 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 423 } 424 425 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 426 { 427 void *set_hca_cap; 428 int req_endianness; 429 int err; 430 431 if (!MLX5_CAP_GEN(dev, atomic)) 432 return 0; 433 434 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 435 if (err) 436 return err; 437 438 req_endianness = 439 MLX5_CAP_ATOMIC(dev, 440 supported_atomic_req_8B_endianness_mode_1); 441 442 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 443 return 0; 444 445 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 446 447 /* Set requestor to host endianness */ 448 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 450 451 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 452 } 453 454 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 455 { 456 void *set_hca_cap; 457 bool do_set = false; 458 int err; 459 460 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 461 !MLX5_CAP_GEN(dev, pg)) 462 return 0; 463 464 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 465 if (err) 466 return err; 467 468 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 469 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 470 MLX5_ST_SZ_BYTES(odp_cap)); 471 472 #define ODP_CAP_SET_MAX(dev, field) \ 473 do { \ 474 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 475 if (_res) { \ 476 do_set = true; \ 477 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 478 } \ 479 } while (0) 480 481 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 482 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 489 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 490 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 491 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 492 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 493 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 494 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 495 496 if (!do_set) 497 return 0; 498 499 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 500 } 501 502 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 503 { 504 struct mlx5_profile *prof = dev->profile; 505 void *set_hca_cap; 506 int err; 507 508 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 509 if (err) 510 return err; 511 512 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 513 capability); 514 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 515 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 516 517 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 518 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 519 128); 520 /* we limit the size of the pkey table to 128 entries for now */ 521 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 522 to_fw_pkey_sz(dev, 128)); 523 524 /* Check log_max_qp from HCA caps to set in current profile */ 525 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 526 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 527 profile[prof_sel].log_max_qp, 528 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 529 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 530 } 531 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 532 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 533 prof->log_max_qp); 534 535 /* disable cmdif checksum */ 536 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 537 538 /* Enable 4K UAR only when HCA supports it and page size is bigger 539 * than 4K. 540 */ 541 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 542 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 543 544 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 545 546 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 547 MLX5_SET(cmd_hca_cap, 548 set_hca_cap, 549 cache_line_128byte, 550 cache_line_size() >= 128 ? 1 : 0); 551 552 if (MLX5_CAP_GEN_MAX(dev, dct)) 553 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 554 555 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 556 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 557 558 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 559 MLX5_SET(cmd_hca_cap, 560 set_hca_cap, 561 num_vhca_ports, 562 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 563 564 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 565 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 566 567 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 568 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 569 570 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 571 } 572 573 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 574 { 575 void *set_hca_cap; 576 int err; 577 578 if (!MLX5_CAP_GEN(dev, roce)) 579 return 0; 580 581 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 582 if (err) 583 return err; 584 585 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 586 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 587 return 0; 588 589 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 590 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 591 MLX5_ST_SZ_BYTES(roce_cap)); 592 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 593 594 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 595 return err; 596 } 597 598 static int set_hca_cap(struct mlx5_core_dev *dev) 599 { 600 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 601 void *set_ctx; 602 int err; 603 604 set_ctx = kzalloc(set_sz, GFP_KERNEL); 605 if (!set_ctx) 606 return -ENOMEM; 607 608 err = handle_hca_cap(dev, set_ctx); 609 if (err) { 610 mlx5_core_err(dev, "handle_hca_cap failed\n"); 611 goto out; 612 } 613 614 memset(set_ctx, 0, set_sz); 615 err = handle_hca_cap_atomic(dev, set_ctx); 616 if (err) { 617 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 618 goto out; 619 } 620 621 memset(set_ctx, 0, set_sz); 622 err = handle_hca_cap_odp(dev, set_ctx); 623 if (err) { 624 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 625 goto out; 626 } 627 628 memset(set_ctx, 0, set_sz); 629 err = handle_hca_cap_roce(dev, set_ctx); 630 if (err) { 631 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 632 goto out; 633 } 634 635 out: 636 kfree(set_ctx); 637 return err; 638 } 639 640 static int set_hca_ctrl(struct mlx5_core_dev *dev) 641 { 642 struct mlx5_reg_host_endianness he_in; 643 struct mlx5_reg_host_endianness he_out; 644 int err; 645 646 if (!mlx5_core_is_pf(dev)) 647 return 0; 648 649 memset(&he_in, 0, sizeof(he_in)); 650 he_in.he = MLX5_SET_HOST_ENDIANNESS; 651 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 652 &he_out, sizeof(he_out), 653 MLX5_REG_HOST_ENDIANNESS, 0, 1); 654 return err; 655 } 656 657 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 658 { 659 int ret = 0; 660 661 /* Disable local_lb by default */ 662 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 663 ret = mlx5_nic_vport_update_local_lb(dev, false); 664 665 return ret; 666 } 667 668 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 669 { 670 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 671 672 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 673 MLX5_SET(enable_hca_in, in, function_id, func_id); 674 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 675 dev->caps.embedded_cpu); 676 return mlx5_cmd_exec_in(dev, enable_hca, in); 677 } 678 679 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 680 { 681 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 682 683 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 684 MLX5_SET(disable_hca_in, in, function_id, func_id); 685 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 686 dev->caps.embedded_cpu); 687 return mlx5_cmd_exec_in(dev, disable_hca, in); 688 } 689 690 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 691 { 692 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 693 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 694 u32 sup_issi; 695 int err; 696 697 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 698 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 699 if (err) { 700 u32 syndrome; 701 u8 status; 702 703 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 704 if (!status || syndrome == MLX5_DRIVER_SYND) { 705 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 706 err, status, syndrome); 707 return err; 708 } 709 710 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 711 dev->issi = 0; 712 return 0; 713 } 714 715 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 716 717 if (sup_issi & (1 << 1)) { 718 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 719 720 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 721 MLX5_SET(set_issi_in, set_in, current_issi, 1); 722 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 723 if (err) { 724 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 725 err); 726 return err; 727 } 728 729 dev->issi = 1; 730 731 return 0; 732 } else if (sup_issi & (1 << 0) || !sup_issi) { 733 return 0; 734 } 735 736 return -EOPNOTSUPP; 737 } 738 739 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 740 const struct pci_device_id *id) 741 { 742 struct mlx5_priv *priv = &dev->priv; 743 int err = 0; 744 745 mutex_init(&dev->pci_status_mutex); 746 pci_set_drvdata(dev->pdev, dev); 747 748 dev->bar_addr = pci_resource_start(pdev, 0); 749 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 750 751 err = mlx5_pci_enable_device(dev); 752 if (err) { 753 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 754 return err; 755 } 756 757 err = request_bar(pdev); 758 if (err) { 759 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 760 goto err_disable; 761 } 762 763 pci_set_master(pdev); 764 765 err = set_dma_caps(pdev); 766 if (err) { 767 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 768 goto err_clr_master; 769 } 770 771 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 774 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 775 776 dev->iseg_base = dev->bar_addr; 777 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 778 if (!dev->iseg) { 779 err = -ENOMEM; 780 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 781 goto err_clr_master; 782 } 783 784 mlx5_pci_vsc_init(dev); 785 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 786 return 0; 787 788 err_clr_master: 789 pci_clear_master(dev->pdev); 790 release_bar(dev->pdev); 791 err_disable: 792 mlx5_pci_disable_device(dev); 793 return err; 794 } 795 796 static void mlx5_pci_close(struct mlx5_core_dev *dev) 797 { 798 /* health work might still be active, and it needs pci bar in 799 * order to know the NIC state. Therefore, drain the health WQ 800 * before removing the pci bars 801 */ 802 mlx5_drain_health_wq(dev); 803 iounmap(dev->iseg); 804 pci_clear_master(dev->pdev); 805 release_bar(dev->pdev); 806 mlx5_pci_disable_device(dev); 807 } 808 809 static int mlx5_init_once(struct mlx5_core_dev *dev) 810 { 811 int err; 812 813 dev->priv.devcom = mlx5_devcom_register_device(dev); 814 if (IS_ERR(dev->priv.devcom)) 815 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 816 dev->priv.devcom); 817 818 err = mlx5_query_board_id(dev); 819 if (err) { 820 mlx5_core_err(dev, "query board id failed\n"); 821 goto err_devcom; 822 } 823 824 err = mlx5_irq_table_init(dev); 825 if (err) { 826 mlx5_core_err(dev, "failed to initialize irq table\n"); 827 goto err_devcom; 828 } 829 830 err = mlx5_eq_table_init(dev); 831 if (err) { 832 mlx5_core_err(dev, "failed to initialize eq\n"); 833 goto err_irq_cleanup; 834 } 835 836 err = mlx5_events_init(dev); 837 if (err) { 838 mlx5_core_err(dev, "failed to initialize events\n"); 839 goto err_eq_cleanup; 840 } 841 842 err = mlx5_fw_reset_init(dev); 843 if (err) { 844 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 845 goto err_events_cleanup; 846 } 847 848 mlx5_cq_debugfs_init(dev); 849 850 mlx5_init_reserved_gids(dev); 851 852 mlx5_init_clock(dev); 853 854 dev->vxlan = mlx5_vxlan_create(dev); 855 dev->geneve = mlx5_geneve_create(dev); 856 857 err = mlx5_init_rl_table(dev); 858 if (err) { 859 mlx5_core_err(dev, "Failed to init rate limiting\n"); 860 goto err_tables_cleanup; 861 } 862 863 err = mlx5_mpfs_init(dev); 864 if (err) { 865 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 866 goto err_rl_cleanup; 867 } 868 869 err = mlx5_sriov_init(dev); 870 if (err) { 871 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 872 goto err_mpfs_cleanup; 873 } 874 875 err = mlx5_eswitch_init(dev); 876 if (err) { 877 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 878 goto err_sriov_cleanup; 879 } 880 881 err = mlx5_fpga_init(dev); 882 if (err) { 883 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 884 goto err_eswitch_cleanup; 885 } 886 887 dev->dm = mlx5_dm_create(dev); 888 if (IS_ERR(dev->dm)) 889 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 890 891 dev->tracer = mlx5_fw_tracer_create(dev); 892 dev->hv_vhca = mlx5_hv_vhca_create(dev); 893 dev->rsc_dump = mlx5_rsc_dump_create(dev); 894 895 return 0; 896 897 err_eswitch_cleanup: 898 mlx5_eswitch_cleanup(dev->priv.eswitch); 899 err_sriov_cleanup: 900 mlx5_sriov_cleanup(dev); 901 err_mpfs_cleanup: 902 mlx5_mpfs_cleanup(dev); 903 err_rl_cleanup: 904 mlx5_cleanup_rl_table(dev); 905 err_tables_cleanup: 906 mlx5_geneve_destroy(dev->geneve); 907 mlx5_vxlan_destroy(dev->vxlan); 908 mlx5_cq_debugfs_cleanup(dev); 909 mlx5_fw_reset_cleanup(dev); 910 err_events_cleanup: 911 mlx5_events_cleanup(dev); 912 err_eq_cleanup: 913 mlx5_eq_table_cleanup(dev); 914 err_irq_cleanup: 915 mlx5_irq_table_cleanup(dev); 916 err_devcom: 917 mlx5_devcom_unregister_device(dev->priv.devcom); 918 919 return err; 920 } 921 922 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 923 { 924 mlx5_rsc_dump_destroy(dev); 925 mlx5_hv_vhca_destroy(dev->hv_vhca); 926 mlx5_fw_tracer_destroy(dev->tracer); 927 mlx5_dm_cleanup(dev); 928 mlx5_fpga_cleanup(dev); 929 mlx5_eswitch_cleanup(dev->priv.eswitch); 930 mlx5_sriov_cleanup(dev); 931 mlx5_mpfs_cleanup(dev); 932 mlx5_cleanup_rl_table(dev); 933 mlx5_geneve_destroy(dev->geneve); 934 mlx5_vxlan_destroy(dev->vxlan); 935 mlx5_cleanup_clock(dev); 936 mlx5_cleanup_reserved_gids(dev); 937 mlx5_cq_debugfs_cleanup(dev); 938 mlx5_fw_reset_cleanup(dev); 939 mlx5_events_cleanup(dev); 940 mlx5_eq_table_cleanup(dev); 941 mlx5_irq_table_cleanup(dev); 942 mlx5_devcom_unregister_device(dev->priv.devcom); 943 } 944 945 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 946 { 947 int err; 948 949 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 950 fw_rev_min(dev), fw_rev_sub(dev)); 951 952 /* Only PFs hold the relevant PCIe information for this query */ 953 if (mlx5_core_is_pf(dev)) 954 pcie_print_link_status(dev->pdev); 955 956 /* wait for firmware to accept initialization segments configurations 957 */ 958 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 959 if (err) { 960 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 961 FW_PRE_INIT_TIMEOUT_MILI); 962 return err; 963 } 964 965 err = mlx5_cmd_init(dev); 966 if (err) { 967 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 968 return err; 969 } 970 971 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 972 if (err) { 973 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 974 FW_INIT_TIMEOUT_MILI); 975 goto err_cmd_cleanup; 976 } 977 978 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 979 980 err = mlx5_core_enable_hca(dev, 0); 981 if (err) { 982 mlx5_core_err(dev, "enable hca failed\n"); 983 goto err_cmd_cleanup; 984 } 985 986 err = mlx5_core_set_issi(dev); 987 if (err) { 988 mlx5_core_err(dev, "failed to set issi\n"); 989 goto err_disable_hca; 990 } 991 992 err = mlx5_satisfy_startup_pages(dev, 1); 993 if (err) { 994 mlx5_core_err(dev, "failed to allocate boot pages\n"); 995 goto err_disable_hca; 996 } 997 998 err = set_hca_ctrl(dev); 999 if (err) { 1000 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1001 goto reclaim_boot_pages; 1002 } 1003 1004 err = set_hca_cap(dev); 1005 if (err) { 1006 mlx5_core_err(dev, "set_hca_cap failed\n"); 1007 goto reclaim_boot_pages; 1008 } 1009 1010 err = mlx5_satisfy_startup_pages(dev, 0); 1011 if (err) { 1012 mlx5_core_err(dev, "failed to allocate init pages\n"); 1013 goto reclaim_boot_pages; 1014 } 1015 1016 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1017 if (err) { 1018 mlx5_core_err(dev, "init hca failed\n"); 1019 goto reclaim_boot_pages; 1020 } 1021 1022 mlx5_set_driver_version(dev); 1023 1024 mlx5_start_health_poll(dev); 1025 1026 err = mlx5_query_hca_caps(dev); 1027 if (err) { 1028 mlx5_core_err(dev, "query hca failed\n"); 1029 goto stop_health; 1030 } 1031 1032 return 0; 1033 1034 stop_health: 1035 mlx5_stop_health_poll(dev, boot); 1036 reclaim_boot_pages: 1037 mlx5_reclaim_startup_pages(dev); 1038 err_disable_hca: 1039 mlx5_core_disable_hca(dev, 0); 1040 err_cmd_cleanup: 1041 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1042 mlx5_cmd_cleanup(dev); 1043 1044 return err; 1045 } 1046 1047 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1048 { 1049 int err; 1050 1051 mlx5_stop_health_poll(dev, boot); 1052 err = mlx5_cmd_teardown_hca(dev); 1053 if (err) { 1054 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1055 return err; 1056 } 1057 mlx5_reclaim_startup_pages(dev); 1058 mlx5_core_disable_hca(dev, 0); 1059 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1060 mlx5_cmd_cleanup(dev); 1061 1062 return 0; 1063 } 1064 1065 static int mlx5_load(struct mlx5_core_dev *dev) 1066 { 1067 int err; 1068 1069 dev->priv.uar = mlx5_get_uars_page(dev); 1070 if (IS_ERR(dev->priv.uar)) { 1071 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1072 err = PTR_ERR(dev->priv.uar); 1073 return err; 1074 } 1075 1076 mlx5_events_start(dev); 1077 mlx5_pagealloc_start(dev); 1078 1079 err = mlx5_irq_table_create(dev); 1080 if (err) { 1081 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1082 goto err_irq_table; 1083 } 1084 1085 err = mlx5_eq_table_create(dev); 1086 if (err) { 1087 mlx5_core_err(dev, "Failed to create EQs\n"); 1088 goto err_eq_table; 1089 } 1090 1091 err = mlx5_fw_tracer_init(dev->tracer); 1092 if (err) { 1093 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1094 goto err_fw_tracer; 1095 } 1096 1097 mlx5_fw_reset_events_start(dev); 1098 mlx5_hv_vhca_init(dev->hv_vhca); 1099 1100 err = mlx5_rsc_dump_init(dev); 1101 if (err) { 1102 mlx5_core_err(dev, "Failed to init Resource dump\n"); 1103 goto err_rsc_dump; 1104 } 1105 1106 err = mlx5_fpga_device_start(dev); 1107 if (err) { 1108 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1109 goto err_fpga_start; 1110 } 1111 1112 mlx5_accel_ipsec_init(dev); 1113 1114 err = mlx5_accel_tls_init(dev); 1115 if (err) { 1116 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1117 goto err_tls_start; 1118 } 1119 1120 err = mlx5_init_fs(dev); 1121 if (err) { 1122 mlx5_core_err(dev, "Failed to init flow steering\n"); 1123 goto err_fs; 1124 } 1125 1126 err = mlx5_core_set_hca_defaults(dev); 1127 if (err) { 1128 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1129 goto err_sriov; 1130 } 1131 1132 err = mlx5_ec_init(dev); 1133 if (err) { 1134 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1135 goto err_ec; 1136 } 1137 1138 err = mlx5_sriov_attach(dev); 1139 if (err) { 1140 mlx5_core_err(dev, "sriov init failed %d\n", err); 1141 goto err_sriov; 1142 } 1143 1144 return 0; 1145 1146 err_sriov: 1147 mlx5_ec_cleanup(dev); 1148 err_ec: 1149 mlx5_cleanup_fs(dev); 1150 err_fs: 1151 mlx5_accel_tls_cleanup(dev); 1152 err_tls_start: 1153 mlx5_accel_ipsec_cleanup(dev); 1154 mlx5_fpga_device_stop(dev); 1155 err_fpga_start: 1156 mlx5_rsc_dump_cleanup(dev); 1157 err_rsc_dump: 1158 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1159 mlx5_fw_reset_events_stop(dev); 1160 mlx5_fw_tracer_cleanup(dev->tracer); 1161 err_fw_tracer: 1162 mlx5_eq_table_destroy(dev); 1163 err_eq_table: 1164 mlx5_irq_table_destroy(dev); 1165 err_irq_table: 1166 mlx5_pagealloc_stop(dev); 1167 mlx5_events_stop(dev); 1168 mlx5_put_uars_page(dev, dev->priv.uar); 1169 return err; 1170 } 1171 1172 static void mlx5_unload(struct mlx5_core_dev *dev) 1173 { 1174 mlx5_sriov_detach(dev); 1175 mlx5_ec_cleanup(dev); 1176 mlx5_cleanup_fs(dev); 1177 mlx5_accel_ipsec_cleanup(dev); 1178 mlx5_accel_tls_cleanup(dev); 1179 mlx5_fpga_device_stop(dev); 1180 mlx5_rsc_dump_cleanup(dev); 1181 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1182 mlx5_fw_reset_events_stop(dev); 1183 mlx5_fw_tracer_cleanup(dev->tracer); 1184 mlx5_eq_table_destroy(dev); 1185 mlx5_irq_table_destroy(dev); 1186 mlx5_pagealloc_stop(dev); 1187 mlx5_events_stop(dev); 1188 mlx5_put_uars_page(dev, dev->priv.uar); 1189 } 1190 1191 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1192 { 1193 int err = 0; 1194 1195 mutex_lock(&dev->intf_state_mutex); 1196 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1197 mlx5_core_warn(dev, "interface is up, NOP\n"); 1198 goto out; 1199 } 1200 /* remove any previous indication of internal error */ 1201 dev->state = MLX5_DEVICE_STATE_UP; 1202 1203 err = mlx5_function_setup(dev, boot); 1204 if (err) 1205 goto err_function; 1206 1207 if (boot) { 1208 err = mlx5_init_once(dev); 1209 if (err) { 1210 mlx5_core_err(dev, "sw objs init failed\n"); 1211 goto function_teardown; 1212 } 1213 } 1214 1215 err = mlx5_load(dev); 1216 if (err) 1217 goto err_load; 1218 1219 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1220 1221 if (boot) { 1222 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1223 if (err) 1224 goto err_devlink_reg; 1225 1226 err = mlx5_register_device(dev); 1227 } else { 1228 err = mlx5_attach_device(dev); 1229 } 1230 1231 if (err) 1232 goto err_register; 1233 1234 mutex_unlock(&dev->intf_state_mutex); 1235 return 0; 1236 1237 err_register: 1238 if (boot) 1239 mlx5_devlink_unregister(priv_to_devlink(dev)); 1240 err_devlink_reg: 1241 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1242 mlx5_unload(dev); 1243 err_load: 1244 if (boot) 1245 mlx5_cleanup_once(dev); 1246 function_teardown: 1247 mlx5_function_teardown(dev, boot); 1248 err_function: 1249 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1250 out: 1251 mutex_unlock(&dev->intf_state_mutex); 1252 return err; 1253 } 1254 1255 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1256 { 1257 mutex_lock(&dev->intf_state_mutex); 1258 1259 if (cleanup) { 1260 mlx5_unregister_device(dev); 1261 mlx5_devlink_unregister(priv_to_devlink(dev)); 1262 } else { 1263 mlx5_detach_device(dev); 1264 } 1265 1266 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1267 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1268 __func__); 1269 if (cleanup) 1270 mlx5_cleanup_once(dev); 1271 goto out; 1272 } 1273 1274 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1275 1276 mlx5_unload(dev); 1277 1278 if (cleanup) 1279 mlx5_cleanup_once(dev); 1280 1281 mlx5_function_teardown(dev, cleanup); 1282 out: 1283 mutex_unlock(&dev->intf_state_mutex); 1284 } 1285 1286 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1287 { 1288 struct mlx5_priv *priv = &dev->priv; 1289 int err; 1290 1291 dev->profile = &profile[profile_idx]; 1292 1293 INIT_LIST_HEAD(&priv->ctx_list); 1294 spin_lock_init(&priv->ctx_lock); 1295 mutex_init(&dev->intf_state_mutex); 1296 1297 mutex_init(&priv->bfregs.reg_head.lock); 1298 mutex_init(&priv->bfregs.wc_head.lock); 1299 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1300 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1301 1302 mutex_init(&priv->alloc_mutex); 1303 mutex_init(&priv->pgdir_mutex); 1304 INIT_LIST_HEAD(&priv->pgdir_list); 1305 1306 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1307 mlx5_debugfs_root); 1308 err = mlx5_health_init(dev); 1309 if (err) 1310 goto err_health_init; 1311 1312 err = mlx5_pagealloc_init(dev); 1313 if (err) 1314 goto err_pagealloc_init; 1315 1316 err = mlx5_adev_init(dev); 1317 if (err) 1318 goto err_adev_init; 1319 1320 return 0; 1321 1322 err_adev_init: 1323 mlx5_pagealloc_cleanup(dev); 1324 err_pagealloc_init: 1325 mlx5_health_cleanup(dev); 1326 err_health_init: 1327 debugfs_remove(dev->priv.dbg_root); 1328 mutex_destroy(&priv->pgdir_mutex); 1329 mutex_destroy(&priv->alloc_mutex); 1330 mutex_destroy(&priv->bfregs.wc_head.lock); 1331 mutex_destroy(&priv->bfregs.reg_head.lock); 1332 mutex_destroy(&dev->intf_state_mutex); 1333 return err; 1334 } 1335 1336 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1337 { 1338 struct mlx5_priv *priv = &dev->priv; 1339 1340 mlx5_adev_cleanup(dev); 1341 mlx5_pagealloc_cleanup(dev); 1342 mlx5_health_cleanup(dev); 1343 debugfs_remove_recursive(dev->priv.dbg_root); 1344 mutex_destroy(&priv->pgdir_mutex); 1345 mutex_destroy(&priv->alloc_mutex); 1346 mutex_destroy(&priv->bfregs.wc_head.lock); 1347 mutex_destroy(&priv->bfregs.reg_head.lock); 1348 mutex_destroy(&dev->intf_state_mutex); 1349 } 1350 1351 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1352 { 1353 struct mlx5_core_dev *dev; 1354 struct devlink *devlink; 1355 int err; 1356 1357 devlink = mlx5_devlink_alloc(); 1358 if (!devlink) { 1359 dev_err(&pdev->dev, "devlink alloc failed\n"); 1360 return -ENOMEM; 1361 } 1362 1363 dev = devlink_priv(devlink); 1364 dev->device = &pdev->dev; 1365 dev->pdev = pdev; 1366 1367 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1368 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1369 1370 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1371 if (dev->priv.adev_idx < 0) { 1372 err = dev->priv.adev_idx; 1373 goto adev_init_err; 1374 } 1375 1376 err = mlx5_mdev_init(dev, prof_sel); 1377 if (err) 1378 goto mdev_init_err; 1379 1380 err = mlx5_pci_init(dev, pdev, id); 1381 if (err) { 1382 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1383 err); 1384 goto pci_init_err; 1385 } 1386 1387 err = mlx5_load_one(dev, true); 1388 if (err) { 1389 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 1390 err); 1391 goto err_load_one; 1392 } 1393 1394 err = mlx5_crdump_enable(dev); 1395 if (err) 1396 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1397 1398 pci_save_state(pdev); 1399 devlink_reload_enable(devlink); 1400 return 0; 1401 1402 err_load_one: 1403 mlx5_pci_close(dev); 1404 pci_init_err: 1405 mlx5_mdev_uninit(dev); 1406 mdev_init_err: 1407 mlx5_adev_idx_free(dev->priv.adev_idx); 1408 adev_init_err: 1409 mlx5_devlink_free(devlink); 1410 1411 return err; 1412 } 1413 1414 static void remove_one(struct pci_dev *pdev) 1415 { 1416 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1417 struct devlink *devlink = priv_to_devlink(dev); 1418 1419 devlink_reload_disable(devlink); 1420 mlx5_crdump_disable(dev); 1421 mlx5_drain_health_wq(dev); 1422 mlx5_unload_one(dev, true); 1423 mlx5_pci_close(dev); 1424 mlx5_mdev_uninit(dev); 1425 mlx5_adev_idx_free(dev->priv.adev_idx); 1426 mlx5_devlink_free(devlink); 1427 } 1428 1429 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1430 pci_channel_state_t state) 1431 { 1432 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1433 1434 mlx5_core_info(dev, "%s was called\n", __func__); 1435 1436 mlx5_enter_error_state(dev, false); 1437 mlx5_error_sw_reset(dev); 1438 mlx5_unload_one(dev, false); 1439 mlx5_drain_health_wq(dev); 1440 mlx5_pci_disable_device(dev); 1441 1442 return state == pci_channel_io_perm_failure ? 1443 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1444 } 1445 1446 /* wait for the device to show vital signs by waiting 1447 * for the health counter to start counting. 1448 */ 1449 static int wait_vital(struct pci_dev *pdev) 1450 { 1451 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1452 struct mlx5_core_health *health = &dev->priv.health; 1453 const int niter = 100; 1454 u32 last_count = 0; 1455 u32 count; 1456 int i; 1457 1458 for (i = 0; i < niter; i++) { 1459 count = ioread32be(health->health_counter); 1460 if (count && count != 0xffffffff) { 1461 if (last_count && last_count != count) { 1462 mlx5_core_info(dev, 1463 "wait vital counter value 0x%x after %d iterations\n", 1464 count, i); 1465 return 0; 1466 } 1467 last_count = count; 1468 } 1469 msleep(50); 1470 } 1471 1472 return -ETIMEDOUT; 1473 } 1474 1475 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1476 { 1477 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1478 int err; 1479 1480 mlx5_core_info(dev, "%s was called\n", __func__); 1481 1482 err = mlx5_pci_enable_device(dev); 1483 if (err) { 1484 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1485 __func__, err); 1486 return PCI_ERS_RESULT_DISCONNECT; 1487 } 1488 1489 pci_set_master(pdev); 1490 pci_restore_state(pdev); 1491 pci_save_state(pdev); 1492 1493 if (wait_vital(pdev)) { 1494 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1495 return PCI_ERS_RESULT_DISCONNECT; 1496 } 1497 1498 return PCI_ERS_RESULT_RECOVERED; 1499 } 1500 1501 static void mlx5_pci_resume(struct pci_dev *pdev) 1502 { 1503 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1504 int err; 1505 1506 mlx5_core_info(dev, "%s was called\n", __func__); 1507 1508 err = mlx5_load_one(dev, false); 1509 if (err) 1510 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1511 __func__, err); 1512 else 1513 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1514 } 1515 1516 static const struct pci_error_handlers mlx5_err_handler = { 1517 .error_detected = mlx5_pci_err_detected, 1518 .slot_reset = mlx5_pci_slot_reset, 1519 .resume = mlx5_pci_resume 1520 }; 1521 1522 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1523 { 1524 bool fast_teardown = false, force_teardown = false; 1525 int ret = 1; 1526 1527 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1528 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1529 1530 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1531 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1532 1533 if (!fast_teardown && !force_teardown) 1534 return -EOPNOTSUPP; 1535 1536 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1537 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1538 return -EAGAIN; 1539 } 1540 1541 /* Panic tear down fw command will stop the PCI bus communication 1542 * with the HCA, so the health polll is no longer needed. 1543 */ 1544 mlx5_drain_health_wq(dev); 1545 mlx5_stop_health_poll(dev, false); 1546 1547 ret = mlx5_cmd_fast_teardown_hca(dev); 1548 if (!ret) 1549 goto succeed; 1550 1551 ret = mlx5_cmd_force_teardown_hca(dev); 1552 if (!ret) 1553 goto succeed; 1554 1555 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1556 mlx5_start_health_poll(dev); 1557 return ret; 1558 1559 succeed: 1560 mlx5_enter_error_state(dev, true); 1561 1562 /* Some platforms requiring freeing the IRQ's in the shutdown 1563 * flow. If they aren't freed they can't be allocated after 1564 * kexec. There is no need to cleanup the mlx5_core software 1565 * contexts. 1566 */ 1567 mlx5_core_eq_free_irqs(dev); 1568 1569 return 0; 1570 } 1571 1572 static void shutdown(struct pci_dev *pdev) 1573 { 1574 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1575 int err; 1576 1577 mlx5_core_info(dev, "Shutdown was called\n"); 1578 err = mlx5_try_fast_unload(dev); 1579 if (err) 1580 mlx5_unload_one(dev, false); 1581 mlx5_pci_disable_device(dev); 1582 } 1583 1584 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1585 { 1586 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1587 1588 mlx5_unload_one(dev, false); 1589 1590 return 0; 1591 } 1592 1593 static int mlx5_resume(struct pci_dev *pdev) 1594 { 1595 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1596 1597 return mlx5_load_one(dev, false); 1598 } 1599 1600 static const struct pci_device_id mlx5_core_pci_table[] = { 1601 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1602 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1603 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1604 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1605 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1606 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1607 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1608 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1609 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1610 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1611 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1612 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1613 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1614 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1615 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1616 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1617 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1618 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1619 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1620 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1621 { 0, } 1622 }; 1623 1624 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1625 1626 void mlx5_disable_device(struct mlx5_core_dev *dev) 1627 { 1628 mlx5_error_sw_reset(dev); 1629 mlx5_unload_one(dev, false); 1630 } 1631 1632 void mlx5_recover_device(struct mlx5_core_dev *dev) 1633 { 1634 mlx5_pci_disable_device(dev); 1635 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1636 mlx5_pci_resume(dev->pdev); 1637 } 1638 1639 static struct pci_driver mlx5_core_driver = { 1640 .name = KBUILD_MODNAME, 1641 .id_table = mlx5_core_pci_table, 1642 .probe = init_one, 1643 .remove = remove_one, 1644 .suspend = mlx5_suspend, 1645 .resume = mlx5_resume, 1646 .shutdown = shutdown, 1647 .err_handler = &mlx5_err_handler, 1648 .sriov_configure = mlx5_core_sriov_configure, 1649 }; 1650 1651 static void mlx5_core_verify_params(void) 1652 { 1653 if (prof_sel >= ARRAY_SIZE(profile)) { 1654 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1655 prof_sel, 1656 ARRAY_SIZE(profile) - 1, 1657 MLX5_DEFAULT_PROF); 1658 prof_sel = MLX5_DEFAULT_PROF; 1659 } 1660 } 1661 1662 static int __init init(void) 1663 { 1664 int err; 1665 1666 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 1667 "mlx5_core name not in sync with kernel module name"); 1668 1669 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1670 1671 mlx5_core_verify_params(); 1672 mlx5_fpga_ipsec_build_fs_cmds(); 1673 mlx5_register_debugfs(); 1674 1675 err = pci_register_driver(&mlx5_core_driver); 1676 if (err) 1677 goto err_debug; 1678 1679 #ifdef CONFIG_MLX5_CORE_EN 1680 err = mlx5e_init(); 1681 if (err) { 1682 pci_unregister_driver(&mlx5_core_driver); 1683 goto err_debug; 1684 } 1685 #endif 1686 1687 return 0; 1688 1689 err_debug: 1690 mlx5_unregister_debugfs(); 1691 return err; 1692 } 1693 1694 static void __exit cleanup(void) 1695 { 1696 #ifdef CONFIG_MLX5_CORE_EN 1697 mlx5e_cleanup(); 1698 #endif 1699 pci_unregister_driver(&mlx5_core_driver); 1700 mlx5_unregister_debugfs(); 1701 } 1702 1703 module_init(init); 1704 module_exit(cleanup); 1705