1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "fpga/core.h" 64 #include "fpga/ipsec.h" 65 #include "accel/ipsec.h" 66 #include "accel/tls.h" 67 #include "lib/clock.h" 68 #include "lib/vxlan.h" 69 #include "lib/geneve.h" 70 #include "lib/devcom.h" 71 #include "lib/pci_vsc.h" 72 #include "diag/fw_tracer.h" 73 #include "ecpf.h" 74 #include "lib/hv_vhca.h" 75 #include "diag/rsc_dump.h" 76 #include "sf/vhca_event.h" 77 #include "sf/dev/dev.h" 78 #include "sf/sf.h" 79 #include "mlx5_irq.h" 80 81 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 82 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 83 MODULE_LICENSE("Dual BSD/GPL"); 84 85 unsigned int mlx5_core_debug_mask; 86 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 87 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 88 89 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 90 module_param_named(prof_sel, prof_sel, uint, 0444); 91 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 92 93 static u32 sw_owner_id[4]; 94 95 enum { 96 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 98 }; 99 100 static struct mlx5_profile profile[] = { 101 [0] = { 102 .mask = 0, 103 }, 104 [1] = { 105 .mask = MLX5_PROF_MASK_QP_SIZE, 106 .log_max_qp = 12, 107 }, 108 [2] = { 109 .mask = MLX5_PROF_MASK_QP_SIZE | 110 MLX5_PROF_MASK_MR_CACHE, 111 .log_max_qp = 18, 112 .mr_cache[0] = { 113 .size = 500, 114 .limit = 250 115 }, 116 .mr_cache[1] = { 117 .size = 500, 118 .limit = 250 119 }, 120 .mr_cache[2] = { 121 .size = 500, 122 .limit = 250 123 }, 124 .mr_cache[3] = { 125 .size = 500, 126 .limit = 250 127 }, 128 .mr_cache[4] = { 129 .size = 500, 130 .limit = 250 131 }, 132 .mr_cache[5] = { 133 .size = 500, 134 .limit = 250 135 }, 136 .mr_cache[6] = { 137 .size = 500, 138 .limit = 250 139 }, 140 .mr_cache[7] = { 141 .size = 500, 142 .limit = 250 143 }, 144 .mr_cache[8] = { 145 .size = 500, 146 .limit = 250 147 }, 148 .mr_cache[9] = { 149 .size = 500, 150 .limit = 250 151 }, 152 .mr_cache[10] = { 153 .size = 500, 154 .limit = 250 155 }, 156 .mr_cache[11] = { 157 .size = 500, 158 .limit = 250 159 }, 160 .mr_cache[12] = { 161 .size = 64, 162 .limit = 32 163 }, 164 .mr_cache[13] = { 165 .size = 32, 166 .limit = 16 167 }, 168 .mr_cache[14] = { 169 .size = 16, 170 .limit = 8 171 }, 172 .mr_cache[15] = { 173 .size = 8, 174 .limit = 4 175 }, 176 }, 177 }; 178 179 #define FW_INIT_TIMEOUT_MILI 2000 180 #define FW_INIT_WAIT_MS 2 181 #define FW_PRE_INIT_TIMEOUT_MILI 120000 182 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 183 184 static int fw_initializing(struct mlx5_core_dev *dev) 185 { 186 return ioread32be(&dev->iseg->initializing) >> 31; 187 } 188 189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 190 u32 warn_time_mili) 191 { 192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 194 int err = 0; 195 196 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 197 198 while (fw_initializing(dev)) { 199 if (time_after(jiffies, end)) { 200 err = -EBUSY; 201 break; 202 } 203 if (warn_time_mili && time_after(jiffies, warn)) { 204 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 205 jiffies_to_msecs(end - warn) / 1000); 206 warn = jiffies + msecs_to_jiffies(warn_time_mili); 207 } 208 msleep(FW_INIT_WAIT_MS); 209 } 210 211 return err; 212 } 213 214 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 215 { 216 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 217 driver_version); 218 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 219 int remaining_size = driver_ver_sz; 220 char *string; 221 222 if (!MLX5_CAP_GEN(dev, driver_version)) 223 return; 224 225 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 226 227 strncpy(string, "Linux", remaining_size); 228 229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 230 strncat(string, ",", remaining_size); 231 232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 233 strncat(string, KBUILD_MODNAME, remaining_size); 234 235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 236 strncat(string, ",", remaining_size); 237 238 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 239 240 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 241 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 242 LINUX_VERSION_SUBLEVEL); 243 244 /*Send the command*/ 245 MLX5_SET(set_driver_version_in, in, opcode, 246 MLX5_CMD_OP_SET_DRIVER_VERSION); 247 248 mlx5_cmd_exec_in(dev, set_driver_version, in); 249 } 250 251 static int set_dma_caps(struct pci_dev *pdev) 252 { 253 int err; 254 255 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 256 if (err) { 257 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 258 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 259 if (err) { 260 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 261 return err; 262 } 263 } 264 265 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 266 return err; 267 } 268 269 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 270 { 271 struct pci_dev *pdev = dev->pdev; 272 int err = 0; 273 274 mutex_lock(&dev->pci_status_mutex); 275 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 276 err = pci_enable_device(pdev); 277 if (!err) 278 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 279 } 280 mutex_unlock(&dev->pci_status_mutex); 281 282 return err; 283 } 284 285 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 286 { 287 struct pci_dev *pdev = dev->pdev; 288 289 mutex_lock(&dev->pci_status_mutex); 290 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 291 pci_disable_device(pdev); 292 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 293 } 294 mutex_unlock(&dev->pci_status_mutex); 295 } 296 297 static int request_bar(struct pci_dev *pdev) 298 { 299 int err = 0; 300 301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 302 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 303 return -ENODEV; 304 } 305 306 err = pci_request_regions(pdev, KBUILD_MODNAME); 307 if (err) 308 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 309 310 return err; 311 } 312 313 static void release_bar(struct pci_dev *pdev) 314 { 315 pci_release_regions(pdev); 316 } 317 318 struct mlx5_reg_host_endianness { 319 u8 he; 320 u8 rsvd[15]; 321 }; 322 323 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 324 325 enum { 326 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 327 MLX5_DEV_CAP_FLAG_DCT, 328 }; 329 330 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 331 { 332 switch (size) { 333 case 128: 334 return 0; 335 case 256: 336 return 1; 337 case 512: 338 return 2; 339 case 1024: 340 return 3; 341 case 2048: 342 return 4; 343 case 4096: 344 return 5; 345 default: 346 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 347 return 0; 348 } 349 } 350 351 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 352 enum mlx5_cap_type cap_type, 353 enum mlx5_cap_mode cap_mode) 354 { 355 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 356 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 357 void *out, *hca_caps; 358 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 359 int err; 360 361 memset(in, 0, sizeof(in)); 362 out = kzalloc(out_sz, GFP_KERNEL); 363 if (!out) 364 return -ENOMEM; 365 366 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 367 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 368 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 369 if (err) { 370 mlx5_core_warn(dev, 371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 372 cap_type, cap_mode, err); 373 goto query_ex; 374 } 375 376 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 377 378 switch (cap_mode) { 379 case HCA_CAP_OPMOD_GET_MAX: 380 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 381 MLX5_UN_SZ_BYTES(hca_cap_union)); 382 break; 383 case HCA_CAP_OPMOD_GET_CUR: 384 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 385 MLX5_UN_SZ_BYTES(hca_cap_union)); 386 break; 387 default: 388 mlx5_core_warn(dev, 389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 390 cap_type, cap_mode); 391 err = -EINVAL; 392 break; 393 } 394 query_ex: 395 kfree(out); 396 return err; 397 } 398 399 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 400 { 401 int ret; 402 403 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 404 if (ret) 405 return ret; 406 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 407 } 408 409 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 410 { 411 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 412 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 413 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 414 } 415 416 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 417 { 418 void *set_hca_cap; 419 int req_endianness; 420 int err; 421 422 if (!MLX5_CAP_GEN(dev, atomic)) 423 return 0; 424 425 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 426 if (err) 427 return err; 428 429 req_endianness = 430 MLX5_CAP_ATOMIC(dev, 431 supported_atomic_req_8B_endianness_mode_1); 432 433 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 434 return 0; 435 436 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 437 438 /* Set requestor to host endianness */ 439 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 440 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 441 442 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 443 } 444 445 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 446 { 447 void *set_hca_cap; 448 bool do_set = false; 449 int err; 450 451 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 452 !MLX5_CAP_GEN(dev, pg)) 453 return 0; 454 455 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 456 if (err) 457 return err; 458 459 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 460 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 461 MLX5_ST_SZ_BYTES(odp_cap)); 462 463 #define ODP_CAP_SET_MAX(dev, field) \ 464 do { \ 465 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 466 if (_res) { \ 467 do_set = true; \ 468 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 469 } \ 470 } while (0) 471 472 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 473 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 476 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 477 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 478 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 480 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 481 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 482 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 483 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 484 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 485 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 486 487 if (!do_set) 488 return 0; 489 490 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 491 } 492 493 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 494 { 495 struct mlx5_profile *prof = &dev->profile; 496 void *set_hca_cap; 497 int err; 498 499 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 500 if (err) 501 return err; 502 503 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 504 capability); 505 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 506 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 507 508 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 509 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 510 128); 511 /* we limit the size of the pkey table to 128 entries for now */ 512 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 513 to_fw_pkey_sz(dev, 128)); 514 515 /* Check log_max_qp from HCA caps to set in current profile */ 516 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 517 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 518 prof->log_max_qp, 519 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 520 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 521 } 522 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 523 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 524 prof->log_max_qp); 525 526 /* disable cmdif checksum */ 527 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 528 529 /* Enable 4K UAR only when HCA supports it and page size is bigger 530 * than 4K. 531 */ 532 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 533 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 534 535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 536 537 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 538 MLX5_SET(cmd_hca_cap, 539 set_hca_cap, 540 cache_line_128byte, 541 cache_line_size() >= 128 ? 1 : 0); 542 543 if (MLX5_CAP_GEN_MAX(dev, dct)) 544 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 545 546 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 547 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 548 549 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 550 MLX5_SET(cmd_hca_cap, 551 set_hca_cap, 552 num_vhca_ports, 553 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 554 555 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 556 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 557 558 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 559 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 560 561 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 562 563 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 564 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 565 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 566 567 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 568 } 569 570 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 571 { 572 void *set_hca_cap; 573 int err; 574 575 if (!MLX5_CAP_GEN(dev, roce)) 576 return 0; 577 578 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 579 if (err) 580 return err; 581 582 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 583 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 584 return 0; 585 586 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 587 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 588 MLX5_ST_SZ_BYTES(roce_cap)); 589 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 590 591 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 592 return err; 593 } 594 595 static int set_hca_cap(struct mlx5_core_dev *dev) 596 { 597 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 598 void *set_ctx; 599 int err; 600 601 set_ctx = kzalloc(set_sz, GFP_KERNEL); 602 if (!set_ctx) 603 return -ENOMEM; 604 605 err = handle_hca_cap(dev, set_ctx); 606 if (err) { 607 mlx5_core_err(dev, "handle_hca_cap failed\n"); 608 goto out; 609 } 610 611 memset(set_ctx, 0, set_sz); 612 err = handle_hca_cap_atomic(dev, set_ctx); 613 if (err) { 614 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 615 goto out; 616 } 617 618 memset(set_ctx, 0, set_sz); 619 err = handle_hca_cap_odp(dev, set_ctx); 620 if (err) { 621 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 622 goto out; 623 } 624 625 memset(set_ctx, 0, set_sz); 626 err = handle_hca_cap_roce(dev, set_ctx); 627 if (err) { 628 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 629 goto out; 630 } 631 632 out: 633 kfree(set_ctx); 634 return err; 635 } 636 637 static int set_hca_ctrl(struct mlx5_core_dev *dev) 638 { 639 struct mlx5_reg_host_endianness he_in; 640 struct mlx5_reg_host_endianness he_out; 641 int err; 642 643 if (!mlx5_core_is_pf(dev)) 644 return 0; 645 646 memset(&he_in, 0, sizeof(he_in)); 647 he_in.he = MLX5_SET_HOST_ENDIANNESS; 648 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 649 &he_out, sizeof(he_out), 650 MLX5_REG_HOST_ENDIANNESS, 0, 1); 651 return err; 652 } 653 654 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 655 { 656 int ret = 0; 657 658 /* Disable local_lb by default */ 659 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 660 ret = mlx5_nic_vport_update_local_lb(dev, false); 661 662 return ret; 663 } 664 665 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 666 { 667 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 668 669 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 670 MLX5_SET(enable_hca_in, in, function_id, func_id); 671 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 672 dev->caps.embedded_cpu); 673 return mlx5_cmd_exec_in(dev, enable_hca, in); 674 } 675 676 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 677 { 678 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 679 680 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 681 MLX5_SET(disable_hca_in, in, function_id, func_id); 682 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 683 dev->caps.embedded_cpu); 684 return mlx5_cmd_exec_in(dev, disable_hca, in); 685 } 686 687 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 688 { 689 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 690 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 691 u32 sup_issi; 692 int err; 693 694 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 695 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 696 if (err) { 697 u32 syndrome; 698 u8 status; 699 700 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 701 if (!status || syndrome == MLX5_DRIVER_SYND) { 702 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 703 err, status, syndrome); 704 return err; 705 } 706 707 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 708 dev->issi = 0; 709 return 0; 710 } 711 712 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 713 714 if (sup_issi & (1 << 1)) { 715 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 716 717 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 718 MLX5_SET(set_issi_in, set_in, current_issi, 1); 719 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 720 if (err) { 721 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 722 err); 723 return err; 724 } 725 726 dev->issi = 1; 727 728 return 0; 729 } else if (sup_issi & (1 << 0) || !sup_issi) { 730 return 0; 731 } 732 733 return -EOPNOTSUPP; 734 } 735 736 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 737 const struct pci_device_id *id) 738 { 739 int err = 0; 740 741 mutex_init(&dev->pci_status_mutex); 742 pci_set_drvdata(dev->pdev, dev); 743 744 dev->bar_addr = pci_resource_start(pdev, 0); 745 746 err = mlx5_pci_enable_device(dev); 747 if (err) { 748 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 749 return err; 750 } 751 752 err = request_bar(pdev); 753 if (err) { 754 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 755 goto err_disable; 756 } 757 758 pci_set_master(pdev); 759 760 err = set_dma_caps(pdev); 761 if (err) { 762 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 763 goto err_clr_master; 764 } 765 766 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 767 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 768 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 769 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 770 771 dev->iseg_base = dev->bar_addr; 772 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 773 if (!dev->iseg) { 774 err = -ENOMEM; 775 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 776 goto err_clr_master; 777 } 778 779 mlx5_pci_vsc_init(dev); 780 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 781 return 0; 782 783 err_clr_master: 784 pci_clear_master(dev->pdev); 785 release_bar(dev->pdev); 786 err_disable: 787 mlx5_pci_disable_device(dev); 788 return err; 789 } 790 791 static void mlx5_pci_close(struct mlx5_core_dev *dev) 792 { 793 /* health work might still be active, and it needs pci bar in 794 * order to know the NIC state. Therefore, drain the health WQ 795 * before removing the pci bars 796 */ 797 mlx5_drain_health_wq(dev); 798 iounmap(dev->iseg); 799 pci_clear_master(dev->pdev); 800 release_bar(dev->pdev); 801 mlx5_pci_disable_device(dev); 802 } 803 804 static int mlx5_init_once(struct mlx5_core_dev *dev) 805 { 806 int err; 807 808 dev->priv.devcom = mlx5_devcom_register_device(dev); 809 if (IS_ERR(dev->priv.devcom)) 810 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 811 dev->priv.devcom); 812 813 err = mlx5_query_board_id(dev); 814 if (err) { 815 mlx5_core_err(dev, "query board id failed\n"); 816 goto err_devcom; 817 } 818 819 err = mlx5_irq_table_init(dev); 820 if (err) { 821 mlx5_core_err(dev, "failed to initialize irq table\n"); 822 goto err_devcom; 823 } 824 825 err = mlx5_eq_table_init(dev); 826 if (err) { 827 mlx5_core_err(dev, "failed to initialize eq\n"); 828 goto err_irq_cleanup; 829 } 830 831 err = mlx5_events_init(dev); 832 if (err) { 833 mlx5_core_err(dev, "failed to initialize events\n"); 834 goto err_eq_cleanup; 835 } 836 837 err = mlx5_fw_reset_init(dev); 838 if (err) { 839 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 840 goto err_events_cleanup; 841 } 842 843 mlx5_cq_debugfs_init(dev); 844 845 mlx5_init_reserved_gids(dev); 846 847 mlx5_init_clock(dev); 848 849 dev->vxlan = mlx5_vxlan_create(dev); 850 dev->geneve = mlx5_geneve_create(dev); 851 852 err = mlx5_init_rl_table(dev); 853 if (err) { 854 mlx5_core_err(dev, "Failed to init rate limiting\n"); 855 goto err_tables_cleanup; 856 } 857 858 err = mlx5_mpfs_init(dev); 859 if (err) { 860 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 861 goto err_rl_cleanup; 862 } 863 864 err = mlx5_sriov_init(dev); 865 if (err) { 866 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 867 goto err_mpfs_cleanup; 868 } 869 870 err = mlx5_eswitch_init(dev); 871 if (err) { 872 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 873 goto err_sriov_cleanup; 874 } 875 876 err = mlx5_fpga_init(dev); 877 if (err) { 878 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 879 goto err_eswitch_cleanup; 880 } 881 882 err = mlx5_vhca_event_init(dev); 883 if (err) { 884 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 885 goto err_fpga_cleanup; 886 } 887 888 err = mlx5_sf_hw_table_init(dev); 889 if (err) { 890 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 891 goto err_sf_hw_table_cleanup; 892 } 893 894 err = mlx5_sf_table_init(dev); 895 if (err) { 896 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 897 goto err_sf_table_cleanup; 898 } 899 900 dev->dm = mlx5_dm_create(dev); 901 if (IS_ERR(dev->dm)) 902 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 903 904 dev->tracer = mlx5_fw_tracer_create(dev); 905 dev->hv_vhca = mlx5_hv_vhca_create(dev); 906 dev->rsc_dump = mlx5_rsc_dump_create(dev); 907 908 return 0; 909 910 err_sf_table_cleanup: 911 mlx5_sf_hw_table_cleanup(dev); 912 err_sf_hw_table_cleanup: 913 mlx5_vhca_event_cleanup(dev); 914 err_fpga_cleanup: 915 mlx5_fpga_cleanup(dev); 916 err_eswitch_cleanup: 917 mlx5_eswitch_cleanup(dev->priv.eswitch); 918 err_sriov_cleanup: 919 mlx5_sriov_cleanup(dev); 920 err_mpfs_cleanup: 921 mlx5_mpfs_cleanup(dev); 922 err_rl_cleanup: 923 mlx5_cleanup_rl_table(dev); 924 err_tables_cleanup: 925 mlx5_geneve_destroy(dev->geneve); 926 mlx5_vxlan_destroy(dev->vxlan); 927 mlx5_cq_debugfs_cleanup(dev); 928 mlx5_fw_reset_cleanup(dev); 929 err_events_cleanup: 930 mlx5_events_cleanup(dev); 931 err_eq_cleanup: 932 mlx5_eq_table_cleanup(dev); 933 err_irq_cleanup: 934 mlx5_irq_table_cleanup(dev); 935 err_devcom: 936 mlx5_devcom_unregister_device(dev->priv.devcom); 937 938 return err; 939 } 940 941 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 942 { 943 mlx5_rsc_dump_destroy(dev); 944 mlx5_hv_vhca_destroy(dev->hv_vhca); 945 mlx5_fw_tracer_destroy(dev->tracer); 946 mlx5_dm_cleanup(dev); 947 mlx5_sf_table_cleanup(dev); 948 mlx5_sf_hw_table_cleanup(dev); 949 mlx5_vhca_event_cleanup(dev); 950 mlx5_fpga_cleanup(dev); 951 mlx5_eswitch_cleanup(dev->priv.eswitch); 952 mlx5_sriov_cleanup(dev); 953 mlx5_mpfs_cleanup(dev); 954 mlx5_cleanup_rl_table(dev); 955 mlx5_geneve_destroy(dev->geneve); 956 mlx5_vxlan_destroy(dev->vxlan); 957 mlx5_cleanup_clock(dev); 958 mlx5_cleanup_reserved_gids(dev); 959 mlx5_cq_debugfs_cleanup(dev); 960 mlx5_fw_reset_cleanup(dev); 961 mlx5_events_cleanup(dev); 962 mlx5_eq_table_cleanup(dev); 963 mlx5_irq_table_cleanup(dev); 964 mlx5_devcom_unregister_device(dev->priv.devcom); 965 } 966 967 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 968 { 969 int err; 970 971 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 972 fw_rev_min(dev), fw_rev_sub(dev)); 973 974 /* Only PFs hold the relevant PCIe information for this query */ 975 if (mlx5_core_is_pf(dev)) 976 pcie_print_link_status(dev->pdev); 977 978 /* wait for firmware to accept initialization segments configurations 979 */ 980 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 981 if (err) { 982 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 983 FW_PRE_INIT_TIMEOUT_MILI); 984 return err; 985 } 986 987 err = mlx5_cmd_init(dev); 988 if (err) { 989 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 990 return err; 991 } 992 993 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 994 if (err) { 995 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 996 FW_INIT_TIMEOUT_MILI); 997 goto err_cmd_cleanup; 998 } 999 1000 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1001 1002 err = mlx5_core_enable_hca(dev, 0); 1003 if (err) { 1004 mlx5_core_err(dev, "enable hca failed\n"); 1005 goto err_cmd_cleanup; 1006 } 1007 1008 err = mlx5_core_set_issi(dev); 1009 if (err) { 1010 mlx5_core_err(dev, "failed to set issi\n"); 1011 goto err_disable_hca; 1012 } 1013 1014 err = mlx5_satisfy_startup_pages(dev, 1); 1015 if (err) { 1016 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1017 goto err_disable_hca; 1018 } 1019 1020 err = set_hca_ctrl(dev); 1021 if (err) { 1022 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1023 goto reclaim_boot_pages; 1024 } 1025 1026 err = set_hca_cap(dev); 1027 if (err) { 1028 mlx5_core_err(dev, "set_hca_cap failed\n"); 1029 goto reclaim_boot_pages; 1030 } 1031 1032 err = mlx5_satisfy_startup_pages(dev, 0); 1033 if (err) { 1034 mlx5_core_err(dev, "failed to allocate init pages\n"); 1035 goto reclaim_boot_pages; 1036 } 1037 1038 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1039 if (err) { 1040 mlx5_core_err(dev, "init hca failed\n"); 1041 goto reclaim_boot_pages; 1042 } 1043 1044 mlx5_set_driver_version(dev); 1045 1046 mlx5_start_health_poll(dev); 1047 1048 err = mlx5_query_hca_caps(dev); 1049 if (err) { 1050 mlx5_core_err(dev, "query hca failed\n"); 1051 goto stop_health; 1052 } 1053 1054 return 0; 1055 1056 stop_health: 1057 mlx5_stop_health_poll(dev, boot); 1058 reclaim_boot_pages: 1059 mlx5_reclaim_startup_pages(dev); 1060 err_disable_hca: 1061 mlx5_core_disable_hca(dev, 0); 1062 err_cmd_cleanup: 1063 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1064 mlx5_cmd_cleanup(dev); 1065 1066 return err; 1067 } 1068 1069 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1070 { 1071 int err; 1072 1073 mlx5_stop_health_poll(dev, boot); 1074 err = mlx5_cmd_teardown_hca(dev); 1075 if (err) { 1076 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1077 return err; 1078 } 1079 mlx5_reclaim_startup_pages(dev); 1080 mlx5_core_disable_hca(dev, 0); 1081 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1082 mlx5_cmd_cleanup(dev); 1083 1084 return 0; 1085 } 1086 1087 static int mlx5_load(struct mlx5_core_dev *dev) 1088 { 1089 int err; 1090 1091 dev->priv.uar = mlx5_get_uars_page(dev); 1092 if (IS_ERR(dev->priv.uar)) { 1093 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1094 err = PTR_ERR(dev->priv.uar); 1095 return err; 1096 } 1097 1098 mlx5_events_start(dev); 1099 mlx5_pagealloc_start(dev); 1100 1101 err = mlx5_irq_table_create(dev); 1102 if (err) { 1103 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1104 goto err_irq_table; 1105 } 1106 1107 err = mlx5_eq_table_create(dev); 1108 if (err) { 1109 mlx5_core_err(dev, "Failed to create EQs\n"); 1110 goto err_eq_table; 1111 } 1112 1113 err = mlx5_fw_tracer_init(dev->tracer); 1114 if (err) { 1115 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1116 goto err_fw_tracer; 1117 } 1118 1119 mlx5_fw_reset_events_start(dev); 1120 mlx5_hv_vhca_init(dev->hv_vhca); 1121 1122 err = mlx5_rsc_dump_init(dev); 1123 if (err) { 1124 mlx5_core_err(dev, "Failed to init Resource dump\n"); 1125 goto err_rsc_dump; 1126 } 1127 1128 err = mlx5_fpga_device_start(dev); 1129 if (err) { 1130 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1131 goto err_fpga_start; 1132 } 1133 1134 mlx5_accel_ipsec_init(dev); 1135 1136 err = mlx5_accel_tls_init(dev); 1137 if (err) { 1138 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1139 goto err_tls_start; 1140 } 1141 1142 err = mlx5_init_fs(dev); 1143 if (err) { 1144 mlx5_core_err(dev, "Failed to init flow steering\n"); 1145 goto err_fs; 1146 } 1147 1148 err = mlx5_core_set_hca_defaults(dev); 1149 if (err) { 1150 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1151 goto err_set_hca; 1152 } 1153 1154 mlx5_vhca_event_start(dev); 1155 1156 err = mlx5_sf_hw_table_create(dev); 1157 if (err) { 1158 mlx5_core_err(dev, "sf table create failed %d\n", err); 1159 goto err_vhca; 1160 } 1161 1162 err = mlx5_ec_init(dev); 1163 if (err) { 1164 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1165 goto err_ec; 1166 } 1167 1168 mlx5_lag_add_mdev(dev); 1169 err = mlx5_sriov_attach(dev); 1170 if (err) { 1171 mlx5_core_err(dev, "sriov init failed %d\n", err); 1172 goto err_sriov; 1173 } 1174 1175 mlx5_sf_dev_table_create(dev); 1176 1177 return 0; 1178 1179 err_sriov: 1180 mlx5_lag_remove_mdev(dev); 1181 mlx5_ec_cleanup(dev); 1182 err_ec: 1183 mlx5_sf_hw_table_destroy(dev); 1184 err_vhca: 1185 mlx5_vhca_event_stop(dev); 1186 err_set_hca: 1187 mlx5_cleanup_fs(dev); 1188 err_fs: 1189 mlx5_accel_tls_cleanup(dev); 1190 err_tls_start: 1191 mlx5_accel_ipsec_cleanup(dev); 1192 mlx5_fpga_device_stop(dev); 1193 err_fpga_start: 1194 mlx5_rsc_dump_cleanup(dev); 1195 err_rsc_dump: 1196 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1197 mlx5_fw_reset_events_stop(dev); 1198 mlx5_fw_tracer_cleanup(dev->tracer); 1199 err_fw_tracer: 1200 mlx5_eq_table_destroy(dev); 1201 err_eq_table: 1202 mlx5_irq_table_destroy(dev); 1203 err_irq_table: 1204 mlx5_pagealloc_stop(dev); 1205 mlx5_events_stop(dev); 1206 mlx5_put_uars_page(dev, dev->priv.uar); 1207 return err; 1208 } 1209 1210 static void mlx5_unload(struct mlx5_core_dev *dev) 1211 { 1212 mlx5_sf_dev_table_destroy(dev); 1213 mlx5_sriov_detach(dev); 1214 mlx5_lag_remove_mdev(dev); 1215 mlx5_ec_cleanup(dev); 1216 mlx5_sf_hw_table_destroy(dev); 1217 mlx5_vhca_event_stop(dev); 1218 mlx5_cleanup_fs(dev); 1219 mlx5_accel_ipsec_cleanup(dev); 1220 mlx5_accel_tls_cleanup(dev); 1221 mlx5_fpga_device_stop(dev); 1222 mlx5_rsc_dump_cleanup(dev); 1223 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1224 mlx5_fw_reset_events_stop(dev); 1225 mlx5_fw_tracer_cleanup(dev->tracer); 1226 mlx5_eq_table_destroy(dev); 1227 mlx5_irq_table_destroy(dev); 1228 mlx5_pagealloc_stop(dev); 1229 mlx5_events_stop(dev); 1230 mlx5_put_uars_page(dev, dev->priv.uar); 1231 } 1232 1233 int mlx5_init_one(struct mlx5_core_dev *dev) 1234 { 1235 int err = 0; 1236 1237 mutex_lock(&dev->intf_state_mutex); 1238 dev->state = MLX5_DEVICE_STATE_UP; 1239 1240 err = mlx5_function_setup(dev, true); 1241 if (err) 1242 goto err_function; 1243 1244 err = mlx5_init_once(dev); 1245 if (err) { 1246 mlx5_core_err(dev, "sw objs init failed\n"); 1247 goto function_teardown; 1248 } 1249 1250 err = mlx5_load(dev); 1251 if (err) 1252 goto err_load; 1253 1254 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1255 1256 err = mlx5_devlink_register(priv_to_devlink(dev)); 1257 if (err) 1258 goto err_devlink_reg; 1259 1260 err = mlx5_register_device(dev); 1261 if (err) 1262 goto err_register; 1263 1264 mutex_unlock(&dev->intf_state_mutex); 1265 return 0; 1266 1267 err_register: 1268 mlx5_devlink_unregister(priv_to_devlink(dev)); 1269 err_devlink_reg: 1270 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1271 mlx5_unload(dev); 1272 err_load: 1273 mlx5_cleanup_once(dev); 1274 function_teardown: 1275 mlx5_function_teardown(dev, true); 1276 err_function: 1277 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1278 mutex_unlock(&dev->intf_state_mutex); 1279 return err; 1280 } 1281 1282 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1283 { 1284 mutex_lock(&dev->intf_state_mutex); 1285 1286 mlx5_unregister_device(dev); 1287 mlx5_devlink_unregister(priv_to_devlink(dev)); 1288 1289 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1290 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1291 __func__); 1292 mlx5_cleanup_once(dev); 1293 goto out; 1294 } 1295 1296 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1297 mlx5_unload(dev); 1298 mlx5_cleanup_once(dev); 1299 mlx5_function_teardown(dev, true); 1300 out: 1301 mutex_unlock(&dev->intf_state_mutex); 1302 } 1303 1304 int mlx5_load_one(struct mlx5_core_dev *dev) 1305 { 1306 int err = 0; 1307 1308 mutex_lock(&dev->intf_state_mutex); 1309 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1310 mlx5_core_warn(dev, "interface is up, NOP\n"); 1311 goto out; 1312 } 1313 /* remove any previous indication of internal error */ 1314 dev->state = MLX5_DEVICE_STATE_UP; 1315 1316 err = mlx5_function_setup(dev, false); 1317 if (err) 1318 goto err_function; 1319 1320 err = mlx5_load(dev); 1321 if (err) 1322 goto err_load; 1323 1324 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1325 1326 err = mlx5_attach_device(dev); 1327 if (err) 1328 goto err_attach; 1329 1330 mutex_unlock(&dev->intf_state_mutex); 1331 return 0; 1332 1333 err_attach: 1334 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1335 mlx5_unload(dev); 1336 err_load: 1337 mlx5_function_teardown(dev, false); 1338 err_function: 1339 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1340 out: 1341 mutex_unlock(&dev->intf_state_mutex); 1342 return err; 1343 } 1344 1345 void mlx5_unload_one(struct mlx5_core_dev *dev) 1346 { 1347 mutex_lock(&dev->intf_state_mutex); 1348 1349 mlx5_detach_device(dev); 1350 1351 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1352 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1353 __func__); 1354 goto out; 1355 } 1356 1357 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1358 mlx5_unload(dev); 1359 mlx5_function_teardown(dev, false); 1360 out: 1361 mutex_unlock(&dev->intf_state_mutex); 1362 } 1363 1364 static const int types[] = { 1365 MLX5_CAP_GENERAL, 1366 MLX5_CAP_GENERAL_2, 1367 MLX5_CAP_ETHERNET_OFFLOADS, 1368 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1369 MLX5_CAP_ODP, 1370 MLX5_CAP_ATOMIC, 1371 MLX5_CAP_ROCE, 1372 MLX5_CAP_IPOIB_OFFLOADS, 1373 MLX5_CAP_FLOW_TABLE, 1374 MLX5_CAP_ESWITCH_FLOW_TABLE, 1375 MLX5_CAP_ESWITCH, 1376 MLX5_CAP_VECTOR_CALC, 1377 MLX5_CAP_QOS, 1378 MLX5_CAP_DEBUG, 1379 MLX5_CAP_DEV_MEM, 1380 MLX5_CAP_DEV_EVENT, 1381 MLX5_CAP_TLS, 1382 MLX5_CAP_VDPA_EMULATION, 1383 MLX5_CAP_IPSEC, 1384 }; 1385 1386 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1387 { 1388 int type; 1389 int i; 1390 1391 for (i = 0; i < ARRAY_SIZE(types); i++) { 1392 type = types[i]; 1393 kfree(dev->caps.hca[type]); 1394 } 1395 } 1396 1397 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1398 { 1399 struct mlx5_hca_cap *cap; 1400 int type; 1401 int i; 1402 1403 for (i = 0; i < ARRAY_SIZE(types); i++) { 1404 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1405 if (!cap) 1406 goto err; 1407 type = types[i]; 1408 dev->caps.hca[type] = cap; 1409 } 1410 1411 return 0; 1412 1413 err: 1414 mlx5_hca_caps_free(dev); 1415 return -ENOMEM; 1416 } 1417 1418 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1419 { 1420 struct mlx5_priv *priv = &dev->priv; 1421 int err; 1422 1423 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1424 INIT_LIST_HEAD(&priv->ctx_list); 1425 spin_lock_init(&priv->ctx_lock); 1426 mutex_init(&dev->intf_state_mutex); 1427 1428 mutex_init(&priv->bfregs.reg_head.lock); 1429 mutex_init(&priv->bfregs.wc_head.lock); 1430 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1431 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1432 1433 mutex_init(&priv->alloc_mutex); 1434 mutex_init(&priv->pgdir_mutex); 1435 INIT_LIST_HEAD(&priv->pgdir_list); 1436 1437 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1438 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1439 mlx5_debugfs_root); 1440 INIT_LIST_HEAD(&priv->traps); 1441 1442 err = mlx5_health_init(dev); 1443 if (err) 1444 goto err_health_init; 1445 1446 err = mlx5_pagealloc_init(dev); 1447 if (err) 1448 goto err_pagealloc_init; 1449 1450 err = mlx5_adev_init(dev); 1451 if (err) 1452 goto err_adev_init; 1453 1454 err = mlx5_hca_caps_alloc(dev); 1455 if (err) 1456 goto err_hca_caps; 1457 1458 return 0; 1459 1460 err_hca_caps: 1461 mlx5_adev_cleanup(dev); 1462 err_adev_init: 1463 mlx5_pagealloc_cleanup(dev); 1464 err_pagealloc_init: 1465 mlx5_health_cleanup(dev); 1466 err_health_init: 1467 debugfs_remove(dev->priv.dbg_root); 1468 mutex_destroy(&priv->pgdir_mutex); 1469 mutex_destroy(&priv->alloc_mutex); 1470 mutex_destroy(&priv->bfregs.wc_head.lock); 1471 mutex_destroy(&priv->bfregs.reg_head.lock); 1472 mutex_destroy(&dev->intf_state_mutex); 1473 return err; 1474 } 1475 1476 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1477 { 1478 struct mlx5_priv *priv = &dev->priv; 1479 1480 mlx5_hca_caps_free(dev); 1481 mlx5_adev_cleanup(dev); 1482 mlx5_pagealloc_cleanup(dev); 1483 mlx5_health_cleanup(dev); 1484 debugfs_remove_recursive(dev->priv.dbg_root); 1485 mutex_destroy(&priv->pgdir_mutex); 1486 mutex_destroy(&priv->alloc_mutex); 1487 mutex_destroy(&priv->bfregs.wc_head.lock); 1488 mutex_destroy(&priv->bfregs.reg_head.lock); 1489 mutex_destroy(&dev->intf_state_mutex); 1490 } 1491 1492 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1493 { 1494 struct mlx5_core_dev *dev; 1495 struct devlink *devlink; 1496 int err; 1497 1498 devlink = mlx5_devlink_alloc(&pdev->dev); 1499 if (!devlink) { 1500 dev_err(&pdev->dev, "devlink alloc failed\n"); 1501 return -ENOMEM; 1502 } 1503 1504 dev = devlink_priv(devlink); 1505 dev->device = &pdev->dev; 1506 dev->pdev = pdev; 1507 1508 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1509 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1510 1511 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1512 if (dev->priv.adev_idx < 0) { 1513 err = dev->priv.adev_idx; 1514 goto adev_init_err; 1515 } 1516 1517 err = mlx5_mdev_init(dev, prof_sel); 1518 if (err) 1519 goto mdev_init_err; 1520 1521 err = mlx5_pci_init(dev, pdev, id); 1522 if (err) { 1523 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1524 err); 1525 goto pci_init_err; 1526 } 1527 1528 err = mlx5_init_one(dev); 1529 if (err) { 1530 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1531 err); 1532 goto err_init_one; 1533 } 1534 1535 err = mlx5_crdump_enable(dev); 1536 if (err) 1537 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1538 1539 pci_save_state(pdev); 1540 if (!mlx5_core_is_mp_slave(dev)) 1541 devlink_reload_enable(devlink); 1542 return 0; 1543 1544 err_init_one: 1545 mlx5_pci_close(dev); 1546 pci_init_err: 1547 mlx5_mdev_uninit(dev); 1548 mdev_init_err: 1549 mlx5_adev_idx_free(dev->priv.adev_idx); 1550 adev_init_err: 1551 mlx5_devlink_free(devlink); 1552 1553 return err; 1554 } 1555 1556 static void remove_one(struct pci_dev *pdev) 1557 { 1558 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1559 struct devlink *devlink = priv_to_devlink(dev); 1560 1561 devlink_reload_disable(devlink); 1562 mlx5_crdump_disable(dev); 1563 mlx5_drain_health_wq(dev); 1564 mlx5_uninit_one(dev); 1565 mlx5_pci_close(dev); 1566 mlx5_mdev_uninit(dev); 1567 mlx5_adev_idx_free(dev->priv.adev_idx); 1568 mlx5_devlink_free(devlink); 1569 } 1570 1571 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1572 pci_channel_state_t state) 1573 { 1574 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1575 1576 mlx5_core_info(dev, "%s was called\n", __func__); 1577 1578 mlx5_enter_error_state(dev, false); 1579 mlx5_error_sw_reset(dev); 1580 mlx5_unload_one(dev); 1581 mlx5_drain_health_wq(dev); 1582 mlx5_pci_disable_device(dev); 1583 1584 return state == pci_channel_io_perm_failure ? 1585 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1586 } 1587 1588 /* wait for the device to show vital signs by waiting 1589 * for the health counter to start counting. 1590 */ 1591 static int wait_vital(struct pci_dev *pdev) 1592 { 1593 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1594 struct mlx5_core_health *health = &dev->priv.health; 1595 const int niter = 100; 1596 u32 last_count = 0; 1597 u32 count; 1598 int i; 1599 1600 for (i = 0; i < niter; i++) { 1601 count = ioread32be(health->health_counter); 1602 if (count && count != 0xffffffff) { 1603 if (last_count && last_count != count) { 1604 mlx5_core_info(dev, 1605 "wait vital counter value 0x%x after %d iterations\n", 1606 count, i); 1607 return 0; 1608 } 1609 last_count = count; 1610 } 1611 msleep(50); 1612 } 1613 1614 return -ETIMEDOUT; 1615 } 1616 1617 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1618 { 1619 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1620 int err; 1621 1622 mlx5_core_info(dev, "%s was called\n", __func__); 1623 1624 err = mlx5_pci_enable_device(dev); 1625 if (err) { 1626 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1627 __func__, err); 1628 return PCI_ERS_RESULT_DISCONNECT; 1629 } 1630 1631 pci_set_master(pdev); 1632 pci_restore_state(pdev); 1633 pci_save_state(pdev); 1634 1635 if (wait_vital(pdev)) { 1636 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1637 return PCI_ERS_RESULT_DISCONNECT; 1638 } 1639 1640 return PCI_ERS_RESULT_RECOVERED; 1641 } 1642 1643 static void mlx5_pci_resume(struct pci_dev *pdev) 1644 { 1645 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1646 int err; 1647 1648 mlx5_core_info(dev, "%s was called\n", __func__); 1649 1650 err = mlx5_load_one(dev); 1651 if (err) 1652 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1653 __func__, err); 1654 else 1655 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1656 } 1657 1658 static const struct pci_error_handlers mlx5_err_handler = { 1659 .error_detected = mlx5_pci_err_detected, 1660 .slot_reset = mlx5_pci_slot_reset, 1661 .resume = mlx5_pci_resume 1662 }; 1663 1664 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1665 { 1666 bool fast_teardown = false, force_teardown = false; 1667 int ret = 1; 1668 1669 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1670 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1671 1672 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1673 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1674 1675 if (!fast_teardown && !force_teardown) 1676 return -EOPNOTSUPP; 1677 1678 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1679 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1680 return -EAGAIN; 1681 } 1682 1683 /* Panic tear down fw command will stop the PCI bus communication 1684 * with the HCA, so the health polll is no longer needed. 1685 */ 1686 mlx5_drain_health_wq(dev); 1687 mlx5_stop_health_poll(dev, false); 1688 1689 ret = mlx5_cmd_fast_teardown_hca(dev); 1690 if (!ret) 1691 goto succeed; 1692 1693 ret = mlx5_cmd_force_teardown_hca(dev); 1694 if (!ret) 1695 goto succeed; 1696 1697 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1698 mlx5_start_health_poll(dev); 1699 return ret; 1700 1701 succeed: 1702 mlx5_enter_error_state(dev, true); 1703 1704 /* Some platforms requiring freeing the IRQ's in the shutdown 1705 * flow. If they aren't freed they can't be allocated after 1706 * kexec. There is no need to cleanup the mlx5_core software 1707 * contexts. 1708 */ 1709 mlx5_core_eq_free_irqs(dev); 1710 1711 return 0; 1712 } 1713 1714 static void shutdown(struct pci_dev *pdev) 1715 { 1716 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1717 int err; 1718 1719 mlx5_core_info(dev, "Shutdown was called\n"); 1720 err = mlx5_try_fast_unload(dev); 1721 if (err) 1722 mlx5_unload_one(dev); 1723 mlx5_pci_disable_device(dev); 1724 } 1725 1726 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1727 { 1728 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1729 1730 mlx5_unload_one(dev); 1731 1732 return 0; 1733 } 1734 1735 static int mlx5_resume(struct pci_dev *pdev) 1736 { 1737 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1738 1739 return mlx5_load_one(dev); 1740 } 1741 1742 static const struct pci_device_id mlx5_core_pci_table[] = { 1743 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1744 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1745 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1746 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1747 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1748 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1749 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1750 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1751 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1752 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1753 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1754 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1755 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1756 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1757 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1758 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1759 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1760 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1761 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1762 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1763 { 0, } 1764 }; 1765 1766 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1767 1768 void mlx5_disable_device(struct mlx5_core_dev *dev) 1769 { 1770 mlx5_error_sw_reset(dev); 1771 mlx5_unload_one(dev); 1772 } 1773 1774 int mlx5_recover_device(struct mlx5_core_dev *dev) 1775 { 1776 int ret = -EIO; 1777 1778 mlx5_pci_disable_device(dev); 1779 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1780 ret = mlx5_load_one(dev); 1781 return ret; 1782 } 1783 1784 static struct pci_driver mlx5_core_driver = { 1785 .name = KBUILD_MODNAME, 1786 .id_table = mlx5_core_pci_table, 1787 .probe = probe_one, 1788 .remove = remove_one, 1789 .suspend = mlx5_suspend, 1790 .resume = mlx5_resume, 1791 .shutdown = shutdown, 1792 .err_handler = &mlx5_err_handler, 1793 .sriov_configure = mlx5_core_sriov_configure, 1794 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1795 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 1796 }; 1797 1798 static void mlx5_core_verify_params(void) 1799 { 1800 if (prof_sel >= ARRAY_SIZE(profile)) { 1801 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1802 prof_sel, 1803 ARRAY_SIZE(profile) - 1, 1804 MLX5_DEFAULT_PROF); 1805 prof_sel = MLX5_DEFAULT_PROF; 1806 } 1807 } 1808 1809 static int __init init(void) 1810 { 1811 int err; 1812 1813 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 1814 "mlx5_core name not in sync with kernel module name"); 1815 1816 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1817 1818 mlx5_core_verify_params(); 1819 mlx5_fpga_ipsec_build_fs_cmds(); 1820 mlx5_register_debugfs(); 1821 1822 err = pci_register_driver(&mlx5_core_driver); 1823 if (err) 1824 goto err_debug; 1825 1826 err = mlx5_sf_driver_register(); 1827 if (err) 1828 goto err_sf; 1829 1830 err = mlx5e_init(); 1831 if (err) 1832 goto err_en; 1833 1834 return 0; 1835 1836 err_en: 1837 mlx5_sf_driver_unregister(); 1838 err_sf: 1839 pci_unregister_driver(&mlx5_core_driver); 1840 err_debug: 1841 mlx5_unregister_debugfs(); 1842 return err; 1843 } 1844 1845 static void __exit cleanup(void) 1846 { 1847 mlx5e_cleanup(); 1848 mlx5_sf_driver_unregister(); 1849 pci_unregister_driver(&mlx5_core_driver); 1850 mlx5_unregister_debugfs(); 1851 } 1852 1853 module_init(init); 1854 module_exit(cleanup); 1855