1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "lib/tout.h" 64 #include "fpga/core.h" 65 #include "fpga/ipsec.h" 66 #include "accel/ipsec.h" 67 #include "accel/tls.h" 68 #include "lib/clock.h" 69 #include "lib/vxlan.h" 70 #include "lib/geneve.h" 71 #include "lib/devcom.h" 72 #include "lib/pci_vsc.h" 73 #include "diag/fw_tracer.h" 74 #include "ecpf.h" 75 #include "lib/hv_vhca.h" 76 #include "diag/rsc_dump.h" 77 #include "sf/vhca_event.h" 78 #include "sf/dev/dev.h" 79 #include "sf/sf.h" 80 #include "mlx5_irq.h" 81 82 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 83 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 84 MODULE_LICENSE("Dual BSD/GPL"); 85 86 unsigned int mlx5_core_debug_mask; 87 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 88 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 89 90 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 91 module_param_named(prof_sel, prof_sel, uint, 0444); 92 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 93 94 static u32 sw_owner_id[4]; 95 96 enum { 97 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 99 }; 100 101 static struct mlx5_profile profile[] = { 102 [0] = { 103 .mask = 0, 104 }, 105 [1] = { 106 .mask = MLX5_PROF_MASK_QP_SIZE, 107 .log_max_qp = 12, 108 }, 109 [2] = { 110 .mask = MLX5_PROF_MASK_QP_SIZE | 111 MLX5_PROF_MASK_MR_CACHE, 112 .log_max_qp = 18, 113 .mr_cache[0] = { 114 .size = 500, 115 .limit = 250 116 }, 117 .mr_cache[1] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[2] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[3] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[4] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[5] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[6] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[7] = { 142 .size = 500, 143 .limit = 250 144 }, 145 .mr_cache[8] = { 146 .size = 500, 147 .limit = 250 148 }, 149 .mr_cache[9] = { 150 .size = 500, 151 .limit = 250 152 }, 153 .mr_cache[10] = { 154 .size = 500, 155 .limit = 250 156 }, 157 .mr_cache[11] = { 158 .size = 500, 159 .limit = 250 160 }, 161 .mr_cache[12] = { 162 .size = 64, 163 .limit = 32 164 }, 165 .mr_cache[13] = { 166 .size = 32, 167 .limit = 16 168 }, 169 .mr_cache[14] = { 170 .size = 16, 171 .limit = 8 172 }, 173 .mr_cache[15] = { 174 .size = 8, 175 .limit = 4 176 }, 177 }, 178 }; 179 180 static int fw_initializing(struct mlx5_core_dev *dev) 181 { 182 return ioread32be(&dev->iseg->initializing) >> 31; 183 } 184 185 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 186 u32 warn_time_mili) 187 { 188 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 189 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 190 int err = 0; 191 192 while (fw_initializing(dev)) { 193 if (time_after(jiffies, end)) { 194 err = -EBUSY; 195 break; 196 } 197 if (warn_time_mili && time_after(jiffies, warn)) { 198 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 199 jiffies_to_msecs(end - warn) / 1000); 200 warn = jiffies + msecs_to_jiffies(warn_time_mili); 201 } 202 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 203 } 204 205 return err; 206 } 207 208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 209 { 210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 211 driver_version); 212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 213 int remaining_size = driver_ver_sz; 214 char *string; 215 216 if (!MLX5_CAP_GEN(dev, driver_version)) 217 return; 218 219 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 220 221 strncpy(string, "Linux", remaining_size); 222 223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 224 strncat(string, ",", remaining_size); 225 226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 227 strncat(string, KBUILD_MODNAME, remaining_size); 228 229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 230 strncat(string, ",", remaining_size); 231 232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 233 234 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 235 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 236 LINUX_VERSION_SUBLEVEL); 237 238 /*Send the command*/ 239 MLX5_SET(set_driver_version_in, in, opcode, 240 MLX5_CMD_OP_SET_DRIVER_VERSION); 241 242 mlx5_cmd_exec_in(dev, set_driver_version, in); 243 } 244 245 static int set_dma_caps(struct pci_dev *pdev) 246 { 247 int err; 248 249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 250 if (err) { 251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 253 if (err) { 254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 255 return err; 256 } 257 } 258 259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 260 return err; 261 } 262 263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 264 { 265 struct pci_dev *pdev = dev->pdev; 266 int err = 0; 267 268 mutex_lock(&dev->pci_status_mutex); 269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 270 err = pci_enable_device(pdev); 271 if (!err) 272 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 273 } 274 mutex_unlock(&dev->pci_status_mutex); 275 276 return err; 277 } 278 279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 280 { 281 struct pci_dev *pdev = dev->pdev; 282 283 mutex_lock(&dev->pci_status_mutex); 284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 285 pci_disable_device(pdev); 286 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 287 } 288 mutex_unlock(&dev->pci_status_mutex); 289 } 290 291 static int request_bar(struct pci_dev *pdev) 292 { 293 int err = 0; 294 295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 297 return -ENODEV; 298 } 299 300 err = pci_request_regions(pdev, KBUILD_MODNAME); 301 if (err) 302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 303 304 return err; 305 } 306 307 static void release_bar(struct pci_dev *pdev) 308 { 309 pci_release_regions(pdev); 310 } 311 312 struct mlx5_reg_host_endianness { 313 u8 he; 314 u8 rsvd[15]; 315 }; 316 317 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 318 319 enum { 320 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 321 MLX5_DEV_CAP_FLAG_DCT, 322 }; 323 324 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 325 { 326 switch (size) { 327 case 128: 328 return 0; 329 case 256: 330 return 1; 331 case 512: 332 return 2; 333 case 1024: 334 return 3; 335 case 2048: 336 return 4; 337 case 4096: 338 return 5; 339 default: 340 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 341 return 0; 342 } 343 } 344 345 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 346 enum mlx5_cap_type cap_type, 347 enum mlx5_cap_mode cap_mode) 348 { 349 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 350 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 351 void *out, *hca_caps; 352 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 353 int err; 354 355 memset(in, 0, sizeof(in)); 356 out = kzalloc(out_sz, GFP_KERNEL); 357 if (!out) 358 return -ENOMEM; 359 360 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 361 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 362 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 363 if (err) { 364 mlx5_core_warn(dev, 365 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 366 cap_type, cap_mode, err); 367 goto query_ex; 368 } 369 370 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 371 372 switch (cap_mode) { 373 case HCA_CAP_OPMOD_GET_MAX: 374 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 375 MLX5_UN_SZ_BYTES(hca_cap_union)); 376 break; 377 case HCA_CAP_OPMOD_GET_CUR: 378 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 379 MLX5_UN_SZ_BYTES(hca_cap_union)); 380 break; 381 default: 382 mlx5_core_warn(dev, 383 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 384 cap_type, cap_mode); 385 err = -EINVAL; 386 break; 387 } 388 query_ex: 389 kfree(out); 390 return err; 391 } 392 393 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 394 { 395 int ret; 396 397 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 398 if (ret) 399 return ret; 400 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 401 } 402 403 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 404 { 405 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 406 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 407 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 408 } 409 410 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 411 { 412 void *set_hca_cap; 413 int req_endianness; 414 int err; 415 416 if (!MLX5_CAP_GEN(dev, atomic)) 417 return 0; 418 419 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 420 if (err) 421 return err; 422 423 req_endianness = 424 MLX5_CAP_ATOMIC(dev, 425 supported_atomic_req_8B_endianness_mode_1); 426 427 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 428 return 0; 429 430 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 431 432 /* Set requestor to host endianness */ 433 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 434 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 435 436 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 437 } 438 439 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 440 { 441 void *set_hca_cap; 442 bool do_set = false; 443 int err; 444 445 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 446 !MLX5_CAP_GEN(dev, pg)) 447 return 0; 448 449 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 450 if (err) 451 return err; 452 453 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 454 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 455 MLX5_ST_SZ_BYTES(odp_cap)); 456 457 #define ODP_CAP_SET_MAX(dev, field) \ 458 do { \ 459 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 460 if (_res) { \ 461 do_set = true; \ 462 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 463 } \ 464 } while (0) 465 466 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 467 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 469 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 474 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 475 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 476 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 477 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 478 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 479 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 480 481 if (!do_set) 482 return 0; 483 484 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 485 } 486 487 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 488 { 489 struct mlx5_profile *prof = &dev->profile; 490 void *set_hca_cap; 491 int err; 492 493 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 494 if (err) 495 return err; 496 497 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 498 capability); 499 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 500 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 501 502 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 503 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 504 128); 505 /* we limit the size of the pkey table to 128 entries for now */ 506 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 507 to_fw_pkey_sz(dev, 128)); 508 509 /* Check log_max_qp from HCA caps to set in current profile */ 510 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 511 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 512 prof->log_max_qp, 513 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 514 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 515 } 516 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 517 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 518 prof->log_max_qp); 519 520 /* disable cmdif checksum */ 521 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 522 523 /* Enable 4K UAR only when HCA supports it and page size is bigger 524 * than 4K. 525 */ 526 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 527 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 528 529 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 530 531 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 532 MLX5_SET(cmd_hca_cap, 533 set_hca_cap, 534 cache_line_128byte, 535 cache_line_size() >= 128 ? 1 : 0); 536 537 if (MLX5_CAP_GEN_MAX(dev, dct)) 538 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 539 540 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 541 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 542 543 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 544 MLX5_SET(cmd_hca_cap, 545 set_hca_cap, 546 num_vhca_ports, 547 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 548 549 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 550 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 551 552 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 553 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 554 555 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 556 557 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 558 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 559 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 560 561 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 562 } 563 564 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 565 { 566 void *set_hca_cap; 567 int err; 568 569 if (!MLX5_CAP_GEN(dev, roce)) 570 return 0; 571 572 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 573 if (err) 574 return err; 575 576 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 577 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 578 return 0; 579 580 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 581 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 582 MLX5_ST_SZ_BYTES(roce_cap)); 583 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 584 585 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 586 return err; 587 } 588 589 static int set_hca_cap(struct mlx5_core_dev *dev) 590 { 591 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 592 void *set_ctx; 593 int err; 594 595 set_ctx = kzalloc(set_sz, GFP_KERNEL); 596 if (!set_ctx) 597 return -ENOMEM; 598 599 err = handle_hca_cap(dev, set_ctx); 600 if (err) { 601 mlx5_core_err(dev, "handle_hca_cap failed\n"); 602 goto out; 603 } 604 605 memset(set_ctx, 0, set_sz); 606 err = handle_hca_cap_atomic(dev, set_ctx); 607 if (err) { 608 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 609 goto out; 610 } 611 612 memset(set_ctx, 0, set_sz); 613 err = handle_hca_cap_odp(dev, set_ctx); 614 if (err) { 615 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 616 goto out; 617 } 618 619 memset(set_ctx, 0, set_sz); 620 err = handle_hca_cap_roce(dev, set_ctx); 621 if (err) { 622 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 623 goto out; 624 } 625 626 out: 627 kfree(set_ctx); 628 return err; 629 } 630 631 static int set_hca_ctrl(struct mlx5_core_dev *dev) 632 { 633 struct mlx5_reg_host_endianness he_in; 634 struct mlx5_reg_host_endianness he_out; 635 int err; 636 637 if (!mlx5_core_is_pf(dev)) 638 return 0; 639 640 memset(&he_in, 0, sizeof(he_in)); 641 he_in.he = MLX5_SET_HOST_ENDIANNESS; 642 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 643 &he_out, sizeof(he_out), 644 MLX5_REG_HOST_ENDIANNESS, 0, 1); 645 return err; 646 } 647 648 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 649 { 650 int ret = 0; 651 652 /* Disable local_lb by default */ 653 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 654 ret = mlx5_nic_vport_update_local_lb(dev, false); 655 656 return ret; 657 } 658 659 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 660 { 661 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 662 663 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 664 MLX5_SET(enable_hca_in, in, function_id, func_id); 665 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 666 dev->caps.embedded_cpu); 667 return mlx5_cmd_exec_in(dev, enable_hca, in); 668 } 669 670 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 671 { 672 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 673 674 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 675 MLX5_SET(disable_hca_in, in, function_id, func_id); 676 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 677 dev->caps.embedded_cpu); 678 return mlx5_cmd_exec_in(dev, disable_hca, in); 679 } 680 681 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 682 { 683 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 684 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 685 u32 sup_issi; 686 int err; 687 688 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 689 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 690 if (err) { 691 u32 syndrome; 692 u8 status; 693 694 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 695 if (!status || syndrome == MLX5_DRIVER_SYND) { 696 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 697 err, status, syndrome); 698 return err; 699 } 700 701 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 702 dev->issi = 0; 703 return 0; 704 } 705 706 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 707 708 if (sup_issi & (1 << 1)) { 709 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 710 711 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 712 MLX5_SET(set_issi_in, set_in, current_issi, 1); 713 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 714 if (err) { 715 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 716 err); 717 return err; 718 } 719 720 dev->issi = 1; 721 722 return 0; 723 } else if (sup_issi & (1 << 0) || !sup_issi) { 724 return 0; 725 } 726 727 return -EOPNOTSUPP; 728 } 729 730 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 731 const struct pci_device_id *id) 732 { 733 int err = 0; 734 735 mutex_init(&dev->pci_status_mutex); 736 pci_set_drvdata(dev->pdev, dev); 737 738 dev->bar_addr = pci_resource_start(pdev, 0); 739 740 err = mlx5_pci_enable_device(dev); 741 if (err) { 742 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 743 return err; 744 } 745 746 err = request_bar(pdev); 747 if (err) { 748 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 749 goto err_disable; 750 } 751 752 pci_set_master(pdev); 753 754 err = set_dma_caps(pdev); 755 if (err) { 756 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 757 goto err_clr_master; 758 } 759 760 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 761 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 762 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 763 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 764 765 dev->iseg_base = dev->bar_addr; 766 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 767 if (!dev->iseg) { 768 err = -ENOMEM; 769 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 770 goto err_clr_master; 771 } 772 773 mlx5_pci_vsc_init(dev); 774 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 775 return 0; 776 777 err_clr_master: 778 pci_clear_master(dev->pdev); 779 release_bar(dev->pdev); 780 err_disable: 781 mlx5_pci_disable_device(dev); 782 return err; 783 } 784 785 static void mlx5_pci_close(struct mlx5_core_dev *dev) 786 { 787 /* health work might still be active, and it needs pci bar in 788 * order to know the NIC state. Therefore, drain the health WQ 789 * before removing the pci bars 790 */ 791 mlx5_drain_health_wq(dev); 792 iounmap(dev->iseg); 793 pci_clear_master(dev->pdev); 794 release_bar(dev->pdev); 795 mlx5_pci_disable_device(dev); 796 } 797 798 static int mlx5_init_once(struct mlx5_core_dev *dev) 799 { 800 int err; 801 802 dev->priv.devcom = mlx5_devcom_register_device(dev); 803 if (IS_ERR(dev->priv.devcom)) 804 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 805 dev->priv.devcom); 806 807 err = mlx5_query_board_id(dev); 808 if (err) { 809 mlx5_core_err(dev, "query board id failed\n"); 810 goto err_devcom; 811 } 812 813 err = mlx5_irq_table_init(dev); 814 if (err) { 815 mlx5_core_err(dev, "failed to initialize irq table\n"); 816 goto err_devcom; 817 } 818 819 err = mlx5_eq_table_init(dev); 820 if (err) { 821 mlx5_core_err(dev, "failed to initialize eq\n"); 822 goto err_irq_cleanup; 823 } 824 825 err = mlx5_events_init(dev); 826 if (err) { 827 mlx5_core_err(dev, "failed to initialize events\n"); 828 goto err_eq_cleanup; 829 } 830 831 err = mlx5_fw_reset_init(dev); 832 if (err) { 833 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 834 goto err_events_cleanup; 835 } 836 837 mlx5_cq_debugfs_init(dev); 838 839 mlx5_init_reserved_gids(dev); 840 841 mlx5_init_clock(dev); 842 843 dev->vxlan = mlx5_vxlan_create(dev); 844 dev->geneve = mlx5_geneve_create(dev); 845 846 err = mlx5_init_rl_table(dev); 847 if (err) { 848 mlx5_core_err(dev, "Failed to init rate limiting\n"); 849 goto err_tables_cleanup; 850 } 851 852 err = mlx5_mpfs_init(dev); 853 if (err) { 854 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 855 goto err_rl_cleanup; 856 } 857 858 err = mlx5_sriov_init(dev); 859 if (err) { 860 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 861 goto err_mpfs_cleanup; 862 } 863 864 err = mlx5_eswitch_init(dev); 865 if (err) { 866 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 867 goto err_sriov_cleanup; 868 } 869 870 err = mlx5_fpga_init(dev); 871 if (err) { 872 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 873 goto err_eswitch_cleanup; 874 } 875 876 err = mlx5_vhca_event_init(dev); 877 if (err) { 878 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 879 goto err_fpga_cleanup; 880 } 881 882 err = mlx5_sf_hw_table_init(dev); 883 if (err) { 884 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 885 goto err_sf_hw_table_cleanup; 886 } 887 888 err = mlx5_sf_table_init(dev); 889 if (err) { 890 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 891 goto err_sf_table_cleanup; 892 } 893 894 dev->dm = mlx5_dm_create(dev); 895 if (IS_ERR(dev->dm)) 896 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 897 898 dev->tracer = mlx5_fw_tracer_create(dev); 899 dev->hv_vhca = mlx5_hv_vhca_create(dev); 900 dev->rsc_dump = mlx5_rsc_dump_create(dev); 901 902 return 0; 903 904 err_sf_table_cleanup: 905 mlx5_sf_hw_table_cleanup(dev); 906 err_sf_hw_table_cleanup: 907 mlx5_vhca_event_cleanup(dev); 908 err_fpga_cleanup: 909 mlx5_fpga_cleanup(dev); 910 err_eswitch_cleanup: 911 mlx5_eswitch_cleanup(dev->priv.eswitch); 912 err_sriov_cleanup: 913 mlx5_sriov_cleanup(dev); 914 err_mpfs_cleanup: 915 mlx5_mpfs_cleanup(dev); 916 err_rl_cleanup: 917 mlx5_cleanup_rl_table(dev); 918 err_tables_cleanup: 919 mlx5_geneve_destroy(dev->geneve); 920 mlx5_vxlan_destroy(dev->vxlan); 921 mlx5_cq_debugfs_cleanup(dev); 922 mlx5_fw_reset_cleanup(dev); 923 err_events_cleanup: 924 mlx5_events_cleanup(dev); 925 err_eq_cleanup: 926 mlx5_eq_table_cleanup(dev); 927 err_irq_cleanup: 928 mlx5_irq_table_cleanup(dev); 929 err_devcom: 930 mlx5_devcom_unregister_device(dev->priv.devcom); 931 932 return err; 933 } 934 935 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 936 { 937 mlx5_rsc_dump_destroy(dev); 938 mlx5_hv_vhca_destroy(dev->hv_vhca); 939 mlx5_fw_tracer_destroy(dev->tracer); 940 mlx5_dm_cleanup(dev); 941 mlx5_sf_table_cleanup(dev); 942 mlx5_sf_hw_table_cleanup(dev); 943 mlx5_vhca_event_cleanup(dev); 944 mlx5_fpga_cleanup(dev); 945 mlx5_eswitch_cleanup(dev->priv.eswitch); 946 mlx5_sriov_cleanup(dev); 947 mlx5_mpfs_cleanup(dev); 948 mlx5_cleanup_rl_table(dev); 949 mlx5_geneve_destroy(dev->geneve); 950 mlx5_vxlan_destroy(dev->vxlan); 951 mlx5_cleanup_clock(dev); 952 mlx5_cleanup_reserved_gids(dev); 953 mlx5_cq_debugfs_cleanup(dev); 954 mlx5_fw_reset_cleanup(dev); 955 mlx5_events_cleanup(dev); 956 mlx5_eq_table_cleanup(dev); 957 mlx5_irq_table_cleanup(dev); 958 mlx5_devcom_unregister_device(dev->priv.devcom); 959 } 960 961 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 962 { 963 int err; 964 965 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 966 fw_rev_min(dev), fw_rev_sub(dev)); 967 968 /* Only PFs hold the relevant PCIe information for this query */ 969 if (mlx5_core_is_pf(dev)) 970 pcie_print_link_status(dev->pdev); 971 972 err = mlx5_tout_init(dev); 973 if (err) { 974 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 975 return err; 976 } 977 978 /* wait for firmware to accept initialization segments configurations 979 */ 980 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT), 981 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 982 if (err) { 983 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 984 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 985 goto err_tout_cleanup; 986 } 987 988 err = mlx5_cmd_init(dev); 989 if (err) { 990 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 991 goto err_tout_cleanup; 992 } 993 994 mlx5_tout_query_iseg(dev); 995 996 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 997 if (err) { 998 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 999 mlx5_tout_ms(dev, FW_INIT)); 1000 goto err_cmd_cleanup; 1001 } 1002 1003 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1004 1005 err = mlx5_core_enable_hca(dev, 0); 1006 if (err) { 1007 mlx5_core_err(dev, "enable hca failed\n"); 1008 goto err_cmd_cleanup; 1009 } 1010 1011 err = mlx5_core_set_issi(dev); 1012 if (err) { 1013 mlx5_core_err(dev, "failed to set issi\n"); 1014 goto err_disable_hca; 1015 } 1016 1017 err = mlx5_satisfy_startup_pages(dev, 1); 1018 if (err) { 1019 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1020 goto err_disable_hca; 1021 } 1022 1023 err = set_hca_ctrl(dev); 1024 if (err) { 1025 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1026 goto reclaim_boot_pages; 1027 } 1028 1029 err = set_hca_cap(dev); 1030 if (err) { 1031 mlx5_core_err(dev, "set_hca_cap failed\n"); 1032 goto reclaim_boot_pages; 1033 } 1034 1035 err = mlx5_satisfy_startup_pages(dev, 0); 1036 if (err) { 1037 mlx5_core_err(dev, "failed to allocate init pages\n"); 1038 goto reclaim_boot_pages; 1039 } 1040 1041 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1042 if (err) { 1043 mlx5_core_err(dev, "init hca failed\n"); 1044 goto reclaim_boot_pages; 1045 } 1046 1047 mlx5_set_driver_version(dev); 1048 1049 mlx5_start_health_poll(dev); 1050 1051 err = mlx5_query_hca_caps(dev); 1052 if (err) { 1053 mlx5_core_err(dev, "query hca failed\n"); 1054 goto stop_health; 1055 } 1056 1057 return 0; 1058 1059 stop_health: 1060 mlx5_stop_health_poll(dev, boot); 1061 reclaim_boot_pages: 1062 mlx5_reclaim_startup_pages(dev); 1063 err_disable_hca: 1064 mlx5_core_disable_hca(dev, 0); 1065 err_cmd_cleanup: 1066 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1067 mlx5_cmd_cleanup(dev); 1068 err_tout_cleanup: 1069 mlx5_tout_cleanup(dev); 1070 1071 return err; 1072 } 1073 1074 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1075 { 1076 int err; 1077 1078 mlx5_stop_health_poll(dev, boot); 1079 err = mlx5_cmd_teardown_hca(dev); 1080 if (err) { 1081 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1082 return err; 1083 } 1084 mlx5_reclaim_startup_pages(dev); 1085 mlx5_core_disable_hca(dev, 0); 1086 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1087 mlx5_cmd_cleanup(dev); 1088 mlx5_tout_cleanup(dev); 1089 1090 return 0; 1091 } 1092 1093 static int mlx5_load(struct mlx5_core_dev *dev) 1094 { 1095 int err; 1096 1097 dev->priv.uar = mlx5_get_uars_page(dev); 1098 if (IS_ERR(dev->priv.uar)) { 1099 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1100 err = PTR_ERR(dev->priv.uar); 1101 return err; 1102 } 1103 1104 mlx5_events_start(dev); 1105 mlx5_pagealloc_start(dev); 1106 1107 err = mlx5_irq_table_create(dev); 1108 if (err) { 1109 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1110 goto err_irq_table; 1111 } 1112 1113 err = mlx5_eq_table_create(dev); 1114 if (err) { 1115 mlx5_core_err(dev, "Failed to create EQs\n"); 1116 goto err_eq_table; 1117 } 1118 1119 err = mlx5_fw_tracer_init(dev->tracer); 1120 if (err) { 1121 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1122 mlx5_fw_tracer_destroy(dev->tracer); 1123 dev->tracer = NULL; 1124 } 1125 1126 mlx5_fw_reset_events_start(dev); 1127 mlx5_hv_vhca_init(dev->hv_vhca); 1128 1129 err = mlx5_rsc_dump_init(dev); 1130 if (err) { 1131 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1132 mlx5_rsc_dump_destroy(dev); 1133 dev->rsc_dump = NULL; 1134 } 1135 1136 err = mlx5_fpga_device_start(dev); 1137 if (err) { 1138 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1139 goto err_fpga_start; 1140 } 1141 1142 mlx5_accel_ipsec_init(dev); 1143 1144 err = mlx5_accel_tls_init(dev); 1145 if (err) { 1146 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1147 goto err_tls_start; 1148 } 1149 1150 err = mlx5_init_fs(dev); 1151 if (err) { 1152 mlx5_core_err(dev, "Failed to init flow steering\n"); 1153 goto err_fs; 1154 } 1155 1156 err = mlx5_core_set_hca_defaults(dev); 1157 if (err) { 1158 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1159 goto err_set_hca; 1160 } 1161 1162 mlx5_vhca_event_start(dev); 1163 1164 err = mlx5_sf_hw_table_create(dev); 1165 if (err) { 1166 mlx5_core_err(dev, "sf table create failed %d\n", err); 1167 goto err_vhca; 1168 } 1169 1170 err = mlx5_ec_init(dev); 1171 if (err) { 1172 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1173 goto err_ec; 1174 } 1175 1176 mlx5_lag_add_mdev(dev); 1177 err = mlx5_sriov_attach(dev); 1178 if (err) { 1179 mlx5_core_err(dev, "sriov init failed %d\n", err); 1180 goto err_sriov; 1181 } 1182 1183 mlx5_sf_dev_table_create(dev); 1184 1185 return 0; 1186 1187 err_sriov: 1188 mlx5_lag_remove_mdev(dev); 1189 mlx5_ec_cleanup(dev); 1190 err_ec: 1191 mlx5_sf_hw_table_destroy(dev); 1192 err_vhca: 1193 mlx5_vhca_event_stop(dev); 1194 err_set_hca: 1195 mlx5_cleanup_fs(dev); 1196 err_fs: 1197 mlx5_accel_tls_cleanup(dev); 1198 err_tls_start: 1199 mlx5_accel_ipsec_cleanup(dev); 1200 mlx5_fpga_device_stop(dev); 1201 err_fpga_start: 1202 mlx5_rsc_dump_cleanup(dev); 1203 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1204 mlx5_fw_reset_events_stop(dev); 1205 mlx5_fw_tracer_cleanup(dev->tracer); 1206 mlx5_eq_table_destroy(dev); 1207 err_eq_table: 1208 mlx5_irq_table_destroy(dev); 1209 err_irq_table: 1210 mlx5_pagealloc_stop(dev); 1211 mlx5_events_stop(dev); 1212 mlx5_put_uars_page(dev, dev->priv.uar); 1213 return err; 1214 } 1215 1216 static void mlx5_unload(struct mlx5_core_dev *dev) 1217 { 1218 mlx5_sf_dev_table_destroy(dev); 1219 mlx5_sriov_detach(dev); 1220 mlx5_lag_remove_mdev(dev); 1221 mlx5_ec_cleanup(dev); 1222 mlx5_sf_hw_table_destroy(dev); 1223 mlx5_vhca_event_stop(dev); 1224 mlx5_cleanup_fs(dev); 1225 mlx5_accel_ipsec_cleanup(dev); 1226 mlx5_accel_tls_cleanup(dev); 1227 mlx5_fpga_device_stop(dev); 1228 mlx5_rsc_dump_cleanup(dev); 1229 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1230 mlx5_fw_reset_events_stop(dev); 1231 mlx5_fw_tracer_cleanup(dev->tracer); 1232 mlx5_eq_table_destroy(dev); 1233 mlx5_irq_table_destroy(dev); 1234 mlx5_pagealloc_stop(dev); 1235 mlx5_events_stop(dev); 1236 mlx5_put_uars_page(dev, dev->priv.uar); 1237 } 1238 1239 int mlx5_init_one(struct mlx5_core_dev *dev) 1240 { 1241 int err = 0; 1242 1243 mutex_lock(&dev->intf_state_mutex); 1244 dev->state = MLX5_DEVICE_STATE_UP; 1245 1246 err = mlx5_function_setup(dev, true); 1247 if (err) 1248 goto err_function; 1249 1250 err = mlx5_init_once(dev); 1251 if (err) { 1252 mlx5_core_err(dev, "sw objs init failed\n"); 1253 goto function_teardown; 1254 } 1255 1256 err = mlx5_load(dev); 1257 if (err) 1258 goto err_load; 1259 1260 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1261 1262 err = mlx5_devlink_register(priv_to_devlink(dev)); 1263 if (err) 1264 goto err_devlink_reg; 1265 1266 err = mlx5_register_device(dev); 1267 if (err) 1268 goto err_register; 1269 1270 mutex_unlock(&dev->intf_state_mutex); 1271 return 0; 1272 1273 err_register: 1274 mlx5_devlink_unregister(priv_to_devlink(dev)); 1275 err_devlink_reg: 1276 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1277 mlx5_unload(dev); 1278 err_load: 1279 mlx5_cleanup_once(dev); 1280 function_teardown: 1281 mlx5_function_teardown(dev, true); 1282 err_function: 1283 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1284 mutex_unlock(&dev->intf_state_mutex); 1285 return err; 1286 } 1287 1288 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1289 { 1290 mutex_lock(&dev->intf_state_mutex); 1291 1292 mlx5_unregister_device(dev); 1293 mlx5_devlink_unregister(priv_to_devlink(dev)); 1294 1295 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1296 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1297 __func__); 1298 mlx5_cleanup_once(dev); 1299 goto out; 1300 } 1301 1302 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1303 mlx5_unload(dev); 1304 mlx5_cleanup_once(dev); 1305 mlx5_function_teardown(dev, true); 1306 out: 1307 mutex_unlock(&dev->intf_state_mutex); 1308 } 1309 1310 int mlx5_load_one(struct mlx5_core_dev *dev) 1311 { 1312 int err = 0; 1313 1314 mutex_lock(&dev->intf_state_mutex); 1315 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1316 mlx5_core_warn(dev, "interface is up, NOP\n"); 1317 goto out; 1318 } 1319 /* remove any previous indication of internal error */ 1320 dev->state = MLX5_DEVICE_STATE_UP; 1321 1322 err = mlx5_function_setup(dev, false); 1323 if (err) 1324 goto err_function; 1325 1326 err = mlx5_load(dev); 1327 if (err) 1328 goto err_load; 1329 1330 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1331 1332 err = mlx5_attach_device(dev); 1333 if (err) 1334 goto err_attach; 1335 1336 mutex_unlock(&dev->intf_state_mutex); 1337 return 0; 1338 1339 err_attach: 1340 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1341 mlx5_unload(dev); 1342 err_load: 1343 mlx5_function_teardown(dev, false); 1344 err_function: 1345 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1346 out: 1347 mutex_unlock(&dev->intf_state_mutex); 1348 return err; 1349 } 1350 1351 void mlx5_unload_one(struct mlx5_core_dev *dev) 1352 { 1353 mutex_lock(&dev->intf_state_mutex); 1354 1355 mlx5_detach_device(dev); 1356 1357 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1358 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1359 __func__); 1360 goto out; 1361 } 1362 1363 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1364 mlx5_unload(dev); 1365 mlx5_function_teardown(dev, false); 1366 out: 1367 mutex_unlock(&dev->intf_state_mutex); 1368 } 1369 1370 static const int types[] = { 1371 MLX5_CAP_GENERAL, 1372 MLX5_CAP_GENERAL_2, 1373 MLX5_CAP_ETHERNET_OFFLOADS, 1374 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1375 MLX5_CAP_ODP, 1376 MLX5_CAP_ATOMIC, 1377 MLX5_CAP_ROCE, 1378 MLX5_CAP_IPOIB_OFFLOADS, 1379 MLX5_CAP_FLOW_TABLE, 1380 MLX5_CAP_ESWITCH_FLOW_TABLE, 1381 MLX5_CAP_ESWITCH, 1382 MLX5_CAP_VECTOR_CALC, 1383 MLX5_CAP_QOS, 1384 MLX5_CAP_DEBUG, 1385 MLX5_CAP_DEV_MEM, 1386 MLX5_CAP_DEV_EVENT, 1387 MLX5_CAP_TLS, 1388 MLX5_CAP_VDPA_EMULATION, 1389 MLX5_CAP_IPSEC, 1390 }; 1391 1392 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1393 { 1394 int type; 1395 int i; 1396 1397 for (i = 0; i < ARRAY_SIZE(types); i++) { 1398 type = types[i]; 1399 kfree(dev->caps.hca[type]); 1400 } 1401 } 1402 1403 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1404 { 1405 struct mlx5_hca_cap *cap; 1406 int type; 1407 int i; 1408 1409 for (i = 0; i < ARRAY_SIZE(types); i++) { 1410 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1411 if (!cap) 1412 goto err; 1413 type = types[i]; 1414 dev->caps.hca[type] = cap; 1415 } 1416 1417 return 0; 1418 1419 err: 1420 mlx5_hca_caps_free(dev); 1421 return -ENOMEM; 1422 } 1423 1424 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1425 { 1426 struct mlx5_priv *priv = &dev->priv; 1427 int err; 1428 1429 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1430 INIT_LIST_HEAD(&priv->ctx_list); 1431 spin_lock_init(&priv->ctx_lock); 1432 mutex_init(&dev->intf_state_mutex); 1433 1434 mutex_init(&priv->bfregs.reg_head.lock); 1435 mutex_init(&priv->bfregs.wc_head.lock); 1436 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1437 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1438 1439 mutex_init(&priv->alloc_mutex); 1440 mutex_init(&priv->pgdir_mutex); 1441 INIT_LIST_HEAD(&priv->pgdir_list); 1442 1443 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1444 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1445 mlx5_debugfs_root); 1446 INIT_LIST_HEAD(&priv->traps); 1447 1448 err = mlx5_health_init(dev); 1449 if (err) 1450 goto err_health_init; 1451 1452 err = mlx5_pagealloc_init(dev); 1453 if (err) 1454 goto err_pagealloc_init; 1455 1456 err = mlx5_adev_init(dev); 1457 if (err) 1458 goto err_adev_init; 1459 1460 err = mlx5_hca_caps_alloc(dev); 1461 if (err) 1462 goto err_hca_caps; 1463 1464 return 0; 1465 1466 err_hca_caps: 1467 mlx5_adev_cleanup(dev); 1468 err_adev_init: 1469 mlx5_pagealloc_cleanup(dev); 1470 err_pagealloc_init: 1471 mlx5_health_cleanup(dev); 1472 err_health_init: 1473 debugfs_remove(dev->priv.dbg_root); 1474 mutex_destroy(&priv->pgdir_mutex); 1475 mutex_destroy(&priv->alloc_mutex); 1476 mutex_destroy(&priv->bfregs.wc_head.lock); 1477 mutex_destroy(&priv->bfregs.reg_head.lock); 1478 mutex_destroy(&dev->intf_state_mutex); 1479 return err; 1480 } 1481 1482 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1483 { 1484 struct mlx5_priv *priv = &dev->priv; 1485 1486 mlx5_hca_caps_free(dev); 1487 mlx5_adev_cleanup(dev); 1488 mlx5_pagealloc_cleanup(dev); 1489 mlx5_health_cleanup(dev); 1490 debugfs_remove_recursive(dev->priv.dbg_root); 1491 mutex_destroy(&priv->pgdir_mutex); 1492 mutex_destroy(&priv->alloc_mutex); 1493 mutex_destroy(&priv->bfregs.wc_head.lock); 1494 mutex_destroy(&priv->bfregs.reg_head.lock); 1495 mutex_destroy(&dev->intf_state_mutex); 1496 } 1497 1498 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1499 { 1500 struct mlx5_core_dev *dev; 1501 struct devlink *devlink; 1502 int err; 1503 1504 devlink = mlx5_devlink_alloc(&pdev->dev); 1505 if (!devlink) { 1506 dev_err(&pdev->dev, "devlink alloc failed\n"); 1507 return -ENOMEM; 1508 } 1509 1510 dev = devlink_priv(devlink); 1511 dev->device = &pdev->dev; 1512 dev->pdev = pdev; 1513 1514 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1515 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1516 1517 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1518 if (dev->priv.adev_idx < 0) { 1519 err = dev->priv.adev_idx; 1520 goto adev_init_err; 1521 } 1522 1523 err = mlx5_mdev_init(dev, prof_sel); 1524 if (err) 1525 goto mdev_init_err; 1526 1527 err = mlx5_pci_init(dev, pdev, id); 1528 if (err) { 1529 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1530 err); 1531 goto pci_init_err; 1532 } 1533 1534 err = mlx5_init_one(dev); 1535 if (err) { 1536 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1537 err); 1538 goto err_init_one; 1539 } 1540 1541 err = mlx5_crdump_enable(dev); 1542 if (err) 1543 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1544 1545 pci_save_state(pdev); 1546 devlink_register(devlink); 1547 return 0; 1548 1549 err_init_one: 1550 mlx5_pci_close(dev); 1551 pci_init_err: 1552 mlx5_mdev_uninit(dev); 1553 mdev_init_err: 1554 mlx5_adev_idx_free(dev->priv.adev_idx); 1555 adev_init_err: 1556 mlx5_devlink_free(devlink); 1557 1558 return err; 1559 } 1560 1561 static void remove_one(struct pci_dev *pdev) 1562 { 1563 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1564 struct devlink *devlink = priv_to_devlink(dev); 1565 1566 devlink_unregister(devlink); 1567 mlx5_crdump_disable(dev); 1568 mlx5_drain_health_wq(dev); 1569 mlx5_uninit_one(dev); 1570 mlx5_pci_close(dev); 1571 mlx5_mdev_uninit(dev); 1572 mlx5_adev_idx_free(dev->priv.adev_idx); 1573 mlx5_devlink_free(devlink); 1574 } 1575 1576 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1577 pci_channel_state_t state) 1578 { 1579 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1580 1581 mlx5_core_info(dev, "%s was called\n", __func__); 1582 1583 mlx5_enter_error_state(dev, false); 1584 mlx5_error_sw_reset(dev); 1585 mlx5_unload_one(dev); 1586 mlx5_drain_health_wq(dev); 1587 mlx5_pci_disable_device(dev); 1588 1589 return state == pci_channel_io_perm_failure ? 1590 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1591 } 1592 1593 /* wait for the device to show vital signs by waiting 1594 * for the health counter to start counting. 1595 */ 1596 static int wait_vital(struct pci_dev *pdev) 1597 { 1598 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1599 struct mlx5_core_health *health = &dev->priv.health; 1600 const int niter = 100; 1601 u32 last_count = 0; 1602 u32 count; 1603 int i; 1604 1605 for (i = 0; i < niter; i++) { 1606 count = ioread32be(health->health_counter); 1607 if (count && count != 0xffffffff) { 1608 if (last_count && last_count != count) { 1609 mlx5_core_info(dev, 1610 "wait vital counter value 0x%x after %d iterations\n", 1611 count, i); 1612 return 0; 1613 } 1614 last_count = count; 1615 } 1616 msleep(50); 1617 } 1618 1619 return -ETIMEDOUT; 1620 } 1621 1622 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1623 { 1624 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1625 int err; 1626 1627 mlx5_core_info(dev, "%s was called\n", __func__); 1628 1629 err = mlx5_pci_enable_device(dev); 1630 if (err) { 1631 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1632 __func__, err); 1633 return PCI_ERS_RESULT_DISCONNECT; 1634 } 1635 1636 pci_set_master(pdev); 1637 pci_restore_state(pdev); 1638 pci_save_state(pdev); 1639 1640 if (wait_vital(pdev)) { 1641 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1642 return PCI_ERS_RESULT_DISCONNECT; 1643 } 1644 1645 return PCI_ERS_RESULT_RECOVERED; 1646 } 1647 1648 static void mlx5_pci_resume(struct pci_dev *pdev) 1649 { 1650 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1651 int err; 1652 1653 mlx5_core_info(dev, "%s was called\n", __func__); 1654 1655 err = mlx5_load_one(dev); 1656 if (err) 1657 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1658 __func__, err); 1659 else 1660 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1661 } 1662 1663 static const struct pci_error_handlers mlx5_err_handler = { 1664 .error_detected = mlx5_pci_err_detected, 1665 .slot_reset = mlx5_pci_slot_reset, 1666 .resume = mlx5_pci_resume 1667 }; 1668 1669 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1670 { 1671 bool fast_teardown = false, force_teardown = false; 1672 int ret = 1; 1673 1674 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1675 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1676 1677 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1678 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1679 1680 if (!fast_teardown && !force_teardown) 1681 return -EOPNOTSUPP; 1682 1683 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1684 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1685 return -EAGAIN; 1686 } 1687 1688 /* Panic tear down fw command will stop the PCI bus communication 1689 * with the HCA, so the health polll is no longer needed. 1690 */ 1691 mlx5_drain_health_wq(dev); 1692 mlx5_stop_health_poll(dev, false); 1693 1694 ret = mlx5_cmd_fast_teardown_hca(dev); 1695 if (!ret) 1696 goto succeed; 1697 1698 ret = mlx5_cmd_force_teardown_hca(dev); 1699 if (!ret) 1700 goto succeed; 1701 1702 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1703 mlx5_start_health_poll(dev); 1704 return ret; 1705 1706 succeed: 1707 mlx5_enter_error_state(dev, true); 1708 1709 /* Some platforms requiring freeing the IRQ's in the shutdown 1710 * flow. If they aren't freed they can't be allocated after 1711 * kexec. There is no need to cleanup the mlx5_core software 1712 * contexts. 1713 */ 1714 mlx5_core_eq_free_irqs(dev); 1715 1716 return 0; 1717 } 1718 1719 static void shutdown(struct pci_dev *pdev) 1720 { 1721 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1722 int err; 1723 1724 mlx5_core_info(dev, "Shutdown was called\n"); 1725 err = mlx5_try_fast_unload(dev); 1726 if (err) 1727 mlx5_unload_one(dev); 1728 mlx5_pci_disable_device(dev); 1729 } 1730 1731 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1732 { 1733 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1734 1735 mlx5_unload_one(dev); 1736 1737 return 0; 1738 } 1739 1740 static int mlx5_resume(struct pci_dev *pdev) 1741 { 1742 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1743 1744 return mlx5_load_one(dev); 1745 } 1746 1747 static const struct pci_device_id mlx5_core_pci_table[] = { 1748 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1749 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1750 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1751 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1752 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1753 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1754 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1755 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1756 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1757 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1758 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1759 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1760 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1761 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1762 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1763 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1764 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1765 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1766 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1767 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1768 { 0, } 1769 }; 1770 1771 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1772 1773 void mlx5_disable_device(struct mlx5_core_dev *dev) 1774 { 1775 mlx5_error_sw_reset(dev); 1776 mlx5_unload_one(dev); 1777 } 1778 1779 int mlx5_recover_device(struct mlx5_core_dev *dev) 1780 { 1781 int ret = -EIO; 1782 1783 mlx5_pci_disable_device(dev); 1784 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1785 ret = mlx5_load_one(dev); 1786 return ret; 1787 } 1788 1789 static struct pci_driver mlx5_core_driver = { 1790 .name = KBUILD_MODNAME, 1791 .id_table = mlx5_core_pci_table, 1792 .probe = probe_one, 1793 .remove = remove_one, 1794 .suspend = mlx5_suspend, 1795 .resume = mlx5_resume, 1796 .shutdown = shutdown, 1797 .err_handler = &mlx5_err_handler, 1798 .sriov_configure = mlx5_core_sriov_configure, 1799 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1800 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 1801 }; 1802 1803 static void mlx5_core_verify_params(void) 1804 { 1805 if (prof_sel >= ARRAY_SIZE(profile)) { 1806 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1807 prof_sel, 1808 ARRAY_SIZE(profile) - 1, 1809 MLX5_DEFAULT_PROF); 1810 prof_sel = MLX5_DEFAULT_PROF; 1811 } 1812 } 1813 1814 static int __init init(void) 1815 { 1816 int err; 1817 1818 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 1819 "mlx5_core name not in sync with kernel module name"); 1820 1821 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1822 1823 mlx5_core_verify_params(); 1824 mlx5_fpga_ipsec_build_fs_cmds(); 1825 mlx5_register_debugfs(); 1826 1827 err = pci_register_driver(&mlx5_core_driver); 1828 if (err) 1829 goto err_debug; 1830 1831 err = mlx5_sf_driver_register(); 1832 if (err) 1833 goto err_sf; 1834 1835 err = mlx5e_init(); 1836 if (err) 1837 goto err_en; 1838 1839 return 0; 1840 1841 err_en: 1842 mlx5_sf_driver_unregister(); 1843 err_sf: 1844 pci_unregister_driver(&mlx5_core_driver); 1845 err_debug: 1846 mlx5_unregister_debugfs(); 1847 return err; 1848 } 1849 1850 static void __exit cleanup(void) 1851 { 1852 mlx5e_cleanup(); 1853 mlx5_sf_driver_unregister(); 1854 pci_unregister_driver(&mlx5_core_driver); 1855 mlx5_unregister_debugfs(); 1856 } 1857 1858 module_init(init); 1859 module_exit(cleanup); 1860