1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/interrupt.h> 41 #include <linux/delay.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/cq.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/debugfs.h> 46 #include <linux/kmod.h> 47 #include <linux/mlx5/mlx5_ifc.h> 48 #include <linux/mlx5/vport.h> 49 #ifdef CONFIG_RFS_ACCEL 50 #include <linux/cpu_rmap.h> 51 #endif 52 #include <linux/version.h> 53 #include <net/devlink.h> 54 #include "mlx5_core.h" 55 #include "lib/eq.h" 56 #include "fs_core.h" 57 #include "lib/mpfs.h" 58 #include "eswitch.h" 59 #include "devlink.h" 60 #include "fw_reset.h" 61 #include "lib/mlx5.h" 62 #include "lib/tout.h" 63 #include "fpga/core.h" 64 #include "en_accel/ipsec.h" 65 #include "lib/clock.h" 66 #include "lib/vxlan.h" 67 #include "lib/geneve.h" 68 #include "lib/devcom.h" 69 #include "lib/pci_vsc.h" 70 #include "diag/fw_tracer.h" 71 #include "ecpf.h" 72 #include "lib/hv_vhca.h" 73 #include "diag/rsc_dump.h" 74 #include "sf/vhca_event.h" 75 #include "sf/dev/dev.h" 76 #include "sf/sf.h" 77 #include "mlx5_irq.h" 78 79 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 80 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 81 MODULE_LICENSE("Dual BSD/GPL"); 82 83 unsigned int mlx5_core_debug_mask; 84 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 85 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 86 87 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 88 module_param_named(prof_sel, prof_sel, uint, 0444); 89 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 90 91 static u32 sw_owner_id[4]; 92 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 93 static DEFINE_IDA(sw_vhca_ida); 94 95 enum { 96 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 98 }; 99 100 #define LOG_MAX_SUPPORTED_QPS 0xff 101 102 static struct mlx5_profile profile[] = { 103 [0] = { 104 .mask = 0, 105 }, 106 [1] = { 107 .mask = MLX5_PROF_MASK_QP_SIZE, 108 .log_max_qp = 12, 109 }, 110 [2] = { 111 .mask = MLX5_PROF_MASK_QP_SIZE | 112 MLX5_PROF_MASK_MR_CACHE, 113 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 114 .mr_cache[0] = { 115 .size = 500, 116 .limit = 250 117 }, 118 .mr_cache[1] = { 119 .size = 500, 120 .limit = 250 121 }, 122 .mr_cache[2] = { 123 .size = 500, 124 .limit = 250 125 }, 126 .mr_cache[3] = { 127 .size = 500, 128 .limit = 250 129 }, 130 .mr_cache[4] = { 131 .size = 500, 132 .limit = 250 133 }, 134 .mr_cache[5] = { 135 .size = 500, 136 .limit = 250 137 }, 138 .mr_cache[6] = { 139 .size = 500, 140 .limit = 250 141 }, 142 .mr_cache[7] = { 143 .size = 500, 144 .limit = 250 145 }, 146 .mr_cache[8] = { 147 .size = 500, 148 .limit = 250 149 }, 150 .mr_cache[9] = { 151 .size = 500, 152 .limit = 250 153 }, 154 .mr_cache[10] = { 155 .size = 500, 156 .limit = 250 157 }, 158 .mr_cache[11] = { 159 .size = 500, 160 .limit = 250 161 }, 162 .mr_cache[12] = { 163 .size = 64, 164 .limit = 32 165 }, 166 .mr_cache[13] = { 167 .size = 32, 168 .limit = 16 169 }, 170 .mr_cache[14] = { 171 .size = 16, 172 .limit = 8 173 }, 174 .mr_cache[15] = { 175 .size = 8, 176 .limit = 4 177 }, 178 }, 179 }; 180 181 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 182 u32 warn_time_mili) 183 { 184 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 185 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 186 u32 fw_initializing; 187 int err = 0; 188 189 do { 190 fw_initializing = ioread32be(&dev->iseg->initializing); 191 if (!(fw_initializing >> 31)) 192 break; 193 if (time_after(jiffies, end) || 194 test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 195 err = -EBUSY; 196 break; 197 } 198 if (warn_time_mili && time_after(jiffies, warn)) { 199 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 200 jiffies_to_msecs(end - warn) / 1000, fw_initializing); 201 warn = jiffies + msecs_to_jiffies(warn_time_mili); 202 } 203 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 204 } while (true); 205 206 return err; 207 } 208 209 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 210 { 211 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 212 driver_version); 213 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 214 int remaining_size = driver_ver_sz; 215 char *string; 216 217 if (!MLX5_CAP_GEN(dev, driver_version)) 218 return; 219 220 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 221 222 strncpy(string, "Linux", remaining_size); 223 224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 225 strncat(string, ",", remaining_size); 226 227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 228 strncat(string, KBUILD_MODNAME, remaining_size); 229 230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 231 strncat(string, ",", remaining_size); 232 233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 234 235 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 236 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 237 LINUX_VERSION_SUBLEVEL); 238 239 /*Send the command*/ 240 MLX5_SET(set_driver_version_in, in, opcode, 241 MLX5_CMD_OP_SET_DRIVER_VERSION); 242 243 mlx5_cmd_exec_in(dev, set_driver_version, in); 244 } 245 246 static int set_dma_caps(struct pci_dev *pdev) 247 { 248 int err; 249 250 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 251 if (err) { 252 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 253 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 254 if (err) { 255 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 256 return err; 257 } 258 } 259 260 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 261 return err; 262 } 263 264 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 265 { 266 struct pci_dev *pdev = dev->pdev; 267 int err = 0; 268 269 mutex_lock(&dev->pci_status_mutex); 270 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 271 err = pci_enable_device(pdev); 272 if (!err) 273 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 274 } 275 mutex_unlock(&dev->pci_status_mutex); 276 277 return err; 278 } 279 280 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 281 { 282 struct pci_dev *pdev = dev->pdev; 283 284 mutex_lock(&dev->pci_status_mutex); 285 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 286 pci_disable_device(pdev); 287 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 288 } 289 mutex_unlock(&dev->pci_status_mutex); 290 } 291 292 static int request_bar(struct pci_dev *pdev) 293 { 294 int err = 0; 295 296 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 297 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 298 return -ENODEV; 299 } 300 301 err = pci_request_regions(pdev, KBUILD_MODNAME); 302 if (err) 303 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 304 305 return err; 306 } 307 308 static void release_bar(struct pci_dev *pdev) 309 { 310 pci_release_regions(pdev); 311 } 312 313 struct mlx5_reg_host_endianness { 314 u8 he; 315 u8 rsvd[15]; 316 }; 317 318 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 319 { 320 switch (size) { 321 case 128: 322 return 0; 323 case 256: 324 return 1; 325 case 512: 326 return 2; 327 case 1024: 328 return 3; 329 case 2048: 330 return 4; 331 case 4096: 332 return 5; 333 default: 334 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 335 return 0; 336 } 337 } 338 339 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 340 enum mlx5_cap_type cap_type, 341 enum mlx5_cap_mode cap_mode) 342 { 343 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 344 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 345 void *out, *hca_caps; 346 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 347 int err; 348 349 memset(in, 0, sizeof(in)); 350 out = kzalloc(out_sz, GFP_KERNEL); 351 if (!out) 352 return -ENOMEM; 353 354 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 355 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 356 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 357 if (err) { 358 mlx5_core_warn(dev, 359 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 360 cap_type, cap_mode, err); 361 goto query_ex; 362 } 363 364 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 365 366 switch (cap_mode) { 367 case HCA_CAP_OPMOD_GET_MAX: 368 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 369 MLX5_UN_SZ_BYTES(hca_cap_union)); 370 break; 371 case HCA_CAP_OPMOD_GET_CUR: 372 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 373 MLX5_UN_SZ_BYTES(hca_cap_union)); 374 break; 375 default: 376 mlx5_core_warn(dev, 377 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 378 cap_type, cap_mode); 379 err = -EINVAL; 380 break; 381 } 382 query_ex: 383 kfree(out); 384 return err; 385 } 386 387 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 388 { 389 int ret; 390 391 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 392 if (ret) 393 return ret; 394 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 395 } 396 397 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 398 { 399 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 400 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 401 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 402 } 403 404 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 405 { 406 void *set_hca_cap; 407 int req_endianness; 408 int err; 409 410 if (!MLX5_CAP_GEN(dev, atomic)) 411 return 0; 412 413 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 414 if (err) 415 return err; 416 417 req_endianness = 418 MLX5_CAP_ATOMIC(dev, 419 supported_atomic_req_8B_endianness_mode_1); 420 421 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 422 return 0; 423 424 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 425 426 /* Set requestor to host endianness */ 427 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 428 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 429 430 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 431 } 432 433 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 434 { 435 void *set_hca_cap; 436 bool do_set = false; 437 int err; 438 439 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 440 !MLX5_CAP_GEN(dev, pg)) 441 return 0; 442 443 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 444 if (err) 445 return err; 446 447 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 448 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 449 MLX5_ST_SZ_BYTES(odp_cap)); 450 451 #define ODP_CAP_SET_MAX(dev, field) \ 452 do { \ 453 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 454 if (_res) { \ 455 do_set = true; \ 456 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 457 } \ 458 } while (0) 459 460 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 461 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 462 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 463 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 464 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 465 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 466 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 467 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 468 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 469 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 470 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 471 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 472 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 473 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 474 475 if (!do_set) 476 return 0; 477 478 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 479 } 480 481 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 482 { 483 struct devlink *devlink = priv_to_devlink(dev); 484 union devlink_param_value val; 485 int err; 486 487 err = devlink_param_driverinit_value_get(devlink, 488 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 489 &val); 490 if (!err) 491 return val.vu32; 492 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 493 return err; 494 } 495 496 bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 497 { 498 struct devlink *devlink = priv_to_devlink(dev); 499 union devlink_param_value val; 500 int err; 501 502 err = devlink_param_driverinit_value_get(devlink, 503 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 504 &val); 505 506 if (!err) 507 return val.vbool; 508 509 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 510 return MLX5_CAP_GEN(dev, roce); 511 } 512 EXPORT_SYMBOL(mlx5_is_roce_on); 513 514 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 515 { 516 void *set_hca_cap; 517 int err; 518 519 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 520 return 0; 521 522 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 523 if (err) 524 return err; 525 526 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 527 !(dev->priv.sw_vhca_id > 0)) 528 return 0; 529 530 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 531 capability); 532 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 533 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 534 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 535 536 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 537 } 538 539 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 540 { 541 struct mlx5_profile *prof = &dev->profile; 542 void *set_hca_cap; 543 int max_uc_list; 544 int err; 545 546 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 547 if (err) 548 return err; 549 550 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 551 capability); 552 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 553 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 554 555 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 556 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 557 128); 558 /* we limit the size of the pkey table to 128 entries for now */ 559 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 560 to_fw_pkey_sz(dev, 128)); 561 562 /* Check log_max_qp from HCA caps to set in current profile */ 563 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 564 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 565 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 566 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 567 prof->log_max_qp, 568 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 569 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 570 } 571 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 572 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 573 prof->log_max_qp); 574 575 /* disable cmdif checksum */ 576 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 577 578 /* Enable 4K UAR only when HCA supports it and page size is bigger 579 * than 4K. 580 */ 581 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 582 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 583 584 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 585 586 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 587 MLX5_SET(cmd_hca_cap, 588 set_hca_cap, 589 cache_line_128byte, 590 cache_line_size() >= 128 ? 1 : 0); 591 592 if (MLX5_CAP_GEN_MAX(dev, dct)) 593 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 594 595 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 596 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 597 598 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 599 MLX5_SET(cmd_hca_cap, 600 set_hca_cap, 601 num_vhca_ports, 602 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 603 604 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 605 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 606 607 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 608 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 609 610 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 611 612 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 613 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 614 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 615 616 if (MLX5_CAP_GEN(dev, roce_rw_supported)) 617 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 618 mlx5_is_roce_on(dev)); 619 620 max_uc_list = max_uc_list_get_devlink_param(dev); 621 if (max_uc_list > 0) 622 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 623 ilog2(max_uc_list)); 624 625 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 626 } 627 628 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 629 * boot process. 630 * In case RoCE cap is writable in FW and user/devlink requested to change the 631 * cap, we are yet to query the final state of the above cap. 632 * Hence, the need for this function. 633 * 634 * Returns 635 * True: 636 * 1) RoCE cap is read only in FW and already disabled 637 * OR: 638 * 2) RoCE cap is writable in FW and user/devlink requested it off. 639 * 640 * In any other case, return False. 641 */ 642 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 643 { 644 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 645 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 646 } 647 648 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 649 { 650 void *set_hca_cap; 651 int err; 652 653 if (is_roce_fw_disabled(dev)) 654 return 0; 655 656 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 657 if (err) 658 return err; 659 660 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 661 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 662 return 0; 663 664 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 665 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 666 MLX5_ST_SZ_BYTES(roce_cap)); 667 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 668 669 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 670 return err; 671 } 672 673 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 674 void *set_ctx) 675 { 676 void *set_hca_cap; 677 int err; 678 679 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 680 return 0; 681 682 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 683 if (err) 684 return err; 685 686 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 687 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 688 return 0; 689 690 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 691 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 692 MLX5_ST_SZ_BYTES(port_selection_cap)); 693 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 694 695 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION); 696 697 return err; 698 } 699 700 static int set_hca_cap(struct mlx5_core_dev *dev) 701 { 702 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 703 void *set_ctx; 704 int err; 705 706 set_ctx = kzalloc(set_sz, GFP_KERNEL); 707 if (!set_ctx) 708 return -ENOMEM; 709 710 err = handle_hca_cap(dev, set_ctx); 711 if (err) { 712 mlx5_core_err(dev, "handle_hca_cap failed\n"); 713 goto out; 714 } 715 716 memset(set_ctx, 0, set_sz); 717 err = handle_hca_cap_atomic(dev, set_ctx); 718 if (err) { 719 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 720 goto out; 721 } 722 723 memset(set_ctx, 0, set_sz); 724 err = handle_hca_cap_odp(dev, set_ctx); 725 if (err) { 726 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 727 goto out; 728 } 729 730 memset(set_ctx, 0, set_sz); 731 err = handle_hca_cap_roce(dev, set_ctx); 732 if (err) { 733 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 734 goto out; 735 } 736 737 memset(set_ctx, 0, set_sz); 738 err = handle_hca_cap_2(dev, set_ctx); 739 if (err) { 740 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 741 goto out; 742 } 743 744 memset(set_ctx, 0, set_sz); 745 err = handle_hca_cap_port_selection(dev, set_ctx); 746 if (err) { 747 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 748 goto out; 749 } 750 751 out: 752 kfree(set_ctx); 753 return err; 754 } 755 756 static int set_hca_ctrl(struct mlx5_core_dev *dev) 757 { 758 struct mlx5_reg_host_endianness he_in; 759 struct mlx5_reg_host_endianness he_out; 760 int err; 761 762 if (!mlx5_core_is_pf(dev)) 763 return 0; 764 765 memset(&he_in, 0, sizeof(he_in)); 766 he_in.he = MLX5_SET_HOST_ENDIANNESS; 767 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 768 &he_out, sizeof(he_out), 769 MLX5_REG_HOST_ENDIANNESS, 0, 1); 770 return err; 771 } 772 773 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 774 { 775 int ret = 0; 776 777 /* Disable local_lb by default */ 778 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 779 ret = mlx5_nic_vport_update_local_lb(dev, false); 780 781 return ret; 782 } 783 784 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 785 { 786 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 787 788 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 789 MLX5_SET(enable_hca_in, in, function_id, func_id); 790 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 791 dev->caps.embedded_cpu); 792 return mlx5_cmd_exec_in(dev, enable_hca, in); 793 } 794 795 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 796 { 797 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 798 799 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 800 MLX5_SET(disable_hca_in, in, function_id, func_id); 801 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 802 dev->caps.embedded_cpu); 803 return mlx5_cmd_exec_in(dev, disable_hca, in); 804 } 805 806 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 807 { 808 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 809 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 810 u32 sup_issi; 811 int err; 812 813 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 814 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 815 if (err) { 816 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 817 u8 status = MLX5_GET(query_issi_out, query_out, status); 818 819 if (!status || syndrome == MLX5_DRIVER_SYND) { 820 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 821 err, status, syndrome); 822 return err; 823 } 824 825 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 826 dev->issi = 0; 827 return 0; 828 } 829 830 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 831 832 if (sup_issi & (1 << 1)) { 833 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 834 835 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 836 MLX5_SET(set_issi_in, set_in, current_issi, 1); 837 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 838 if (err) { 839 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 840 err); 841 return err; 842 } 843 844 dev->issi = 1; 845 846 return 0; 847 } else if (sup_issi & (1 << 0) || !sup_issi) { 848 return 0; 849 } 850 851 return -EOPNOTSUPP; 852 } 853 854 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 855 const struct pci_device_id *id) 856 { 857 int err = 0; 858 859 mutex_init(&dev->pci_status_mutex); 860 pci_set_drvdata(dev->pdev, dev); 861 862 dev->bar_addr = pci_resource_start(pdev, 0); 863 864 err = mlx5_pci_enable_device(dev); 865 if (err) { 866 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 867 return err; 868 } 869 870 err = request_bar(pdev); 871 if (err) { 872 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 873 goto err_disable; 874 } 875 876 pci_set_master(pdev); 877 878 err = set_dma_caps(pdev); 879 if (err) { 880 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 881 goto err_clr_master; 882 } 883 884 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 885 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 886 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 887 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 888 889 dev->iseg_base = dev->bar_addr; 890 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 891 if (!dev->iseg) { 892 err = -ENOMEM; 893 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 894 goto err_clr_master; 895 } 896 897 mlx5_pci_vsc_init(dev); 898 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 899 return 0; 900 901 err_clr_master: 902 pci_clear_master(dev->pdev); 903 release_bar(dev->pdev); 904 err_disable: 905 mlx5_pci_disable_device(dev); 906 return err; 907 } 908 909 static void mlx5_pci_close(struct mlx5_core_dev *dev) 910 { 911 /* health work might still be active, and it needs pci bar in 912 * order to know the NIC state. Therefore, drain the health WQ 913 * before removing the pci bars 914 */ 915 mlx5_drain_health_wq(dev); 916 iounmap(dev->iseg); 917 pci_clear_master(dev->pdev); 918 release_bar(dev->pdev); 919 mlx5_pci_disable_device(dev); 920 } 921 922 static int mlx5_init_once(struct mlx5_core_dev *dev) 923 { 924 int err; 925 926 dev->priv.devcom = mlx5_devcom_register_device(dev); 927 if (IS_ERR(dev->priv.devcom)) 928 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 929 dev->priv.devcom); 930 931 err = mlx5_query_board_id(dev); 932 if (err) { 933 mlx5_core_err(dev, "query board id failed\n"); 934 goto err_devcom; 935 } 936 937 err = mlx5_irq_table_init(dev); 938 if (err) { 939 mlx5_core_err(dev, "failed to initialize irq table\n"); 940 goto err_devcom; 941 } 942 943 err = mlx5_eq_table_init(dev); 944 if (err) { 945 mlx5_core_err(dev, "failed to initialize eq\n"); 946 goto err_irq_cleanup; 947 } 948 949 err = mlx5_events_init(dev); 950 if (err) { 951 mlx5_core_err(dev, "failed to initialize events\n"); 952 goto err_eq_cleanup; 953 } 954 955 err = mlx5_fw_reset_init(dev); 956 if (err) { 957 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 958 goto err_events_cleanup; 959 } 960 961 mlx5_cq_debugfs_init(dev); 962 963 mlx5_init_reserved_gids(dev); 964 965 mlx5_init_clock(dev); 966 967 dev->vxlan = mlx5_vxlan_create(dev); 968 dev->geneve = mlx5_geneve_create(dev); 969 970 err = mlx5_init_rl_table(dev); 971 if (err) { 972 mlx5_core_err(dev, "Failed to init rate limiting\n"); 973 goto err_tables_cleanup; 974 } 975 976 err = mlx5_mpfs_init(dev); 977 if (err) { 978 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 979 goto err_rl_cleanup; 980 } 981 982 err = mlx5_sriov_init(dev); 983 if (err) { 984 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 985 goto err_mpfs_cleanup; 986 } 987 988 err = mlx5_eswitch_init(dev); 989 if (err) { 990 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 991 goto err_sriov_cleanup; 992 } 993 994 err = mlx5_fpga_init(dev); 995 if (err) { 996 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 997 goto err_eswitch_cleanup; 998 } 999 1000 err = mlx5_vhca_event_init(dev); 1001 if (err) { 1002 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1003 goto err_fpga_cleanup; 1004 } 1005 1006 err = mlx5_sf_hw_table_init(dev); 1007 if (err) { 1008 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1009 goto err_sf_hw_table_cleanup; 1010 } 1011 1012 err = mlx5_sf_table_init(dev); 1013 if (err) { 1014 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1015 goto err_sf_table_cleanup; 1016 } 1017 1018 err = mlx5_fs_core_alloc(dev); 1019 if (err) { 1020 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1021 goto err_fs; 1022 } 1023 1024 dev->dm = mlx5_dm_create(dev); 1025 if (IS_ERR(dev->dm)) 1026 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 1027 1028 dev->tracer = mlx5_fw_tracer_create(dev); 1029 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1030 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1031 1032 return 0; 1033 1034 err_fs: 1035 mlx5_sf_table_cleanup(dev); 1036 err_sf_table_cleanup: 1037 mlx5_sf_hw_table_cleanup(dev); 1038 err_sf_hw_table_cleanup: 1039 mlx5_vhca_event_cleanup(dev); 1040 err_fpga_cleanup: 1041 mlx5_fpga_cleanup(dev); 1042 err_eswitch_cleanup: 1043 mlx5_eswitch_cleanup(dev->priv.eswitch); 1044 err_sriov_cleanup: 1045 mlx5_sriov_cleanup(dev); 1046 err_mpfs_cleanup: 1047 mlx5_mpfs_cleanup(dev); 1048 err_rl_cleanup: 1049 mlx5_cleanup_rl_table(dev); 1050 err_tables_cleanup: 1051 mlx5_geneve_destroy(dev->geneve); 1052 mlx5_vxlan_destroy(dev->vxlan); 1053 mlx5_cq_debugfs_cleanup(dev); 1054 mlx5_fw_reset_cleanup(dev); 1055 err_events_cleanup: 1056 mlx5_events_cleanup(dev); 1057 err_eq_cleanup: 1058 mlx5_eq_table_cleanup(dev); 1059 err_irq_cleanup: 1060 mlx5_irq_table_cleanup(dev); 1061 err_devcom: 1062 mlx5_devcom_unregister_device(dev->priv.devcom); 1063 1064 return err; 1065 } 1066 1067 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1068 { 1069 mlx5_rsc_dump_destroy(dev); 1070 mlx5_hv_vhca_destroy(dev->hv_vhca); 1071 mlx5_fw_tracer_destroy(dev->tracer); 1072 mlx5_dm_cleanup(dev); 1073 mlx5_fs_core_free(dev); 1074 mlx5_sf_table_cleanup(dev); 1075 mlx5_sf_hw_table_cleanup(dev); 1076 mlx5_vhca_event_cleanup(dev); 1077 mlx5_fpga_cleanup(dev); 1078 mlx5_eswitch_cleanup(dev->priv.eswitch); 1079 mlx5_sriov_cleanup(dev); 1080 mlx5_mpfs_cleanup(dev); 1081 mlx5_cleanup_rl_table(dev); 1082 mlx5_geneve_destroy(dev->geneve); 1083 mlx5_vxlan_destroy(dev->vxlan); 1084 mlx5_cleanup_clock(dev); 1085 mlx5_cleanup_reserved_gids(dev); 1086 mlx5_cq_debugfs_cleanup(dev); 1087 mlx5_fw_reset_cleanup(dev); 1088 mlx5_events_cleanup(dev); 1089 mlx5_eq_table_cleanup(dev); 1090 mlx5_irq_table_cleanup(dev); 1091 mlx5_devcom_unregister_device(dev->priv.devcom); 1092 } 1093 1094 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1095 { 1096 int err; 1097 1098 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1099 fw_rev_min(dev), fw_rev_sub(dev)); 1100 1101 /* Only PFs hold the relevant PCIe information for this query */ 1102 if (mlx5_core_is_pf(dev)) 1103 pcie_print_link_status(dev->pdev); 1104 1105 /* wait for firmware to accept initialization segments configurations 1106 */ 1107 err = wait_fw_init(dev, timeout, 1108 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 1109 if (err) { 1110 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 1111 timeout); 1112 return err; 1113 } 1114 1115 err = mlx5_cmd_init(dev); 1116 if (err) { 1117 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1118 return err; 1119 } 1120 1121 mlx5_tout_query_iseg(dev); 1122 1123 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1124 if (err) { 1125 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 1126 mlx5_tout_ms(dev, FW_INIT)); 1127 goto err_cmd_cleanup; 1128 } 1129 1130 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1131 1132 mlx5_start_health_poll(dev); 1133 1134 err = mlx5_core_enable_hca(dev, 0); 1135 if (err) { 1136 mlx5_core_err(dev, "enable hca failed\n"); 1137 goto stop_health_poll; 1138 } 1139 1140 err = mlx5_core_set_issi(dev); 1141 if (err) { 1142 mlx5_core_err(dev, "failed to set issi\n"); 1143 goto err_disable_hca; 1144 } 1145 1146 err = mlx5_satisfy_startup_pages(dev, 1); 1147 if (err) { 1148 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1149 goto err_disable_hca; 1150 } 1151 1152 err = mlx5_tout_query_dtor(dev); 1153 if (err) { 1154 mlx5_core_err(dev, "failed to read dtor\n"); 1155 goto reclaim_boot_pages; 1156 } 1157 1158 err = set_hca_ctrl(dev); 1159 if (err) { 1160 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1161 goto reclaim_boot_pages; 1162 } 1163 1164 err = set_hca_cap(dev); 1165 if (err) { 1166 mlx5_core_err(dev, "set_hca_cap failed\n"); 1167 goto reclaim_boot_pages; 1168 } 1169 1170 err = mlx5_satisfy_startup_pages(dev, 0); 1171 if (err) { 1172 mlx5_core_err(dev, "failed to allocate init pages\n"); 1173 goto reclaim_boot_pages; 1174 } 1175 1176 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1177 if (err) { 1178 mlx5_core_err(dev, "init hca failed\n"); 1179 goto reclaim_boot_pages; 1180 } 1181 1182 mlx5_set_driver_version(dev); 1183 1184 err = mlx5_query_hca_caps(dev); 1185 if (err) { 1186 mlx5_core_err(dev, "query hca failed\n"); 1187 goto reclaim_boot_pages; 1188 } 1189 mlx5_start_health_fw_log_up(dev); 1190 1191 return 0; 1192 1193 reclaim_boot_pages: 1194 mlx5_reclaim_startup_pages(dev); 1195 err_disable_hca: 1196 mlx5_core_disable_hca(dev, 0); 1197 stop_health_poll: 1198 mlx5_stop_health_poll(dev, boot); 1199 err_cmd_cleanup: 1200 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1201 mlx5_cmd_cleanup(dev); 1202 1203 return err; 1204 } 1205 1206 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1207 { 1208 int err; 1209 1210 err = mlx5_cmd_teardown_hca(dev); 1211 if (err) { 1212 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1213 return err; 1214 } 1215 mlx5_reclaim_startup_pages(dev); 1216 mlx5_core_disable_hca(dev, 0); 1217 mlx5_stop_health_poll(dev, boot); 1218 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1219 mlx5_cmd_cleanup(dev); 1220 1221 return 0; 1222 } 1223 1224 static int mlx5_load(struct mlx5_core_dev *dev) 1225 { 1226 int err; 1227 1228 dev->priv.uar = mlx5_get_uars_page(dev); 1229 if (IS_ERR(dev->priv.uar)) { 1230 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1231 err = PTR_ERR(dev->priv.uar); 1232 return err; 1233 } 1234 1235 mlx5_events_start(dev); 1236 mlx5_pagealloc_start(dev); 1237 1238 err = mlx5_irq_table_create(dev); 1239 if (err) { 1240 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1241 goto err_irq_table; 1242 } 1243 1244 err = mlx5_eq_table_create(dev); 1245 if (err) { 1246 mlx5_core_err(dev, "Failed to create EQs\n"); 1247 goto err_eq_table; 1248 } 1249 1250 err = mlx5_fw_tracer_init(dev->tracer); 1251 if (err) { 1252 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1253 mlx5_fw_tracer_destroy(dev->tracer); 1254 dev->tracer = NULL; 1255 } 1256 1257 mlx5_fw_reset_events_start(dev); 1258 mlx5_hv_vhca_init(dev->hv_vhca); 1259 1260 err = mlx5_rsc_dump_init(dev); 1261 if (err) { 1262 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1263 mlx5_rsc_dump_destroy(dev); 1264 dev->rsc_dump = NULL; 1265 } 1266 1267 err = mlx5_fpga_device_start(dev); 1268 if (err) { 1269 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1270 goto err_fpga_start; 1271 } 1272 1273 err = mlx5_fs_core_init(dev); 1274 if (err) { 1275 mlx5_core_err(dev, "Failed to init flow steering\n"); 1276 goto err_fs; 1277 } 1278 1279 err = mlx5_core_set_hca_defaults(dev); 1280 if (err) { 1281 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1282 goto err_set_hca; 1283 } 1284 1285 mlx5_vhca_event_start(dev); 1286 1287 err = mlx5_sf_hw_table_create(dev); 1288 if (err) { 1289 mlx5_core_err(dev, "sf table create failed %d\n", err); 1290 goto err_vhca; 1291 } 1292 1293 err = mlx5_ec_init(dev); 1294 if (err) { 1295 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1296 goto err_ec; 1297 } 1298 1299 mlx5_lag_add_mdev(dev); 1300 err = mlx5_sriov_attach(dev); 1301 if (err) { 1302 mlx5_core_err(dev, "sriov init failed %d\n", err); 1303 goto err_sriov; 1304 } 1305 1306 mlx5_sf_dev_table_create(dev); 1307 1308 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1309 if (err) 1310 goto err_traps_reg; 1311 1312 return 0; 1313 1314 err_traps_reg: 1315 mlx5_sf_dev_table_destroy(dev); 1316 mlx5_sriov_detach(dev); 1317 err_sriov: 1318 mlx5_lag_remove_mdev(dev); 1319 mlx5_ec_cleanup(dev); 1320 err_ec: 1321 mlx5_sf_hw_table_destroy(dev); 1322 err_vhca: 1323 mlx5_vhca_event_stop(dev); 1324 err_set_hca: 1325 mlx5_fs_core_cleanup(dev); 1326 err_fs: 1327 mlx5_fpga_device_stop(dev); 1328 err_fpga_start: 1329 mlx5_rsc_dump_cleanup(dev); 1330 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1331 mlx5_fw_reset_events_stop(dev); 1332 mlx5_fw_tracer_cleanup(dev->tracer); 1333 mlx5_eq_table_destroy(dev); 1334 err_eq_table: 1335 mlx5_irq_table_destroy(dev); 1336 err_irq_table: 1337 mlx5_pagealloc_stop(dev); 1338 mlx5_events_stop(dev); 1339 mlx5_put_uars_page(dev, dev->priv.uar); 1340 return err; 1341 } 1342 1343 static void mlx5_unload(struct mlx5_core_dev *dev) 1344 { 1345 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1346 mlx5_sf_dev_table_destroy(dev); 1347 mlx5_sriov_detach(dev); 1348 mlx5_eswitch_disable(dev->priv.eswitch); 1349 mlx5_lag_remove_mdev(dev); 1350 mlx5_ec_cleanup(dev); 1351 mlx5_sf_hw_table_destroy(dev); 1352 mlx5_vhca_event_stop(dev); 1353 mlx5_fs_core_cleanup(dev); 1354 mlx5_fpga_device_stop(dev); 1355 mlx5_rsc_dump_cleanup(dev); 1356 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1357 mlx5_fw_reset_events_stop(dev); 1358 mlx5_fw_tracer_cleanup(dev->tracer); 1359 mlx5_eq_table_destroy(dev); 1360 mlx5_irq_table_destroy(dev); 1361 mlx5_pagealloc_stop(dev); 1362 mlx5_events_stop(dev); 1363 mlx5_put_uars_page(dev, dev->priv.uar); 1364 } 1365 1366 int mlx5_init_one(struct mlx5_core_dev *dev) 1367 { 1368 struct devlink *devlink = priv_to_devlink(dev); 1369 int err = 0; 1370 1371 devl_lock(devlink); 1372 mutex_lock(&dev->intf_state_mutex); 1373 dev->state = MLX5_DEVICE_STATE_UP; 1374 1375 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1376 if (err) 1377 goto err_function; 1378 1379 err = mlx5_init_once(dev); 1380 if (err) { 1381 mlx5_core_err(dev, "sw objs init failed\n"); 1382 goto function_teardown; 1383 } 1384 1385 err = mlx5_load(dev); 1386 if (err) 1387 goto err_load; 1388 1389 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1390 1391 err = mlx5_devlink_register(priv_to_devlink(dev)); 1392 if (err) 1393 goto err_devlink_reg; 1394 1395 err = mlx5_register_device(dev); 1396 if (err) 1397 goto err_register; 1398 1399 mutex_unlock(&dev->intf_state_mutex); 1400 devl_unlock(devlink); 1401 return 0; 1402 1403 err_register: 1404 mlx5_devlink_unregister(priv_to_devlink(dev)); 1405 err_devlink_reg: 1406 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1407 mlx5_unload(dev); 1408 err_load: 1409 mlx5_cleanup_once(dev); 1410 function_teardown: 1411 mlx5_function_teardown(dev, true); 1412 err_function: 1413 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1414 mutex_unlock(&dev->intf_state_mutex); 1415 devl_unlock(devlink); 1416 return err; 1417 } 1418 1419 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1420 { 1421 struct devlink *devlink = priv_to_devlink(dev); 1422 1423 devl_lock(devlink); 1424 mutex_lock(&dev->intf_state_mutex); 1425 1426 mlx5_unregister_device(dev); 1427 mlx5_devlink_unregister(priv_to_devlink(dev)); 1428 1429 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1430 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1431 __func__); 1432 mlx5_cleanup_once(dev); 1433 goto out; 1434 } 1435 1436 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1437 mlx5_unload(dev); 1438 mlx5_cleanup_once(dev); 1439 mlx5_function_teardown(dev, true); 1440 out: 1441 mutex_unlock(&dev->intf_state_mutex); 1442 devl_unlock(devlink); 1443 } 1444 1445 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1446 { 1447 int err = 0; 1448 u64 timeout; 1449 1450 devl_assert_locked(priv_to_devlink(dev)); 1451 mutex_lock(&dev->intf_state_mutex); 1452 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1453 mlx5_core_warn(dev, "interface is up, NOP\n"); 1454 goto out; 1455 } 1456 /* remove any previous indication of internal error */ 1457 dev->state = MLX5_DEVICE_STATE_UP; 1458 1459 if (recovery) 1460 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1461 else 1462 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1463 err = mlx5_function_setup(dev, false, timeout); 1464 if (err) 1465 goto err_function; 1466 1467 err = mlx5_load(dev); 1468 if (err) 1469 goto err_load; 1470 1471 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1472 1473 err = mlx5_attach_device(dev); 1474 if (err) 1475 goto err_attach; 1476 1477 mutex_unlock(&dev->intf_state_mutex); 1478 return 0; 1479 1480 err_attach: 1481 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1482 mlx5_unload(dev); 1483 err_load: 1484 mlx5_function_teardown(dev, false); 1485 err_function: 1486 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1487 out: 1488 mutex_unlock(&dev->intf_state_mutex); 1489 return err; 1490 } 1491 1492 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1493 { 1494 struct devlink *devlink = priv_to_devlink(dev); 1495 int ret; 1496 1497 devl_lock(devlink); 1498 ret = mlx5_load_one_devl_locked(dev, recovery); 1499 devl_unlock(devlink); 1500 return ret; 1501 } 1502 1503 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev) 1504 { 1505 devl_assert_locked(priv_to_devlink(dev)); 1506 mutex_lock(&dev->intf_state_mutex); 1507 1508 mlx5_detach_device(dev); 1509 1510 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1511 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1512 __func__); 1513 goto out; 1514 } 1515 1516 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1517 mlx5_unload(dev); 1518 mlx5_function_teardown(dev, false); 1519 out: 1520 mutex_unlock(&dev->intf_state_mutex); 1521 } 1522 1523 void mlx5_unload_one(struct mlx5_core_dev *dev) 1524 { 1525 struct devlink *devlink = priv_to_devlink(dev); 1526 1527 devl_lock(devlink); 1528 mlx5_unload_one_devl_locked(dev); 1529 devl_unlock(devlink); 1530 } 1531 1532 static const int types[] = { 1533 MLX5_CAP_GENERAL, 1534 MLX5_CAP_GENERAL_2, 1535 MLX5_CAP_ETHERNET_OFFLOADS, 1536 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1537 MLX5_CAP_ODP, 1538 MLX5_CAP_ATOMIC, 1539 MLX5_CAP_ROCE, 1540 MLX5_CAP_IPOIB_OFFLOADS, 1541 MLX5_CAP_FLOW_TABLE, 1542 MLX5_CAP_ESWITCH_FLOW_TABLE, 1543 MLX5_CAP_ESWITCH, 1544 MLX5_CAP_VECTOR_CALC, 1545 MLX5_CAP_QOS, 1546 MLX5_CAP_DEBUG, 1547 MLX5_CAP_DEV_MEM, 1548 MLX5_CAP_DEV_EVENT, 1549 MLX5_CAP_TLS, 1550 MLX5_CAP_VDPA_EMULATION, 1551 MLX5_CAP_IPSEC, 1552 MLX5_CAP_PORT_SELECTION, 1553 MLX5_CAP_DEV_SHAMPO, 1554 MLX5_CAP_MACSEC, 1555 MLX5_CAP_ADV_VIRTUALIZATION, 1556 }; 1557 1558 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1559 { 1560 int type; 1561 int i; 1562 1563 for (i = 0; i < ARRAY_SIZE(types); i++) { 1564 type = types[i]; 1565 kfree(dev->caps.hca[type]); 1566 } 1567 } 1568 1569 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1570 { 1571 struct mlx5_hca_cap *cap; 1572 int type; 1573 int i; 1574 1575 for (i = 0; i < ARRAY_SIZE(types); i++) { 1576 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1577 if (!cap) 1578 goto err; 1579 type = types[i]; 1580 dev->caps.hca[type] = cap; 1581 } 1582 1583 return 0; 1584 1585 err: 1586 mlx5_hca_caps_free(dev); 1587 return -ENOMEM; 1588 } 1589 1590 static int vhca_id_show(struct seq_file *file, void *priv) 1591 { 1592 struct mlx5_core_dev *dev = file->private; 1593 1594 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1595 return 0; 1596 } 1597 1598 DEFINE_SHOW_ATTRIBUTE(vhca_id); 1599 1600 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1601 { 1602 struct mlx5_priv *priv = &dev->priv; 1603 int err; 1604 1605 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1606 lockdep_register_key(&dev->lock_key); 1607 mutex_init(&dev->intf_state_mutex); 1608 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1609 1610 mutex_init(&priv->bfregs.reg_head.lock); 1611 mutex_init(&priv->bfregs.wc_head.lock); 1612 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1613 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1614 1615 mutex_init(&priv->alloc_mutex); 1616 mutex_init(&priv->pgdir_mutex); 1617 INIT_LIST_HEAD(&priv->pgdir_list); 1618 1619 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1620 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1621 mlx5_debugfs_root); 1622 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 1623 INIT_LIST_HEAD(&priv->traps); 1624 1625 err = mlx5_tout_init(dev); 1626 if (err) { 1627 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1628 goto err_timeout_init; 1629 } 1630 1631 err = mlx5_health_init(dev); 1632 if (err) 1633 goto err_health_init; 1634 1635 err = mlx5_pagealloc_init(dev); 1636 if (err) 1637 goto err_pagealloc_init; 1638 1639 err = mlx5_adev_init(dev); 1640 if (err) 1641 goto err_adev_init; 1642 1643 err = mlx5_hca_caps_alloc(dev); 1644 if (err) 1645 goto err_hca_caps; 1646 1647 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1648 * unique id per function which uses mlx5_core. 1649 * Those values are supplied to FW as part of the init HCA command to 1650 * be used by both driver and FW when it's applicable. 1651 */ 1652 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1653 MAX_SW_VHCA_ID, 1654 GFP_KERNEL); 1655 if (dev->priv.sw_vhca_id < 0) 1656 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1657 dev->priv.sw_vhca_id); 1658 1659 return 0; 1660 1661 err_hca_caps: 1662 mlx5_adev_cleanup(dev); 1663 err_adev_init: 1664 mlx5_pagealloc_cleanup(dev); 1665 err_pagealloc_init: 1666 mlx5_health_cleanup(dev); 1667 err_health_init: 1668 mlx5_tout_cleanup(dev); 1669 err_timeout_init: 1670 debugfs_remove(dev->priv.dbg.dbg_root); 1671 mutex_destroy(&priv->pgdir_mutex); 1672 mutex_destroy(&priv->alloc_mutex); 1673 mutex_destroy(&priv->bfregs.wc_head.lock); 1674 mutex_destroy(&priv->bfregs.reg_head.lock); 1675 mutex_destroy(&dev->intf_state_mutex); 1676 lockdep_unregister_key(&dev->lock_key); 1677 return err; 1678 } 1679 1680 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1681 { 1682 struct mlx5_priv *priv = &dev->priv; 1683 1684 if (priv->sw_vhca_id > 0) 1685 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1686 1687 mlx5_hca_caps_free(dev); 1688 mlx5_adev_cleanup(dev); 1689 mlx5_pagealloc_cleanup(dev); 1690 mlx5_health_cleanup(dev); 1691 mlx5_tout_cleanup(dev); 1692 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1693 mutex_destroy(&priv->pgdir_mutex); 1694 mutex_destroy(&priv->alloc_mutex); 1695 mutex_destroy(&priv->bfregs.wc_head.lock); 1696 mutex_destroy(&priv->bfregs.reg_head.lock); 1697 mutex_destroy(&dev->intf_state_mutex); 1698 lockdep_unregister_key(&dev->lock_key); 1699 } 1700 1701 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1702 { 1703 struct mlx5_core_dev *dev; 1704 struct devlink *devlink; 1705 int err; 1706 1707 devlink = mlx5_devlink_alloc(&pdev->dev); 1708 if (!devlink) { 1709 dev_err(&pdev->dev, "devlink alloc failed\n"); 1710 return -ENOMEM; 1711 } 1712 1713 dev = devlink_priv(devlink); 1714 dev->device = &pdev->dev; 1715 dev->pdev = pdev; 1716 1717 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1718 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1719 1720 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1721 if (dev->priv.adev_idx < 0) { 1722 err = dev->priv.adev_idx; 1723 goto adev_init_err; 1724 } 1725 1726 err = mlx5_mdev_init(dev, prof_sel); 1727 if (err) 1728 goto mdev_init_err; 1729 1730 err = mlx5_pci_init(dev, pdev, id); 1731 if (err) { 1732 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1733 err); 1734 goto pci_init_err; 1735 } 1736 1737 err = mlx5_init_one(dev); 1738 if (err) { 1739 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1740 err); 1741 goto err_init_one; 1742 } 1743 1744 err = mlx5_crdump_enable(dev); 1745 if (err) 1746 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1747 1748 pci_save_state(pdev); 1749 devlink_register(devlink); 1750 return 0; 1751 1752 err_init_one: 1753 mlx5_pci_close(dev); 1754 pci_init_err: 1755 mlx5_mdev_uninit(dev); 1756 mdev_init_err: 1757 mlx5_adev_idx_free(dev->priv.adev_idx); 1758 adev_init_err: 1759 mlx5_devlink_free(devlink); 1760 1761 return err; 1762 } 1763 1764 static void remove_one(struct pci_dev *pdev) 1765 { 1766 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1767 struct devlink *devlink = priv_to_devlink(dev); 1768 1769 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 1770 * fw_reset before unregistering the devlink. 1771 */ 1772 mlx5_drain_fw_reset(dev); 1773 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1774 devlink_unregister(devlink); 1775 mlx5_sriov_disable(pdev); 1776 mlx5_crdump_disable(dev); 1777 mlx5_drain_health_wq(dev); 1778 mlx5_uninit_one(dev); 1779 mlx5_pci_close(dev); 1780 mlx5_mdev_uninit(dev); 1781 mlx5_adev_idx_free(dev->priv.adev_idx); 1782 mlx5_devlink_free(devlink); 1783 } 1784 1785 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1786 struct mlx5_core_dev *__dev = (dev); \ 1787 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1788 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1789 __dev->pci_status, ##__VA_ARGS__); \ 1790 }) 1791 1792 static const char *result2str(enum pci_ers_result result) 1793 { 1794 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1795 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1796 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1797 "unknown"; 1798 } 1799 1800 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1801 pci_channel_state_t state) 1802 { 1803 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1804 enum pci_ers_result res; 1805 1806 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 1807 1808 mlx5_enter_error_state(dev, false); 1809 mlx5_error_sw_reset(dev); 1810 mlx5_unload_one(dev); 1811 mlx5_drain_health_wq(dev); 1812 mlx5_pci_disable_device(dev); 1813 1814 res = state == pci_channel_io_perm_failure ? 1815 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1816 1817 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 1818 __func__, dev->state, dev->pci_status, res, result2str(res)); 1819 return res; 1820 } 1821 1822 /* wait for the device to show vital signs by waiting 1823 * for the health counter to start counting. 1824 */ 1825 static int wait_vital(struct pci_dev *pdev) 1826 { 1827 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1828 struct mlx5_core_health *health = &dev->priv.health; 1829 const int niter = 100; 1830 u32 last_count = 0; 1831 u32 count; 1832 int i; 1833 1834 for (i = 0; i < niter; i++) { 1835 count = ioread32be(health->health_counter); 1836 if (count && count != 0xffffffff) { 1837 if (last_count && last_count != count) { 1838 mlx5_core_info(dev, 1839 "wait vital counter value 0x%x after %d iterations\n", 1840 count, i); 1841 return 0; 1842 } 1843 last_count = count; 1844 } 1845 msleep(50); 1846 } 1847 1848 return -ETIMEDOUT; 1849 } 1850 1851 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1852 { 1853 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 1854 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1855 int err; 1856 1857 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 1858 __func__, dev->state, dev->pci_status); 1859 1860 err = mlx5_pci_enable_device(dev); 1861 if (err) { 1862 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1863 __func__, err); 1864 goto out; 1865 } 1866 1867 pci_set_master(pdev); 1868 pci_restore_state(pdev); 1869 pci_save_state(pdev); 1870 1871 err = wait_vital(pdev); 1872 if (err) { 1873 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1874 __func__, err); 1875 goto out; 1876 } 1877 1878 res = PCI_ERS_RESULT_RECOVERED; 1879 out: 1880 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 1881 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 1882 return res; 1883 } 1884 1885 static void mlx5_pci_resume(struct pci_dev *pdev) 1886 { 1887 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1888 int err; 1889 1890 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 1891 1892 err = mlx5_load_one(dev, false); 1893 1894 if (!err) 1895 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1896 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1897 1898 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1899 !err ? "recovered" : "Failed"); 1900 } 1901 1902 static const struct pci_error_handlers mlx5_err_handler = { 1903 .error_detected = mlx5_pci_err_detected, 1904 .slot_reset = mlx5_pci_slot_reset, 1905 .resume = mlx5_pci_resume 1906 }; 1907 1908 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1909 { 1910 bool fast_teardown = false, force_teardown = false; 1911 int ret = 1; 1912 1913 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1914 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1915 1916 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1917 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1918 1919 if (!fast_teardown && !force_teardown) 1920 return -EOPNOTSUPP; 1921 1922 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1923 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1924 return -EAGAIN; 1925 } 1926 1927 /* Panic tear down fw command will stop the PCI bus communication 1928 * with the HCA, so the health poll is no longer needed. 1929 */ 1930 mlx5_drain_health_wq(dev); 1931 mlx5_stop_health_poll(dev, false); 1932 1933 ret = mlx5_cmd_fast_teardown_hca(dev); 1934 if (!ret) 1935 goto succeed; 1936 1937 ret = mlx5_cmd_force_teardown_hca(dev); 1938 if (!ret) 1939 goto succeed; 1940 1941 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1942 mlx5_start_health_poll(dev); 1943 return ret; 1944 1945 succeed: 1946 mlx5_enter_error_state(dev, true); 1947 1948 /* Some platforms requiring freeing the IRQ's in the shutdown 1949 * flow. If they aren't freed they can't be allocated after 1950 * kexec. There is no need to cleanup the mlx5_core software 1951 * contexts. 1952 */ 1953 mlx5_core_eq_free_irqs(dev); 1954 1955 return 0; 1956 } 1957 1958 static void shutdown(struct pci_dev *pdev) 1959 { 1960 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1961 int err; 1962 1963 mlx5_core_info(dev, "Shutdown was called\n"); 1964 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1965 err = mlx5_try_fast_unload(dev); 1966 if (err) 1967 mlx5_unload_one(dev); 1968 mlx5_pci_disable_device(dev); 1969 } 1970 1971 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1972 { 1973 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1974 1975 mlx5_unload_one(dev); 1976 1977 return 0; 1978 } 1979 1980 static int mlx5_resume(struct pci_dev *pdev) 1981 { 1982 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1983 1984 return mlx5_load_one(dev, false); 1985 } 1986 1987 static const struct pci_device_id mlx5_core_pci_table[] = { 1988 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1989 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1990 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1991 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1992 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1993 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1994 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1995 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1996 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1997 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1998 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1999 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 2000 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2001 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2002 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2003 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2004 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2005 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2006 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2007 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2008 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2009 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2010 { 0, } 2011 }; 2012 2013 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2014 2015 void mlx5_disable_device(struct mlx5_core_dev *dev) 2016 { 2017 mlx5_error_sw_reset(dev); 2018 mlx5_unload_one_devl_locked(dev); 2019 } 2020 2021 int mlx5_recover_device(struct mlx5_core_dev *dev) 2022 { 2023 if (!mlx5_core_is_sf(dev)) { 2024 mlx5_pci_disable_device(dev); 2025 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2026 return -EIO; 2027 } 2028 2029 return mlx5_load_one_devl_locked(dev, true); 2030 } 2031 2032 static struct pci_driver mlx5_core_driver = { 2033 .name = KBUILD_MODNAME, 2034 .id_table = mlx5_core_pci_table, 2035 .probe = probe_one, 2036 .remove = remove_one, 2037 .suspend = mlx5_suspend, 2038 .resume = mlx5_resume, 2039 .shutdown = shutdown, 2040 .err_handler = &mlx5_err_handler, 2041 .sriov_configure = mlx5_core_sriov_configure, 2042 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2043 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2044 }; 2045 2046 /** 2047 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2048 * mlx5_core is its driver. 2049 * @pdev: The associated PCI device. 2050 * 2051 * Upon return the interface state lock stay held to let caller uses it safely. 2052 * Caller must ensure to use the returned mlx5 device for a narrow window 2053 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2054 * 2055 * Return: Pointer to the associated mlx5_core_dev or NULL. 2056 */ 2057 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2058 { 2059 struct mlx5_core_dev *mdev; 2060 2061 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2062 if (IS_ERR(mdev)) 2063 return NULL; 2064 2065 mutex_lock(&mdev->intf_state_mutex); 2066 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2067 mutex_unlock(&mdev->intf_state_mutex); 2068 return NULL; 2069 } 2070 2071 return mdev; 2072 } 2073 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2074 2075 /** 2076 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2077 * @mdev: The mlx5 core device. 2078 * 2079 * Upon return the interface state lock is unlocked and caller should not 2080 * access the mdev any more. 2081 */ 2082 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2083 { 2084 mutex_unlock(&mdev->intf_state_mutex); 2085 } 2086 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2087 2088 static void mlx5_core_verify_params(void) 2089 { 2090 if (prof_sel >= ARRAY_SIZE(profile)) { 2091 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2092 prof_sel, 2093 ARRAY_SIZE(profile) - 1, 2094 MLX5_DEFAULT_PROF); 2095 prof_sel = MLX5_DEFAULT_PROF; 2096 } 2097 } 2098 2099 static int __init init(void) 2100 { 2101 int err; 2102 2103 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2104 "mlx5_core name not in sync with kernel module name"); 2105 2106 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2107 2108 mlx5_core_verify_params(); 2109 mlx5_register_debugfs(); 2110 2111 err = pci_register_driver(&mlx5_core_driver); 2112 if (err) 2113 goto err_debug; 2114 2115 err = mlx5_sf_driver_register(); 2116 if (err) 2117 goto err_sf; 2118 2119 err = mlx5e_init(); 2120 if (err) 2121 goto err_en; 2122 2123 return 0; 2124 2125 err_en: 2126 mlx5_sf_driver_unregister(); 2127 err_sf: 2128 pci_unregister_driver(&mlx5_core_driver); 2129 err_debug: 2130 mlx5_unregister_debugfs(); 2131 return err; 2132 } 2133 2134 static void __exit cleanup(void) 2135 { 2136 mlx5e_cleanup(); 2137 mlx5_sf_driver_unregister(); 2138 pci_unregister_driver(&mlx5_core_driver); 2139 mlx5_unregister_debugfs(); 2140 } 2141 2142 module_init(init); 2143 module_exit(cleanup); 2144