1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "fpga/core.h" 64 #include "fpga/ipsec.h" 65 #include "accel/ipsec.h" 66 #include "accel/tls.h" 67 #include "lib/clock.h" 68 #include "lib/vxlan.h" 69 #include "lib/geneve.h" 70 #include "lib/devcom.h" 71 #include "lib/pci_vsc.h" 72 #include "diag/fw_tracer.h" 73 #include "ecpf.h" 74 #include "lib/hv_vhca.h" 75 #include "diag/rsc_dump.h" 76 #include "sf/vhca_event.h" 77 #include "sf/dev/dev.h" 78 #include "sf/sf.h" 79 #include "mlx5_irq.h" 80 81 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 82 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 83 MODULE_LICENSE("Dual BSD/GPL"); 84 85 unsigned int mlx5_core_debug_mask; 86 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 87 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 88 89 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 90 module_param_named(prof_sel, prof_sel, uint, 0444); 91 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 92 93 static u32 sw_owner_id[4]; 94 95 enum { 96 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 98 }; 99 100 #define LOG_MAX_SUPPORTED_QPS 0xff 101 102 static struct mlx5_profile profile[] = { 103 [0] = { 104 .mask = 0, 105 }, 106 [1] = { 107 .mask = MLX5_PROF_MASK_QP_SIZE, 108 .log_max_qp = 12, 109 }, 110 [2] = { 111 .mask = MLX5_PROF_MASK_QP_SIZE | 112 MLX5_PROF_MASK_MR_CACHE, 113 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 114 .mr_cache[0] = { 115 .size = 500, 116 .limit = 250 117 }, 118 .mr_cache[1] = { 119 .size = 500, 120 .limit = 250 121 }, 122 .mr_cache[2] = { 123 .size = 500, 124 .limit = 250 125 }, 126 .mr_cache[3] = { 127 .size = 500, 128 .limit = 250 129 }, 130 .mr_cache[4] = { 131 .size = 500, 132 .limit = 250 133 }, 134 .mr_cache[5] = { 135 .size = 500, 136 .limit = 250 137 }, 138 .mr_cache[6] = { 139 .size = 500, 140 .limit = 250 141 }, 142 .mr_cache[7] = { 143 .size = 500, 144 .limit = 250 145 }, 146 .mr_cache[8] = { 147 .size = 500, 148 .limit = 250 149 }, 150 .mr_cache[9] = { 151 .size = 500, 152 .limit = 250 153 }, 154 .mr_cache[10] = { 155 .size = 500, 156 .limit = 250 157 }, 158 .mr_cache[11] = { 159 .size = 500, 160 .limit = 250 161 }, 162 .mr_cache[12] = { 163 .size = 64, 164 .limit = 32 165 }, 166 .mr_cache[13] = { 167 .size = 32, 168 .limit = 16 169 }, 170 .mr_cache[14] = { 171 .size = 16, 172 .limit = 8 173 }, 174 .mr_cache[15] = { 175 .size = 8, 176 .limit = 4 177 }, 178 }, 179 }; 180 181 #define FW_INIT_TIMEOUT_MILI 2000 182 #define FW_INIT_WAIT_MS 2 183 #define FW_PRE_INIT_TIMEOUT_MILI 120000 184 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 185 186 static int fw_initializing(struct mlx5_core_dev *dev) 187 { 188 return ioread32be(&dev->iseg->initializing) >> 31; 189 } 190 191 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 192 u32 warn_time_mili) 193 { 194 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 195 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 196 int err = 0; 197 198 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 199 200 while (fw_initializing(dev)) { 201 if (time_after(jiffies, end)) { 202 err = -EBUSY; 203 break; 204 } 205 if (warn_time_mili && time_after(jiffies, warn)) { 206 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 207 jiffies_to_msecs(end - warn) / 1000); 208 warn = jiffies + msecs_to_jiffies(warn_time_mili); 209 } 210 msleep(FW_INIT_WAIT_MS); 211 } 212 213 return err; 214 } 215 216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 217 { 218 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 219 driver_version); 220 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 221 int remaining_size = driver_ver_sz; 222 char *string; 223 224 if (!MLX5_CAP_GEN(dev, driver_version)) 225 return; 226 227 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 228 229 strncpy(string, "Linux", remaining_size); 230 231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232 strncat(string, ",", remaining_size); 233 234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235 strncat(string, KBUILD_MODNAME, remaining_size); 236 237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238 strncat(string, ",", remaining_size); 239 240 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 241 242 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 243 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 244 LINUX_VERSION_SUBLEVEL); 245 246 /*Send the command*/ 247 MLX5_SET(set_driver_version_in, in, opcode, 248 MLX5_CMD_OP_SET_DRIVER_VERSION); 249 250 mlx5_cmd_exec_in(dev, set_driver_version, in); 251 } 252 253 static int set_dma_caps(struct pci_dev *pdev) 254 { 255 int err; 256 257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 258 if (err) { 259 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 261 if (err) { 262 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 263 return err; 264 } 265 } 266 267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 268 return err; 269 } 270 271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 272 { 273 struct pci_dev *pdev = dev->pdev; 274 int err = 0; 275 276 mutex_lock(&dev->pci_status_mutex); 277 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 278 err = pci_enable_device(pdev); 279 if (!err) 280 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 281 } 282 mutex_unlock(&dev->pci_status_mutex); 283 284 return err; 285 } 286 287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 288 { 289 struct pci_dev *pdev = dev->pdev; 290 291 mutex_lock(&dev->pci_status_mutex); 292 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 293 pci_disable_device(pdev); 294 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 295 } 296 mutex_unlock(&dev->pci_status_mutex); 297 } 298 299 static int request_bar(struct pci_dev *pdev) 300 { 301 int err = 0; 302 303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 304 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 305 return -ENODEV; 306 } 307 308 err = pci_request_regions(pdev, KBUILD_MODNAME); 309 if (err) 310 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 311 312 return err; 313 } 314 315 static void release_bar(struct pci_dev *pdev) 316 { 317 pci_release_regions(pdev); 318 } 319 320 struct mlx5_reg_host_endianness { 321 u8 he; 322 u8 rsvd[15]; 323 }; 324 325 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 326 327 enum { 328 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 329 MLX5_DEV_CAP_FLAG_DCT, 330 }; 331 332 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 333 { 334 switch (size) { 335 case 128: 336 return 0; 337 case 256: 338 return 1; 339 case 512: 340 return 2; 341 case 1024: 342 return 3; 343 case 2048: 344 return 4; 345 case 4096: 346 return 5; 347 default: 348 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 349 return 0; 350 } 351 } 352 353 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 354 enum mlx5_cap_type cap_type, 355 enum mlx5_cap_mode cap_mode) 356 { 357 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 358 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 359 void *out, *hca_caps; 360 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 361 int err; 362 363 memset(in, 0, sizeof(in)); 364 out = kzalloc(out_sz, GFP_KERNEL); 365 if (!out) 366 return -ENOMEM; 367 368 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 369 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 370 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 371 if (err) { 372 mlx5_core_warn(dev, 373 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 374 cap_type, cap_mode, err); 375 goto query_ex; 376 } 377 378 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 379 380 switch (cap_mode) { 381 case HCA_CAP_OPMOD_GET_MAX: 382 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 383 MLX5_UN_SZ_BYTES(hca_cap_union)); 384 break; 385 case HCA_CAP_OPMOD_GET_CUR: 386 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 387 MLX5_UN_SZ_BYTES(hca_cap_union)); 388 break; 389 default: 390 mlx5_core_warn(dev, 391 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 392 cap_type, cap_mode); 393 err = -EINVAL; 394 break; 395 } 396 query_ex: 397 kfree(out); 398 return err; 399 } 400 401 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 402 { 403 int ret; 404 405 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 406 if (ret) 407 return ret; 408 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 409 } 410 411 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 412 { 413 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 414 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 415 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 416 } 417 418 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 419 { 420 void *set_hca_cap; 421 int req_endianness; 422 int err; 423 424 if (!MLX5_CAP_GEN(dev, atomic)) 425 return 0; 426 427 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 428 if (err) 429 return err; 430 431 req_endianness = 432 MLX5_CAP_ATOMIC(dev, 433 supported_atomic_req_8B_endianness_mode_1); 434 435 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 436 return 0; 437 438 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 439 440 /* Set requestor to host endianness */ 441 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 442 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 443 444 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 445 } 446 447 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 448 { 449 void *set_hca_cap; 450 bool do_set = false; 451 int err; 452 453 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 454 !MLX5_CAP_GEN(dev, pg)) 455 return 0; 456 457 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 458 if (err) 459 return err; 460 461 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 462 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 463 MLX5_ST_SZ_BYTES(odp_cap)); 464 465 #define ODP_CAP_SET_MAX(dev, field) \ 466 do { \ 467 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 468 if (_res) { \ 469 do_set = true; \ 470 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 471 } \ 472 } while (0) 473 474 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 475 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 476 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 477 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 478 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 482 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 483 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 484 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 485 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 486 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 487 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 488 489 if (!do_set) 490 return 0; 491 492 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 493 } 494 495 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 496 { 497 struct mlx5_profile *prof = &dev->profile; 498 void *set_hca_cap; 499 int err; 500 501 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 502 if (err) 503 return err; 504 505 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 506 capability); 507 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 508 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 509 510 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 511 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 512 128); 513 /* we limit the size of the pkey table to 128 entries for now */ 514 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 515 to_fw_pkey_sz(dev, 128)); 516 517 /* Check log_max_qp from HCA caps to set in current profile */ 518 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 519 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 520 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 521 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 522 prof->log_max_qp, 523 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 524 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 525 } 526 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 527 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 528 prof->log_max_qp); 529 530 /* disable cmdif checksum */ 531 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 532 533 /* Enable 4K UAR only when HCA supports it and page size is bigger 534 * than 4K. 535 */ 536 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 537 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 538 539 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 540 541 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 542 MLX5_SET(cmd_hca_cap, 543 set_hca_cap, 544 cache_line_128byte, 545 cache_line_size() >= 128 ? 1 : 0); 546 547 if (MLX5_CAP_GEN_MAX(dev, dct)) 548 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 549 550 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 551 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 552 553 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 554 MLX5_SET(cmd_hca_cap, 555 set_hca_cap, 556 num_vhca_ports, 557 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 558 559 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 560 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 561 562 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 563 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 564 565 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 566 567 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 568 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 569 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 570 571 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 572 } 573 574 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 575 { 576 void *set_hca_cap; 577 int err; 578 579 if (!MLX5_CAP_GEN(dev, roce)) 580 return 0; 581 582 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 583 if (err) 584 return err; 585 586 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 587 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 588 return 0; 589 590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 591 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 592 MLX5_ST_SZ_BYTES(roce_cap)); 593 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 594 595 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 596 return err; 597 } 598 599 static int set_hca_cap(struct mlx5_core_dev *dev) 600 { 601 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 602 void *set_ctx; 603 int err; 604 605 set_ctx = kzalloc(set_sz, GFP_KERNEL); 606 if (!set_ctx) 607 return -ENOMEM; 608 609 err = handle_hca_cap(dev, set_ctx); 610 if (err) { 611 mlx5_core_err(dev, "handle_hca_cap failed\n"); 612 goto out; 613 } 614 615 memset(set_ctx, 0, set_sz); 616 err = handle_hca_cap_atomic(dev, set_ctx); 617 if (err) { 618 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 619 goto out; 620 } 621 622 memset(set_ctx, 0, set_sz); 623 err = handle_hca_cap_odp(dev, set_ctx); 624 if (err) { 625 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 626 goto out; 627 } 628 629 memset(set_ctx, 0, set_sz); 630 err = handle_hca_cap_roce(dev, set_ctx); 631 if (err) { 632 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 633 goto out; 634 } 635 636 out: 637 kfree(set_ctx); 638 return err; 639 } 640 641 static int set_hca_ctrl(struct mlx5_core_dev *dev) 642 { 643 struct mlx5_reg_host_endianness he_in; 644 struct mlx5_reg_host_endianness he_out; 645 int err; 646 647 if (!mlx5_core_is_pf(dev)) 648 return 0; 649 650 memset(&he_in, 0, sizeof(he_in)); 651 he_in.he = MLX5_SET_HOST_ENDIANNESS; 652 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 653 &he_out, sizeof(he_out), 654 MLX5_REG_HOST_ENDIANNESS, 0, 1); 655 return err; 656 } 657 658 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 659 { 660 int ret = 0; 661 662 /* Disable local_lb by default */ 663 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 664 ret = mlx5_nic_vport_update_local_lb(dev, false); 665 666 return ret; 667 } 668 669 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 670 { 671 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 672 673 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 674 MLX5_SET(enable_hca_in, in, function_id, func_id); 675 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 676 dev->caps.embedded_cpu); 677 return mlx5_cmd_exec_in(dev, enable_hca, in); 678 } 679 680 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 681 { 682 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 683 684 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 685 MLX5_SET(disable_hca_in, in, function_id, func_id); 686 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 687 dev->caps.embedded_cpu); 688 return mlx5_cmd_exec_in(dev, disable_hca, in); 689 } 690 691 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 692 { 693 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 694 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 695 u32 sup_issi; 696 int err; 697 698 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 699 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 700 if (err) { 701 u32 syndrome; 702 u8 status; 703 704 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 705 if (!status || syndrome == MLX5_DRIVER_SYND) { 706 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 707 err, status, syndrome); 708 return err; 709 } 710 711 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 712 dev->issi = 0; 713 return 0; 714 } 715 716 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 717 718 if (sup_issi & (1 << 1)) { 719 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 720 721 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 722 MLX5_SET(set_issi_in, set_in, current_issi, 1); 723 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 724 if (err) { 725 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 726 err); 727 return err; 728 } 729 730 dev->issi = 1; 731 732 return 0; 733 } else if (sup_issi & (1 << 0) || !sup_issi) { 734 return 0; 735 } 736 737 return -EOPNOTSUPP; 738 } 739 740 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 741 const struct pci_device_id *id) 742 { 743 int err = 0; 744 745 mutex_init(&dev->pci_status_mutex); 746 pci_set_drvdata(dev->pdev, dev); 747 748 dev->bar_addr = pci_resource_start(pdev, 0); 749 750 err = mlx5_pci_enable_device(dev); 751 if (err) { 752 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 753 return err; 754 } 755 756 err = request_bar(pdev); 757 if (err) { 758 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 759 goto err_disable; 760 } 761 762 pci_set_master(pdev); 763 764 err = set_dma_caps(pdev); 765 if (err) { 766 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 767 goto err_clr_master; 768 } 769 770 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 771 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 773 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 774 775 dev->iseg_base = dev->bar_addr; 776 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 777 if (!dev->iseg) { 778 err = -ENOMEM; 779 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 780 goto err_clr_master; 781 } 782 783 mlx5_pci_vsc_init(dev); 784 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 785 return 0; 786 787 err_clr_master: 788 pci_clear_master(dev->pdev); 789 release_bar(dev->pdev); 790 err_disable: 791 mlx5_pci_disable_device(dev); 792 return err; 793 } 794 795 static void mlx5_pci_close(struct mlx5_core_dev *dev) 796 { 797 /* health work might still be active, and it needs pci bar in 798 * order to know the NIC state. Therefore, drain the health WQ 799 * before removing the pci bars 800 */ 801 mlx5_drain_health_wq(dev); 802 iounmap(dev->iseg); 803 pci_clear_master(dev->pdev); 804 release_bar(dev->pdev); 805 mlx5_pci_disable_device(dev); 806 } 807 808 static int mlx5_init_once(struct mlx5_core_dev *dev) 809 { 810 int err; 811 812 dev->priv.devcom = mlx5_devcom_register_device(dev); 813 if (IS_ERR(dev->priv.devcom)) 814 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 815 dev->priv.devcom); 816 817 err = mlx5_query_board_id(dev); 818 if (err) { 819 mlx5_core_err(dev, "query board id failed\n"); 820 goto err_devcom; 821 } 822 823 err = mlx5_irq_table_init(dev); 824 if (err) { 825 mlx5_core_err(dev, "failed to initialize irq table\n"); 826 goto err_devcom; 827 } 828 829 err = mlx5_eq_table_init(dev); 830 if (err) { 831 mlx5_core_err(dev, "failed to initialize eq\n"); 832 goto err_irq_cleanup; 833 } 834 835 err = mlx5_events_init(dev); 836 if (err) { 837 mlx5_core_err(dev, "failed to initialize events\n"); 838 goto err_eq_cleanup; 839 } 840 841 err = mlx5_fw_reset_init(dev); 842 if (err) { 843 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 844 goto err_events_cleanup; 845 } 846 847 mlx5_cq_debugfs_init(dev); 848 849 mlx5_init_reserved_gids(dev); 850 851 mlx5_init_clock(dev); 852 853 dev->vxlan = mlx5_vxlan_create(dev); 854 dev->geneve = mlx5_geneve_create(dev); 855 856 err = mlx5_init_rl_table(dev); 857 if (err) { 858 mlx5_core_err(dev, "Failed to init rate limiting\n"); 859 goto err_tables_cleanup; 860 } 861 862 err = mlx5_mpfs_init(dev); 863 if (err) { 864 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 865 goto err_rl_cleanup; 866 } 867 868 err = mlx5_sriov_init(dev); 869 if (err) { 870 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 871 goto err_mpfs_cleanup; 872 } 873 874 err = mlx5_eswitch_init(dev); 875 if (err) { 876 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 877 goto err_sriov_cleanup; 878 } 879 880 err = mlx5_fpga_init(dev); 881 if (err) { 882 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 883 goto err_eswitch_cleanup; 884 } 885 886 err = mlx5_vhca_event_init(dev); 887 if (err) { 888 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 889 goto err_fpga_cleanup; 890 } 891 892 err = mlx5_sf_hw_table_init(dev); 893 if (err) { 894 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 895 goto err_sf_hw_table_cleanup; 896 } 897 898 err = mlx5_sf_table_init(dev); 899 if (err) { 900 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 901 goto err_sf_table_cleanup; 902 } 903 904 dev->dm = mlx5_dm_create(dev); 905 if (IS_ERR(dev->dm)) 906 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 907 908 dev->tracer = mlx5_fw_tracer_create(dev); 909 dev->hv_vhca = mlx5_hv_vhca_create(dev); 910 dev->rsc_dump = mlx5_rsc_dump_create(dev); 911 912 return 0; 913 914 err_sf_table_cleanup: 915 mlx5_sf_hw_table_cleanup(dev); 916 err_sf_hw_table_cleanup: 917 mlx5_vhca_event_cleanup(dev); 918 err_fpga_cleanup: 919 mlx5_fpga_cleanup(dev); 920 err_eswitch_cleanup: 921 mlx5_eswitch_cleanup(dev->priv.eswitch); 922 err_sriov_cleanup: 923 mlx5_sriov_cleanup(dev); 924 err_mpfs_cleanup: 925 mlx5_mpfs_cleanup(dev); 926 err_rl_cleanup: 927 mlx5_cleanup_rl_table(dev); 928 err_tables_cleanup: 929 mlx5_geneve_destroy(dev->geneve); 930 mlx5_vxlan_destroy(dev->vxlan); 931 mlx5_cq_debugfs_cleanup(dev); 932 mlx5_fw_reset_cleanup(dev); 933 err_events_cleanup: 934 mlx5_events_cleanup(dev); 935 err_eq_cleanup: 936 mlx5_eq_table_cleanup(dev); 937 err_irq_cleanup: 938 mlx5_irq_table_cleanup(dev); 939 err_devcom: 940 mlx5_devcom_unregister_device(dev->priv.devcom); 941 942 return err; 943 } 944 945 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 946 { 947 mlx5_rsc_dump_destroy(dev); 948 mlx5_hv_vhca_destroy(dev->hv_vhca); 949 mlx5_fw_tracer_destroy(dev->tracer); 950 mlx5_dm_cleanup(dev); 951 mlx5_sf_table_cleanup(dev); 952 mlx5_sf_hw_table_cleanup(dev); 953 mlx5_vhca_event_cleanup(dev); 954 mlx5_fpga_cleanup(dev); 955 mlx5_eswitch_cleanup(dev->priv.eswitch); 956 mlx5_sriov_cleanup(dev); 957 mlx5_mpfs_cleanup(dev); 958 mlx5_cleanup_rl_table(dev); 959 mlx5_geneve_destroy(dev->geneve); 960 mlx5_vxlan_destroy(dev->vxlan); 961 mlx5_cleanup_clock(dev); 962 mlx5_cleanup_reserved_gids(dev); 963 mlx5_cq_debugfs_cleanup(dev); 964 mlx5_fw_reset_cleanup(dev); 965 mlx5_events_cleanup(dev); 966 mlx5_eq_table_cleanup(dev); 967 mlx5_irq_table_cleanup(dev); 968 mlx5_devcom_unregister_device(dev->priv.devcom); 969 } 970 971 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 972 { 973 int err; 974 975 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 976 fw_rev_min(dev), fw_rev_sub(dev)); 977 978 /* Only PFs hold the relevant PCIe information for this query */ 979 if (mlx5_core_is_pf(dev)) 980 pcie_print_link_status(dev->pdev); 981 982 /* wait for firmware to accept initialization segments configurations 983 */ 984 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 985 if (err) { 986 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 987 FW_PRE_INIT_TIMEOUT_MILI); 988 return err; 989 } 990 991 err = mlx5_cmd_init(dev); 992 if (err) { 993 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 994 return err; 995 } 996 997 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 998 if (err) { 999 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 1000 FW_INIT_TIMEOUT_MILI); 1001 goto err_cmd_cleanup; 1002 } 1003 1004 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1005 1006 err = mlx5_core_enable_hca(dev, 0); 1007 if (err) { 1008 mlx5_core_err(dev, "enable hca failed\n"); 1009 goto err_cmd_cleanup; 1010 } 1011 1012 err = mlx5_core_set_issi(dev); 1013 if (err) { 1014 mlx5_core_err(dev, "failed to set issi\n"); 1015 goto err_disable_hca; 1016 } 1017 1018 err = mlx5_satisfy_startup_pages(dev, 1); 1019 if (err) { 1020 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1021 goto err_disable_hca; 1022 } 1023 1024 err = set_hca_ctrl(dev); 1025 if (err) { 1026 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1027 goto reclaim_boot_pages; 1028 } 1029 1030 err = set_hca_cap(dev); 1031 if (err) { 1032 mlx5_core_err(dev, "set_hca_cap failed\n"); 1033 goto reclaim_boot_pages; 1034 } 1035 1036 err = mlx5_satisfy_startup_pages(dev, 0); 1037 if (err) { 1038 mlx5_core_err(dev, "failed to allocate init pages\n"); 1039 goto reclaim_boot_pages; 1040 } 1041 1042 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1043 if (err) { 1044 mlx5_core_err(dev, "init hca failed\n"); 1045 goto reclaim_boot_pages; 1046 } 1047 1048 mlx5_set_driver_version(dev); 1049 1050 mlx5_start_health_poll(dev); 1051 1052 err = mlx5_query_hca_caps(dev); 1053 if (err) { 1054 mlx5_core_err(dev, "query hca failed\n"); 1055 goto stop_health; 1056 } 1057 1058 return 0; 1059 1060 stop_health: 1061 mlx5_stop_health_poll(dev, boot); 1062 reclaim_boot_pages: 1063 mlx5_reclaim_startup_pages(dev); 1064 err_disable_hca: 1065 mlx5_core_disable_hca(dev, 0); 1066 err_cmd_cleanup: 1067 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1068 mlx5_cmd_cleanup(dev); 1069 1070 return err; 1071 } 1072 1073 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1074 { 1075 int err; 1076 1077 mlx5_stop_health_poll(dev, boot); 1078 err = mlx5_cmd_teardown_hca(dev); 1079 if (err) { 1080 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1081 return err; 1082 } 1083 mlx5_reclaim_startup_pages(dev); 1084 mlx5_core_disable_hca(dev, 0); 1085 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1086 mlx5_cmd_cleanup(dev); 1087 1088 return 0; 1089 } 1090 1091 static int mlx5_load(struct mlx5_core_dev *dev) 1092 { 1093 int err; 1094 1095 dev->priv.uar = mlx5_get_uars_page(dev); 1096 if (IS_ERR(dev->priv.uar)) { 1097 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1098 err = PTR_ERR(dev->priv.uar); 1099 return err; 1100 } 1101 1102 mlx5_events_start(dev); 1103 mlx5_pagealloc_start(dev); 1104 1105 err = mlx5_irq_table_create(dev); 1106 if (err) { 1107 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1108 goto err_irq_table; 1109 } 1110 1111 err = mlx5_eq_table_create(dev); 1112 if (err) { 1113 mlx5_core_err(dev, "Failed to create EQs\n"); 1114 goto err_eq_table; 1115 } 1116 1117 err = mlx5_fw_tracer_init(dev->tracer); 1118 if (err) { 1119 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1120 goto err_fw_tracer; 1121 } 1122 1123 mlx5_fw_reset_events_start(dev); 1124 mlx5_hv_vhca_init(dev->hv_vhca); 1125 1126 err = mlx5_rsc_dump_init(dev); 1127 if (err) { 1128 mlx5_core_err(dev, "Failed to init Resource dump\n"); 1129 goto err_rsc_dump; 1130 } 1131 1132 err = mlx5_fpga_device_start(dev); 1133 if (err) { 1134 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1135 goto err_fpga_start; 1136 } 1137 1138 mlx5_accel_ipsec_init(dev); 1139 1140 err = mlx5_accel_tls_init(dev); 1141 if (err) { 1142 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1143 goto err_tls_start; 1144 } 1145 1146 err = mlx5_init_fs(dev); 1147 if (err) { 1148 mlx5_core_err(dev, "Failed to init flow steering\n"); 1149 goto err_fs; 1150 } 1151 1152 err = mlx5_core_set_hca_defaults(dev); 1153 if (err) { 1154 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1155 goto err_set_hca; 1156 } 1157 1158 mlx5_vhca_event_start(dev); 1159 1160 err = mlx5_sf_hw_table_create(dev); 1161 if (err) { 1162 mlx5_core_err(dev, "sf table create failed %d\n", err); 1163 goto err_vhca; 1164 } 1165 1166 err = mlx5_ec_init(dev); 1167 if (err) { 1168 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1169 goto err_ec; 1170 } 1171 1172 mlx5_lag_add_mdev(dev); 1173 err = mlx5_sriov_attach(dev); 1174 if (err) { 1175 mlx5_core_err(dev, "sriov init failed %d\n", err); 1176 goto err_sriov; 1177 } 1178 1179 mlx5_sf_dev_table_create(dev); 1180 1181 return 0; 1182 1183 err_sriov: 1184 mlx5_lag_remove_mdev(dev); 1185 mlx5_ec_cleanup(dev); 1186 err_ec: 1187 mlx5_sf_hw_table_destroy(dev); 1188 err_vhca: 1189 mlx5_vhca_event_stop(dev); 1190 err_set_hca: 1191 mlx5_cleanup_fs(dev); 1192 err_fs: 1193 mlx5_accel_tls_cleanup(dev); 1194 err_tls_start: 1195 mlx5_accel_ipsec_cleanup(dev); 1196 mlx5_fpga_device_stop(dev); 1197 err_fpga_start: 1198 mlx5_rsc_dump_cleanup(dev); 1199 err_rsc_dump: 1200 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1201 mlx5_fw_reset_events_stop(dev); 1202 mlx5_fw_tracer_cleanup(dev->tracer); 1203 err_fw_tracer: 1204 mlx5_eq_table_destroy(dev); 1205 err_eq_table: 1206 mlx5_irq_table_destroy(dev); 1207 err_irq_table: 1208 mlx5_pagealloc_stop(dev); 1209 mlx5_events_stop(dev); 1210 mlx5_put_uars_page(dev, dev->priv.uar); 1211 return err; 1212 } 1213 1214 static void mlx5_unload(struct mlx5_core_dev *dev) 1215 { 1216 mlx5_sf_dev_table_destroy(dev); 1217 mlx5_sriov_detach(dev); 1218 mlx5_lag_remove_mdev(dev); 1219 mlx5_ec_cleanup(dev); 1220 mlx5_sf_hw_table_destroy(dev); 1221 mlx5_vhca_event_stop(dev); 1222 mlx5_cleanup_fs(dev); 1223 mlx5_accel_ipsec_cleanup(dev); 1224 mlx5_accel_tls_cleanup(dev); 1225 mlx5_fpga_device_stop(dev); 1226 mlx5_rsc_dump_cleanup(dev); 1227 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1228 mlx5_fw_reset_events_stop(dev); 1229 mlx5_fw_tracer_cleanup(dev->tracer); 1230 mlx5_eq_table_destroy(dev); 1231 mlx5_irq_table_destroy(dev); 1232 mlx5_pagealloc_stop(dev); 1233 mlx5_events_stop(dev); 1234 mlx5_put_uars_page(dev, dev->priv.uar); 1235 } 1236 1237 int mlx5_init_one(struct mlx5_core_dev *dev) 1238 { 1239 int err = 0; 1240 1241 mutex_lock(&dev->intf_state_mutex); 1242 dev->state = MLX5_DEVICE_STATE_UP; 1243 1244 err = mlx5_function_setup(dev, true); 1245 if (err) 1246 goto err_function; 1247 1248 err = mlx5_init_once(dev); 1249 if (err) { 1250 mlx5_core_err(dev, "sw objs init failed\n"); 1251 goto function_teardown; 1252 } 1253 1254 err = mlx5_load(dev); 1255 if (err) 1256 goto err_load; 1257 1258 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1259 1260 err = mlx5_devlink_register(priv_to_devlink(dev)); 1261 if (err) 1262 goto err_devlink_reg; 1263 1264 err = mlx5_register_device(dev); 1265 if (err) 1266 goto err_register; 1267 1268 mutex_unlock(&dev->intf_state_mutex); 1269 return 0; 1270 1271 err_register: 1272 mlx5_devlink_unregister(priv_to_devlink(dev)); 1273 err_devlink_reg: 1274 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1275 mlx5_unload(dev); 1276 err_load: 1277 mlx5_cleanup_once(dev); 1278 function_teardown: 1279 mlx5_function_teardown(dev, true); 1280 err_function: 1281 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1282 mutex_unlock(&dev->intf_state_mutex); 1283 return err; 1284 } 1285 1286 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1287 { 1288 mutex_lock(&dev->intf_state_mutex); 1289 1290 mlx5_unregister_device(dev); 1291 mlx5_devlink_unregister(priv_to_devlink(dev)); 1292 1293 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1294 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1295 __func__); 1296 mlx5_cleanup_once(dev); 1297 goto out; 1298 } 1299 1300 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1301 mlx5_unload(dev); 1302 mlx5_cleanup_once(dev); 1303 mlx5_function_teardown(dev, true); 1304 out: 1305 mutex_unlock(&dev->intf_state_mutex); 1306 } 1307 1308 int mlx5_load_one(struct mlx5_core_dev *dev) 1309 { 1310 int err = 0; 1311 1312 mutex_lock(&dev->intf_state_mutex); 1313 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1314 mlx5_core_warn(dev, "interface is up, NOP\n"); 1315 goto out; 1316 } 1317 /* remove any previous indication of internal error */ 1318 dev->state = MLX5_DEVICE_STATE_UP; 1319 1320 err = mlx5_function_setup(dev, false); 1321 if (err) 1322 goto err_function; 1323 1324 err = mlx5_load(dev); 1325 if (err) 1326 goto err_load; 1327 1328 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1329 1330 err = mlx5_attach_device(dev); 1331 if (err) 1332 goto err_attach; 1333 1334 mutex_unlock(&dev->intf_state_mutex); 1335 return 0; 1336 1337 err_attach: 1338 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1339 mlx5_unload(dev); 1340 err_load: 1341 mlx5_function_teardown(dev, false); 1342 err_function: 1343 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1344 out: 1345 mutex_unlock(&dev->intf_state_mutex); 1346 return err; 1347 } 1348 1349 void mlx5_unload_one(struct mlx5_core_dev *dev) 1350 { 1351 mutex_lock(&dev->intf_state_mutex); 1352 1353 mlx5_detach_device(dev); 1354 1355 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1356 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1357 __func__); 1358 goto out; 1359 } 1360 1361 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1362 mlx5_unload(dev); 1363 mlx5_function_teardown(dev, false); 1364 out: 1365 mutex_unlock(&dev->intf_state_mutex); 1366 } 1367 1368 static const int types[] = { 1369 MLX5_CAP_GENERAL, 1370 MLX5_CAP_GENERAL_2, 1371 MLX5_CAP_ETHERNET_OFFLOADS, 1372 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1373 MLX5_CAP_ODP, 1374 MLX5_CAP_ATOMIC, 1375 MLX5_CAP_ROCE, 1376 MLX5_CAP_IPOIB_OFFLOADS, 1377 MLX5_CAP_FLOW_TABLE, 1378 MLX5_CAP_ESWITCH_FLOW_TABLE, 1379 MLX5_CAP_ESWITCH, 1380 MLX5_CAP_VECTOR_CALC, 1381 MLX5_CAP_QOS, 1382 MLX5_CAP_DEBUG, 1383 MLX5_CAP_DEV_MEM, 1384 MLX5_CAP_DEV_EVENT, 1385 MLX5_CAP_TLS, 1386 MLX5_CAP_VDPA_EMULATION, 1387 MLX5_CAP_IPSEC, 1388 }; 1389 1390 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1391 { 1392 int type; 1393 int i; 1394 1395 for (i = 0; i < ARRAY_SIZE(types); i++) { 1396 type = types[i]; 1397 kfree(dev->caps.hca[type]); 1398 } 1399 } 1400 1401 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1402 { 1403 struct mlx5_hca_cap *cap; 1404 int type; 1405 int i; 1406 1407 for (i = 0; i < ARRAY_SIZE(types); i++) { 1408 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1409 if (!cap) 1410 goto err; 1411 type = types[i]; 1412 dev->caps.hca[type] = cap; 1413 } 1414 1415 return 0; 1416 1417 err: 1418 mlx5_hca_caps_free(dev); 1419 return -ENOMEM; 1420 } 1421 1422 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1423 { 1424 struct mlx5_priv *priv = &dev->priv; 1425 int err; 1426 1427 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1428 INIT_LIST_HEAD(&priv->ctx_list); 1429 spin_lock_init(&priv->ctx_lock); 1430 lockdep_register_key(&dev->lock_key); 1431 mutex_init(&dev->intf_state_mutex); 1432 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1433 1434 mutex_init(&priv->bfregs.reg_head.lock); 1435 mutex_init(&priv->bfregs.wc_head.lock); 1436 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1437 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1438 1439 mutex_init(&priv->alloc_mutex); 1440 mutex_init(&priv->pgdir_mutex); 1441 INIT_LIST_HEAD(&priv->pgdir_list); 1442 1443 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1444 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1445 mlx5_debugfs_root); 1446 INIT_LIST_HEAD(&priv->traps); 1447 1448 err = mlx5_health_init(dev); 1449 if (err) 1450 goto err_health_init; 1451 1452 err = mlx5_pagealloc_init(dev); 1453 if (err) 1454 goto err_pagealloc_init; 1455 1456 err = mlx5_adev_init(dev); 1457 if (err) 1458 goto err_adev_init; 1459 1460 err = mlx5_hca_caps_alloc(dev); 1461 if (err) 1462 goto err_hca_caps; 1463 1464 return 0; 1465 1466 err_hca_caps: 1467 mlx5_adev_cleanup(dev); 1468 err_adev_init: 1469 mlx5_pagealloc_cleanup(dev); 1470 err_pagealloc_init: 1471 mlx5_health_cleanup(dev); 1472 err_health_init: 1473 debugfs_remove(dev->priv.dbg_root); 1474 mutex_destroy(&priv->pgdir_mutex); 1475 mutex_destroy(&priv->alloc_mutex); 1476 mutex_destroy(&priv->bfregs.wc_head.lock); 1477 mutex_destroy(&priv->bfregs.reg_head.lock); 1478 mutex_destroy(&dev->intf_state_mutex); 1479 lockdep_unregister_key(&dev->lock_key); 1480 return err; 1481 } 1482 1483 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1484 { 1485 struct mlx5_priv *priv = &dev->priv; 1486 1487 mlx5_hca_caps_free(dev); 1488 mlx5_adev_cleanup(dev); 1489 mlx5_pagealloc_cleanup(dev); 1490 mlx5_health_cleanup(dev); 1491 debugfs_remove_recursive(dev->priv.dbg_root); 1492 mutex_destroy(&priv->pgdir_mutex); 1493 mutex_destroy(&priv->alloc_mutex); 1494 mutex_destroy(&priv->bfregs.wc_head.lock); 1495 mutex_destroy(&priv->bfregs.reg_head.lock); 1496 mutex_destroy(&dev->intf_state_mutex); 1497 lockdep_unregister_key(&dev->lock_key); 1498 } 1499 1500 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1501 { 1502 struct mlx5_core_dev *dev; 1503 struct devlink *devlink; 1504 int err; 1505 1506 devlink = mlx5_devlink_alloc(&pdev->dev); 1507 if (!devlink) { 1508 dev_err(&pdev->dev, "devlink alloc failed\n"); 1509 return -ENOMEM; 1510 } 1511 1512 dev = devlink_priv(devlink); 1513 dev->device = &pdev->dev; 1514 dev->pdev = pdev; 1515 1516 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1517 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1518 1519 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1520 if (dev->priv.adev_idx < 0) { 1521 err = dev->priv.adev_idx; 1522 goto adev_init_err; 1523 } 1524 1525 err = mlx5_mdev_init(dev, prof_sel); 1526 if (err) 1527 goto mdev_init_err; 1528 1529 err = mlx5_pci_init(dev, pdev, id); 1530 if (err) { 1531 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1532 err); 1533 goto pci_init_err; 1534 } 1535 1536 err = mlx5_init_one(dev); 1537 if (err) { 1538 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1539 err); 1540 goto err_init_one; 1541 } 1542 1543 err = mlx5_crdump_enable(dev); 1544 if (err) 1545 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1546 1547 pci_save_state(pdev); 1548 if (!mlx5_core_is_mp_slave(dev)) 1549 devlink_reload_enable(devlink); 1550 return 0; 1551 1552 err_init_one: 1553 mlx5_pci_close(dev); 1554 pci_init_err: 1555 mlx5_mdev_uninit(dev); 1556 mdev_init_err: 1557 mlx5_adev_idx_free(dev->priv.adev_idx); 1558 adev_init_err: 1559 mlx5_devlink_free(devlink); 1560 1561 return err; 1562 } 1563 1564 static void remove_one(struct pci_dev *pdev) 1565 { 1566 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1567 struct devlink *devlink = priv_to_devlink(dev); 1568 1569 devlink_reload_disable(devlink); 1570 mlx5_crdump_disable(dev); 1571 mlx5_drain_health_wq(dev); 1572 mlx5_uninit_one(dev); 1573 mlx5_pci_close(dev); 1574 mlx5_mdev_uninit(dev); 1575 mlx5_adev_idx_free(dev->priv.adev_idx); 1576 mlx5_devlink_free(devlink); 1577 } 1578 1579 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1580 struct mlx5_core_dev *__dev = (dev); \ 1581 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1582 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1583 __dev->pci_status, ##__VA_ARGS__); \ 1584 }) 1585 1586 static const char *result2str(enum pci_ers_result result) 1587 { 1588 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1589 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1590 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1591 "unknown"; 1592 } 1593 1594 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1595 pci_channel_state_t state) 1596 { 1597 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1598 enum pci_ers_result res; 1599 1600 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 1601 1602 mlx5_enter_error_state(dev, false); 1603 mlx5_error_sw_reset(dev); 1604 mlx5_unload_one(dev); 1605 mlx5_drain_health_wq(dev); 1606 mlx5_pci_disable_device(dev); 1607 1608 res = state == pci_channel_io_perm_failure ? 1609 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1610 1611 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res)); 1612 return res; 1613 } 1614 1615 /* wait for the device to show vital signs by waiting 1616 * for the health counter to start counting. 1617 */ 1618 static int wait_vital(struct pci_dev *pdev) 1619 { 1620 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1621 struct mlx5_core_health *health = &dev->priv.health; 1622 const int niter = 100; 1623 u32 last_count = 0; 1624 u32 count; 1625 int i; 1626 1627 for (i = 0; i < niter; i++) { 1628 count = ioread32be(health->health_counter); 1629 if (count && count != 0xffffffff) { 1630 if (last_count && last_count != count) { 1631 mlx5_core_info(dev, 1632 "wait vital counter value 0x%x after %d iterations\n", 1633 count, i); 1634 return 0; 1635 } 1636 last_count = count; 1637 } 1638 msleep(50); 1639 } 1640 1641 return -ETIMEDOUT; 1642 } 1643 1644 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1645 { 1646 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 1647 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1648 int err; 1649 1650 mlx5_pci_trace(dev, "Enter\n"); 1651 1652 err = mlx5_pci_enable_device(dev); 1653 if (err) { 1654 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1655 __func__, err); 1656 goto out; 1657 } 1658 1659 pci_set_master(pdev); 1660 pci_restore_state(pdev); 1661 pci_save_state(pdev); 1662 1663 err = wait_vital(pdev); 1664 if (err) { 1665 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1666 __func__, err); 1667 goto out; 1668 } 1669 1670 res = PCI_ERS_RESULT_RECOVERED; 1671 out: 1672 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res)); 1673 return res; 1674 } 1675 1676 static void mlx5_pci_resume(struct pci_dev *pdev) 1677 { 1678 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1679 int err; 1680 1681 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 1682 1683 err = mlx5_load_one(dev); 1684 1685 if (!err) 1686 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1687 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1688 1689 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1690 !err ? "recovered" : "Failed"); 1691 } 1692 1693 static const struct pci_error_handlers mlx5_err_handler = { 1694 .error_detected = mlx5_pci_err_detected, 1695 .slot_reset = mlx5_pci_slot_reset, 1696 .resume = mlx5_pci_resume 1697 }; 1698 1699 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1700 { 1701 bool fast_teardown = false, force_teardown = false; 1702 int ret = 1; 1703 1704 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1705 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1706 1707 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1708 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1709 1710 if (!fast_teardown && !force_teardown) 1711 return -EOPNOTSUPP; 1712 1713 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1714 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1715 return -EAGAIN; 1716 } 1717 1718 /* Panic tear down fw command will stop the PCI bus communication 1719 * with the HCA, so the health polll is no longer needed. 1720 */ 1721 mlx5_drain_health_wq(dev); 1722 mlx5_stop_health_poll(dev, false); 1723 1724 ret = mlx5_cmd_fast_teardown_hca(dev); 1725 if (!ret) 1726 goto succeed; 1727 1728 ret = mlx5_cmd_force_teardown_hca(dev); 1729 if (!ret) 1730 goto succeed; 1731 1732 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1733 mlx5_start_health_poll(dev); 1734 return ret; 1735 1736 succeed: 1737 mlx5_enter_error_state(dev, true); 1738 1739 /* Some platforms requiring freeing the IRQ's in the shutdown 1740 * flow. If they aren't freed they can't be allocated after 1741 * kexec. There is no need to cleanup the mlx5_core software 1742 * contexts. 1743 */ 1744 mlx5_core_eq_free_irqs(dev); 1745 1746 return 0; 1747 } 1748 1749 static void shutdown(struct pci_dev *pdev) 1750 { 1751 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1752 int err; 1753 1754 mlx5_core_info(dev, "Shutdown was called\n"); 1755 err = mlx5_try_fast_unload(dev); 1756 if (err) 1757 mlx5_unload_one(dev); 1758 mlx5_pci_disable_device(dev); 1759 } 1760 1761 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1762 { 1763 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1764 1765 mlx5_unload_one(dev); 1766 1767 return 0; 1768 } 1769 1770 static int mlx5_resume(struct pci_dev *pdev) 1771 { 1772 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1773 1774 return mlx5_load_one(dev); 1775 } 1776 1777 static const struct pci_device_id mlx5_core_pci_table[] = { 1778 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1779 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1780 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1781 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1782 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1783 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1784 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1785 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1786 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1787 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1788 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1789 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1790 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1791 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1792 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1793 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1794 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 1795 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1796 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1797 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1798 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1799 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 1800 { 0, } 1801 }; 1802 1803 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1804 1805 void mlx5_disable_device(struct mlx5_core_dev *dev) 1806 { 1807 mlx5_error_sw_reset(dev); 1808 mlx5_unload_one(dev); 1809 } 1810 1811 int mlx5_recover_device(struct mlx5_core_dev *dev) 1812 { 1813 if (!mlx5_core_is_sf(dev)) { 1814 mlx5_pci_disable_device(dev); 1815 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 1816 return -EIO; 1817 } 1818 1819 return mlx5_load_one(dev); 1820 } 1821 1822 static struct pci_driver mlx5_core_driver = { 1823 .name = KBUILD_MODNAME, 1824 .id_table = mlx5_core_pci_table, 1825 .probe = probe_one, 1826 .remove = remove_one, 1827 .suspend = mlx5_suspend, 1828 .resume = mlx5_resume, 1829 .shutdown = shutdown, 1830 .err_handler = &mlx5_err_handler, 1831 .sriov_configure = mlx5_core_sriov_configure, 1832 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1833 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 1834 }; 1835 1836 static void mlx5_core_verify_params(void) 1837 { 1838 if (prof_sel >= ARRAY_SIZE(profile)) { 1839 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1840 prof_sel, 1841 ARRAY_SIZE(profile) - 1, 1842 MLX5_DEFAULT_PROF); 1843 prof_sel = MLX5_DEFAULT_PROF; 1844 } 1845 } 1846 1847 static int __init init(void) 1848 { 1849 int err; 1850 1851 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 1852 "mlx5_core name not in sync with kernel module name"); 1853 1854 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1855 1856 mlx5_core_verify_params(); 1857 mlx5_fpga_ipsec_build_fs_cmds(); 1858 mlx5_register_debugfs(); 1859 1860 err = pci_register_driver(&mlx5_core_driver); 1861 if (err) 1862 goto err_debug; 1863 1864 err = mlx5_sf_driver_register(); 1865 if (err) 1866 goto err_sf; 1867 1868 err = mlx5e_init(); 1869 if (err) 1870 goto err_en; 1871 1872 return 0; 1873 1874 err_en: 1875 mlx5_sf_driver_unregister(); 1876 err_sf: 1877 pci_unregister_driver(&mlx5_core_driver); 1878 err_debug: 1879 mlx5_unregister_debugfs(); 1880 return err; 1881 } 1882 1883 static void __exit cleanup(void) 1884 { 1885 mlx5e_cleanup(); 1886 mlx5_sf_driver_unregister(); 1887 pci_unregister_driver(&mlx5_core_driver); 1888 mlx5_unregister_debugfs(); 1889 } 1890 1891 module_init(init); 1892 module_exit(cleanup); 1893