1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "lib/tout.h" 64 #include "fpga/core.h" 65 #include "en_accel/ipsec.h" 66 #include "lib/clock.h" 67 #include "lib/vxlan.h" 68 #include "lib/geneve.h" 69 #include "lib/devcom.h" 70 #include "lib/pci_vsc.h" 71 #include "diag/fw_tracer.h" 72 #include "ecpf.h" 73 #include "lib/hv_vhca.h" 74 #include "diag/rsc_dump.h" 75 #include "sf/vhca_event.h" 76 #include "sf/dev/dev.h" 77 #include "sf/sf.h" 78 #include "mlx5_irq.h" 79 80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 82 MODULE_LICENSE("Dual BSD/GPL"); 83 84 unsigned int mlx5_core_debug_mask; 85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 87 88 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 89 module_param_named(prof_sel, prof_sel, uint, 0444); 90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 91 92 static u32 sw_owner_id[4]; 93 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 94 static DEFINE_IDA(sw_vhca_ida); 95 96 enum { 97 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 99 }; 100 101 #define LOG_MAX_SUPPORTED_QPS 0xff 102 103 static struct mlx5_profile profile[] = { 104 [0] = { 105 .mask = 0, 106 }, 107 [1] = { 108 .mask = MLX5_PROF_MASK_QP_SIZE, 109 .log_max_qp = 12, 110 }, 111 [2] = { 112 .mask = MLX5_PROF_MASK_QP_SIZE | 113 MLX5_PROF_MASK_MR_CACHE, 114 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 115 .mr_cache[0] = { 116 .size = 500, 117 .limit = 250 118 }, 119 .mr_cache[1] = { 120 .size = 500, 121 .limit = 250 122 }, 123 .mr_cache[2] = { 124 .size = 500, 125 .limit = 250 126 }, 127 .mr_cache[3] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[4] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[5] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[6] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[7] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[8] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[9] = { 152 .size = 500, 153 .limit = 250 154 }, 155 .mr_cache[10] = { 156 .size = 500, 157 .limit = 250 158 }, 159 .mr_cache[11] = { 160 .size = 500, 161 .limit = 250 162 }, 163 .mr_cache[12] = { 164 .size = 64, 165 .limit = 32 166 }, 167 .mr_cache[13] = { 168 .size = 32, 169 .limit = 16 170 }, 171 .mr_cache[14] = { 172 .size = 16, 173 .limit = 8 174 }, 175 .mr_cache[15] = { 176 .size = 8, 177 .limit = 4 178 }, 179 }, 180 }; 181 182 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 183 u32 warn_time_mili) 184 { 185 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 186 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 187 u32 fw_initializing; 188 int err = 0; 189 190 do { 191 fw_initializing = ioread32be(&dev->iseg->initializing); 192 if (!(fw_initializing >> 31)) 193 break; 194 if (time_after(jiffies, end) || 195 test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 196 err = -EBUSY; 197 break; 198 } 199 if (warn_time_mili && time_after(jiffies, warn)) { 200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 201 jiffies_to_msecs(end - warn) / 1000, fw_initializing); 202 warn = jiffies + msecs_to_jiffies(warn_time_mili); 203 } 204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 205 } while (true); 206 207 return err; 208 } 209 210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 211 { 212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 213 driver_version); 214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 215 int remaining_size = driver_ver_sz; 216 char *string; 217 218 if (!MLX5_CAP_GEN(dev, driver_version)) 219 return; 220 221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 222 223 strncpy(string, "Linux", remaining_size); 224 225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 226 strncat(string, ",", remaining_size); 227 228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229 strncat(string, KBUILD_MODNAME, remaining_size); 230 231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232 strncat(string, ",", remaining_size); 233 234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235 236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 238 LINUX_VERSION_SUBLEVEL); 239 240 /*Send the command*/ 241 MLX5_SET(set_driver_version_in, in, opcode, 242 MLX5_CMD_OP_SET_DRIVER_VERSION); 243 244 mlx5_cmd_exec_in(dev, set_driver_version, in); 245 } 246 247 static int set_dma_caps(struct pci_dev *pdev) 248 { 249 int err; 250 251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 252 if (err) { 253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 255 if (err) { 256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 257 return err; 258 } 259 } 260 261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 262 return err; 263 } 264 265 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 266 { 267 struct pci_dev *pdev = dev->pdev; 268 int err = 0; 269 270 mutex_lock(&dev->pci_status_mutex); 271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 272 err = pci_enable_device(pdev); 273 if (!err) 274 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 275 } 276 mutex_unlock(&dev->pci_status_mutex); 277 278 return err; 279 } 280 281 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 282 { 283 struct pci_dev *pdev = dev->pdev; 284 285 mutex_lock(&dev->pci_status_mutex); 286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 287 pci_disable_device(pdev); 288 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 289 } 290 mutex_unlock(&dev->pci_status_mutex); 291 } 292 293 static int request_bar(struct pci_dev *pdev) 294 { 295 int err = 0; 296 297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 299 return -ENODEV; 300 } 301 302 err = pci_request_regions(pdev, KBUILD_MODNAME); 303 if (err) 304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 305 306 return err; 307 } 308 309 static void release_bar(struct pci_dev *pdev) 310 { 311 pci_release_regions(pdev); 312 } 313 314 struct mlx5_reg_host_endianness { 315 u8 he; 316 u8 rsvd[15]; 317 }; 318 319 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 320 { 321 switch (size) { 322 case 128: 323 return 0; 324 case 256: 325 return 1; 326 case 512: 327 return 2; 328 case 1024: 329 return 3; 330 case 2048: 331 return 4; 332 case 4096: 333 return 5; 334 default: 335 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 336 return 0; 337 } 338 } 339 340 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 341 enum mlx5_cap_type cap_type, 342 enum mlx5_cap_mode cap_mode) 343 { 344 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 345 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 346 void *out, *hca_caps; 347 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 348 int err; 349 350 memset(in, 0, sizeof(in)); 351 out = kzalloc(out_sz, GFP_KERNEL); 352 if (!out) 353 return -ENOMEM; 354 355 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 356 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 357 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 358 if (err) { 359 mlx5_core_warn(dev, 360 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 361 cap_type, cap_mode, err); 362 goto query_ex; 363 } 364 365 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 366 367 switch (cap_mode) { 368 case HCA_CAP_OPMOD_GET_MAX: 369 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 370 MLX5_UN_SZ_BYTES(hca_cap_union)); 371 break; 372 case HCA_CAP_OPMOD_GET_CUR: 373 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 374 MLX5_UN_SZ_BYTES(hca_cap_union)); 375 break; 376 default: 377 mlx5_core_warn(dev, 378 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 379 cap_type, cap_mode); 380 err = -EINVAL; 381 break; 382 } 383 query_ex: 384 kfree(out); 385 return err; 386 } 387 388 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 389 { 390 int ret; 391 392 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 393 if (ret) 394 return ret; 395 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 396 } 397 398 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 399 { 400 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 401 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 402 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 403 } 404 405 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 406 { 407 void *set_hca_cap; 408 int req_endianness; 409 int err; 410 411 if (!MLX5_CAP_GEN(dev, atomic)) 412 return 0; 413 414 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 415 if (err) 416 return err; 417 418 req_endianness = 419 MLX5_CAP_ATOMIC(dev, 420 supported_atomic_req_8B_endianness_mode_1); 421 422 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 423 return 0; 424 425 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 426 427 /* Set requestor to host endianness */ 428 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 429 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 430 431 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 432 } 433 434 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 435 { 436 void *set_hca_cap; 437 bool do_set = false; 438 int err; 439 440 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 441 !MLX5_CAP_GEN(dev, pg)) 442 return 0; 443 444 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 445 if (err) 446 return err; 447 448 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 449 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 450 MLX5_ST_SZ_BYTES(odp_cap)); 451 452 #define ODP_CAP_SET_MAX(dev, field) \ 453 do { \ 454 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 455 if (_res) { \ 456 do_set = true; \ 457 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 458 } \ 459 } while (0) 460 461 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 462 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 463 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 464 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 465 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 466 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 467 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 469 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 470 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 471 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 472 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 473 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 474 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 475 476 if (!do_set) 477 return 0; 478 479 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 480 } 481 482 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 483 { 484 struct devlink *devlink = priv_to_devlink(dev); 485 union devlink_param_value val; 486 int err; 487 488 err = devlink_param_driverinit_value_get(devlink, 489 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 490 &val); 491 if (!err) 492 return val.vu32; 493 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 494 return err; 495 } 496 497 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 498 { 499 void *set_hca_cap; 500 int err; 501 502 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 503 return 0; 504 505 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 506 if (err) 507 return err; 508 509 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 510 !(dev->priv.sw_vhca_id > 0)) 511 return 0; 512 513 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 514 capability); 515 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 516 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 517 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 518 519 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 520 } 521 522 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 523 { 524 struct mlx5_profile *prof = &dev->profile; 525 void *set_hca_cap; 526 int max_uc_list; 527 int err; 528 529 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 530 if (err) 531 return err; 532 533 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 534 capability); 535 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 536 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 537 538 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 539 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 540 128); 541 /* we limit the size of the pkey table to 128 entries for now */ 542 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 543 to_fw_pkey_sz(dev, 128)); 544 545 /* Check log_max_qp from HCA caps to set in current profile */ 546 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 547 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 548 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 549 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 550 prof->log_max_qp, 551 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 552 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 553 } 554 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 555 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 556 prof->log_max_qp); 557 558 /* disable cmdif checksum */ 559 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 560 561 /* Enable 4K UAR only when HCA supports it and page size is bigger 562 * than 4K. 563 */ 564 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 565 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 566 567 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 568 569 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 570 MLX5_SET(cmd_hca_cap, 571 set_hca_cap, 572 cache_line_128byte, 573 cache_line_size() >= 128 ? 1 : 0); 574 575 if (MLX5_CAP_GEN_MAX(dev, dct)) 576 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 577 578 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 579 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 580 581 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 582 MLX5_SET(cmd_hca_cap, 583 set_hca_cap, 584 num_vhca_ports, 585 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 586 587 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 588 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 589 590 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 591 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 592 593 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 594 595 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 596 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 597 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 598 599 if (MLX5_CAP_GEN(dev, roce_rw_supported)) 600 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev)); 601 602 max_uc_list = max_uc_list_get_devlink_param(dev); 603 if (max_uc_list > 0) 604 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 605 ilog2(max_uc_list)); 606 607 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 608 } 609 610 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 611 * boot process. 612 * In case RoCE cap is writable in FW and user/devlink requested to change the 613 * cap, we are yet to query the final state of the above cap. 614 * Hence, the need for this function. 615 * 616 * Returns 617 * True: 618 * 1) RoCE cap is read only in FW and already disabled 619 * OR: 620 * 2) RoCE cap is writable in FW and user/devlink requested it off. 621 * 622 * In any other case, return False. 623 */ 624 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 625 { 626 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) || 627 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 628 } 629 630 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 631 { 632 void *set_hca_cap; 633 int err; 634 635 if (is_roce_fw_disabled(dev)) 636 return 0; 637 638 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 639 if (err) 640 return err; 641 642 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 643 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 644 return 0; 645 646 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 647 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 648 MLX5_ST_SZ_BYTES(roce_cap)); 649 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 650 651 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 652 return err; 653 } 654 655 static int set_hca_cap(struct mlx5_core_dev *dev) 656 { 657 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 658 void *set_ctx; 659 int err; 660 661 set_ctx = kzalloc(set_sz, GFP_KERNEL); 662 if (!set_ctx) 663 return -ENOMEM; 664 665 err = handle_hca_cap(dev, set_ctx); 666 if (err) { 667 mlx5_core_err(dev, "handle_hca_cap failed\n"); 668 goto out; 669 } 670 671 memset(set_ctx, 0, set_sz); 672 err = handle_hca_cap_atomic(dev, set_ctx); 673 if (err) { 674 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 675 goto out; 676 } 677 678 memset(set_ctx, 0, set_sz); 679 err = handle_hca_cap_odp(dev, set_ctx); 680 if (err) { 681 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 682 goto out; 683 } 684 685 memset(set_ctx, 0, set_sz); 686 err = handle_hca_cap_roce(dev, set_ctx); 687 if (err) { 688 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 689 goto out; 690 } 691 692 memset(set_ctx, 0, set_sz); 693 err = handle_hca_cap_2(dev, set_ctx); 694 if (err) { 695 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 696 goto out; 697 } 698 699 out: 700 kfree(set_ctx); 701 return err; 702 } 703 704 static int set_hca_ctrl(struct mlx5_core_dev *dev) 705 { 706 struct mlx5_reg_host_endianness he_in; 707 struct mlx5_reg_host_endianness he_out; 708 int err; 709 710 if (!mlx5_core_is_pf(dev)) 711 return 0; 712 713 memset(&he_in, 0, sizeof(he_in)); 714 he_in.he = MLX5_SET_HOST_ENDIANNESS; 715 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 716 &he_out, sizeof(he_out), 717 MLX5_REG_HOST_ENDIANNESS, 0, 1); 718 return err; 719 } 720 721 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 722 { 723 int ret = 0; 724 725 /* Disable local_lb by default */ 726 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 727 ret = mlx5_nic_vport_update_local_lb(dev, false); 728 729 return ret; 730 } 731 732 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 733 { 734 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 735 736 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 737 MLX5_SET(enable_hca_in, in, function_id, func_id); 738 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 739 dev->caps.embedded_cpu); 740 return mlx5_cmd_exec_in(dev, enable_hca, in); 741 } 742 743 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 744 { 745 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 746 747 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 748 MLX5_SET(disable_hca_in, in, function_id, func_id); 749 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 750 dev->caps.embedded_cpu); 751 return mlx5_cmd_exec_in(dev, disable_hca, in); 752 } 753 754 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 755 { 756 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 757 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 758 u32 sup_issi; 759 int err; 760 761 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 762 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 763 if (err) { 764 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 765 u8 status = MLX5_GET(query_issi_out, query_out, status); 766 767 if (!status || syndrome == MLX5_DRIVER_SYND) { 768 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 769 err, status, syndrome); 770 return err; 771 } 772 773 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 774 dev->issi = 0; 775 return 0; 776 } 777 778 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 779 780 if (sup_issi & (1 << 1)) { 781 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 782 783 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 784 MLX5_SET(set_issi_in, set_in, current_issi, 1); 785 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 786 if (err) { 787 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 788 err); 789 return err; 790 } 791 792 dev->issi = 1; 793 794 return 0; 795 } else if (sup_issi & (1 << 0) || !sup_issi) { 796 return 0; 797 } 798 799 return -EOPNOTSUPP; 800 } 801 802 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 803 const struct pci_device_id *id) 804 { 805 int err = 0; 806 807 mutex_init(&dev->pci_status_mutex); 808 pci_set_drvdata(dev->pdev, dev); 809 810 dev->bar_addr = pci_resource_start(pdev, 0); 811 812 err = mlx5_pci_enable_device(dev); 813 if (err) { 814 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 815 return err; 816 } 817 818 err = request_bar(pdev); 819 if (err) { 820 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 821 goto err_disable; 822 } 823 824 pci_set_master(pdev); 825 826 err = set_dma_caps(pdev); 827 if (err) { 828 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 829 goto err_clr_master; 830 } 831 832 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 833 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 834 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 835 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 836 837 dev->iseg_base = dev->bar_addr; 838 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 839 if (!dev->iseg) { 840 err = -ENOMEM; 841 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 842 goto err_clr_master; 843 } 844 845 mlx5_pci_vsc_init(dev); 846 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 847 return 0; 848 849 err_clr_master: 850 pci_clear_master(dev->pdev); 851 release_bar(dev->pdev); 852 err_disable: 853 mlx5_pci_disable_device(dev); 854 return err; 855 } 856 857 static void mlx5_pci_close(struct mlx5_core_dev *dev) 858 { 859 /* health work might still be active, and it needs pci bar in 860 * order to know the NIC state. Therefore, drain the health WQ 861 * before removing the pci bars 862 */ 863 mlx5_drain_health_wq(dev); 864 iounmap(dev->iseg); 865 pci_clear_master(dev->pdev); 866 release_bar(dev->pdev); 867 mlx5_pci_disable_device(dev); 868 } 869 870 static int mlx5_init_once(struct mlx5_core_dev *dev) 871 { 872 int err; 873 874 dev->priv.devcom = mlx5_devcom_register_device(dev); 875 if (IS_ERR(dev->priv.devcom)) 876 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 877 dev->priv.devcom); 878 879 err = mlx5_query_board_id(dev); 880 if (err) { 881 mlx5_core_err(dev, "query board id failed\n"); 882 goto err_devcom; 883 } 884 885 err = mlx5_irq_table_init(dev); 886 if (err) { 887 mlx5_core_err(dev, "failed to initialize irq table\n"); 888 goto err_devcom; 889 } 890 891 err = mlx5_eq_table_init(dev); 892 if (err) { 893 mlx5_core_err(dev, "failed to initialize eq\n"); 894 goto err_irq_cleanup; 895 } 896 897 err = mlx5_events_init(dev); 898 if (err) { 899 mlx5_core_err(dev, "failed to initialize events\n"); 900 goto err_eq_cleanup; 901 } 902 903 err = mlx5_fw_reset_init(dev); 904 if (err) { 905 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 906 goto err_events_cleanup; 907 } 908 909 mlx5_cq_debugfs_init(dev); 910 911 mlx5_init_reserved_gids(dev); 912 913 mlx5_init_clock(dev); 914 915 dev->vxlan = mlx5_vxlan_create(dev); 916 dev->geneve = mlx5_geneve_create(dev); 917 918 err = mlx5_init_rl_table(dev); 919 if (err) { 920 mlx5_core_err(dev, "Failed to init rate limiting\n"); 921 goto err_tables_cleanup; 922 } 923 924 err = mlx5_mpfs_init(dev); 925 if (err) { 926 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 927 goto err_rl_cleanup; 928 } 929 930 err = mlx5_sriov_init(dev); 931 if (err) { 932 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 933 goto err_mpfs_cleanup; 934 } 935 936 err = mlx5_eswitch_init(dev); 937 if (err) { 938 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 939 goto err_sriov_cleanup; 940 } 941 942 err = mlx5_fpga_init(dev); 943 if (err) { 944 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 945 goto err_eswitch_cleanup; 946 } 947 948 err = mlx5_vhca_event_init(dev); 949 if (err) { 950 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 951 goto err_fpga_cleanup; 952 } 953 954 err = mlx5_sf_hw_table_init(dev); 955 if (err) { 956 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 957 goto err_sf_hw_table_cleanup; 958 } 959 960 err = mlx5_sf_table_init(dev); 961 if (err) { 962 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 963 goto err_sf_table_cleanup; 964 } 965 966 err = mlx5_fs_core_alloc(dev); 967 if (err) { 968 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 969 goto err_fs; 970 } 971 972 dev->dm = mlx5_dm_create(dev); 973 if (IS_ERR(dev->dm)) 974 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 975 976 dev->tracer = mlx5_fw_tracer_create(dev); 977 dev->hv_vhca = mlx5_hv_vhca_create(dev); 978 dev->rsc_dump = mlx5_rsc_dump_create(dev); 979 980 return 0; 981 982 err_fs: 983 mlx5_sf_table_cleanup(dev); 984 err_sf_table_cleanup: 985 mlx5_sf_hw_table_cleanup(dev); 986 err_sf_hw_table_cleanup: 987 mlx5_vhca_event_cleanup(dev); 988 err_fpga_cleanup: 989 mlx5_fpga_cleanup(dev); 990 err_eswitch_cleanup: 991 mlx5_eswitch_cleanup(dev->priv.eswitch); 992 err_sriov_cleanup: 993 mlx5_sriov_cleanup(dev); 994 err_mpfs_cleanup: 995 mlx5_mpfs_cleanup(dev); 996 err_rl_cleanup: 997 mlx5_cleanup_rl_table(dev); 998 err_tables_cleanup: 999 mlx5_geneve_destroy(dev->geneve); 1000 mlx5_vxlan_destroy(dev->vxlan); 1001 mlx5_cq_debugfs_cleanup(dev); 1002 mlx5_fw_reset_cleanup(dev); 1003 err_events_cleanup: 1004 mlx5_events_cleanup(dev); 1005 err_eq_cleanup: 1006 mlx5_eq_table_cleanup(dev); 1007 err_irq_cleanup: 1008 mlx5_irq_table_cleanup(dev); 1009 err_devcom: 1010 mlx5_devcom_unregister_device(dev->priv.devcom); 1011 1012 return err; 1013 } 1014 1015 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1016 { 1017 mlx5_rsc_dump_destroy(dev); 1018 mlx5_hv_vhca_destroy(dev->hv_vhca); 1019 mlx5_fw_tracer_destroy(dev->tracer); 1020 mlx5_dm_cleanup(dev); 1021 mlx5_fs_core_free(dev); 1022 mlx5_sf_table_cleanup(dev); 1023 mlx5_sf_hw_table_cleanup(dev); 1024 mlx5_vhca_event_cleanup(dev); 1025 mlx5_fpga_cleanup(dev); 1026 mlx5_eswitch_cleanup(dev->priv.eswitch); 1027 mlx5_sriov_cleanup(dev); 1028 mlx5_mpfs_cleanup(dev); 1029 mlx5_cleanup_rl_table(dev); 1030 mlx5_geneve_destroy(dev->geneve); 1031 mlx5_vxlan_destroy(dev->vxlan); 1032 mlx5_cleanup_clock(dev); 1033 mlx5_cleanup_reserved_gids(dev); 1034 mlx5_cq_debugfs_cleanup(dev); 1035 mlx5_fw_reset_cleanup(dev); 1036 mlx5_events_cleanup(dev); 1037 mlx5_eq_table_cleanup(dev); 1038 mlx5_irq_table_cleanup(dev); 1039 mlx5_devcom_unregister_device(dev->priv.devcom); 1040 } 1041 1042 static int mlx5_function_setup(struct mlx5_core_dev *dev, u64 timeout) 1043 { 1044 int err; 1045 1046 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1047 fw_rev_min(dev), fw_rev_sub(dev)); 1048 1049 /* Only PFs hold the relevant PCIe information for this query */ 1050 if (mlx5_core_is_pf(dev)) 1051 pcie_print_link_status(dev->pdev); 1052 1053 /* wait for firmware to accept initialization segments configurations 1054 */ 1055 err = wait_fw_init(dev, timeout, 1056 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 1057 if (err) { 1058 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 1059 timeout); 1060 return err; 1061 } 1062 1063 err = mlx5_cmd_init(dev); 1064 if (err) { 1065 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1066 return err; 1067 } 1068 1069 mlx5_tout_query_iseg(dev); 1070 1071 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1072 if (err) { 1073 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 1074 mlx5_tout_ms(dev, FW_INIT)); 1075 goto err_cmd_cleanup; 1076 } 1077 1078 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1079 1080 err = mlx5_core_enable_hca(dev, 0); 1081 if (err) { 1082 mlx5_core_err(dev, "enable hca failed\n"); 1083 goto err_cmd_cleanup; 1084 } 1085 1086 err = mlx5_core_set_issi(dev); 1087 if (err) { 1088 mlx5_core_err(dev, "failed to set issi\n"); 1089 goto err_disable_hca; 1090 } 1091 1092 err = mlx5_satisfy_startup_pages(dev, 1); 1093 if (err) { 1094 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1095 goto err_disable_hca; 1096 } 1097 1098 err = mlx5_tout_query_dtor(dev); 1099 if (err) { 1100 mlx5_core_err(dev, "failed to read dtor\n"); 1101 goto reclaim_boot_pages; 1102 } 1103 1104 err = set_hca_ctrl(dev); 1105 if (err) { 1106 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1107 goto reclaim_boot_pages; 1108 } 1109 1110 err = set_hca_cap(dev); 1111 if (err) { 1112 mlx5_core_err(dev, "set_hca_cap failed\n"); 1113 goto reclaim_boot_pages; 1114 } 1115 1116 err = mlx5_satisfy_startup_pages(dev, 0); 1117 if (err) { 1118 mlx5_core_err(dev, "failed to allocate init pages\n"); 1119 goto reclaim_boot_pages; 1120 } 1121 1122 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1123 if (err) { 1124 mlx5_core_err(dev, "init hca failed\n"); 1125 goto reclaim_boot_pages; 1126 } 1127 1128 mlx5_set_driver_version(dev); 1129 1130 err = mlx5_query_hca_caps(dev); 1131 if (err) { 1132 mlx5_core_err(dev, "query hca failed\n"); 1133 goto reclaim_boot_pages; 1134 } 1135 1136 mlx5_start_health_poll(dev); 1137 1138 return 0; 1139 1140 reclaim_boot_pages: 1141 mlx5_reclaim_startup_pages(dev); 1142 err_disable_hca: 1143 mlx5_core_disable_hca(dev, 0); 1144 err_cmd_cleanup: 1145 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1146 mlx5_cmd_cleanup(dev); 1147 1148 return err; 1149 } 1150 1151 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1152 { 1153 int err; 1154 1155 mlx5_stop_health_poll(dev, boot); 1156 err = mlx5_cmd_teardown_hca(dev); 1157 if (err) { 1158 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1159 return err; 1160 } 1161 mlx5_reclaim_startup_pages(dev); 1162 mlx5_core_disable_hca(dev, 0); 1163 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1164 mlx5_cmd_cleanup(dev); 1165 1166 return 0; 1167 } 1168 1169 static int mlx5_load(struct mlx5_core_dev *dev) 1170 { 1171 int err; 1172 1173 dev->priv.uar = mlx5_get_uars_page(dev); 1174 if (IS_ERR(dev->priv.uar)) { 1175 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1176 err = PTR_ERR(dev->priv.uar); 1177 return err; 1178 } 1179 1180 mlx5_events_start(dev); 1181 mlx5_pagealloc_start(dev); 1182 1183 err = mlx5_irq_table_create(dev); 1184 if (err) { 1185 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1186 goto err_irq_table; 1187 } 1188 1189 err = mlx5_eq_table_create(dev); 1190 if (err) { 1191 mlx5_core_err(dev, "Failed to create EQs\n"); 1192 goto err_eq_table; 1193 } 1194 1195 err = mlx5_fw_tracer_init(dev->tracer); 1196 if (err) { 1197 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1198 mlx5_fw_tracer_destroy(dev->tracer); 1199 dev->tracer = NULL; 1200 } 1201 1202 mlx5_fw_reset_events_start(dev); 1203 mlx5_hv_vhca_init(dev->hv_vhca); 1204 1205 err = mlx5_rsc_dump_init(dev); 1206 if (err) { 1207 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1208 mlx5_rsc_dump_destroy(dev); 1209 dev->rsc_dump = NULL; 1210 } 1211 1212 err = mlx5_fpga_device_start(dev); 1213 if (err) { 1214 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1215 goto err_fpga_start; 1216 } 1217 1218 err = mlx5_fs_core_init(dev); 1219 if (err) { 1220 mlx5_core_err(dev, "Failed to init flow steering\n"); 1221 goto err_fs; 1222 } 1223 1224 err = mlx5_core_set_hca_defaults(dev); 1225 if (err) { 1226 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1227 goto err_set_hca; 1228 } 1229 1230 mlx5_vhca_event_start(dev); 1231 1232 err = mlx5_sf_hw_table_create(dev); 1233 if (err) { 1234 mlx5_core_err(dev, "sf table create failed %d\n", err); 1235 goto err_vhca; 1236 } 1237 1238 err = mlx5_ec_init(dev); 1239 if (err) { 1240 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1241 goto err_ec; 1242 } 1243 1244 mlx5_lag_add_mdev(dev); 1245 err = mlx5_sriov_attach(dev); 1246 if (err) { 1247 mlx5_core_err(dev, "sriov init failed %d\n", err); 1248 goto err_sriov; 1249 } 1250 1251 mlx5_sf_dev_table_create(dev); 1252 1253 return 0; 1254 1255 err_sriov: 1256 mlx5_lag_remove_mdev(dev); 1257 mlx5_ec_cleanup(dev); 1258 err_ec: 1259 mlx5_sf_hw_table_destroy(dev); 1260 err_vhca: 1261 mlx5_vhca_event_stop(dev); 1262 err_set_hca: 1263 mlx5_fs_core_cleanup(dev); 1264 err_fs: 1265 mlx5_fpga_device_stop(dev); 1266 err_fpga_start: 1267 mlx5_rsc_dump_cleanup(dev); 1268 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1269 mlx5_fw_reset_events_stop(dev); 1270 mlx5_fw_tracer_cleanup(dev->tracer); 1271 mlx5_eq_table_destroy(dev); 1272 err_eq_table: 1273 mlx5_irq_table_destroy(dev); 1274 err_irq_table: 1275 mlx5_pagealloc_stop(dev); 1276 mlx5_events_stop(dev); 1277 mlx5_put_uars_page(dev, dev->priv.uar); 1278 return err; 1279 } 1280 1281 static void mlx5_unload(struct mlx5_core_dev *dev) 1282 { 1283 mlx5_sf_dev_table_destroy(dev); 1284 mlx5_sriov_detach(dev); 1285 mlx5_eswitch_disable(dev->priv.eswitch); 1286 mlx5_lag_remove_mdev(dev); 1287 mlx5_ec_cleanup(dev); 1288 mlx5_sf_hw_table_destroy(dev); 1289 mlx5_vhca_event_stop(dev); 1290 mlx5_fs_core_cleanup(dev); 1291 mlx5_fpga_device_stop(dev); 1292 mlx5_rsc_dump_cleanup(dev); 1293 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1294 mlx5_fw_reset_events_stop(dev); 1295 mlx5_fw_tracer_cleanup(dev->tracer); 1296 mlx5_eq_table_destroy(dev); 1297 mlx5_irq_table_destroy(dev); 1298 mlx5_pagealloc_stop(dev); 1299 mlx5_events_stop(dev); 1300 mlx5_put_uars_page(dev, dev->priv.uar); 1301 } 1302 1303 int mlx5_init_one(struct mlx5_core_dev *dev) 1304 { 1305 struct devlink *devlink = priv_to_devlink(dev); 1306 int err = 0; 1307 1308 devl_lock(devlink); 1309 mutex_lock(&dev->intf_state_mutex); 1310 dev->state = MLX5_DEVICE_STATE_UP; 1311 1312 err = mlx5_function_setup(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1313 if (err) 1314 goto err_function; 1315 1316 err = mlx5_init_once(dev); 1317 if (err) { 1318 mlx5_core_err(dev, "sw objs init failed\n"); 1319 goto function_teardown; 1320 } 1321 1322 err = mlx5_load(dev); 1323 if (err) 1324 goto err_load; 1325 1326 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1327 1328 err = mlx5_devlink_register(priv_to_devlink(dev)); 1329 if (err) 1330 goto err_devlink_reg; 1331 1332 err = mlx5_register_device(dev); 1333 if (err) 1334 goto err_register; 1335 1336 mutex_unlock(&dev->intf_state_mutex); 1337 devl_unlock(devlink); 1338 return 0; 1339 1340 err_register: 1341 mlx5_devlink_unregister(priv_to_devlink(dev)); 1342 err_devlink_reg: 1343 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1344 mlx5_unload(dev); 1345 err_load: 1346 mlx5_cleanup_once(dev); 1347 function_teardown: 1348 mlx5_function_teardown(dev, true); 1349 err_function: 1350 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1351 mutex_unlock(&dev->intf_state_mutex); 1352 devl_unlock(devlink); 1353 return err; 1354 } 1355 1356 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1357 { 1358 struct devlink *devlink = priv_to_devlink(dev); 1359 1360 devl_lock(devlink); 1361 mutex_lock(&dev->intf_state_mutex); 1362 1363 mlx5_unregister_device(dev); 1364 mlx5_devlink_unregister(priv_to_devlink(dev)); 1365 1366 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1367 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1368 __func__); 1369 mlx5_cleanup_once(dev); 1370 goto out; 1371 } 1372 1373 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1374 mlx5_unload(dev); 1375 mlx5_cleanup_once(dev); 1376 mlx5_function_teardown(dev, true); 1377 out: 1378 mutex_unlock(&dev->intf_state_mutex); 1379 devl_unlock(devlink); 1380 } 1381 1382 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1383 { 1384 int err = 0; 1385 u64 timeout; 1386 1387 devl_assert_locked(priv_to_devlink(dev)); 1388 mutex_lock(&dev->intf_state_mutex); 1389 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1390 mlx5_core_warn(dev, "interface is up, NOP\n"); 1391 goto out; 1392 } 1393 /* remove any previous indication of internal error */ 1394 dev->state = MLX5_DEVICE_STATE_UP; 1395 1396 if (recovery) 1397 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1398 else 1399 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1400 err = mlx5_function_setup(dev, timeout); 1401 if (err) 1402 goto err_function; 1403 1404 err = mlx5_load(dev); 1405 if (err) 1406 goto err_load; 1407 1408 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1409 1410 err = mlx5_attach_device(dev); 1411 if (err) 1412 goto err_attach; 1413 1414 mutex_unlock(&dev->intf_state_mutex); 1415 return 0; 1416 1417 err_attach: 1418 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1419 mlx5_unload(dev); 1420 err_load: 1421 mlx5_function_teardown(dev, false); 1422 err_function: 1423 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1424 out: 1425 mutex_unlock(&dev->intf_state_mutex); 1426 return err; 1427 } 1428 1429 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1430 { 1431 struct devlink *devlink = priv_to_devlink(dev); 1432 int ret; 1433 1434 devl_lock(devlink); 1435 ret = mlx5_load_one_devl_locked(dev, recovery); 1436 devl_unlock(devlink); 1437 return ret; 1438 } 1439 1440 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev) 1441 { 1442 devl_assert_locked(priv_to_devlink(dev)); 1443 mutex_lock(&dev->intf_state_mutex); 1444 1445 mlx5_detach_device(dev); 1446 1447 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1448 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1449 __func__); 1450 goto out; 1451 } 1452 1453 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1454 mlx5_unload(dev); 1455 mlx5_function_teardown(dev, false); 1456 out: 1457 mutex_unlock(&dev->intf_state_mutex); 1458 } 1459 1460 void mlx5_unload_one(struct mlx5_core_dev *dev) 1461 { 1462 struct devlink *devlink = priv_to_devlink(dev); 1463 1464 devl_lock(devlink); 1465 mlx5_unload_one_devl_locked(dev); 1466 devl_unlock(devlink); 1467 } 1468 1469 static const int types[] = { 1470 MLX5_CAP_GENERAL, 1471 MLX5_CAP_GENERAL_2, 1472 MLX5_CAP_ETHERNET_OFFLOADS, 1473 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1474 MLX5_CAP_ODP, 1475 MLX5_CAP_ATOMIC, 1476 MLX5_CAP_ROCE, 1477 MLX5_CAP_IPOIB_OFFLOADS, 1478 MLX5_CAP_FLOW_TABLE, 1479 MLX5_CAP_ESWITCH_FLOW_TABLE, 1480 MLX5_CAP_ESWITCH, 1481 MLX5_CAP_VECTOR_CALC, 1482 MLX5_CAP_QOS, 1483 MLX5_CAP_DEBUG, 1484 MLX5_CAP_DEV_MEM, 1485 MLX5_CAP_DEV_EVENT, 1486 MLX5_CAP_TLS, 1487 MLX5_CAP_VDPA_EMULATION, 1488 MLX5_CAP_IPSEC, 1489 MLX5_CAP_PORT_SELECTION, 1490 MLX5_CAP_DEV_SHAMPO, 1491 }; 1492 1493 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1494 { 1495 int type; 1496 int i; 1497 1498 for (i = 0; i < ARRAY_SIZE(types); i++) { 1499 type = types[i]; 1500 kfree(dev->caps.hca[type]); 1501 } 1502 } 1503 1504 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1505 { 1506 struct mlx5_hca_cap *cap; 1507 int type; 1508 int i; 1509 1510 for (i = 0; i < ARRAY_SIZE(types); i++) { 1511 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1512 if (!cap) 1513 goto err; 1514 type = types[i]; 1515 dev->caps.hca[type] = cap; 1516 } 1517 1518 return 0; 1519 1520 err: 1521 mlx5_hca_caps_free(dev); 1522 return -ENOMEM; 1523 } 1524 1525 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1526 { 1527 struct mlx5_priv *priv = &dev->priv; 1528 int err; 1529 1530 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1531 INIT_LIST_HEAD(&priv->ctx_list); 1532 spin_lock_init(&priv->ctx_lock); 1533 mutex_init(&dev->intf_state_mutex); 1534 1535 mutex_init(&priv->bfregs.reg_head.lock); 1536 mutex_init(&priv->bfregs.wc_head.lock); 1537 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1538 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1539 1540 mutex_init(&priv->alloc_mutex); 1541 mutex_init(&priv->pgdir_mutex); 1542 INIT_LIST_HEAD(&priv->pgdir_list); 1543 1544 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1545 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1546 mlx5_debugfs_root); 1547 INIT_LIST_HEAD(&priv->traps); 1548 1549 err = mlx5_tout_init(dev); 1550 if (err) { 1551 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1552 goto err_timeout_init; 1553 } 1554 1555 err = mlx5_health_init(dev); 1556 if (err) 1557 goto err_health_init; 1558 1559 err = mlx5_pagealloc_init(dev); 1560 if (err) 1561 goto err_pagealloc_init; 1562 1563 err = mlx5_adev_init(dev); 1564 if (err) 1565 goto err_adev_init; 1566 1567 err = mlx5_hca_caps_alloc(dev); 1568 if (err) 1569 goto err_hca_caps; 1570 1571 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1572 * unique id per function which uses mlx5_core. 1573 * Those values are supplied to FW as part of the init HCA command to 1574 * be used by both driver and FW when it's applicable. 1575 */ 1576 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1577 MAX_SW_VHCA_ID, 1578 GFP_KERNEL); 1579 if (dev->priv.sw_vhca_id < 0) 1580 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1581 dev->priv.sw_vhca_id); 1582 1583 return 0; 1584 1585 err_hca_caps: 1586 mlx5_adev_cleanup(dev); 1587 err_adev_init: 1588 mlx5_pagealloc_cleanup(dev); 1589 err_pagealloc_init: 1590 mlx5_health_cleanup(dev); 1591 err_health_init: 1592 mlx5_tout_cleanup(dev); 1593 err_timeout_init: 1594 debugfs_remove(dev->priv.dbg.dbg_root); 1595 mutex_destroy(&priv->pgdir_mutex); 1596 mutex_destroy(&priv->alloc_mutex); 1597 mutex_destroy(&priv->bfregs.wc_head.lock); 1598 mutex_destroy(&priv->bfregs.reg_head.lock); 1599 mutex_destroy(&dev->intf_state_mutex); 1600 return err; 1601 } 1602 1603 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1604 { 1605 struct mlx5_priv *priv = &dev->priv; 1606 1607 if (priv->sw_vhca_id > 0) 1608 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1609 1610 mlx5_hca_caps_free(dev); 1611 mlx5_adev_cleanup(dev); 1612 mlx5_pagealloc_cleanup(dev); 1613 mlx5_health_cleanup(dev); 1614 mlx5_tout_cleanup(dev); 1615 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1616 mutex_destroy(&priv->pgdir_mutex); 1617 mutex_destroy(&priv->alloc_mutex); 1618 mutex_destroy(&priv->bfregs.wc_head.lock); 1619 mutex_destroy(&priv->bfregs.reg_head.lock); 1620 mutex_destroy(&dev->intf_state_mutex); 1621 } 1622 1623 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1624 { 1625 struct mlx5_core_dev *dev; 1626 struct devlink *devlink; 1627 int err; 1628 1629 devlink = mlx5_devlink_alloc(&pdev->dev); 1630 if (!devlink) { 1631 dev_err(&pdev->dev, "devlink alloc failed\n"); 1632 return -ENOMEM; 1633 } 1634 1635 dev = devlink_priv(devlink); 1636 dev->device = &pdev->dev; 1637 dev->pdev = pdev; 1638 1639 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1640 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1641 1642 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1643 if (dev->priv.adev_idx < 0) { 1644 err = dev->priv.adev_idx; 1645 goto adev_init_err; 1646 } 1647 1648 err = mlx5_mdev_init(dev, prof_sel); 1649 if (err) 1650 goto mdev_init_err; 1651 1652 err = mlx5_pci_init(dev, pdev, id); 1653 if (err) { 1654 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1655 err); 1656 goto pci_init_err; 1657 } 1658 1659 err = mlx5_init_one(dev); 1660 if (err) { 1661 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1662 err); 1663 goto err_init_one; 1664 } 1665 1666 err = mlx5_crdump_enable(dev); 1667 if (err) 1668 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1669 1670 pci_save_state(pdev); 1671 devlink_register(devlink); 1672 return 0; 1673 1674 err_init_one: 1675 mlx5_pci_close(dev); 1676 pci_init_err: 1677 mlx5_mdev_uninit(dev); 1678 mdev_init_err: 1679 mlx5_adev_idx_free(dev->priv.adev_idx); 1680 adev_init_err: 1681 mlx5_devlink_free(devlink); 1682 1683 return err; 1684 } 1685 1686 static void remove_one(struct pci_dev *pdev) 1687 { 1688 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1689 struct devlink *devlink = priv_to_devlink(dev); 1690 1691 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 1692 * fw_reset before unregistering the devlink. 1693 */ 1694 mlx5_drain_fw_reset(dev); 1695 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1696 devlink_unregister(devlink); 1697 mlx5_sriov_disable(pdev); 1698 mlx5_crdump_disable(dev); 1699 mlx5_drain_health_wq(dev); 1700 mlx5_uninit_one(dev); 1701 mlx5_pci_close(dev); 1702 mlx5_mdev_uninit(dev); 1703 mlx5_adev_idx_free(dev->priv.adev_idx); 1704 mlx5_devlink_free(devlink); 1705 } 1706 1707 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1708 struct mlx5_core_dev *__dev = (dev); \ 1709 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1710 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1711 __dev->pci_status, ##__VA_ARGS__); \ 1712 }) 1713 1714 static const char *result2str(enum pci_ers_result result) 1715 { 1716 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1717 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1718 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1719 "unknown"; 1720 } 1721 1722 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1723 pci_channel_state_t state) 1724 { 1725 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1726 enum pci_ers_result res; 1727 1728 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 1729 1730 mlx5_enter_error_state(dev, false); 1731 mlx5_error_sw_reset(dev); 1732 mlx5_unload_one(dev); 1733 mlx5_drain_health_wq(dev); 1734 mlx5_pci_disable_device(dev); 1735 1736 res = state == pci_channel_io_perm_failure ? 1737 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1738 1739 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res)); 1740 return res; 1741 } 1742 1743 /* wait for the device to show vital signs by waiting 1744 * for the health counter to start counting. 1745 */ 1746 static int wait_vital(struct pci_dev *pdev) 1747 { 1748 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1749 struct mlx5_core_health *health = &dev->priv.health; 1750 const int niter = 100; 1751 u32 last_count = 0; 1752 u32 count; 1753 int i; 1754 1755 for (i = 0; i < niter; i++) { 1756 count = ioread32be(health->health_counter); 1757 if (count && count != 0xffffffff) { 1758 if (last_count && last_count != count) { 1759 mlx5_core_info(dev, 1760 "wait vital counter value 0x%x after %d iterations\n", 1761 count, i); 1762 return 0; 1763 } 1764 last_count = count; 1765 } 1766 msleep(50); 1767 } 1768 1769 return -ETIMEDOUT; 1770 } 1771 1772 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1773 { 1774 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 1775 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1776 int err; 1777 1778 mlx5_pci_trace(dev, "Enter\n"); 1779 1780 err = mlx5_pci_enable_device(dev); 1781 if (err) { 1782 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1783 __func__, err); 1784 goto out; 1785 } 1786 1787 pci_set_master(pdev); 1788 pci_restore_state(pdev); 1789 pci_save_state(pdev); 1790 1791 err = wait_vital(pdev); 1792 if (err) { 1793 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1794 __func__, err); 1795 goto out; 1796 } 1797 1798 res = PCI_ERS_RESULT_RECOVERED; 1799 out: 1800 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res)); 1801 return res; 1802 } 1803 1804 static void mlx5_pci_resume(struct pci_dev *pdev) 1805 { 1806 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1807 int err; 1808 1809 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 1810 1811 err = mlx5_load_one(dev, false); 1812 1813 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1814 !err ? "recovered" : "Failed"); 1815 } 1816 1817 static const struct pci_error_handlers mlx5_err_handler = { 1818 .error_detected = mlx5_pci_err_detected, 1819 .slot_reset = mlx5_pci_slot_reset, 1820 .resume = mlx5_pci_resume 1821 }; 1822 1823 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1824 { 1825 bool fast_teardown = false, force_teardown = false; 1826 int ret = 1; 1827 1828 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1829 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1830 1831 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1832 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1833 1834 if (!fast_teardown && !force_teardown) 1835 return -EOPNOTSUPP; 1836 1837 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1838 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1839 return -EAGAIN; 1840 } 1841 1842 /* Panic tear down fw command will stop the PCI bus communication 1843 * with the HCA, so the health poll is no longer needed. 1844 */ 1845 mlx5_drain_health_wq(dev); 1846 mlx5_stop_health_poll(dev, false); 1847 1848 ret = mlx5_cmd_fast_teardown_hca(dev); 1849 if (!ret) 1850 goto succeed; 1851 1852 ret = mlx5_cmd_force_teardown_hca(dev); 1853 if (!ret) 1854 goto succeed; 1855 1856 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1857 mlx5_start_health_poll(dev); 1858 return ret; 1859 1860 succeed: 1861 mlx5_enter_error_state(dev, true); 1862 1863 /* Some platforms requiring freeing the IRQ's in the shutdown 1864 * flow. If they aren't freed they can't be allocated after 1865 * kexec. There is no need to cleanup the mlx5_core software 1866 * contexts. 1867 */ 1868 mlx5_core_eq_free_irqs(dev); 1869 1870 return 0; 1871 } 1872 1873 static void shutdown(struct pci_dev *pdev) 1874 { 1875 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1876 int err; 1877 1878 mlx5_core_info(dev, "Shutdown was called\n"); 1879 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1880 err = mlx5_try_fast_unload(dev); 1881 if (err) 1882 mlx5_unload_one(dev); 1883 mlx5_pci_disable_device(dev); 1884 } 1885 1886 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1887 { 1888 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1889 1890 mlx5_unload_one(dev); 1891 1892 return 0; 1893 } 1894 1895 static int mlx5_resume(struct pci_dev *pdev) 1896 { 1897 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1898 1899 return mlx5_load_one(dev, false); 1900 } 1901 1902 static const struct pci_device_id mlx5_core_pci_table[] = { 1903 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1904 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1905 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1906 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1907 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1908 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1909 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1910 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1911 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1912 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1913 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1914 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1915 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1916 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1917 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1918 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1919 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 1920 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1921 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1922 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1923 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1924 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 1925 { 0, } 1926 }; 1927 1928 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1929 1930 void mlx5_disable_device(struct mlx5_core_dev *dev) 1931 { 1932 mlx5_error_sw_reset(dev); 1933 mlx5_unload_one_devl_locked(dev); 1934 } 1935 1936 int mlx5_recover_device(struct mlx5_core_dev *dev) 1937 { 1938 if (!mlx5_core_is_sf(dev)) { 1939 mlx5_pci_disable_device(dev); 1940 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 1941 return -EIO; 1942 } 1943 1944 return mlx5_load_one_devl_locked(dev, true); 1945 } 1946 1947 static struct pci_driver mlx5_core_driver = { 1948 .name = KBUILD_MODNAME, 1949 .id_table = mlx5_core_pci_table, 1950 .probe = probe_one, 1951 .remove = remove_one, 1952 .suspend = mlx5_suspend, 1953 .resume = mlx5_resume, 1954 .shutdown = shutdown, 1955 .err_handler = &mlx5_err_handler, 1956 .sriov_configure = mlx5_core_sriov_configure, 1957 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1958 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 1959 }; 1960 1961 /** 1962 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 1963 * mlx5_core is its driver. 1964 * @pdev: The associated PCI device. 1965 * 1966 * Upon return the interface state lock stay held to let caller uses it safely. 1967 * Caller must ensure to use the returned mlx5 device for a narrow window 1968 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 1969 * 1970 * Return: Pointer to the associated mlx5_core_dev or NULL. 1971 */ 1972 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 1973 { 1974 struct mlx5_core_dev *mdev; 1975 1976 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 1977 if (IS_ERR(mdev)) 1978 return NULL; 1979 1980 mutex_lock(&mdev->intf_state_mutex); 1981 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 1982 mutex_unlock(&mdev->intf_state_mutex); 1983 return NULL; 1984 } 1985 1986 return mdev; 1987 } 1988 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 1989 1990 /** 1991 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 1992 * @mdev: The mlx5 core device. 1993 * 1994 * Upon return the interface state lock is unlocked and caller should not 1995 * access the mdev any more. 1996 */ 1997 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 1998 { 1999 mutex_unlock(&mdev->intf_state_mutex); 2000 } 2001 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2002 2003 static void mlx5_core_verify_params(void) 2004 { 2005 if (prof_sel >= ARRAY_SIZE(profile)) { 2006 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2007 prof_sel, 2008 ARRAY_SIZE(profile) - 1, 2009 MLX5_DEFAULT_PROF); 2010 prof_sel = MLX5_DEFAULT_PROF; 2011 } 2012 } 2013 2014 static int __init init(void) 2015 { 2016 int err; 2017 2018 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2019 "mlx5_core name not in sync with kernel module name"); 2020 2021 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2022 2023 mlx5_core_verify_params(); 2024 mlx5_register_debugfs(); 2025 2026 err = pci_register_driver(&mlx5_core_driver); 2027 if (err) 2028 goto err_debug; 2029 2030 err = mlx5_sf_driver_register(); 2031 if (err) 2032 goto err_sf; 2033 2034 err = mlx5e_init(); 2035 if (err) 2036 goto err_en; 2037 2038 return 0; 2039 2040 err_en: 2041 mlx5_sf_driver_unregister(); 2042 err_sf: 2043 pci_unregister_driver(&mlx5_core_driver); 2044 err_debug: 2045 mlx5_unregister_debugfs(); 2046 return err; 2047 } 2048 2049 static void __exit cleanup(void) 2050 { 2051 mlx5e_cleanup(); 2052 mlx5_sf_driver_unregister(); 2053 pci_unregister_driver(&mlx5_core_driver); 2054 mlx5_unregister_debugfs(); 2055 } 2056 2057 module_init(init); 2058 module_exit(cleanup); 2059