1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/interrupt.h> 41 #include <linux/delay.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/cq.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/debugfs.h> 46 #include <linux/kmod.h> 47 #include <linux/mlx5/mlx5_ifc.h> 48 #include <linux/mlx5/vport.h> 49 #include <linux/version.h> 50 #include <net/devlink.h> 51 #include "mlx5_core.h" 52 #include "lib/eq.h" 53 #include "fs_core.h" 54 #include "lib/mpfs.h" 55 #include "eswitch.h" 56 #include "devlink.h" 57 #include "fw_reset.h" 58 #include "lib/mlx5.h" 59 #include "lib/tout.h" 60 #include "fpga/core.h" 61 #include "en_accel/ipsec.h" 62 #include "lib/clock.h" 63 #include "lib/vxlan.h" 64 #include "lib/geneve.h" 65 #include "lib/devcom.h" 66 #include "lib/pci_vsc.h" 67 #include "diag/fw_tracer.h" 68 #include "ecpf.h" 69 #include "lib/hv_vhca.h" 70 #include "diag/rsc_dump.h" 71 #include "sf/vhca_event.h" 72 #include "sf/dev/dev.h" 73 #include "sf/sf.h" 74 #include "mlx5_irq.h" 75 #include "hwmon.h" 76 77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79 MODULE_LICENSE("Dual BSD/GPL"); 80 81 unsigned int mlx5_core_debug_mask; 82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84 85 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86 module_param_named(prof_sel, prof_sel, uint, 0444); 87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 88 89 static u32 sw_owner_id[4]; 90 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 91 static DEFINE_IDA(sw_vhca_ida); 92 93 enum { 94 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 95 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 96 }; 97 98 #define LOG_MAX_SUPPORTED_QPS 0xff 99 100 static struct mlx5_profile profile[] = { 101 [0] = { 102 .mask = 0, 103 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 104 }, 105 [1] = { 106 .mask = MLX5_PROF_MASK_QP_SIZE, 107 .log_max_qp = 12, 108 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 109 110 }, 111 [2] = { 112 .mask = MLX5_PROF_MASK_QP_SIZE | 113 MLX5_PROF_MASK_MR_CACHE, 114 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 115 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 116 .mr_cache[0] = { 117 .size = 500, 118 .limit = 250 119 }, 120 .mr_cache[1] = { 121 .size = 500, 122 .limit = 250 123 }, 124 .mr_cache[2] = { 125 .size = 500, 126 .limit = 250 127 }, 128 .mr_cache[3] = { 129 .size = 500, 130 .limit = 250 131 }, 132 .mr_cache[4] = { 133 .size = 500, 134 .limit = 250 135 }, 136 .mr_cache[5] = { 137 .size = 500, 138 .limit = 250 139 }, 140 .mr_cache[6] = { 141 .size = 500, 142 .limit = 250 143 }, 144 .mr_cache[7] = { 145 .size = 500, 146 .limit = 250 147 }, 148 .mr_cache[8] = { 149 .size = 500, 150 .limit = 250 151 }, 152 .mr_cache[9] = { 153 .size = 500, 154 .limit = 250 155 }, 156 .mr_cache[10] = { 157 .size = 500, 158 .limit = 250 159 }, 160 .mr_cache[11] = { 161 .size = 500, 162 .limit = 250 163 }, 164 .mr_cache[12] = { 165 .size = 64, 166 .limit = 32 167 }, 168 .mr_cache[13] = { 169 .size = 32, 170 .limit = 16 171 }, 172 .mr_cache[14] = { 173 .size = 16, 174 .limit = 8 175 }, 176 .mr_cache[15] = { 177 .size = 8, 178 .limit = 4 179 }, 180 }, 181 [3] = { 182 .mask = MLX5_PROF_MASK_QP_SIZE, 183 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 184 .num_cmd_caches = 0, 185 }, 186 }; 187 188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189 u32 warn_time_mili) 190 { 191 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193 u32 fw_initializing; 194 int err = 0; 195 196 do { 197 fw_initializing = ioread32be(&dev->iseg->initializing); 198 if (!(fw_initializing >> 31)) 199 break; 200 if (time_after(jiffies, end) || 201 test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 202 err = -EBUSY; 203 break; 204 } 205 if (warn_time_mili && time_after(jiffies, warn)) { 206 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 207 jiffies_to_msecs(end - warn) / 1000, fw_initializing); 208 warn = jiffies + msecs_to_jiffies(warn_time_mili); 209 } 210 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 211 } while (true); 212 213 return err; 214 } 215 216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 217 { 218 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 219 driver_version); 220 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 221 int remaining_size = driver_ver_sz; 222 char *string; 223 224 if (!MLX5_CAP_GEN(dev, driver_version)) 225 return; 226 227 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 228 229 strncpy(string, "Linux", remaining_size); 230 231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232 strncat(string, ",", remaining_size); 233 234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235 strncat(string, KBUILD_MODNAME, remaining_size); 236 237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238 strncat(string, ",", remaining_size); 239 240 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 241 242 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 243 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 244 LINUX_VERSION_SUBLEVEL); 245 246 /*Send the command*/ 247 MLX5_SET(set_driver_version_in, in, opcode, 248 MLX5_CMD_OP_SET_DRIVER_VERSION); 249 250 mlx5_cmd_exec_in(dev, set_driver_version, in); 251 } 252 253 static int set_dma_caps(struct pci_dev *pdev) 254 { 255 int err; 256 257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 258 if (err) { 259 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 261 if (err) { 262 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 263 return err; 264 } 265 } 266 267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 268 return err; 269 } 270 271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 272 { 273 struct pci_dev *pdev = dev->pdev; 274 int err = 0; 275 276 mutex_lock(&dev->pci_status_mutex); 277 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 278 err = pci_enable_device(pdev); 279 if (!err) 280 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 281 } 282 mutex_unlock(&dev->pci_status_mutex); 283 284 return err; 285 } 286 287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 288 { 289 struct pci_dev *pdev = dev->pdev; 290 291 mutex_lock(&dev->pci_status_mutex); 292 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 293 pci_disable_device(pdev); 294 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 295 } 296 mutex_unlock(&dev->pci_status_mutex); 297 } 298 299 static int request_bar(struct pci_dev *pdev) 300 { 301 int err = 0; 302 303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 304 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 305 return -ENODEV; 306 } 307 308 err = pci_request_regions(pdev, KBUILD_MODNAME); 309 if (err) 310 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 311 312 return err; 313 } 314 315 static void release_bar(struct pci_dev *pdev) 316 { 317 pci_release_regions(pdev); 318 } 319 320 struct mlx5_reg_host_endianness { 321 u8 he; 322 u8 rsvd[15]; 323 }; 324 325 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 326 { 327 switch (size) { 328 case 128: 329 return 0; 330 case 256: 331 return 1; 332 case 512: 333 return 2; 334 case 1024: 335 return 3; 336 case 2048: 337 return 4; 338 case 4096: 339 return 5; 340 default: 341 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 342 return 0; 343 } 344 } 345 346 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 347 { 348 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 349 dev->mlx5e_res.uplink_netdev = netdev; 350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351 netdev); 352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353 } 354 355 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 356 { 357 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 358 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 359 dev->mlx5e_res.uplink_netdev); 360 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 361 } 362 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 363 364 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data) 365 { 366 mlx5_blocking_notifier_call_chain(dev, event, data); 367 } 368 EXPORT_SYMBOL(mlx5_core_mp_event_replay); 369 370 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 371 enum mlx5_cap_mode cap_mode) 372 { 373 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 374 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 375 void *out, *hca_caps; 376 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 377 int err; 378 379 memset(in, 0, sizeof(in)); 380 out = kzalloc(out_sz, GFP_KERNEL); 381 if (!out) 382 return -ENOMEM; 383 384 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 385 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 386 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 387 if (err) { 388 mlx5_core_warn(dev, 389 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 390 cap_type, cap_mode, err); 391 goto query_ex; 392 } 393 394 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 395 396 switch (cap_mode) { 397 case HCA_CAP_OPMOD_GET_MAX: 398 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 399 MLX5_UN_SZ_BYTES(hca_cap_union)); 400 break; 401 case HCA_CAP_OPMOD_GET_CUR: 402 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 403 MLX5_UN_SZ_BYTES(hca_cap_union)); 404 break; 405 default: 406 mlx5_core_warn(dev, 407 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 408 cap_type, cap_mode); 409 err = -EINVAL; 410 break; 411 } 412 query_ex: 413 kfree(out); 414 return err; 415 } 416 417 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 418 { 419 int ret; 420 421 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 422 if (ret) 423 return ret; 424 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 425 } 426 427 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 428 { 429 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 430 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 431 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 432 } 433 434 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 435 { 436 void *set_hca_cap; 437 int req_endianness; 438 int err; 439 440 if (!MLX5_CAP_GEN(dev, atomic)) 441 return 0; 442 443 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 444 if (err) 445 return err; 446 447 req_endianness = 448 MLX5_CAP_ATOMIC(dev, 449 supported_atomic_req_8B_endianness_mode_1); 450 451 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 452 return 0; 453 454 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 455 456 /* Set requestor to host endianness */ 457 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 458 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 459 460 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 461 } 462 463 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 464 { 465 void *set_hca_cap; 466 bool do_set = false; 467 int err; 468 469 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 470 !MLX5_CAP_GEN(dev, pg)) 471 return 0; 472 473 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 474 if (err) 475 return err; 476 477 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 478 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 479 MLX5_ST_SZ_BYTES(odp_cap)); 480 481 #define ODP_CAP_SET_MAX(dev, field) \ 482 do { \ 483 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 484 if (_res) { \ 485 do_set = true; \ 486 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 487 } \ 488 } while (0) 489 490 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 491 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 492 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 493 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 494 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 495 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 496 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 497 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 498 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 499 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 500 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 501 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 502 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 503 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 504 505 if (!do_set) 506 return 0; 507 508 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 509 } 510 511 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 512 { 513 struct devlink *devlink = priv_to_devlink(dev); 514 union devlink_param_value val; 515 int err; 516 517 err = devl_param_driverinit_value_get(devlink, 518 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 519 &val); 520 if (!err) 521 return val.vu32; 522 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 523 return err; 524 } 525 526 bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 527 { 528 struct devlink *devlink = priv_to_devlink(dev); 529 union devlink_param_value val; 530 int err; 531 532 err = devl_param_driverinit_value_get(devlink, 533 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 534 &val); 535 536 if (!err) 537 return val.vbool; 538 539 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 540 return MLX5_CAP_GEN(dev, roce); 541 } 542 EXPORT_SYMBOL(mlx5_is_roce_on); 543 544 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 545 { 546 void *set_hca_cap; 547 int err; 548 549 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 550 return 0; 551 552 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 553 if (err) 554 return err; 555 556 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 557 !(dev->priv.sw_vhca_id > 0)) 558 return 0; 559 560 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 561 capability); 562 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 563 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 564 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 565 566 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 567 } 568 569 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 570 { 571 struct mlx5_profile *prof = &dev->profile; 572 void *set_hca_cap; 573 int max_uc_list; 574 int err; 575 576 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 577 if (err) 578 return err; 579 580 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 581 capability); 582 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 583 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 584 585 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 586 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 587 128); 588 /* we limit the size of the pkey table to 128 entries for now */ 589 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 590 to_fw_pkey_sz(dev, 128)); 591 592 /* Check log_max_qp from HCA caps to set in current profile */ 593 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 594 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 595 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 596 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 597 prof->log_max_qp, 598 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 599 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 600 } 601 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 602 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 603 prof->log_max_qp); 604 605 /* disable cmdif checksum */ 606 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 607 608 /* Enable 4K UAR only when HCA supports it and page size is bigger 609 * than 4K. 610 */ 611 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 612 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 613 614 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 615 616 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 617 MLX5_SET(cmd_hca_cap, 618 set_hca_cap, 619 cache_line_128byte, 620 cache_line_size() >= 128 ? 1 : 0); 621 622 if (MLX5_CAP_GEN_MAX(dev, dct)) 623 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 624 625 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 626 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 627 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload)) 628 MLX5_SET(cmd_hca_cap, set_hca_cap, 629 pci_sync_for_fw_update_with_driver_unload, 1); 630 631 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 632 MLX5_SET(cmd_hca_cap, 633 set_hca_cap, 634 num_vhca_ports, 635 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 636 637 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 638 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 639 640 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 641 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 642 643 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 644 645 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 646 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 647 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 648 649 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 650 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 651 mlx5_is_roce_on(dev)); 652 653 max_uc_list = max_uc_list_get_devlink_param(dev); 654 if (max_uc_list > 0) 655 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 656 ilog2(max_uc_list)); 657 658 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 659 } 660 661 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 662 * boot process. 663 * In case RoCE cap is writable in FW and user/devlink requested to change the 664 * cap, we are yet to query the final state of the above cap. 665 * Hence, the need for this function. 666 * 667 * Returns 668 * True: 669 * 1) RoCE cap is read only in FW and already disabled 670 * OR: 671 * 2) RoCE cap is writable in FW and user/devlink requested it off. 672 * 673 * In any other case, return False. 674 */ 675 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 676 { 677 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 678 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 679 } 680 681 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 682 { 683 void *set_hca_cap; 684 int err; 685 686 if (is_roce_fw_disabled(dev)) 687 return 0; 688 689 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 690 if (err) 691 return err; 692 693 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 694 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 695 return 0; 696 697 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 698 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 699 MLX5_ST_SZ_BYTES(roce_cap)); 700 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 701 702 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 703 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 704 705 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 706 return err; 707 } 708 709 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 710 void *set_ctx) 711 { 712 void *set_hca_cap; 713 int err; 714 715 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 716 return 0; 717 718 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 719 if (err) 720 return err; 721 722 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 723 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 724 return 0; 725 726 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 727 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 728 MLX5_ST_SZ_BYTES(port_selection_cap)); 729 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 730 731 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 732 733 return err; 734 } 735 736 static int set_hca_cap(struct mlx5_core_dev *dev) 737 { 738 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 739 void *set_ctx; 740 int err; 741 742 set_ctx = kzalloc(set_sz, GFP_KERNEL); 743 if (!set_ctx) 744 return -ENOMEM; 745 746 err = handle_hca_cap(dev, set_ctx); 747 if (err) { 748 mlx5_core_err(dev, "handle_hca_cap failed\n"); 749 goto out; 750 } 751 752 memset(set_ctx, 0, set_sz); 753 err = handle_hca_cap_atomic(dev, set_ctx); 754 if (err) { 755 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 756 goto out; 757 } 758 759 memset(set_ctx, 0, set_sz); 760 err = handle_hca_cap_odp(dev, set_ctx); 761 if (err) { 762 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 763 goto out; 764 } 765 766 memset(set_ctx, 0, set_sz); 767 err = handle_hca_cap_roce(dev, set_ctx); 768 if (err) { 769 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 770 goto out; 771 } 772 773 memset(set_ctx, 0, set_sz); 774 err = handle_hca_cap_2(dev, set_ctx); 775 if (err) { 776 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 777 goto out; 778 } 779 780 memset(set_ctx, 0, set_sz); 781 err = handle_hca_cap_port_selection(dev, set_ctx); 782 if (err) { 783 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 784 goto out; 785 } 786 787 out: 788 kfree(set_ctx); 789 return err; 790 } 791 792 static int set_hca_ctrl(struct mlx5_core_dev *dev) 793 { 794 struct mlx5_reg_host_endianness he_in; 795 struct mlx5_reg_host_endianness he_out; 796 int err; 797 798 if (!mlx5_core_is_pf(dev)) 799 return 0; 800 801 memset(&he_in, 0, sizeof(he_in)); 802 he_in.he = MLX5_SET_HOST_ENDIANNESS; 803 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 804 &he_out, sizeof(he_out), 805 MLX5_REG_HOST_ENDIANNESS, 0, 1); 806 return err; 807 } 808 809 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 810 { 811 int ret = 0; 812 813 /* Disable local_lb by default */ 814 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 815 ret = mlx5_nic_vport_update_local_lb(dev, false); 816 817 return ret; 818 } 819 820 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 821 { 822 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 823 824 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 825 MLX5_SET(enable_hca_in, in, function_id, func_id); 826 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 827 dev->caps.embedded_cpu); 828 return mlx5_cmd_exec_in(dev, enable_hca, in); 829 } 830 831 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 832 { 833 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 834 835 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 836 MLX5_SET(disable_hca_in, in, function_id, func_id); 837 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 838 dev->caps.embedded_cpu); 839 return mlx5_cmd_exec_in(dev, disable_hca, in); 840 } 841 842 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 843 { 844 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 845 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 846 u32 sup_issi; 847 int err; 848 849 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 850 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 851 if (err) { 852 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 853 u8 status = MLX5_GET(query_issi_out, query_out, status); 854 855 if (!status || syndrome == MLX5_DRIVER_SYND) { 856 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 857 err, status, syndrome); 858 return err; 859 } 860 861 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 862 dev->issi = 0; 863 return 0; 864 } 865 866 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 867 868 if (sup_issi & (1 << 1)) { 869 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 870 871 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 872 MLX5_SET(set_issi_in, set_in, current_issi, 1); 873 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 874 if (err) { 875 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 876 err); 877 return err; 878 } 879 880 dev->issi = 1; 881 882 return 0; 883 } else if (sup_issi & (1 << 0) || !sup_issi) { 884 return 0; 885 } 886 887 return -EOPNOTSUPP; 888 } 889 890 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 891 const struct pci_device_id *id) 892 { 893 int err = 0; 894 895 mutex_init(&dev->pci_status_mutex); 896 pci_set_drvdata(dev->pdev, dev); 897 898 dev->bar_addr = pci_resource_start(pdev, 0); 899 900 err = mlx5_pci_enable_device(dev); 901 if (err) { 902 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 903 return err; 904 } 905 906 err = request_bar(pdev); 907 if (err) { 908 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 909 goto err_disable; 910 } 911 912 pci_set_master(pdev); 913 914 err = set_dma_caps(pdev); 915 if (err) { 916 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 917 goto err_clr_master; 918 } 919 920 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 921 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 922 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 923 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 924 925 dev->iseg_base = dev->bar_addr; 926 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 927 if (!dev->iseg) { 928 err = -ENOMEM; 929 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 930 goto err_clr_master; 931 } 932 933 mlx5_pci_vsc_init(dev); 934 return 0; 935 936 err_clr_master: 937 release_bar(dev->pdev); 938 err_disable: 939 mlx5_pci_disable_device(dev); 940 return err; 941 } 942 943 static void mlx5_pci_close(struct mlx5_core_dev *dev) 944 { 945 /* health work might still be active, and it needs pci bar in 946 * order to know the NIC state. Therefore, drain the health WQ 947 * before removing the pci bars 948 */ 949 mlx5_drain_health_wq(dev); 950 iounmap(dev->iseg); 951 release_bar(dev->pdev); 952 mlx5_pci_disable_device(dev); 953 } 954 955 static int mlx5_init_once(struct mlx5_core_dev *dev) 956 { 957 int err; 958 959 dev->priv.devc = mlx5_devcom_register_device(dev); 960 if (IS_ERR(dev->priv.devc)) 961 mlx5_core_warn(dev, "failed to register devcom device %ld\n", 962 PTR_ERR(dev->priv.devc)); 963 964 err = mlx5_query_board_id(dev); 965 if (err) { 966 mlx5_core_err(dev, "query board id failed\n"); 967 goto err_devcom; 968 } 969 970 err = mlx5_irq_table_init(dev); 971 if (err) { 972 mlx5_core_err(dev, "failed to initialize irq table\n"); 973 goto err_devcom; 974 } 975 976 err = mlx5_eq_table_init(dev); 977 if (err) { 978 mlx5_core_err(dev, "failed to initialize eq\n"); 979 goto err_irq_cleanup; 980 } 981 982 err = mlx5_events_init(dev); 983 if (err) { 984 mlx5_core_err(dev, "failed to initialize events\n"); 985 goto err_eq_cleanup; 986 } 987 988 err = mlx5_fw_reset_init(dev); 989 if (err) { 990 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 991 goto err_events_cleanup; 992 } 993 994 mlx5_cq_debugfs_init(dev); 995 996 mlx5_init_reserved_gids(dev); 997 998 mlx5_init_clock(dev); 999 1000 dev->vxlan = mlx5_vxlan_create(dev); 1001 dev->geneve = mlx5_geneve_create(dev); 1002 1003 err = mlx5_init_rl_table(dev); 1004 if (err) { 1005 mlx5_core_err(dev, "Failed to init rate limiting\n"); 1006 goto err_tables_cleanup; 1007 } 1008 1009 err = mlx5_mpfs_init(dev); 1010 if (err) { 1011 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1012 goto err_rl_cleanup; 1013 } 1014 1015 err = mlx5_sriov_init(dev); 1016 if (err) { 1017 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 1018 goto err_mpfs_cleanup; 1019 } 1020 1021 err = mlx5_eswitch_init(dev); 1022 if (err) { 1023 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 1024 goto err_sriov_cleanup; 1025 } 1026 1027 err = mlx5_fpga_init(dev); 1028 if (err) { 1029 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 1030 goto err_eswitch_cleanup; 1031 } 1032 1033 err = mlx5_vhca_event_init(dev); 1034 if (err) { 1035 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1036 goto err_fpga_cleanup; 1037 } 1038 1039 err = mlx5_sf_hw_table_init(dev); 1040 if (err) { 1041 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1042 goto err_sf_hw_table_cleanup; 1043 } 1044 1045 err = mlx5_sf_table_init(dev); 1046 if (err) { 1047 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1048 goto err_sf_table_cleanup; 1049 } 1050 1051 err = mlx5_fs_core_alloc(dev); 1052 if (err) { 1053 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1054 goto err_fs; 1055 } 1056 1057 dev->dm = mlx5_dm_create(dev); 1058 if (IS_ERR(dev->dm)) 1059 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm)); 1060 1061 dev->tracer = mlx5_fw_tracer_create(dev); 1062 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1063 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1064 1065 return 0; 1066 1067 err_fs: 1068 mlx5_sf_table_cleanup(dev); 1069 err_sf_table_cleanup: 1070 mlx5_sf_hw_table_cleanup(dev); 1071 err_sf_hw_table_cleanup: 1072 mlx5_vhca_event_cleanup(dev); 1073 err_fpga_cleanup: 1074 mlx5_fpga_cleanup(dev); 1075 err_eswitch_cleanup: 1076 mlx5_eswitch_cleanup(dev->priv.eswitch); 1077 err_sriov_cleanup: 1078 mlx5_sriov_cleanup(dev); 1079 err_mpfs_cleanup: 1080 mlx5_mpfs_cleanup(dev); 1081 err_rl_cleanup: 1082 mlx5_cleanup_rl_table(dev); 1083 err_tables_cleanup: 1084 mlx5_geneve_destroy(dev->geneve); 1085 mlx5_vxlan_destroy(dev->vxlan); 1086 mlx5_cleanup_clock(dev); 1087 mlx5_cleanup_reserved_gids(dev); 1088 mlx5_cq_debugfs_cleanup(dev); 1089 mlx5_fw_reset_cleanup(dev); 1090 err_events_cleanup: 1091 mlx5_events_cleanup(dev); 1092 err_eq_cleanup: 1093 mlx5_eq_table_cleanup(dev); 1094 err_irq_cleanup: 1095 mlx5_irq_table_cleanup(dev); 1096 err_devcom: 1097 mlx5_devcom_unregister_device(dev->priv.devc); 1098 1099 return err; 1100 } 1101 1102 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1103 { 1104 mlx5_rsc_dump_destroy(dev); 1105 mlx5_hv_vhca_destroy(dev->hv_vhca); 1106 mlx5_fw_tracer_destroy(dev->tracer); 1107 mlx5_dm_cleanup(dev); 1108 mlx5_fs_core_free(dev); 1109 mlx5_sf_table_cleanup(dev); 1110 mlx5_sf_hw_table_cleanup(dev); 1111 mlx5_vhca_event_cleanup(dev); 1112 mlx5_fpga_cleanup(dev); 1113 mlx5_eswitch_cleanup(dev->priv.eswitch); 1114 mlx5_sriov_cleanup(dev); 1115 mlx5_mpfs_cleanup(dev); 1116 mlx5_cleanup_rl_table(dev); 1117 mlx5_geneve_destroy(dev->geneve); 1118 mlx5_vxlan_destroy(dev->vxlan); 1119 mlx5_cleanup_clock(dev); 1120 mlx5_cleanup_reserved_gids(dev); 1121 mlx5_cq_debugfs_cleanup(dev); 1122 mlx5_fw_reset_cleanup(dev); 1123 mlx5_events_cleanup(dev); 1124 mlx5_eq_table_cleanup(dev); 1125 mlx5_irq_table_cleanup(dev); 1126 mlx5_devcom_unregister_device(dev->priv.devc); 1127 } 1128 1129 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1130 { 1131 int err; 1132 1133 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1134 fw_rev_min(dev), fw_rev_sub(dev)); 1135 1136 /* Only PFs hold the relevant PCIe information for this query */ 1137 if (mlx5_core_is_pf(dev)) 1138 pcie_print_link_status(dev->pdev); 1139 1140 /* wait for firmware to accept initialization segments configurations 1141 */ 1142 err = wait_fw_init(dev, timeout, 1143 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 1144 if (err) { 1145 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 1146 timeout); 1147 return err; 1148 } 1149 1150 err = mlx5_cmd_enable(dev); 1151 if (err) { 1152 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1153 return err; 1154 } 1155 1156 mlx5_tout_query_iseg(dev); 1157 1158 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1159 if (err) { 1160 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 1161 mlx5_tout_ms(dev, FW_INIT)); 1162 goto err_cmd_cleanup; 1163 } 1164 1165 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1166 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1167 1168 mlx5_start_health_poll(dev); 1169 1170 err = mlx5_core_enable_hca(dev, 0); 1171 if (err) { 1172 mlx5_core_err(dev, "enable hca failed\n"); 1173 goto stop_health_poll; 1174 } 1175 1176 err = mlx5_core_set_issi(dev); 1177 if (err) { 1178 mlx5_core_err(dev, "failed to set issi\n"); 1179 goto err_disable_hca; 1180 } 1181 1182 err = mlx5_satisfy_startup_pages(dev, 1); 1183 if (err) { 1184 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1185 goto err_disable_hca; 1186 } 1187 1188 err = mlx5_tout_query_dtor(dev); 1189 if (err) { 1190 mlx5_core_err(dev, "failed to read dtor\n"); 1191 goto reclaim_boot_pages; 1192 } 1193 1194 return 0; 1195 1196 reclaim_boot_pages: 1197 mlx5_reclaim_startup_pages(dev); 1198 err_disable_hca: 1199 mlx5_core_disable_hca(dev, 0); 1200 stop_health_poll: 1201 mlx5_stop_health_poll(dev, boot); 1202 err_cmd_cleanup: 1203 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1204 mlx5_cmd_disable(dev); 1205 1206 return err; 1207 } 1208 1209 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot) 1210 { 1211 mlx5_reclaim_startup_pages(dev); 1212 mlx5_core_disable_hca(dev, 0); 1213 mlx5_stop_health_poll(dev, boot); 1214 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1215 mlx5_cmd_disable(dev); 1216 } 1217 1218 static int mlx5_function_open(struct mlx5_core_dev *dev) 1219 { 1220 int err; 1221 1222 err = set_hca_ctrl(dev); 1223 if (err) { 1224 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1225 return err; 1226 } 1227 1228 err = set_hca_cap(dev); 1229 if (err) { 1230 mlx5_core_err(dev, "set_hca_cap failed\n"); 1231 return err; 1232 } 1233 1234 err = mlx5_satisfy_startup_pages(dev, 0); 1235 if (err) { 1236 mlx5_core_err(dev, "failed to allocate init pages\n"); 1237 return err; 1238 } 1239 1240 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1241 if (err) { 1242 mlx5_core_err(dev, "init hca failed\n"); 1243 return err; 1244 } 1245 1246 mlx5_set_driver_version(dev); 1247 1248 err = mlx5_query_hca_caps(dev); 1249 if (err) { 1250 mlx5_core_err(dev, "query hca failed\n"); 1251 return err; 1252 } 1253 mlx5_start_health_fw_log_up(dev); 1254 return 0; 1255 } 1256 1257 static int mlx5_function_close(struct mlx5_core_dev *dev) 1258 { 1259 int err; 1260 1261 err = mlx5_cmd_teardown_hca(dev); 1262 if (err) { 1263 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1264 return err; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1271 { 1272 int err; 1273 1274 err = mlx5_function_enable(dev, boot, timeout); 1275 if (err) 1276 return err; 1277 1278 err = mlx5_function_open(dev); 1279 if (err) 1280 mlx5_function_disable(dev, boot); 1281 return err; 1282 } 1283 1284 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1285 { 1286 int err = mlx5_function_close(dev); 1287 1288 if (!err) 1289 mlx5_function_disable(dev, boot); 1290 return err; 1291 } 1292 1293 static int mlx5_load(struct mlx5_core_dev *dev) 1294 { 1295 int err; 1296 1297 dev->priv.uar = mlx5_get_uars_page(dev); 1298 if (IS_ERR(dev->priv.uar)) { 1299 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1300 err = PTR_ERR(dev->priv.uar); 1301 return err; 1302 } 1303 1304 mlx5_events_start(dev); 1305 mlx5_pagealloc_start(dev); 1306 1307 err = mlx5_irq_table_create(dev); 1308 if (err) { 1309 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1310 goto err_irq_table; 1311 } 1312 1313 err = mlx5_eq_table_create(dev); 1314 if (err) { 1315 mlx5_core_err(dev, "Failed to create EQs\n"); 1316 goto err_eq_table; 1317 } 1318 1319 err = mlx5_fw_tracer_init(dev->tracer); 1320 if (err) { 1321 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1322 mlx5_fw_tracer_destroy(dev->tracer); 1323 dev->tracer = NULL; 1324 } 1325 1326 mlx5_fw_reset_events_start(dev); 1327 mlx5_hv_vhca_init(dev->hv_vhca); 1328 1329 err = mlx5_rsc_dump_init(dev); 1330 if (err) { 1331 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1332 mlx5_rsc_dump_destroy(dev); 1333 dev->rsc_dump = NULL; 1334 } 1335 1336 err = mlx5_fpga_device_start(dev); 1337 if (err) { 1338 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1339 goto err_fpga_start; 1340 } 1341 1342 err = mlx5_fs_core_init(dev); 1343 if (err) { 1344 mlx5_core_err(dev, "Failed to init flow steering\n"); 1345 goto err_fs; 1346 } 1347 1348 err = mlx5_core_set_hca_defaults(dev); 1349 if (err) { 1350 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1351 goto err_set_hca; 1352 } 1353 1354 mlx5_vhca_event_start(dev); 1355 1356 err = mlx5_sf_hw_table_create(dev); 1357 if (err) { 1358 mlx5_core_err(dev, "sf table create failed %d\n", err); 1359 goto err_vhca; 1360 } 1361 1362 err = mlx5_ec_init(dev); 1363 if (err) { 1364 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1365 goto err_ec; 1366 } 1367 1368 mlx5_lag_add_mdev(dev); 1369 err = mlx5_sriov_attach(dev); 1370 if (err) { 1371 mlx5_core_err(dev, "sriov init failed %d\n", err); 1372 goto err_sriov; 1373 } 1374 1375 mlx5_sf_dev_table_create(dev); 1376 1377 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1378 if (err) 1379 goto err_traps_reg; 1380 1381 return 0; 1382 1383 err_traps_reg: 1384 mlx5_sf_dev_table_destroy(dev); 1385 mlx5_sriov_detach(dev); 1386 err_sriov: 1387 mlx5_lag_remove_mdev(dev); 1388 mlx5_ec_cleanup(dev); 1389 err_ec: 1390 mlx5_sf_hw_table_destroy(dev); 1391 err_vhca: 1392 mlx5_vhca_event_stop(dev); 1393 err_set_hca: 1394 mlx5_fs_core_cleanup(dev); 1395 err_fs: 1396 mlx5_fpga_device_stop(dev); 1397 err_fpga_start: 1398 mlx5_rsc_dump_cleanup(dev); 1399 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1400 mlx5_fw_reset_events_stop(dev); 1401 mlx5_fw_tracer_cleanup(dev->tracer); 1402 mlx5_eq_table_destroy(dev); 1403 err_eq_table: 1404 mlx5_irq_table_destroy(dev); 1405 err_irq_table: 1406 mlx5_pagealloc_stop(dev); 1407 mlx5_events_stop(dev); 1408 mlx5_put_uars_page(dev, dev->priv.uar); 1409 return err; 1410 } 1411 1412 static void mlx5_unload(struct mlx5_core_dev *dev) 1413 { 1414 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1415 mlx5_sf_dev_table_destroy(dev); 1416 mlx5_eswitch_disable(dev->priv.eswitch); 1417 mlx5_sriov_detach(dev); 1418 mlx5_lag_remove_mdev(dev); 1419 mlx5_ec_cleanup(dev); 1420 mlx5_sf_hw_table_destroy(dev); 1421 mlx5_vhca_event_stop(dev); 1422 mlx5_fs_core_cleanup(dev); 1423 mlx5_fpga_device_stop(dev); 1424 mlx5_rsc_dump_cleanup(dev); 1425 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1426 mlx5_fw_reset_events_stop(dev); 1427 mlx5_fw_tracer_cleanup(dev->tracer); 1428 mlx5_eq_table_destroy(dev); 1429 mlx5_irq_table_destroy(dev); 1430 mlx5_pagealloc_stop(dev); 1431 mlx5_events_stop(dev); 1432 mlx5_put_uars_page(dev, dev->priv.uar); 1433 } 1434 1435 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) 1436 { 1437 bool light_probe = mlx5_dev_is_lightweight(dev); 1438 int err = 0; 1439 1440 mutex_lock(&dev->intf_state_mutex); 1441 dev->state = MLX5_DEVICE_STATE_UP; 1442 1443 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1444 if (err) 1445 goto err_function; 1446 1447 err = mlx5_init_once(dev); 1448 if (err) { 1449 mlx5_core_err(dev, "sw objs init failed\n"); 1450 goto function_teardown; 1451 } 1452 1453 /* In case of light_probe, mlx5_devlink is already registered. 1454 * Hence, don't register devlink again. 1455 */ 1456 if (!light_probe) { 1457 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1458 if (err) 1459 goto err_devlink_params_reg; 1460 } 1461 1462 err = mlx5_load(dev); 1463 if (err) 1464 goto err_load; 1465 1466 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1467 1468 err = mlx5_register_device(dev); 1469 if (err) 1470 goto err_register; 1471 1472 err = mlx5_crdump_enable(dev); 1473 if (err) 1474 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err); 1475 1476 err = mlx5_hwmon_dev_register(dev); 1477 if (err) 1478 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err); 1479 1480 mutex_unlock(&dev->intf_state_mutex); 1481 return 0; 1482 1483 err_register: 1484 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1485 mlx5_unload(dev); 1486 err_load: 1487 if (!light_probe) 1488 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1489 err_devlink_params_reg: 1490 mlx5_cleanup_once(dev); 1491 function_teardown: 1492 mlx5_function_teardown(dev, true); 1493 err_function: 1494 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1495 mutex_unlock(&dev->intf_state_mutex); 1496 return err; 1497 } 1498 1499 int mlx5_init_one(struct mlx5_core_dev *dev) 1500 { 1501 struct devlink *devlink = priv_to_devlink(dev); 1502 int err; 1503 1504 devl_lock(devlink); 1505 devl_register(devlink); 1506 err = mlx5_init_one_devl_locked(dev); 1507 if (err) 1508 devl_unregister(devlink); 1509 devl_unlock(devlink); 1510 return err; 1511 } 1512 1513 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1514 { 1515 struct devlink *devlink = priv_to_devlink(dev); 1516 1517 devl_lock(devlink); 1518 mutex_lock(&dev->intf_state_mutex); 1519 1520 mlx5_hwmon_dev_unregister(dev); 1521 mlx5_crdump_disable(dev); 1522 mlx5_unregister_device(dev); 1523 1524 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1525 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1526 __func__); 1527 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1528 mlx5_cleanup_once(dev); 1529 goto out; 1530 } 1531 1532 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1533 mlx5_unload(dev); 1534 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1535 mlx5_cleanup_once(dev); 1536 mlx5_function_teardown(dev, true); 1537 out: 1538 mutex_unlock(&dev->intf_state_mutex); 1539 devl_unregister(devlink); 1540 devl_unlock(devlink); 1541 } 1542 1543 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1544 { 1545 int err = 0; 1546 u64 timeout; 1547 1548 devl_assert_locked(priv_to_devlink(dev)); 1549 mutex_lock(&dev->intf_state_mutex); 1550 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1551 mlx5_core_warn(dev, "interface is up, NOP\n"); 1552 goto out; 1553 } 1554 /* remove any previous indication of internal error */ 1555 dev->state = MLX5_DEVICE_STATE_UP; 1556 1557 if (recovery) 1558 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1559 else 1560 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1561 err = mlx5_function_setup(dev, false, timeout); 1562 if (err) 1563 goto err_function; 1564 1565 err = mlx5_load(dev); 1566 if (err) 1567 goto err_load; 1568 1569 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1570 1571 err = mlx5_attach_device(dev); 1572 if (err) 1573 goto err_attach; 1574 1575 mutex_unlock(&dev->intf_state_mutex); 1576 return 0; 1577 1578 err_attach: 1579 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1580 mlx5_unload(dev); 1581 err_load: 1582 mlx5_function_teardown(dev, false); 1583 err_function: 1584 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1585 out: 1586 mutex_unlock(&dev->intf_state_mutex); 1587 return err; 1588 } 1589 1590 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1591 { 1592 struct devlink *devlink = priv_to_devlink(dev); 1593 int ret; 1594 1595 devl_lock(devlink); 1596 ret = mlx5_load_one_devl_locked(dev, recovery); 1597 devl_unlock(devlink); 1598 return ret; 1599 } 1600 1601 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 1602 { 1603 devl_assert_locked(priv_to_devlink(dev)); 1604 mutex_lock(&dev->intf_state_mutex); 1605 1606 mlx5_detach_device(dev, suspend); 1607 1608 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1609 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1610 __func__); 1611 goto out; 1612 } 1613 1614 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1615 mlx5_unload(dev); 1616 mlx5_function_teardown(dev, false); 1617 out: 1618 mutex_unlock(&dev->intf_state_mutex); 1619 } 1620 1621 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 1622 { 1623 struct devlink *devlink = priv_to_devlink(dev); 1624 1625 devl_lock(devlink); 1626 mlx5_unload_one_devl_locked(dev, suspend); 1627 devl_unlock(devlink); 1628 } 1629 1630 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps. 1631 * A full query of hca_caps will be done when the device will reload. 1632 */ 1633 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev) 1634 { 1635 int err; 1636 1637 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 1638 if (err) 1639 return err; 1640 1641 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 1642 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 1643 HCA_CAP_OPMOD_GET_CUR); 1644 if (err) 1645 return err; 1646 } 1647 1648 if (MLX5_CAP_GEN(dev, nic_flow_table) || 1649 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 1650 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, 1651 HCA_CAP_OPMOD_GET_CUR); 1652 if (err) 1653 return err; 1654 } 1655 1656 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 1657 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 1658 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, 1659 HCA_CAP_OPMOD_GET_CUR); 1660 if (err) 1661 return err; 1662 } 1663 1664 return 0; 1665 } 1666 1667 int mlx5_init_one_light(struct mlx5_core_dev *dev) 1668 { 1669 struct devlink *devlink = priv_to_devlink(dev); 1670 int err; 1671 1672 dev->state = MLX5_DEVICE_STATE_UP; 1673 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1674 if (err) { 1675 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err); 1676 goto out; 1677 } 1678 1679 err = mlx5_query_hca_caps_light(dev); 1680 if (err) { 1681 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err); 1682 goto query_hca_caps_err; 1683 } 1684 1685 devl_lock(devlink); 1686 devl_register(devlink); 1687 1688 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1689 if (err) { 1690 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); 1691 goto query_hca_caps_err; 1692 } 1693 1694 devl_unlock(devlink); 1695 return 0; 1696 1697 query_hca_caps_err: 1698 devl_unregister(devlink); 1699 devl_unlock(devlink); 1700 mlx5_function_disable(dev, true); 1701 out: 1702 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1703 return err; 1704 } 1705 1706 void mlx5_uninit_one_light(struct mlx5_core_dev *dev) 1707 { 1708 struct devlink *devlink = priv_to_devlink(dev); 1709 1710 devl_lock(devlink); 1711 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1712 devl_unregister(devlink); 1713 devl_unlock(devlink); 1714 if (dev->state != MLX5_DEVICE_STATE_UP) 1715 return; 1716 mlx5_function_disable(dev, true); 1717 } 1718 1719 /* xxx_light() function are used in order to configure the device without full 1720 * init (light init). e.g.: There isn't a point in reload a device to light state. 1721 * Hence, mlx5_load_one_light() isn't needed. 1722 */ 1723 1724 void mlx5_unload_one_light(struct mlx5_core_dev *dev) 1725 { 1726 if (dev->state != MLX5_DEVICE_STATE_UP) 1727 return; 1728 mlx5_function_disable(dev, false); 1729 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1730 } 1731 1732 static const int types[] = { 1733 MLX5_CAP_GENERAL, 1734 MLX5_CAP_GENERAL_2, 1735 MLX5_CAP_ETHERNET_OFFLOADS, 1736 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1737 MLX5_CAP_ODP, 1738 MLX5_CAP_ATOMIC, 1739 MLX5_CAP_ROCE, 1740 MLX5_CAP_IPOIB_OFFLOADS, 1741 MLX5_CAP_FLOW_TABLE, 1742 MLX5_CAP_ESWITCH_FLOW_TABLE, 1743 MLX5_CAP_ESWITCH, 1744 MLX5_CAP_QOS, 1745 MLX5_CAP_DEBUG, 1746 MLX5_CAP_DEV_MEM, 1747 MLX5_CAP_DEV_EVENT, 1748 MLX5_CAP_TLS, 1749 MLX5_CAP_VDPA_EMULATION, 1750 MLX5_CAP_IPSEC, 1751 MLX5_CAP_PORT_SELECTION, 1752 MLX5_CAP_MACSEC, 1753 MLX5_CAP_ADV_VIRTUALIZATION, 1754 MLX5_CAP_CRYPTO, 1755 }; 1756 1757 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1758 { 1759 int type; 1760 int i; 1761 1762 for (i = 0; i < ARRAY_SIZE(types); i++) { 1763 type = types[i]; 1764 kfree(dev->caps.hca[type]); 1765 } 1766 } 1767 1768 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1769 { 1770 struct mlx5_hca_cap *cap; 1771 int type; 1772 int i; 1773 1774 for (i = 0; i < ARRAY_SIZE(types); i++) { 1775 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1776 if (!cap) 1777 goto err; 1778 type = types[i]; 1779 dev->caps.hca[type] = cap; 1780 } 1781 1782 return 0; 1783 1784 err: 1785 mlx5_hca_caps_free(dev); 1786 return -ENOMEM; 1787 } 1788 1789 static int vhca_id_show(struct seq_file *file, void *priv) 1790 { 1791 struct mlx5_core_dev *dev = file->private; 1792 1793 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1794 return 0; 1795 } 1796 1797 DEFINE_SHOW_ATTRIBUTE(vhca_id); 1798 1799 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1800 { 1801 struct mlx5_priv *priv = &dev->priv; 1802 int err; 1803 1804 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1805 lockdep_register_key(&dev->lock_key); 1806 mutex_init(&dev->intf_state_mutex); 1807 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1808 mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1809 1810 mutex_init(&priv->bfregs.reg_head.lock); 1811 mutex_init(&priv->bfregs.wc_head.lock); 1812 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1813 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1814 1815 mutex_init(&priv->alloc_mutex); 1816 mutex_init(&priv->pgdir_mutex); 1817 INIT_LIST_HEAD(&priv->pgdir_list); 1818 1819 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1820 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1821 mlx5_debugfs_root); 1822 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 1823 INIT_LIST_HEAD(&priv->traps); 1824 1825 err = mlx5_cmd_init(dev); 1826 if (err) { 1827 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n"); 1828 goto err_cmd_init; 1829 } 1830 1831 err = mlx5_tout_init(dev); 1832 if (err) { 1833 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1834 goto err_timeout_init; 1835 } 1836 1837 err = mlx5_health_init(dev); 1838 if (err) 1839 goto err_health_init; 1840 1841 err = mlx5_pagealloc_init(dev); 1842 if (err) 1843 goto err_pagealloc_init; 1844 1845 err = mlx5_adev_init(dev); 1846 if (err) 1847 goto err_adev_init; 1848 1849 err = mlx5_hca_caps_alloc(dev); 1850 if (err) 1851 goto err_hca_caps; 1852 1853 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1854 * unique id per function which uses mlx5_core. 1855 * Those values are supplied to FW as part of the init HCA command to 1856 * be used by both driver and FW when it's applicable. 1857 */ 1858 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1859 MAX_SW_VHCA_ID, 1860 GFP_KERNEL); 1861 if (dev->priv.sw_vhca_id < 0) 1862 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1863 dev->priv.sw_vhca_id); 1864 1865 return 0; 1866 1867 err_hca_caps: 1868 mlx5_adev_cleanup(dev); 1869 err_adev_init: 1870 mlx5_pagealloc_cleanup(dev); 1871 err_pagealloc_init: 1872 mlx5_health_cleanup(dev); 1873 err_health_init: 1874 mlx5_tout_cleanup(dev); 1875 err_timeout_init: 1876 mlx5_cmd_cleanup(dev); 1877 err_cmd_init: 1878 debugfs_remove(dev->priv.dbg.dbg_root); 1879 mutex_destroy(&priv->pgdir_mutex); 1880 mutex_destroy(&priv->alloc_mutex); 1881 mutex_destroy(&priv->bfregs.wc_head.lock); 1882 mutex_destroy(&priv->bfregs.reg_head.lock); 1883 mutex_destroy(&dev->intf_state_mutex); 1884 lockdep_unregister_key(&dev->lock_key); 1885 return err; 1886 } 1887 1888 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1889 { 1890 struct mlx5_priv *priv = &dev->priv; 1891 1892 if (priv->sw_vhca_id > 0) 1893 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1894 1895 mlx5_hca_caps_free(dev); 1896 mlx5_adev_cleanup(dev); 1897 mlx5_pagealloc_cleanup(dev); 1898 mlx5_health_cleanup(dev); 1899 mlx5_tout_cleanup(dev); 1900 mlx5_cmd_cleanup(dev); 1901 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1902 mutex_destroy(&priv->pgdir_mutex); 1903 mutex_destroy(&priv->alloc_mutex); 1904 mutex_destroy(&priv->bfregs.wc_head.lock); 1905 mutex_destroy(&priv->bfregs.reg_head.lock); 1906 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1907 mutex_destroy(&dev->intf_state_mutex); 1908 lockdep_unregister_key(&dev->lock_key); 1909 } 1910 1911 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1912 { 1913 struct mlx5_core_dev *dev; 1914 struct devlink *devlink; 1915 int err; 1916 1917 devlink = mlx5_devlink_alloc(&pdev->dev); 1918 if (!devlink) { 1919 dev_err(&pdev->dev, "devlink alloc failed\n"); 1920 return -ENOMEM; 1921 } 1922 1923 dev = devlink_priv(devlink); 1924 dev->device = &pdev->dev; 1925 dev->pdev = pdev; 1926 1927 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1928 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1929 1930 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1931 if (dev->priv.adev_idx < 0) { 1932 err = dev->priv.adev_idx; 1933 goto adev_init_err; 1934 } 1935 1936 err = mlx5_mdev_init(dev, prof_sel); 1937 if (err) 1938 goto mdev_init_err; 1939 1940 err = mlx5_pci_init(dev, pdev, id); 1941 if (err) { 1942 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1943 err); 1944 goto pci_init_err; 1945 } 1946 1947 err = mlx5_init_one(dev); 1948 if (err) { 1949 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1950 err); 1951 goto err_init_one; 1952 } 1953 1954 pci_save_state(pdev); 1955 return 0; 1956 1957 err_init_one: 1958 mlx5_pci_close(dev); 1959 pci_init_err: 1960 mlx5_mdev_uninit(dev); 1961 mdev_init_err: 1962 mlx5_adev_idx_free(dev->priv.adev_idx); 1963 adev_init_err: 1964 mlx5_devlink_free(devlink); 1965 1966 return err; 1967 } 1968 1969 static void remove_one(struct pci_dev *pdev) 1970 { 1971 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1972 struct devlink *devlink = priv_to_devlink(dev); 1973 1974 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1975 mlx5_drain_fw_reset(dev); 1976 mlx5_drain_health_wq(dev); 1977 mlx5_sriov_disable(pdev, false); 1978 mlx5_uninit_one(dev); 1979 mlx5_pci_close(dev); 1980 mlx5_mdev_uninit(dev); 1981 mlx5_adev_idx_free(dev->priv.adev_idx); 1982 mlx5_devlink_free(devlink); 1983 } 1984 1985 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1986 struct mlx5_core_dev *__dev = (dev); \ 1987 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1988 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1989 __dev->pci_status, ##__VA_ARGS__); \ 1990 }) 1991 1992 static const char *result2str(enum pci_ers_result result) 1993 { 1994 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1995 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1996 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1997 "unknown"; 1998 } 1999 2000 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 2001 pci_channel_state_t state) 2002 { 2003 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2004 enum pci_ers_result res; 2005 2006 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 2007 2008 mlx5_enter_error_state(dev, false); 2009 mlx5_error_sw_reset(dev); 2010 mlx5_unload_one(dev, false); 2011 mlx5_drain_health_wq(dev); 2012 mlx5_pci_disable_device(dev); 2013 2014 res = state == pci_channel_io_perm_failure ? 2015 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2016 2017 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 2018 __func__, dev->state, dev->pci_status, res, result2str(res)); 2019 return res; 2020 } 2021 2022 /* wait for the device to show vital signs by waiting 2023 * for the health counter to start counting. 2024 */ 2025 static int wait_vital(struct pci_dev *pdev) 2026 { 2027 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2028 struct mlx5_core_health *health = &dev->priv.health; 2029 const int niter = 100; 2030 u32 last_count = 0; 2031 u32 count; 2032 int i; 2033 2034 for (i = 0; i < niter; i++) { 2035 count = ioread32be(health->health_counter); 2036 if (count && count != 0xffffffff) { 2037 if (last_count && last_count != count) { 2038 mlx5_core_info(dev, 2039 "wait vital counter value 0x%x after %d iterations\n", 2040 count, i); 2041 return 0; 2042 } 2043 last_count = count; 2044 } 2045 msleep(50); 2046 } 2047 2048 return -ETIMEDOUT; 2049 } 2050 2051 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 2052 { 2053 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 2054 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2055 int err; 2056 2057 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 2058 __func__, dev->state, dev->pci_status); 2059 2060 err = mlx5_pci_enable_device(dev); 2061 if (err) { 2062 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 2063 __func__, err); 2064 goto out; 2065 } 2066 2067 pci_set_master(pdev); 2068 pci_restore_state(pdev); 2069 pci_save_state(pdev); 2070 2071 err = wait_vital(pdev); 2072 if (err) { 2073 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 2074 __func__, err); 2075 goto out; 2076 } 2077 2078 res = PCI_ERS_RESULT_RECOVERED; 2079 out: 2080 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 2081 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 2082 return res; 2083 } 2084 2085 static void mlx5_pci_resume(struct pci_dev *pdev) 2086 { 2087 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2088 int err; 2089 2090 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 2091 2092 err = mlx5_load_one(dev, false); 2093 2094 if (!err) 2095 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 2096 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 2097 2098 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 2099 !err ? "recovered" : "Failed"); 2100 } 2101 2102 static const struct pci_error_handlers mlx5_err_handler = { 2103 .error_detected = mlx5_pci_err_detected, 2104 .slot_reset = mlx5_pci_slot_reset, 2105 .resume = mlx5_pci_resume 2106 }; 2107 2108 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 2109 { 2110 bool fast_teardown = false, force_teardown = false; 2111 int ret = 1; 2112 2113 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2114 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2115 2116 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2117 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2118 2119 if (!fast_teardown && !force_teardown) 2120 return -EOPNOTSUPP; 2121 2122 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 2123 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 2124 return -EAGAIN; 2125 } 2126 2127 /* Panic tear down fw command will stop the PCI bus communication 2128 * with the HCA, so the health poll is no longer needed. 2129 */ 2130 mlx5_drain_health_wq(dev); 2131 mlx5_stop_health_poll(dev, false); 2132 2133 ret = mlx5_cmd_fast_teardown_hca(dev); 2134 if (!ret) 2135 goto succeed; 2136 2137 ret = mlx5_cmd_force_teardown_hca(dev); 2138 if (!ret) 2139 goto succeed; 2140 2141 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 2142 mlx5_start_health_poll(dev); 2143 return ret; 2144 2145 succeed: 2146 mlx5_enter_error_state(dev, true); 2147 2148 /* Some platforms requiring freeing the IRQ's in the shutdown 2149 * flow. If they aren't freed they can't be allocated after 2150 * kexec. There is no need to cleanup the mlx5_core software 2151 * contexts. 2152 */ 2153 mlx5_core_eq_free_irqs(dev); 2154 2155 return 0; 2156 } 2157 2158 static void shutdown(struct pci_dev *pdev) 2159 { 2160 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2161 int err; 2162 2163 mlx5_core_info(dev, "Shutdown was called\n"); 2164 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2165 err = mlx5_try_fast_unload(dev); 2166 if (err) 2167 mlx5_unload_one(dev, false); 2168 mlx5_pci_disable_device(dev); 2169 } 2170 2171 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 2172 { 2173 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2174 2175 mlx5_unload_one(dev, true); 2176 2177 return 0; 2178 } 2179 2180 static int mlx5_resume(struct pci_dev *pdev) 2181 { 2182 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2183 2184 return mlx5_load_one(dev, false); 2185 } 2186 2187 static const struct pci_device_id mlx5_core_pci_table[] = { 2188 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2189 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2190 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2191 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2192 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2193 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 2194 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 2195 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2196 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2197 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2198 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2199 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 2200 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2201 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2202 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2203 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2204 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2205 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2206 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2207 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2208 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2209 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2210 { 0, } 2211 }; 2212 2213 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2214 2215 void mlx5_disable_device(struct mlx5_core_dev *dev) 2216 { 2217 mlx5_error_sw_reset(dev); 2218 mlx5_unload_one_devl_locked(dev, false); 2219 } 2220 2221 int mlx5_recover_device(struct mlx5_core_dev *dev) 2222 { 2223 if (!mlx5_core_is_sf(dev)) { 2224 mlx5_pci_disable_device(dev); 2225 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2226 return -EIO; 2227 } 2228 2229 return mlx5_load_one_devl_locked(dev, true); 2230 } 2231 2232 static struct pci_driver mlx5_core_driver = { 2233 .name = KBUILD_MODNAME, 2234 .id_table = mlx5_core_pci_table, 2235 .probe = probe_one, 2236 .remove = remove_one, 2237 .suspend = mlx5_suspend, 2238 .resume = mlx5_resume, 2239 .shutdown = shutdown, 2240 .err_handler = &mlx5_err_handler, 2241 .sriov_configure = mlx5_core_sriov_configure, 2242 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2243 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2244 }; 2245 2246 /** 2247 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2248 * mlx5_core is its driver. 2249 * @pdev: The associated PCI device. 2250 * 2251 * Upon return the interface state lock stay held to let caller uses it safely. 2252 * Caller must ensure to use the returned mlx5 device for a narrow window 2253 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2254 * 2255 * Return: Pointer to the associated mlx5_core_dev or NULL. 2256 */ 2257 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2258 { 2259 struct mlx5_core_dev *mdev; 2260 2261 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2262 if (IS_ERR(mdev)) 2263 return NULL; 2264 2265 mutex_lock(&mdev->intf_state_mutex); 2266 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2267 mutex_unlock(&mdev->intf_state_mutex); 2268 return NULL; 2269 } 2270 2271 return mdev; 2272 } 2273 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2274 2275 /** 2276 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2277 * @mdev: The mlx5 core device. 2278 * 2279 * Upon return the interface state lock is unlocked and caller should not 2280 * access the mdev any more. 2281 */ 2282 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2283 { 2284 mutex_unlock(&mdev->intf_state_mutex); 2285 } 2286 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2287 2288 static void mlx5_core_verify_params(void) 2289 { 2290 if (prof_sel >= ARRAY_SIZE(profile)) { 2291 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2292 prof_sel, 2293 ARRAY_SIZE(profile) - 1, 2294 MLX5_DEFAULT_PROF); 2295 prof_sel = MLX5_DEFAULT_PROF; 2296 } 2297 } 2298 2299 static int __init mlx5_init(void) 2300 { 2301 int err; 2302 2303 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2304 "mlx5_core name not in sync with kernel module name"); 2305 2306 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2307 2308 mlx5_core_verify_params(); 2309 mlx5_register_debugfs(); 2310 2311 err = mlx5e_init(); 2312 if (err) 2313 goto err_debug; 2314 2315 err = mlx5_sf_driver_register(); 2316 if (err) 2317 goto err_sf; 2318 2319 err = pci_register_driver(&mlx5_core_driver); 2320 if (err) 2321 goto err_pci; 2322 2323 return 0; 2324 2325 err_pci: 2326 mlx5_sf_driver_unregister(); 2327 err_sf: 2328 mlx5e_cleanup(); 2329 err_debug: 2330 mlx5_unregister_debugfs(); 2331 return err; 2332 } 2333 2334 static void __exit mlx5_cleanup(void) 2335 { 2336 pci_unregister_driver(&mlx5_core_driver); 2337 mlx5_sf_driver_unregister(); 2338 mlx5e_cleanup(); 2339 mlx5_unregister_debugfs(); 2340 } 2341 2342 module_init(mlx5_init); 2343 module_exit(mlx5_cleanup); 2344