1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/interrupt.h> 41 #include <linux/delay.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/cq.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/debugfs.h> 46 #include <linux/kmod.h> 47 #include <linux/mlx5/mlx5_ifc.h> 48 #include <linux/mlx5/vport.h> 49 #include <linux/version.h> 50 #include <net/devlink.h> 51 #include "mlx5_core.h" 52 #include "thermal.h" 53 #include "lib/eq.h" 54 #include "fs_core.h" 55 #include "lib/mpfs.h" 56 #include "eswitch.h" 57 #include "devlink.h" 58 #include "fw_reset.h" 59 #include "lib/mlx5.h" 60 #include "lib/tout.h" 61 #include "fpga/core.h" 62 #include "en_accel/ipsec.h" 63 #include "lib/clock.h" 64 #include "lib/vxlan.h" 65 #include "lib/geneve.h" 66 #include "lib/devcom.h" 67 #include "lib/pci_vsc.h" 68 #include "diag/fw_tracer.h" 69 #include "ecpf.h" 70 #include "lib/hv_vhca.h" 71 #include "diag/rsc_dump.h" 72 #include "sf/vhca_event.h" 73 #include "sf/dev/dev.h" 74 #include "sf/sf.h" 75 #include "mlx5_irq.h" 76 77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79 MODULE_LICENSE("Dual BSD/GPL"); 80 81 unsigned int mlx5_core_debug_mask; 82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84 85 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86 module_param_named(prof_sel, prof_sel, uint, 0444); 87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 88 89 static u32 sw_owner_id[4]; 90 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 91 static DEFINE_IDA(sw_vhca_ida); 92 93 enum { 94 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 95 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 96 }; 97 98 #define LOG_MAX_SUPPORTED_QPS 0xff 99 100 static struct mlx5_profile profile[] = { 101 [0] = { 102 .mask = 0, 103 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 104 }, 105 [1] = { 106 .mask = MLX5_PROF_MASK_QP_SIZE, 107 .log_max_qp = 12, 108 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 109 110 }, 111 [2] = { 112 .mask = MLX5_PROF_MASK_QP_SIZE | 113 MLX5_PROF_MASK_MR_CACHE, 114 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 115 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 116 .mr_cache[0] = { 117 .size = 500, 118 .limit = 250 119 }, 120 .mr_cache[1] = { 121 .size = 500, 122 .limit = 250 123 }, 124 .mr_cache[2] = { 125 .size = 500, 126 .limit = 250 127 }, 128 .mr_cache[3] = { 129 .size = 500, 130 .limit = 250 131 }, 132 .mr_cache[4] = { 133 .size = 500, 134 .limit = 250 135 }, 136 .mr_cache[5] = { 137 .size = 500, 138 .limit = 250 139 }, 140 .mr_cache[6] = { 141 .size = 500, 142 .limit = 250 143 }, 144 .mr_cache[7] = { 145 .size = 500, 146 .limit = 250 147 }, 148 .mr_cache[8] = { 149 .size = 500, 150 .limit = 250 151 }, 152 .mr_cache[9] = { 153 .size = 500, 154 .limit = 250 155 }, 156 .mr_cache[10] = { 157 .size = 500, 158 .limit = 250 159 }, 160 .mr_cache[11] = { 161 .size = 500, 162 .limit = 250 163 }, 164 .mr_cache[12] = { 165 .size = 64, 166 .limit = 32 167 }, 168 .mr_cache[13] = { 169 .size = 32, 170 .limit = 16 171 }, 172 .mr_cache[14] = { 173 .size = 16, 174 .limit = 8 175 }, 176 .mr_cache[15] = { 177 .size = 8, 178 .limit = 4 179 }, 180 }, 181 [3] = { 182 .mask = MLX5_PROF_MASK_QP_SIZE, 183 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 184 .num_cmd_caches = 0, 185 }, 186 }; 187 188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189 u32 warn_time_mili) 190 { 191 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193 u32 fw_initializing; 194 int err = 0; 195 196 do { 197 fw_initializing = ioread32be(&dev->iseg->initializing); 198 if (!(fw_initializing >> 31)) 199 break; 200 if (time_after(jiffies, end) || 201 test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 202 err = -EBUSY; 203 break; 204 } 205 if (warn_time_mili && time_after(jiffies, warn)) { 206 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 207 jiffies_to_msecs(end - warn) / 1000, fw_initializing); 208 warn = jiffies + msecs_to_jiffies(warn_time_mili); 209 } 210 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 211 } while (true); 212 213 return err; 214 } 215 216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 217 { 218 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 219 driver_version); 220 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 221 int remaining_size = driver_ver_sz; 222 char *string; 223 224 if (!MLX5_CAP_GEN(dev, driver_version)) 225 return; 226 227 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 228 229 strncpy(string, "Linux", remaining_size); 230 231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232 strncat(string, ",", remaining_size); 233 234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235 strncat(string, KBUILD_MODNAME, remaining_size); 236 237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238 strncat(string, ",", remaining_size); 239 240 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 241 242 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 243 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 244 LINUX_VERSION_SUBLEVEL); 245 246 /*Send the command*/ 247 MLX5_SET(set_driver_version_in, in, opcode, 248 MLX5_CMD_OP_SET_DRIVER_VERSION); 249 250 mlx5_cmd_exec_in(dev, set_driver_version, in); 251 } 252 253 static int set_dma_caps(struct pci_dev *pdev) 254 { 255 int err; 256 257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 258 if (err) { 259 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 261 if (err) { 262 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 263 return err; 264 } 265 } 266 267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 268 return err; 269 } 270 271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 272 { 273 struct pci_dev *pdev = dev->pdev; 274 int err = 0; 275 276 mutex_lock(&dev->pci_status_mutex); 277 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 278 err = pci_enable_device(pdev); 279 if (!err) 280 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 281 } 282 mutex_unlock(&dev->pci_status_mutex); 283 284 return err; 285 } 286 287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 288 { 289 struct pci_dev *pdev = dev->pdev; 290 291 mutex_lock(&dev->pci_status_mutex); 292 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 293 pci_disable_device(pdev); 294 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 295 } 296 mutex_unlock(&dev->pci_status_mutex); 297 } 298 299 static int request_bar(struct pci_dev *pdev) 300 { 301 int err = 0; 302 303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 304 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 305 return -ENODEV; 306 } 307 308 err = pci_request_regions(pdev, KBUILD_MODNAME); 309 if (err) 310 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 311 312 return err; 313 } 314 315 static void release_bar(struct pci_dev *pdev) 316 { 317 pci_release_regions(pdev); 318 } 319 320 struct mlx5_reg_host_endianness { 321 u8 he; 322 u8 rsvd[15]; 323 }; 324 325 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 326 { 327 switch (size) { 328 case 128: 329 return 0; 330 case 256: 331 return 1; 332 case 512: 333 return 2; 334 case 1024: 335 return 3; 336 case 2048: 337 return 4; 338 case 4096: 339 return 5; 340 default: 341 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 342 return 0; 343 } 344 } 345 346 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 347 { 348 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 349 dev->mlx5e_res.uplink_netdev = netdev; 350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351 netdev); 352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353 } 354 355 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 356 { 357 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 358 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 359 dev->mlx5e_res.uplink_netdev); 360 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 361 } 362 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 363 364 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 365 enum mlx5_cap_type cap_type, 366 enum mlx5_cap_mode cap_mode) 367 { 368 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 369 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 370 void *out, *hca_caps; 371 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 372 int err; 373 374 memset(in, 0, sizeof(in)); 375 out = kzalloc(out_sz, GFP_KERNEL); 376 if (!out) 377 return -ENOMEM; 378 379 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 380 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 381 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 382 if (err) { 383 mlx5_core_warn(dev, 384 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 385 cap_type, cap_mode, err); 386 goto query_ex; 387 } 388 389 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 390 391 switch (cap_mode) { 392 case HCA_CAP_OPMOD_GET_MAX: 393 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 394 MLX5_UN_SZ_BYTES(hca_cap_union)); 395 break; 396 case HCA_CAP_OPMOD_GET_CUR: 397 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 398 MLX5_UN_SZ_BYTES(hca_cap_union)); 399 break; 400 default: 401 mlx5_core_warn(dev, 402 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 403 cap_type, cap_mode); 404 err = -EINVAL; 405 break; 406 } 407 query_ex: 408 kfree(out); 409 return err; 410 } 411 412 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 413 { 414 int ret; 415 416 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 417 if (ret) 418 return ret; 419 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 420 } 421 422 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 423 { 424 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 425 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 426 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 427 } 428 429 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 430 { 431 void *set_hca_cap; 432 int req_endianness; 433 int err; 434 435 if (!MLX5_CAP_GEN(dev, atomic)) 436 return 0; 437 438 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 439 if (err) 440 return err; 441 442 req_endianness = 443 MLX5_CAP_ATOMIC(dev, 444 supported_atomic_req_8B_endianness_mode_1); 445 446 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 447 return 0; 448 449 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 450 451 /* Set requestor to host endianness */ 452 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 453 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 454 455 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 456 } 457 458 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 459 { 460 void *set_hca_cap; 461 bool do_set = false; 462 int err; 463 464 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 465 !MLX5_CAP_GEN(dev, pg)) 466 return 0; 467 468 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 469 if (err) 470 return err; 471 472 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 473 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 474 MLX5_ST_SZ_BYTES(odp_cap)); 475 476 #define ODP_CAP_SET_MAX(dev, field) \ 477 do { \ 478 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 479 if (_res) { \ 480 do_set = true; \ 481 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 482 } \ 483 } while (0) 484 485 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 486 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 490 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 491 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 492 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 493 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 494 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 495 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 496 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 497 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 498 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 499 500 if (!do_set) 501 return 0; 502 503 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 504 } 505 506 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 507 { 508 struct devlink *devlink = priv_to_devlink(dev); 509 union devlink_param_value val; 510 int err; 511 512 err = devl_param_driverinit_value_get(devlink, 513 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 514 &val); 515 if (!err) 516 return val.vu32; 517 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 518 return err; 519 } 520 521 bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 522 { 523 struct devlink *devlink = priv_to_devlink(dev); 524 union devlink_param_value val; 525 int err; 526 527 err = devl_param_driverinit_value_get(devlink, 528 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 529 &val); 530 531 if (!err) 532 return val.vbool; 533 534 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 535 return MLX5_CAP_GEN(dev, roce); 536 } 537 EXPORT_SYMBOL(mlx5_is_roce_on); 538 539 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 540 { 541 void *set_hca_cap; 542 int err; 543 544 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 545 return 0; 546 547 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 548 if (err) 549 return err; 550 551 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 552 !(dev->priv.sw_vhca_id > 0)) 553 return 0; 554 555 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 556 capability); 557 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 558 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 559 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 560 561 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 562 } 563 564 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 565 { 566 struct mlx5_profile *prof = &dev->profile; 567 void *set_hca_cap; 568 int max_uc_list; 569 int err; 570 571 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 572 if (err) 573 return err; 574 575 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 576 capability); 577 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 578 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 579 580 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 581 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 582 128); 583 /* we limit the size of the pkey table to 128 entries for now */ 584 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 585 to_fw_pkey_sz(dev, 128)); 586 587 /* Check log_max_qp from HCA caps to set in current profile */ 588 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 589 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 590 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 591 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 592 prof->log_max_qp, 593 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 594 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 595 } 596 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 597 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 598 prof->log_max_qp); 599 600 /* disable cmdif checksum */ 601 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 602 603 /* Enable 4K UAR only when HCA supports it and page size is bigger 604 * than 4K. 605 */ 606 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 607 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 608 609 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 610 611 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 612 MLX5_SET(cmd_hca_cap, 613 set_hca_cap, 614 cache_line_128byte, 615 cache_line_size() >= 128 ? 1 : 0); 616 617 if (MLX5_CAP_GEN_MAX(dev, dct)) 618 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 619 620 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 621 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 622 623 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 624 MLX5_SET(cmd_hca_cap, 625 set_hca_cap, 626 num_vhca_ports, 627 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 628 629 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 630 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 631 632 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 633 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 634 635 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 636 637 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 638 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 639 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 640 641 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 642 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 643 mlx5_is_roce_on(dev)); 644 645 max_uc_list = max_uc_list_get_devlink_param(dev); 646 if (max_uc_list > 0) 647 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 648 ilog2(max_uc_list)); 649 650 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 651 } 652 653 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 654 * boot process. 655 * In case RoCE cap is writable in FW and user/devlink requested to change the 656 * cap, we are yet to query the final state of the above cap. 657 * Hence, the need for this function. 658 * 659 * Returns 660 * True: 661 * 1) RoCE cap is read only in FW and already disabled 662 * OR: 663 * 2) RoCE cap is writable in FW and user/devlink requested it off. 664 * 665 * In any other case, return False. 666 */ 667 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 668 { 669 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 670 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 671 } 672 673 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 674 { 675 void *set_hca_cap; 676 int err; 677 678 if (is_roce_fw_disabled(dev)) 679 return 0; 680 681 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 682 if (err) 683 return err; 684 685 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 686 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 687 return 0; 688 689 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 690 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 691 MLX5_ST_SZ_BYTES(roce_cap)); 692 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 693 694 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 695 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 696 697 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 698 return err; 699 } 700 701 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 702 void *set_ctx) 703 { 704 void *set_hca_cap; 705 int err; 706 707 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 708 return 0; 709 710 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 711 if (err) 712 return err; 713 714 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 715 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 716 return 0; 717 718 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 719 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 720 MLX5_ST_SZ_BYTES(port_selection_cap)); 721 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 722 723 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 724 725 return err; 726 } 727 728 static int set_hca_cap(struct mlx5_core_dev *dev) 729 { 730 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 731 void *set_ctx; 732 int err; 733 734 set_ctx = kzalloc(set_sz, GFP_KERNEL); 735 if (!set_ctx) 736 return -ENOMEM; 737 738 err = handle_hca_cap(dev, set_ctx); 739 if (err) { 740 mlx5_core_err(dev, "handle_hca_cap failed\n"); 741 goto out; 742 } 743 744 memset(set_ctx, 0, set_sz); 745 err = handle_hca_cap_atomic(dev, set_ctx); 746 if (err) { 747 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 748 goto out; 749 } 750 751 memset(set_ctx, 0, set_sz); 752 err = handle_hca_cap_odp(dev, set_ctx); 753 if (err) { 754 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 755 goto out; 756 } 757 758 memset(set_ctx, 0, set_sz); 759 err = handle_hca_cap_roce(dev, set_ctx); 760 if (err) { 761 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 762 goto out; 763 } 764 765 memset(set_ctx, 0, set_sz); 766 err = handle_hca_cap_2(dev, set_ctx); 767 if (err) { 768 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 769 goto out; 770 } 771 772 memset(set_ctx, 0, set_sz); 773 err = handle_hca_cap_port_selection(dev, set_ctx); 774 if (err) { 775 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 776 goto out; 777 } 778 779 out: 780 kfree(set_ctx); 781 return err; 782 } 783 784 static int set_hca_ctrl(struct mlx5_core_dev *dev) 785 { 786 struct mlx5_reg_host_endianness he_in; 787 struct mlx5_reg_host_endianness he_out; 788 int err; 789 790 if (!mlx5_core_is_pf(dev)) 791 return 0; 792 793 memset(&he_in, 0, sizeof(he_in)); 794 he_in.he = MLX5_SET_HOST_ENDIANNESS; 795 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 796 &he_out, sizeof(he_out), 797 MLX5_REG_HOST_ENDIANNESS, 0, 1); 798 return err; 799 } 800 801 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 802 { 803 int ret = 0; 804 805 /* Disable local_lb by default */ 806 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 807 ret = mlx5_nic_vport_update_local_lb(dev, false); 808 809 return ret; 810 } 811 812 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 813 { 814 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 815 816 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 817 MLX5_SET(enable_hca_in, in, function_id, func_id); 818 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 819 dev->caps.embedded_cpu); 820 return mlx5_cmd_exec_in(dev, enable_hca, in); 821 } 822 823 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 824 { 825 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 826 827 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 828 MLX5_SET(disable_hca_in, in, function_id, func_id); 829 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 830 dev->caps.embedded_cpu); 831 return mlx5_cmd_exec_in(dev, disable_hca, in); 832 } 833 834 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 835 { 836 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 837 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 838 u32 sup_issi; 839 int err; 840 841 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 842 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 843 if (err) { 844 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 845 u8 status = MLX5_GET(query_issi_out, query_out, status); 846 847 if (!status || syndrome == MLX5_DRIVER_SYND) { 848 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 849 err, status, syndrome); 850 return err; 851 } 852 853 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 854 dev->issi = 0; 855 return 0; 856 } 857 858 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 859 860 if (sup_issi & (1 << 1)) { 861 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 862 863 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 864 MLX5_SET(set_issi_in, set_in, current_issi, 1); 865 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 866 if (err) { 867 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 868 err); 869 return err; 870 } 871 872 dev->issi = 1; 873 874 return 0; 875 } else if (sup_issi & (1 << 0) || !sup_issi) { 876 return 0; 877 } 878 879 return -EOPNOTSUPP; 880 } 881 882 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 883 const struct pci_device_id *id) 884 { 885 int err = 0; 886 887 mutex_init(&dev->pci_status_mutex); 888 pci_set_drvdata(dev->pdev, dev); 889 890 dev->bar_addr = pci_resource_start(pdev, 0); 891 892 err = mlx5_pci_enable_device(dev); 893 if (err) { 894 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 895 return err; 896 } 897 898 err = request_bar(pdev); 899 if (err) { 900 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 901 goto err_disable; 902 } 903 904 pci_set_master(pdev); 905 906 err = set_dma_caps(pdev); 907 if (err) { 908 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 909 goto err_clr_master; 910 } 911 912 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 913 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 914 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 915 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 916 917 dev->iseg_base = dev->bar_addr; 918 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 919 if (!dev->iseg) { 920 err = -ENOMEM; 921 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 922 goto err_clr_master; 923 } 924 925 mlx5_pci_vsc_init(dev); 926 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 927 return 0; 928 929 err_clr_master: 930 release_bar(dev->pdev); 931 err_disable: 932 mlx5_pci_disable_device(dev); 933 return err; 934 } 935 936 static void mlx5_pci_close(struct mlx5_core_dev *dev) 937 { 938 /* health work might still be active, and it needs pci bar in 939 * order to know the NIC state. Therefore, drain the health WQ 940 * before removing the pci bars 941 */ 942 mlx5_drain_health_wq(dev); 943 iounmap(dev->iseg); 944 release_bar(dev->pdev); 945 mlx5_pci_disable_device(dev); 946 } 947 948 static int mlx5_init_once(struct mlx5_core_dev *dev) 949 { 950 int err; 951 952 dev->priv.devcom = mlx5_devcom_register_device(dev); 953 if (IS_ERR(dev->priv.devcom)) 954 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 955 dev->priv.devcom); 956 957 err = mlx5_query_board_id(dev); 958 if (err) { 959 mlx5_core_err(dev, "query board id failed\n"); 960 goto err_devcom; 961 } 962 963 err = mlx5_irq_table_init(dev); 964 if (err) { 965 mlx5_core_err(dev, "failed to initialize irq table\n"); 966 goto err_devcom; 967 } 968 969 err = mlx5_eq_table_init(dev); 970 if (err) { 971 mlx5_core_err(dev, "failed to initialize eq\n"); 972 goto err_irq_cleanup; 973 } 974 975 err = mlx5_events_init(dev); 976 if (err) { 977 mlx5_core_err(dev, "failed to initialize events\n"); 978 goto err_eq_cleanup; 979 } 980 981 err = mlx5_fw_reset_init(dev); 982 if (err) { 983 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 984 goto err_events_cleanup; 985 } 986 987 mlx5_cq_debugfs_init(dev); 988 989 mlx5_init_reserved_gids(dev); 990 991 mlx5_init_clock(dev); 992 993 dev->vxlan = mlx5_vxlan_create(dev); 994 dev->geneve = mlx5_geneve_create(dev); 995 996 err = mlx5_init_rl_table(dev); 997 if (err) { 998 mlx5_core_err(dev, "Failed to init rate limiting\n"); 999 goto err_tables_cleanup; 1000 } 1001 1002 err = mlx5_mpfs_init(dev); 1003 if (err) { 1004 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1005 goto err_rl_cleanup; 1006 } 1007 1008 err = mlx5_sriov_init(dev); 1009 if (err) { 1010 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 1011 goto err_mpfs_cleanup; 1012 } 1013 1014 err = mlx5_eswitch_init(dev); 1015 if (err) { 1016 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 1017 goto err_sriov_cleanup; 1018 } 1019 1020 err = mlx5_fpga_init(dev); 1021 if (err) { 1022 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 1023 goto err_eswitch_cleanup; 1024 } 1025 1026 err = mlx5_vhca_event_init(dev); 1027 if (err) { 1028 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1029 goto err_fpga_cleanup; 1030 } 1031 1032 err = mlx5_sf_hw_table_init(dev); 1033 if (err) { 1034 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1035 goto err_sf_hw_table_cleanup; 1036 } 1037 1038 err = mlx5_sf_table_init(dev); 1039 if (err) { 1040 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1041 goto err_sf_table_cleanup; 1042 } 1043 1044 err = mlx5_fs_core_alloc(dev); 1045 if (err) { 1046 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1047 goto err_fs; 1048 } 1049 1050 dev->dm = mlx5_dm_create(dev); 1051 if (IS_ERR(dev->dm)) 1052 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 1053 1054 dev->tracer = mlx5_fw_tracer_create(dev); 1055 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1056 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1057 1058 return 0; 1059 1060 err_fs: 1061 mlx5_sf_table_cleanup(dev); 1062 err_sf_table_cleanup: 1063 mlx5_sf_hw_table_cleanup(dev); 1064 err_sf_hw_table_cleanup: 1065 mlx5_vhca_event_cleanup(dev); 1066 err_fpga_cleanup: 1067 mlx5_fpga_cleanup(dev); 1068 err_eswitch_cleanup: 1069 mlx5_eswitch_cleanup(dev->priv.eswitch); 1070 err_sriov_cleanup: 1071 mlx5_sriov_cleanup(dev); 1072 err_mpfs_cleanup: 1073 mlx5_mpfs_cleanup(dev); 1074 err_rl_cleanup: 1075 mlx5_cleanup_rl_table(dev); 1076 err_tables_cleanup: 1077 mlx5_geneve_destroy(dev->geneve); 1078 mlx5_vxlan_destroy(dev->vxlan); 1079 mlx5_cleanup_clock(dev); 1080 mlx5_cleanup_reserved_gids(dev); 1081 mlx5_cq_debugfs_cleanup(dev); 1082 mlx5_fw_reset_cleanup(dev); 1083 err_events_cleanup: 1084 mlx5_events_cleanup(dev); 1085 err_eq_cleanup: 1086 mlx5_eq_table_cleanup(dev); 1087 err_irq_cleanup: 1088 mlx5_irq_table_cleanup(dev); 1089 err_devcom: 1090 mlx5_devcom_unregister_device(dev->priv.devcom); 1091 1092 return err; 1093 } 1094 1095 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1096 { 1097 mlx5_rsc_dump_destroy(dev); 1098 mlx5_hv_vhca_destroy(dev->hv_vhca); 1099 mlx5_fw_tracer_destroy(dev->tracer); 1100 mlx5_dm_cleanup(dev); 1101 mlx5_fs_core_free(dev); 1102 mlx5_sf_table_cleanup(dev); 1103 mlx5_sf_hw_table_cleanup(dev); 1104 mlx5_vhca_event_cleanup(dev); 1105 mlx5_fpga_cleanup(dev); 1106 mlx5_eswitch_cleanup(dev->priv.eswitch); 1107 mlx5_sriov_cleanup(dev); 1108 mlx5_mpfs_cleanup(dev); 1109 mlx5_cleanup_rl_table(dev); 1110 mlx5_geneve_destroy(dev->geneve); 1111 mlx5_vxlan_destroy(dev->vxlan); 1112 mlx5_cleanup_clock(dev); 1113 mlx5_cleanup_reserved_gids(dev); 1114 mlx5_cq_debugfs_cleanup(dev); 1115 mlx5_fw_reset_cleanup(dev); 1116 mlx5_events_cleanup(dev); 1117 mlx5_eq_table_cleanup(dev); 1118 mlx5_irq_table_cleanup(dev); 1119 mlx5_devcom_unregister_device(dev->priv.devcom); 1120 } 1121 1122 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1123 { 1124 int err; 1125 1126 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1127 fw_rev_min(dev), fw_rev_sub(dev)); 1128 1129 /* Only PFs hold the relevant PCIe information for this query */ 1130 if (mlx5_core_is_pf(dev)) 1131 pcie_print_link_status(dev->pdev); 1132 1133 /* wait for firmware to accept initialization segments configurations 1134 */ 1135 err = wait_fw_init(dev, timeout, 1136 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 1137 if (err) { 1138 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 1139 timeout); 1140 return err; 1141 } 1142 1143 err = mlx5_cmd_init(dev); 1144 if (err) { 1145 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1146 return err; 1147 } 1148 1149 mlx5_tout_query_iseg(dev); 1150 1151 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1152 if (err) { 1153 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 1154 mlx5_tout_ms(dev, FW_INIT)); 1155 goto err_cmd_cleanup; 1156 } 1157 1158 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1159 1160 mlx5_start_health_poll(dev); 1161 1162 err = mlx5_core_enable_hca(dev, 0); 1163 if (err) { 1164 mlx5_core_err(dev, "enable hca failed\n"); 1165 goto stop_health_poll; 1166 } 1167 1168 err = mlx5_core_set_issi(dev); 1169 if (err) { 1170 mlx5_core_err(dev, "failed to set issi\n"); 1171 goto err_disable_hca; 1172 } 1173 1174 err = mlx5_satisfy_startup_pages(dev, 1); 1175 if (err) { 1176 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1177 goto err_disable_hca; 1178 } 1179 1180 err = mlx5_tout_query_dtor(dev); 1181 if (err) { 1182 mlx5_core_err(dev, "failed to read dtor\n"); 1183 goto reclaim_boot_pages; 1184 } 1185 1186 err = set_hca_ctrl(dev); 1187 if (err) { 1188 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1189 goto reclaim_boot_pages; 1190 } 1191 1192 err = set_hca_cap(dev); 1193 if (err) { 1194 mlx5_core_err(dev, "set_hca_cap failed\n"); 1195 goto reclaim_boot_pages; 1196 } 1197 1198 err = mlx5_satisfy_startup_pages(dev, 0); 1199 if (err) { 1200 mlx5_core_err(dev, "failed to allocate init pages\n"); 1201 goto reclaim_boot_pages; 1202 } 1203 1204 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1205 if (err) { 1206 mlx5_core_err(dev, "init hca failed\n"); 1207 goto reclaim_boot_pages; 1208 } 1209 1210 mlx5_set_driver_version(dev); 1211 1212 err = mlx5_query_hca_caps(dev); 1213 if (err) { 1214 mlx5_core_err(dev, "query hca failed\n"); 1215 goto reclaim_boot_pages; 1216 } 1217 mlx5_start_health_fw_log_up(dev); 1218 1219 return 0; 1220 1221 reclaim_boot_pages: 1222 mlx5_reclaim_startup_pages(dev); 1223 err_disable_hca: 1224 mlx5_core_disable_hca(dev, 0); 1225 stop_health_poll: 1226 mlx5_stop_health_poll(dev, boot); 1227 err_cmd_cleanup: 1228 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1229 mlx5_cmd_cleanup(dev); 1230 1231 return err; 1232 } 1233 1234 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1235 { 1236 int err; 1237 1238 err = mlx5_cmd_teardown_hca(dev); 1239 if (err) { 1240 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1241 return err; 1242 } 1243 mlx5_reclaim_startup_pages(dev); 1244 mlx5_core_disable_hca(dev, 0); 1245 mlx5_stop_health_poll(dev, boot); 1246 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1247 mlx5_cmd_cleanup(dev); 1248 1249 return 0; 1250 } 1251 1252 static int mlx5_load(struct mlx5_core_dev *dev) 1253 { 1254 int err; 1255 1256 dev->priv.uar = mlx5_get_uars_page(dev); 1257 if (IS_ERR(dev->priv.uar)) { 1258 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1259 err = PTR_ERR(dev->priv.uar); 1260 return err; 1261 } 1262 1263 mlx5_events_start(dev); 1264 mlx5_pagealloc_start(dev); 1265 1266 err = mlx5_irq_table_create(dev); 1267 if (err) { 1268 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1269 goto err_irq_table; 1270 } 1271 1272 err = mlx5_eq_table_create(dev); 1273 if (err) { 1274 mlx5_core_err(dev, "Failed to create EQs\n"); 1275 goto err_eq_table; 1276 } 1277 1278 err = mlx5_fw_tracer_init(dev->tracer); 1279 if (err) { 1280 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1281 mlx5_fw_tracer_destroy(dev->tracer); 1282 dev->tracer = NULL; 1283 } 1284 1285 mlx5_fw_reset_events_start(dev); 1286 mlx5_hv_vhca_init(dev->hv_vhca); 1287 1288 err = mlx5_rsc_dump_init(dev); 1289 if (err) { 1290 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1291 mlx5_rsc_dump_destroy(dev); 1292 dev->rsc_dump = NULL; 1293 } 1294 1295 err = mlx5_fpga_device_start(dev); 1296 if (err) { 1297 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1298 goto err_fpga_start; 1299 } 1300 1301 err = mlx5_fs_core_init(dev); 1302 if (err) { 1303 mlx5_core_err(dev, "Failed to init flow steering\n"); 1304 goto err_fs; 1305 } 1306 1307 err = mlx5_core_set_hca_defaults(dev); 1308 if (err) { 1309 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1310 goto err_set_hca; 1311 } 1312 1313 mlx5_vhca_event_start(dev); 1314 1315 err = mlx5_sf_hw_table_create(dev); 1316 if (err) { 1317 mlx5_core_err(dev, "sf table create failed %d\n", err); 1318 goto err_vhca; 1319 } 1320 1321 err = mlx5_ec_init(dev); 1322 if (err) { 1323 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1324 goto err_ec; 1325 } 1326 1327 mlx5_lag_add_mdev(dev); 1328 err = mlx5_sriov_attach(dev); 1329 if (err) { 1330 mlx5_core_err(dev, "sriov init failed %d\n", err); 1331 goto err_sriov; 1332 } 1333 1334 mlx5_sf_dev_table_create(dev); 1335 1336 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1337 if (err) 1338 goto err_traps_reg; 1339 1340 return 0; 1341 1342 err_traps_reg: 1343 mlx5_sf_dev_table_destroy(dev); 1344 mlx5_sriov_detach(dev); 1345 err_sriov: 1346 mlx5_lag_remove_mdev(dev); 1347 mlx5_ec_cleanup(dev); 1348 err_ec: 1349 mlx5_sf_hw_table_destroy(dev); 1350 err_vhca: 1351 mlx5_vhca_event_stop(dev); 1352 err_set_hca: 1353 mlx5_fs_core_cleanup(dev); 1354 err_fs: 1355 mlx5_fpga_device_stop(dev); 1356 err_fpga_start: 1357 mlx5_rsc_dump_cleanup(dev); 1358 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1359 mlx5_fw_reset_events_stop(dev); 1360 mlx5_fw_tracer_cleanup(dev->tracer); 1361 mlx5_eq_table_destroy(dev); 1362 err_eq_table: 1363 mlx5_irq_table_destroy(dev); 1364 err_irq_table: 1365 mlx5_pagealloc_stop(dev); 1366 mlx5_events_stop(dev); 1367 mlx5_put_uars_page(dev, dev->priv.uar); 1368 return err; 1369 } 1370 1371 static void mlx5_unload(struct mlx5_core_dev *dev) 1372 { 1373 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1374 mlx5_sf_dev_table_destroy(dev); 1375 mlx5_eswitch_disable(dev->priv.eswitch); 1376 mlx5_sriov_detach(dev); 1377 mlx5_lag_remove_mdev(dev); 1378 mlx5_ec_cleanup(dev); 1379 mlx5_sf_hw_table_destroy(dev); 1380 mlx5_vhca_event_stop(dev); 1381 mlx5_fs_core_cleanup(dev); 1382 mlx5_fpga_device_stop(dev); 1383 mlx5_rsc_dump_cleanup(dev); 1384 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1385 mlx5_fw_reset_events_stop(dev); 1386 mlx5_fw_tracer_cleanup(dev->tracer); 1387 mlx5_eq_table_destroy(dev); 1388 mlx5_irq_table_destroy(dev); 1389 mlx5_pagealloc_stop(dev); 1390 mlx5_events_stop(dev); 1391 mlx5_put_uars_page(dev, dev->priv.uar); 1392 } 1393 1394 int mlx5_init_one(struct mlx5_core_dev *dev) 1395 { 1396 struct devlink *devlink = priv_to_devlink(dev); 1397 int err = 0; 1398 1399 devl_lock(devlink); 1400 mutex_lock(&dev->intf_state_mutex); 1401 dev->state = MLX5_DEVICE_STATE_UP; 1402 1403 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1404 if (err) 1405 goto err_function; 1406 1407 err = mlx5_init_once(dev); 1408 if (err) { 1409 mlx5_core_err(dev, "sw objs init failed\n"); 1410 goto function_teardown; 1411 } 1412 1413 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1414 if (err) 1415 goto err_devlink_params_reg; 1416 1417 err = mlx5_load(dev); 1418 if (err) 1419 goto err_load; 1420 1421 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1422 1423 err = mlx5_register_device(dev); 1424 if (err) 1425 goto err_register; 1426 1427 mutex_unlock(&dev->intf_state_mutex); 1428 devl_unlock(devlink); 1429 return 0; 1430 1431 err_register: 1432 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1433 mlx5_unload(dev); 1434 err_load: 1435 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1436 err_devlink_params_reg: 1437 mlx5_cleanup_once(dev); 1438 function_teardown: 1439 mlx5_function_teardown(dev, true); 1440 err_function: 1441 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1442 mutex_unlock(&dev->intf_state_mutex); 1443 devl_unlock(devlink); 1444 return err; 1445 } 1446 1447 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1448 { 1449 struct devlink *devlink = priv_to_devlink(dev); 1450 1451 devl_lock(devlink); 1452 mutex_lock(&dev->intf_state_mutex); 1453 1454 mlx5_unregister_device(dev); 1455 1456 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1457 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1458 __func__); 1459 mlx5_cleanup_once(dev); 1460 goto out; 1461 } 1462 1463 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1464 mlx5_unload(dev); 1465 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1466 mlx5_cleanup_once(dev); 1467 mlx5_function_teardown(dev, true); 1468 out: 1469 mutex_unlock(&dev->intf_state_mutex); 1470 devl_unlock(devlink); 1471 } 1472 1473 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1474 { 1475 int err = 0; 1476 u64 timeout; 1477 1478 devl_assert_locked(priv_to_devlink(dev)); 1479 mutex_lock(&dev->intf_state_mutex); 1480 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1481 mlx5_core_warn(dev, "interface is up, NOP\n"); 1482 goto out; 1483 } 1484 /* remove any previous indication of internal error */ 1485 dev->state = MLX5_DEVICE_STATE_UP; 1486 1487 if (recovery) 1488 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1489 else 1490 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1491 err = mlx5_function_setup(dev, false, timeout); 1492 if (err) 1493 goto err_function; 1494 1495 err = mlx5_load(dev); 1496 if (err) 1497 goto err_load; 1498 1499 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1500 1501 err = mlx5_attach_device(dev); 1502 if (err) 1503 goto err_attach; 1504 1505 mutex_unlock(&dev->intf_state_mutex); 1506 return 0; 1507 1508 err_attach: 1509 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1510 mlx5_unload(dev); 1511 err_load: 1512 mlx5_function_teardown(dev, false); 1513 err_function: 1514 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1515 out: 1516 mutex_unlock(&dev->intf_state_mutex); 1517 return err; 1518 } 1519 1520 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1521 { 1522 struct devlink *devlink = priv_to_devlink(dev); 1523 int ret; 1524 1525 devl_lock(devlink); 1526 ret = mlx5_load_one_devl_locked(dev, recovery); 1527 devl_unlock(devlink); 1528 return ret; 1529 } 1530 1531 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 1532 { 1533 devl_assert_locked(priv_to_devlink(dev)); 1534 mutex_lock(&dev->intf_state_mutex); 1535 1536 mlx5_detach_device(dev, suspend); 1537 1538 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1539 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1540 __func__); 1541 goto out; 1542 } 1543 1544 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1545 mlx5_unload(dev); 1546 mlx5_function_teardown(dev, false); 1547 out: 1548 mutex_unlock(&dev->intf_state_mutex); 1549 } 1550 1551 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 1552 { 1553 struct devlink *devlink = priv_to_devlink(dev); 1554 1555 devl_lock(devlink); 1556 mlx5_unload_one_devl_locked(dev, suspend); 1557 devl_unlock(devlink); 1558 } 1559 1560 static const int types[] = { 1561 MLX5_CAP_GENERAL, 1562 MLX5_CAP_GENERAL_2, 1563 MLX5_CAP_ETHERNET_OFFLOADS, 1564 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1565 MLX5_CAP_ODP, 1566 MLX5_CAP_ATOMIC, 1567 MLX5_CAP_ROCE, 1568 MLX5_CAP_IPOIB_OFFLOADS, 1569 MLX5_CAP_FLOW_TABLE, 1570 MLX5_CAP_ESWITCH_FLOW_TABLE, 1571 MLX5_CAP_ESWITCH, 1572 MLX5_CAP_VECTOR_CALC, 1573 MLX5_CAP_QOS, 1574 MLX5_CAP_DEBUG, 1575 MLX5_CAP_DEV_MEM, 1576 MLX5_CAP_DEV_EVENT, 1577 MLX5_CAP_TLS, 1578 MLX5_CAP_VDPA_EMULATION, 1579 MLX5_CAP_IPSEC, 1580 MLX5_CAP_PORT_SELECTION, 1581 MLX5_CAP_DEV_SHAMPO, 1582 MLX5_CAP_MACSEC, 1583 MLX5_CAP_ADV_VIRTUALIZATION, 1584 MLX5_CAP_CRYPTO, 1585 }; 1586 1587 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1588 { 1589 int type; 1590 int i; 1591 1592 for (i = 0; i < ARRAY_SIZE(types); i++) { 1593 type = types[i]; 1594 kfree(dev->caps.hca[type]); 1595 } 1596 } 1597 1598 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1599 { 1600 struct mlx5_hca_cap *cap; 1601 int type; 1602 int i; 1603 1604 for (i = 0; i < ARRAY_SIZE(types); i++) { 1605 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1606 if (!cap) 1607 goto err; 1608 type = types[i]; 1609 dev->caps.hca[type] = cap; 1610 } 1611 1612 return 0; 1613 1614 err: 1615 mlx5_hca_caps_free(dev); 1616 return -ENOMEM; 1617 } 1618 1619 static int vhca_id_show(struct seq_file *file, void *priv) 1620 { 1621 struct mlx5_core_dev *dev = file->private; 1622 1623 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1624 return 0; 1625 } 1626 1627 DEFINE_SHOW_ATTRIBUTE(vhca_id); 1628 1629 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1630 { 1631 struct mlx5_priv *priv = &dev->priv; 1632 int err; 1633 1634 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1635 lockdep_register_key(&dev->lock_key); 1636 mutex_init(&dev->intf_state_mutex); 1637 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1638 mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1639 1640 mutex_init(&priv->bfregs.reg_head.lock); 1641 mutex_init(&priv->bfregs.wc_head.lock); 1642 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1643 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1644 1645 mutex_init(&priv->alloc_mutex); 1646 mutex_init(&priv->pgdir_mutex); 1647 INIT_LIST_HEAD(&priv->pgdir_list); 1648 1649 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1650 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1651 mlx5_debugfs_root); 1652 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 1653 INIT_LIST_HEAD(&priv->traps); 1654 1655 err = mlx5_tout_init(dev); 1656 if (err) { 1657 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1658 goto err_timeout_init; 1659 } 1660 1661 err = mlx5_health_init(dev); 1662 if (err) 1663 goto err_health_init; 1664 1665 err = mlx5_pagealloc_init(dev); 1666 if (err) 1667 goto err_pagealloc_init; 1668 1669 err = mlx5_adev_init(dev); 1670 if (err) 1671 goto err_adev_init; 1672 1673 err = mlx5_hca_caps_alloc(dev); 1674 if (err) 1675 goto err_hca_caps; 1676 1677 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1678 * unique id per function which uses mlx5_core. 1679 * Those values are supplied to FW as part of the init HCA command to 1680 * be used by both driver and FW when it's applicable. 1681 */ 1682 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1683 MAX_SW_VHCA_ID, 1684 GFP_KERNEL); 1685 if (dev->priv.sw_vhca_id < 0) 1686 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1687 dev->priv.sw_vhca_id); 1688 1689 return 0; 1690 1691 err_hca_caps: 1692 mlx5_adev_cleanup(dev); 1693 err_adev_init: 1694 mlx5_pagealloc_cleanup(dev); 1695 err_pagealloc_init: 1696 mlx5_health_cleanup(dev); 1697 err_health_init: 1698 mlx5_tout_cleanup(dev); 1699 err_timeout_init: 1700 debugfs_remove(dev->priv.dbg.dbg_root); 1701 mutex_destroy(&priv->pgdir_mutex); 1702 mutex_destroy(&priv->alloc_mutex); 1703 mutex_destroy(&priv->bfregs.wc_head.lock); 1704 mutex_destroy(&priv->bfregs.reg_head.lock); 1705 mutex_destroy(&dev->intf_state_mutex); 1706 lockdep_unregister_key(&dev->lock_key); 1707 return err; 1708 } 1709 1710 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1711 { 1712 struct mlx5_priv *priv = &dev->priv; 1713 1714 if (priv->sw_vhca_id > 0) 1715 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1716 1717 mlx5_hca_caps_free(dev); 1718 mlx5_adev_cleanup(dev); 1719 mlx5_pagealloc_cleanup(dev); 1720 mlx5_health_cleanup(dev); 1721 mlx5_tout_cleanup(dev); 1722 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1723 mutex_destroy(&priv->pgdir_mutex); 1724 mutex_destroy(&priv->alloc_mutex); 1725 mutex_destroy(&priv->bfregs.wc_head.lock); 1726 mutex_destroy(&priv->bfregs.reg_head.lock); 1727 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1728 mutex_destroy(&dev->intf_state_mutex); 1729 lockdep_unregister_key(&dev->lock_key); 1730 } 1731 1732 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1733 { 1734 struct mlx5_core_dev *dev; 1735 struct devlink *devlink; 1736 int err; 1737 1738 devlink = mlx5_devlink_alloc(&pdev->dev); 1739 if (!devlink) { 1740 dev_err(&pdev->dev, "devlink alloc failed\n"); 1741 return -ENOMEM; 1742 } 1743 1744 dev = devlink_priv(devlink); 1745 dev->device = &pdev->dev; 1746 dev->pdev = pdev; 1747 1748 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1749 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1750 1751 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1752 if (dev->priv.adev_idx < 0) { 1753 err = dev->priv.adev_idx; 1754 goto adev_init_err; 1755 } 1756 1757 err = mlx5_mdev_init(dev, prof_sel); 1758 if (err) 1759 goto mdev_init_err; 1760 1761 err = mlx5_pci_init(dev, pdev, id); 1762 if (err) { 1763 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1764 err); 1765 goto pci_init_err; 1766 } 1767 1768 err = mlx5_init_one(dev); 1769 if (err) { 1770 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1771 err); 1772 goto err_init_one; 1773 } 1774 1775 err = mlx5_crdump_enable(dev); 1776 if (err) 1777 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1778 1779 err = mlx5_thermal_init(dev); 1780 if (err) 1781 dev_err(&pdev->dev, "mlx5_thermal_init failed with error code %d\n", err); 1782 1783 pci_save_state(pdev); 1784 devlink_register(devlink); 1785 return 0; 1786 1787 err_init_one: 1788 mlx5_pci_close(dev); 1789 pci_init_err: 1790 mlx5_mdev_uninit(dev); 1791 mdev_init_err: 1792 mlx5_adev_idx_free(dev->priv.adev_idx); 1793 adev_init_err: 1794 mlx5_devlink_free(devlink); 1795 1796 return err; 1797 } 1798 1799 static void remove_one(struct pci_dev *pdev) 1800 { 1801 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1802 struct devlink *devlink = priv_to_devlink(dev); 1803 1804 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1805 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 1806 * fw_reset before unregistering the devlink. 1807 */ 1808 mlx5_drain_fw_reset(dev); 1809 devlink_unregister(devlink); 1810 mlx5_sriov_disable(pdev); 1811 mlx5_thermal_uninit(dev); 1812 mlx5_crdump_disable(dev); 1813 mlx5_drain_health_wq(dev); 1814 mlx5_uninit_one(dev); 1815 mlx5_pci_close(dev); 1816 mlx5_mdev_uninit(dev); 1817 mlx5_adev_idx_free(dev->priv.adev_idx); 1818 mlx5_devlink_free(devlink); 1819 } 1820 1821 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1822 struct mlx5_core_dev *__dev = (dev); \ 1823 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1824 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1825 __dev->pci_status, ##__VA_ARGS__); \ 1826 }) 1827 1828 static const char *result2str(enum pci_ers_result result) 1829 { 1830 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1831 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1832 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1833 "unknown"; 1834 } 1835 1836 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1837 pci_channel_state_t state) 1838 { 1839 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1840 enum pci_ers_result res; 1841 1842 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 1843 1844 mlx5_enter_error_state(dev, false); 1845 mlx5_error_sw_reset(dev); 1846 mlx5_unload_one(dev, true); 1847 mlx5_drain_health_wq(dev); 1848 mlx5_pci_disable_device(dev); 1849 1850 res = state == pci_channel_io_perm_failure ? 1851 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1852 1853 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 1854 __func__, dev->state, dev->pci_status, res, result2str(res)); 1855 return res; 1856 } 1857 1858 /* wait for the device to show vital signs by waiting 1859 * for the health counter to start counting. 1860 */ 1861 static int wait_vital(struct pci_dev *pdev) 1862 { 1863 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1864 struct mlx5_core_health *health = &dev->priv.health; 1865 const int niter = 100; 1866 u32 last_count = 0; 1867 u32 count; 1868 int i; 1869 1870 for (i = 0; i < niter; i++) { 1871 count = ioread32be(health->health_counter); 1872 if (count && count != 0xffffffff) { 1873 if (last_count && last_count != count) { 1874 mlx5_core_info(dev, 1875 "wait vital counter value 0x%x after %d iterations\n", 1876 count, i); 1877 return 0; 1878 } 1879 last_count = count; 1880 } 1881 msleep(50); 1882 } 1883 1884 return -ETIMEDOUT; 1885 } 1886 1887 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1888 { 1889 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 1890 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1891 int err; 1892 1893 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 1894 __func__, dev->state, dev->pci_status); 1895 1896 err = mlx5_pci_enable_device(dev); 1897 if (err) { 1898 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1899 __func__, err); 1900 goto out; 1901 } 1902 1903 pci_set_master(pdev); 1904 pci_restore_state(pdev); 1905 pci_save_state(pdev); 1906 1907 err = wait_vital(pdev); 1908 if (err) { 1909 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1910 __func__, err); 1911 goto out; 1912 } 1913 1914 res = PCI_ERS_RESULT_RECOVERED; 1915 out: 1916 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 1917 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 1918 return res; 1919 } 1920 1921 static void mlx5_pci_resume(struct pci_dev *pdev) 1922 { 1923 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1924 int err; 1925 1926 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 1927 1928 err = mlx5_load_one(dev, false); 1929 1930 if (!err) 1931 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1932 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1933 1934 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1935 !err ? "recovered" : "Failed"); 1936 } 1937 1938 static const struct pci_error_handlers mlx5_err_handler = { 1939 .error_detected = mlx5_pci_err_detected, 1940 .slot_reset = mlx5_pci_slot_reset, 1941 .resume = mlx5_pci_resume 1942 }; 1943 1944 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1945 { 1946 bool fast_teardown = false, force_teardown = false; 1947 int ret = 1; 1948 1949 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1950 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1951 1952 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1953 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1954 1955 if (!fast_teardown && !force_teardown) 1956 return -EOPNOTSUPP; 1957 1958 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1959 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1960 return -EAGAIN; 1961 } 1962 1963 /* Panic tear down fw command will stop the PCI bus communication 1964 * with the HCA, so the health poll is no longer needed. 1965 */ 1966 mlx5_drain_health_wq(dev); 1967 mlx5_stop_health_poll(dev, false); 1968 1969 ret = mlx5_cmd_fast_teardown_hca(dev); 1970 if (!ret) 1971 goto succeed; 1972 1973 ret = mlx5_cmd_force_teardown_hca(dev); 1974 if (!ret) 1975 goto succeed; 1976 1977 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1978 mlx5_start_health_poll(dev); 1979 return ret; 1980 1981 succeed: 1982 mlx5_enter_error_state(dev, true); 1983 1984 /* Some platforms requiring freeing the IRQ's in the shutdown 1985 * flow. If they aren't freed they can't be allocated after 1986 * kexec. There is no need to cleanup the mlx5_core software 1987 * contexts. 1988 */ 1989 mlx5_core_eq_free_irqs(dev); 1990 1991 return 0; 1992 } 1993 1994 static void shutdown(struct pci_dev *pdev) 1995 { 1996 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1997 int err; 1998 1999 mlx5_core_info(dev, "Shutdown was called\n"); 2000 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2001 err = mlx5_try_fast_unload(dev); 2002 if (err) 2003 mlx5_unload_one(dev, false); 2004 mlx5_pci_disable_device(dev); 2005 } 2006 2007 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 2008 { 2009 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2010 2011 mlx5_unload_one(dev, true); 2012 2013 return 0; 2014 } 2015 2016 static int mlx5_resume(struct pci_dev *pdev) 2017 { 2018 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2019 2020 return mlx5_load_one(dev, false); 2021 } 2022 2023 static const struct pci_device_id mlx5_core_pci_table[] = { 2024 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2025 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2026 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2027 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2028 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2029 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 2030 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 2031 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2032 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2033 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2034 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2035 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 2036 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2037 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2038 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2039 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2040 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2041 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2042 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2043 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2044 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2045 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2046 { 0, } 2047 }; 2048 2049 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2050 2051 void mlx5_disable_device(struct mlx5_core_dev *dev) 2052 { 2053 mlx5_error_sw_reset(dev); 2054 mlx5_unload_one_devl_locked(dev, false); 2055 } 2056 2057 int mlx5_recover_device(struct mlx5_core_dev *dev) 2058 { 2059 if (!mlx5_core_is_sf(dev)) { 2060 mlx5_pci_disable_device(dev); 2061 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2062 return -EIO; 2063 } 2064 2065 return mlx5_load_one_devl_locked(dev, true); 2066 } 2067 2068 static struct pci_driver mlx5_core_driver = { 2069 .name = KBUILD_MODNAME, 2070 .id_table = mlx5_core_pci_table, 2071 .probe = probe_one, 2072 .remove = remove_one, 2073 .suspend = mlx5_suspend, 2074 .resume = mlx5_resume, 2075 .shutdown = shutdown, 2076 .err_handler = &mlx5_err_handler, 2077 .sriov_configure = mlx5_core_sriov_configure, 2078 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2079 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2080 }; 2081 2082 /** 2083 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2084 * mlx5_core is its driver. 2085 * @pdev: The associated PCI device. 2086 * 2087 * Upon return the interface state lock stay held to let caller uses it safely. 2088 * Caller must ensure to use the returned mlx5 device for a narrow window 2089 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2090 * 2091 * Return: Pointer to the associated mlx5_core_dev or NULL. 2092 */ 2093 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2094 { 2095 struct mlx5_core_dev *mdev; 2096 2097 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2098 if (IS_ERR(mdev)) 2099 return NULL; 2100 2101 mutex_lock(&mdev->intf_state_mutex); 2102 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2103 mutex_unlock(&mdev->intf_state_mutex); 2104 return NULL; 2105 } 2106 2107 return mdev; 2108 } 2109 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2110 2111 /** 2112 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2113 * @mdev: The mlx5 core device. 2114 * 2115 * Upon return the interface state lock is unlocked and caller should not 2116 * access the mdev any more. 2117 */ 2118 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2119 { 2120 mutex_unlock(&mdev->intf_state_mutex); 2121 } 2122 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2123 2124 static void mlx5_core_verify_params(void) 2125 { 2126 if (prof_sel >= ARRAY_SIZE(profile)) { 2127 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2128 prof_sel, 2129 ARRAY_SIZE(profile) - 1, 2130 MLX5_DEFAULT_PROF); 2131 prof_sel = MLX5_DEFAULT_PROF; 2132 } 2133 } 2134 2135 static int __init mlx5_init(void) 2136 { 2137 int err; 2138 2139 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2140 "mlx5_core name not in sync with kernel module name"); 2141 2142 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2143 2144 mlx5_core_verify_params(); 2145 mlx5_register_debugfs(); 2146 2147 err = mlx5e_init(); 2148 if (err) 2149 goto err_debug; 2150 2151 err = mlx5_sf_driver_register(); 2152 if (err) 2153 goto err_sf; 2154 2155 err = pci_register_driver(&mlx5_core_driver); 2156 if (err) 2157 goto err_pci; 2158 2159 return 0; 2160 2161 err_pci: 2162 mlx5_sf_driver_unregister(); 2163 err_sf: 2164 mlx5e_cleanup(); 2165 err_debug: 2166 mlx5_unregister_debugfs(); 2167 return err; 2168 } 2169 2170 static void __exit mlx5_cleanup(void) 2171 { 2172 pci_unregister_driver(&mlx5_core_driver); 2173 mlx5_sf_driver_unregister(); 2174 mlx5e_cleanup(); 2175 mlx5_unregister_debugfs(); 2176 } 2177 2178 module_init(mlx5_init); 2179 module_exit(mlx5_cleanup); 2180