1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <net/devlink.h> 54 #include "mlx5_core.h" 55 #include "lib/eq.h" 56 #include "fs_core.h" 57 #include "lib/mpfs.h" 58 #include "eswitch.h" 59 #include "devlink.h" 60 #include "lib/mlx5.h" 61 #include "fpga/core.h" 62 #include "fpga/ipsec.h" 63 #include "accel/ipsec.h" 64 #include "accel/tls.h" 65 #include "lib/clock.h" 66 #include "lib/vxlan.h" 67 #include "lib/geneve.h" 68 #include "lib/devcom.h" 69 #include "lib/pci_vsc.h" 70 #include "diag/fw_tracer.h" 71 #include "ecpf.h" 72 #include "lib/hv_vhca.h" 73 #include "diag/rsc_dump.h" 74 75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 MODULE_VERSION(DRIVER_VERSION); 79 80 unsigned int mlx5_core_debug_mask; 81 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 82 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 83 84 #define MLX5_DEFAULT_PROF 2 85 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86 module_param_named(prof_sel, prof_sel, uint, 0444); 87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 88 89 static u32 sw_owner_id[4]; 90 91 enum { 92 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 93 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 94 }; 95 96 static struct mlx5_profile profile[] = { 97 [0] = { 98 .mask = 0, 99 }, 100 [1] = { 101 .mask = MLX5_PROF_MASK_QP_SIZE, 102 .log_max_qp = 12, 103 }, 104 [2] = { 105 .mask = MLX5_PROF_MASK_QP_SIZE | 106 MLX5_PROF_MASK_MR_CACHE, 107 .log_max_qp = 18, 108 .mr_cache[0] = { 109 .size = 500, 110 .limit = 250 111 }, 112 .mr_cache[1] = { 113 .size = 500, 114 .limit = 250 115 }, 116 .mr_cache[2] = { 117 .size = 500, 118 .limit = 250 119 }, 120 .mr_cache[3] = { 121 .size = 500, 122 .limit = 250 123 }, 124 .mr_cache[4] = { 125 .size = 500, 126 .limit = 250 127 }, 128 .mr_cache[5] = { 129 .size = 500, 130 .limit = 250 131 }, 132 .mr_cache[6] = { 133 .size = 500, 134 .limit = 250 135 }, 136 .mr_cache[7] = { 137 .size = 500, 138 .limit = 250 139 }, 140 .mr_cache[8] = { 141 .size = 500, 142 .limit = 250 143 }, 144 .mr_cache[9] = { 145 .size = 500, 146 .limit = 250 147 }, 148 .mr_cache[10] = { 149 .size = 500, 150 .limit = 250 151 }, 152 .mr_cache[11] = { 153 .size = 500, 154 .limit = 250 155 }, 156 .mr_cache[12] = { 157 .size = 64, 158 .limit = 32 159 }, 160 .mr_cache[13] = { 161 .size = 32, 162 .limit = 16 163 }, 164 .mr_cache[14] = { 165 .size = 16, 166 .limit = 8 167 }, 168 .mr_cache[15] = { 169 .size = 8, 170 .limit = 4 171 }, 172 }, 173 }; 174 175 #define FW_INIT_TIMEOUT_MILI 2000 176 #define FW_INIT_WAIT_MS 2 177 #define FW_PRE_INIT_TIMEOUT_MILI 120000 178 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 179 180 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 181 u32 warn_time_mili) 182 { 183 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 184 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 185 int err = 0; 186 187 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 188 189 while (fw_initializing(dev)) { 190 if (time_after(jiffies, end)) { 191 err = -EBUSY; 192 break; 193 } 194 if (warn_time_mili && time_after(jiffies, warn)) { 195 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 196 jiffies_to_msecs(end - warn) / 1000); 197 warn = jiffies + msecs_to_jiffies(warn_time_mili); 198 } 199 msleep(FW_INIT_WAIT_MS); 200 } 201 202 return err; 203 } 204 205 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 206 { 207 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 208 driver_version); 209 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 210 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 211 int remaining_size = driver_ver_sz; 212 char *string; 213 214 if (!MLX5_CAP_GEN(dev, driver_version)) 215 return; 216 217 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 218 219 strncpy(string, "Linux", remaining_size); 220 221 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 222 strncat(string, ",", remaining_size); 223 224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 225 strncat(string, DRIVER_NAME, remaining_size); 226 227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 228 strncat(string, ",", remaining_size); 229 230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 231 strncat(string, DRIVER_VERSION, remaining_size); 232 233 /*Send the command*/ 234 MLX5_SET(set_driver_version_in, in, opcode, 235 MLX5_CMD_OP_SET_DRIVER_VERSION); 236 237 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 238 } 239 240 static int set_dma_caps(struct pci_dev *pdev) 241 { 242 int err; 243 244 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 245 if (err) { 246 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 248 if (err) { 249 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 250 return err; 251 } 252 } 253 254 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 255 if (err) { 256 dev_warn(&pdev->dev, 257 "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 258 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 259 if (err) { 260 dev_err(&pdev->dev, 261 "Can't set consistent PCI DMA mask, aborting\n"); 262 return err; 263 } 264 } 265 266 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 267 return err; 268 } 269 270 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 271 { 272 struct pci_dev *pdev = dev->pdev; 273 int err = 0; 274 275 mutex_lock(&dev->pci_status_mutex); 276 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 277 err = pci_enable_device(pdev); 278 if (!err) 279 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 280 } 281 mutex_unlock(&dev->pci_status_mutex); 282 283 return err; 284 } 285 286 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 287 { 288 struct pci_dev *pdev = dev->pdev; 289 290 mutex_lock(&dev->pci_status_mutex); 291 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 292 pci_disable_device(pdev); 293 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 294 } 295 mutex_unlock(&dev->pci_status_mutex); 296 } 297 298 static int request_bar(struct pci_dev *pdev) 299 { 300 int err = 0; 301 302 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 303 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 304 return -ENODEV; 305 } 306 307 err = pci_request_regions(pdev, DRIVER_NAME); 308 if (err) 309 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 310 311 return err; 312 } 313 314 static void release_bar(struct pci_dev *pdev) 315 { 316 pci_release_regions(pdev); 317 } 318 319 struct mlx5_reg_host_endianness { 320 u8 he; 321 u8 rsvd[15]; 322 }; 323 324 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 325 326 enum { 327 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 328 MLX5_DEV_CAP_FLAG_DCT, 329 }; 330 331 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 332 { 333 switch (size) { 334 case 128: 335 return 0; 336 case 256: 337 return 1; 338 case 512: 339 return 2; 340 case 1024: 341 return 3; 342 case 2048: 343 return 4; 344 case 4096: 345 return 5; 346 default: 347 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 348 return 0; 349 } 350 } 351 352 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 353 enum mlx5_cap_type cap_type, 354 enum mlx5_cap_mode cap_mode) 355 { 356 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 357 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 358 void *out, *hca_caps; 359 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 360 int err; 361 362 memset(in, 0, sizeof(in)); 363 out = kzalloc(out_sz, GFP_KERNEL); 364 if (!out) 365 return -ENOMEM; 366 367 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 368 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 369 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 370 if (err) { 371 mlx5_core_warn(dev, 372 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 373 cap_type, cap_mode, err); 374 goto query_ex; 375 } 376 377 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 378 379 switch (cap_mode) { 380 case HCA_CAP_OPMOD_GET_MAX: 381 memcpy(dev->caps.hca_max[cap_type], hca_caps, 382 MLX5_UN_SZ_BYTES(hca_cap_union)); 383 break; 384 case HCA_CAP_OPMOD_GET_CUR: 385 memcpy(dev->caps.hca_cur[cap_type], hca_caps, 386 MLX5_UN_SZ_BYTES(hca_cap_union)); 387 break; 388 default: 389 mlx5_core_warn(dev, 390 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 391 cap_type, cap_mode); 392 err = -EINVAL; 393 break; 394 } 395 query_ex: 396 kfree(out); 397 return err; 398 } 399 400 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 401 { 402 int ret; 403 404 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 405 if (ret) 406 return ret; 407 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 408 } 409 410 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 411 { 412 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 413 414 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 415 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 416 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 417 } 418 419 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 420 { 421 void *set_ctx; 422 void *set_hca_cap; 423 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 424 int req_endianness; 425 int err; 426 427 if (MLX5_CAP_GEN(dev, atomic)) { 428 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 429 if (err) 430 return err; 431 } else { 432 return 0; 433 } 434 435 req_endianness = 436 MLX5_CAP_ATOMIC(dev, 437 supported_atomic_req_8B_endianness_mode_1); 438 439 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 440 return 0; 441 442 set_ctx = kzalloc(set_sz, GFP_KERNEL); 443 if (!set_ctx) 444 return -ENOMEM; 445 446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 447 448 /* Set requestor to host endianness */ 449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 451 452 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 453 454 kfree(set_ctx); 455 return err; 456 } 457 458 static int handle_hca_cap_odp(struct mlx5_core_dev *dev) 459 { 460 void *set_hca_cap; 461 void *set_ctx; 462 int set_sz; 463 bool do_set = false; 464 int err; 465 466 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 467 !MLX5_CAP_GEN(dev, pg)) 468 return 0; 469 470 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 471 if (err) 472 return err; 473 474 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 475 set_ctx = kzalloc(set_sz, GFP_KERNEL); 476 if (!set_ctx) 477 return -ENOMEM; 478 479 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 480 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 481 MLX5_ST_SZ_BYTES(odp_cap)); 482 483 #define ODP_CAP_SET_MAX(dev, field) \ 484 do { \ 485 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 486 if (_res) { \ 487 do_set = true; \ 488 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 489 } \ 490 } while (0) 491 492 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 493 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 494 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 495 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 496 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 497 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 498 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 499 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 500 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 501 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 502 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 503 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 504 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 505 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 506 507 if (do_set) 508 err = set_caps(dev, set_ctx, set_sz, 509 MLX5_SET_HCA_CAP_OP_MOD_ODP); 510 511 kfree(set_ctx); 512 513 return err; 514 } 515 516 static int handle_hca_cap(struct mlx5_core_dev *dev) 517 { 518 void *set_ctx = NULL; 519 struct mlx5_profile *prof = dev->profile; 520 int err = -ENOMEM; 521 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 522 void *set_hca_cap; 523 524 set_ctx = kzalloc(set_sz, GFP_KERNEL); 525 if (!set_ctx) 526 goto query_ex; 527 528 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 529 if (err) 530 goto query_ex; 531 532 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 533 capability); 534 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 535 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 536 537 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 538 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 539 128); 540 /* we limit the size of the pkey table to 128 entries for now */ 541 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 542 to_fw_pkey_sz(dev, 128)); 543 544 /* Check log_max_qp from HCA caps to set in current profile */ 545 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 546 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 547 profile[prof_sel].log_max_qp, 548 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 549 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 550 } 551 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 552 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 553 prof->log_max_qp); 554 555 /* disable cmdif checksum */ 556 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 557 558 /* Enable 4K UAR only when HCA supports it and page size is bigger 559 * than 4K. 560 */ 561 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 562 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 563 564 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 565 566 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 567 MLX5_SET(cmd_hca_cap, 568 set_hca_cap, 569 cache_line_128byte, 570 cache_line_size() >= 128 ? 1 : 0); 571 572 if (MLX5_CAP_GEN_MAX(dev, dct)) 573 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 574 575 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 576 MLX5_SET(cmd_hca_cap, 577 set_hca_cap, 578 num_vhca_ports, 579 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 580 581 err = set_caps(dev, set_ctx, set_sz, 582 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 583 584 query_ex: 585 kfree(set_ctx); 586 return err; 587 } 588 589 static int set_hca_cap(struct mlx5_core_dev *dev) 590 { 591 int err; 592 593 err = handle_hca_cap(dev); 594 if (err) { 595 mlx5_core_err(dev, "handle_hca_cap failed\n"); 596 goto out; 597 } 598 599 err = handle_hca_cap_atomic(dev); 600 if (err) { 601 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 602 goto out; 603 } 604 605 err = handle_hca_cap_odp(dev); 606 if (err) { 607 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 608 goto out; 609 } 610 611 out: 612 return err; 613 } 614 615 static int set_hca_ctrl(struct mlx5_core_dev *dev) 616 { 617 struct mlx5_reg_host_endianness he_in; 618 struct mlx5_reg_host_endianness he_out; 619 int err; 620 621 if (!mlx5_core_is_pf(dev)) 622 return 0; 623 624 memset(&he_in, 0, sizeof(he_in)); 625 he_in.he = MLX5_SET_HOST_ENDIANNESS; 626 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 627 &he_out, sizeof(he_out), 628 MLX5_REG_HOST_ENDIANNESS, 0, 1); 629 return err; 630 } 631 632 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 633 { 634 int ret = 0; 635 636 /* Disable local_lb by default */ 637 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 638 ret = mlx5_nic_vport_update_local_lb(dev, false); 639 640 return ret; 641 } 642 643 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 644 { 645 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 646 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 647 648 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 649 MLX5_SET(enable_hca_in, in, function_id, func_id); 650 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 651 dev->caps.embedded_cpu); 652 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 653 } 654 655 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 656 { 657 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 658 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 659 660 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 661 MLX5_SET(disable_hca_in, in, function_id, func_id); 662 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 663 dev->caps.embedded_cpu); 664 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 665 } 666 667 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 668 struct ptp_system_timestamp *sts) 669 { 670 u32 timer_h, timer_h1, timer_l; 671 672 timer_h = ioread32be(&dev->iseg->internal_timer_h); 673 ptp_read_system_prets(sts); 674 timer_l = ioread32be(&dev->iseg->internal_timer_l); 675 ptp_read_system_postts(sts); 676 timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 677 if (timer_h != timer_h1) { 678 /* wrap around */ 679 ptp_read_system_prets(sts); 680 timer_l = ioread32be(&dev->iseg->internal_timer_l); 681 ptp_read_system_postts(sts); 682 } 683 684 return (u64)timer_l | (u64)timer_h1 << 32; 685 } 686 687 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 688 { 689 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 690 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 691 u32 sup_issi; 692 int err; 693 694 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 695 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 696 query_out, sizeof(query_out)); 697 if (err) { 698 u32 syndrome; 699 u8 status; 700 701 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 702 if (!status || syndrome == MLX5_DRIVER_SYND) { 703 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 704 err, status, syndrome); 705 return err; 706 } 707 708 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 709 dev->issi = 0; 710 return 0; 711 } 712 713 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 714 715 if (sup_issi & (1 << 1)) { 716 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 717 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 718 719 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 720 MLX5_SET(set_issi_in, set_in, current_issi, 1); 721 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 722 set_out, sizeof(set_out)); 723 if (err) { 724 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 725 err); 726 return err; 727 } 728 729 dev->issi = 1; 730 731 return 0; 732 } else if (sup_issi & (1 << 0) || !sup_issi) { 733 return 0; 734 } 735 736 return -EOPNOTSUPP; 737 } 738 739 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 740 const struct pci_device_id *id) 741 { 742 struct mlx5_priv *priv = &dev->priv; 743 int err = 0; 744 745 mutex_init(&dev->pci_status_mutex); 746 pci_set_drvdata(dev->pdev, dev); 747 748 dev->bar_addr = pci_resource_start(pdev, 0); 749 priv->numa_node = dev_to_node(&dev->pdev->dev); 750 751 err = mlx5_pci_enable_device(dev); 752 if (err) { 753 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 754 return err; 755 } 756 757 err = request_bar(pdev); 758 if (err) { 759 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 760 goto err_disable; 761 } 762 763 pci_set_master(pdev); 764 765 err = set_dma_caps(pdev); 766 if (err) { 767 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 768 goto err_clr_master; 769 } 770 771 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 774 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 775 776 dev->iseg_base = dev->bar_addr; 777 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 778 if (!dev->iseg) { 779 err = -ENOMEM; 780 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 781 goto err_clr_master; 782 } 783 784 mlx5_pci_vsc_init(dev); 785 786 return 0; 787 788 err_clr_master: 789 pci_clear_master(dev->pdev); 790 release_bar(dev->pdev); 791 err_disable: 792 mlx5_pci_disable_device(dev); 793 return err; 794 } 795 796 static void mlx5_pci_close(struct mlx5_core_dev *dev) 797 { 798 iounmap(dev->iseg); 799 pci_clear_master(dev->pdev); 800 release_bar(dev->pdev); 801 mlx5_pci_disable_device(dev); 802 } 803 804 static int mlx5_init_once(struct mlx5_core_dev *dev) 805 { 806 int err; 807 808 dev->priv.devcom = mlx5_devcom_register_device(dev); 809 if (IS_ERR(dev->priv.devcom)) 810 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 811 dev->priv.devcom); 812 813 err = mlx5_query_board_id(dev); 814 if (err) { 815 mlx5_core_err(dev, "query board id failed\n"); 816 goto err_devcom; 817 } 818 819 err = mlx5_irq_table_init(dev); 820 if (err) { 821 mlx5_core_err(dev, "failed to initialize irq table\n"); 822 goto err_devcom; 823 } 824 825 err = mlx5_eq_table_init(dev); 826 if (err) { 827 mlx5_core_err(dev, "failed to initialize eq\n"); 828 goto err_irq_cleanup; 829 } 830 831 err = mlx5_events_init(dev); 832 if (err) { 833 mlx5_core_err(dev, "failed to initialize events\n"); 834 goto err_eq_cleanup; 835 } 836 837 mlx5_cq_debugfs_init(dev); 838 839 mlx5_init_qp_table(dev); 840 841 mlx5_init_reserved_gids(dev); 842 843 mlx5_init_clock(dev); 844 845 dev->vxlan = mlx5_vxlan_create(dev); 846 dev->geneve = mlx5_geneve_create(dev); 847 848 err = mlx5_init_rl_table(dev); 849 if (err) { 850 mlx5_core_err(dev, "Failed to init rate limiting\n"); 851 goto err_tables_cleanup; 852 } 853 854 err = mlx5_mpfs_init(dev); 855 if (err) { 856 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 857 goto err_rl_cleanup; 858 } 859 860 err = mlx5_sriov_init(dev); 861 if (err) { 862 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 863 goto err_mpfs_cleanup; 864 } 865 866 err = mlx5_eswitch_init(dev); 867 if (err) { 868 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 869 goto err_sriov_cleanup; 870 } 871 872 err = mlx5_fpga_init(dev); 873 if (err) { 874 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 875 goto err_eswitch_cleanup; 876 } 877 878 dev->dm = mlx5_dm_create(dev); 879 if (IS_ERR(dev->dm)) 880 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 881 882 dev->tracer = mlx5_fw_tracer_create(dev); 883 dev->hv_vhca = mlx5_hv_vhca_create(dev); 884 dev->rsc_dump = mlx5_rsc_dump_create(dev); 885 886 return 0; 887 888 err_eswitch_cleanup: 889 mlx5_eswitch_cleanup(dev->priv.eswitch); 890 err_sriov_cleanup: 891 mlx5_sriov_cleanup(dev); 892 err_mpfs_cleanup: 893 mlx5_mpfs_cleanup(dev); 894 err_rl_cleanup: 895 mlx5_cleanup_rl_table(dev); 896 err_tables_cleanup: 897 mlx5_geneve_destroy(dev->geneve); 898 mlx5_vxlan_destroy(dev->vxlan); 899 mlx5_cleanup_qp_table(dev); 900 mlx5_cq_debugfs_cleanup(dev); 901 mlx5_events_cleanup(dev); 902 err_eq_cleanup: 903 mlx5_eq_table_cleanup(dev); 904 err_irq_cleanup: 905 mlx5_irq_table_cleanup(dev); 906 err_devcom: 907 mlx5_devcom_unregister_device(dev->priv.devcom); 908 909 return err; 910 } 911 912 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 913 { 914 mlx5_rsc_dump_destroy(dev); 915 mlx5_hv_vhca_destroy(dev->hv_vhca); 916 mlx5_fw_tracer_destroy(dev->tracer); 917 mlx5_dm_cleanup(dev); 918 mlx5_fpga_cleanup(dev); 919 mlx5_eswitch_cleanup(dev->priv.eswitch); 920 mlx5_sriov_cleanup(dev); 921 mlx5_mpfs_cleanup(dev); 922 mlx5_cleanup_rl_table(dev); 923 mlx5_geneve_destroy(dev->geneve); 924 mlx5_vxlan_destroy(dev->vxlan); 925 mlx5_cleanup_clock(dev); 926 mlx5_cleanup_reserved_gids(dev); 927 mlx5_cleanup_qp_table(dev); 928 mlx5_cq_debugfs_cleanup(dev); 929 mlx5_events_cleanup(dev); 930 mlx5_eq_table_cleanup(dev); 931 mlx5_irq_table_cleanup(dev); 932 mlx5_devcom_unregister_device(dev->priv.devcom); 933 } 934 935 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 936 { 937 int err; 938 939 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 940 fw_rev_min(dev), fw_rev_sub(dev)); 941 942 /* Only PFs hold the relevant PCIe information for this query */ 943 if (mlx5_core_is_pf(dev)) 944 pcie_print_link_status(dev->pdev); 945 946 /* wait for firmware to accept initialization segments configurations 947 */ 948 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 949 if (err) { 950 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 951 FW_PRE_INIT_TIMEOUT_MILI); 952 return err; 953 } 954 955 err = mlx5_cmd_init(dev); 956 if (err) { 957 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 958 return err; 959 } 960 961 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 962 if (err) { 963 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 964 FW_INIT_TIMEOUT_MILI); 965 goto err_cmd_cleanup; 966 } 967 968 err = mlx5_core_enable_hca(dev, 0); 969 if (err) { 970 mlx5_core_err(dev, "enable hca failed\n"); 971 goto err_cmd_cleanup; 972 } 973 974 err = mlx5_core_set_issi(dev); 975 if (err) { 976 mlx5_core_err(dev, "failed to set issi\n"); 977 goto err_disable_hca; 978 } 979 980 err = mlx5_satisfy_startup_pages(dev, 1); 981 if (err) { 982 mlx5_core_err(dev, "failed to allocate boot pages\n"); 983 goto err_disable_hca; 984 } 985 986 err = set_hca_ctrl(dev); 987 if (err) { 988 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 989 goto reclaim_boot_pages; 990 } 991 992 err = set_hca_cap(dev); 993 if (err) { 994 mlx5_core_err(dev, "set_hca_cap failed\n"); 995 goto reclaim_boot_pages; 996 } 997 998 err = mlx5_satisfy_startup_pages(dev, 0); 999 if (err) { 1000 mlx5_core_err(dev, "failed to allocate init pages\n"); 1001 goto reclaim_boot_pages; 1002 } 1003 1004 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1005 if (err) { 1006 mlx5_core_err(dev, "init hca failed\n"); 1007 goto reclaim_boot_pages; 1008 } 1009 1010 mlx5_set_driver_version(dev); 1011 1012 mlx5_start_health_poll(dev); 1013 1014 err = mlx5_query_hca_caps(dev); 1015 if (err) { 1016 mlx5_core_err(dev, "query hca failed\n"); 1017 goto stop_health; 1018 } 1019 1020 return 0; 1021 1022 stop_health: 1023 mlx5_stop_health_poll(dev, boot); 1024 reclaim_boot_pages: 1025 mlx5_reclaim_startup_pages(dev); 1026 err_disable_hca: 1027 mlx5_core_disable_hca(dev, 0); 1028 err_cmd_cleanup: 1029 mlx5_cmd_cleanup(dev); 1030 1031 return err; 1032 } 1033 1034 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1035 { 1036 int err; 1037 1038 mlx5_stop_health_poll(dev, boot); 1039 err = mlx5_cmd_teardown_hca(dev); 1040 if (err) { 1041 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1042 return err; 1043 } 1044 mlx5_reclaim_startup_pages(dev); 1045 mlx5_core_disable_hca(dev, 0); 1046 mlx5_cmd_cleanup(dev); 1047 1048 return 0; 1049 } 1050 1051 static int mlx5_load(struct mlx5_core_dev *dev) 1052 { 1053 int err; 1054 1055 dev->priv.uar = mlx5_get_uars_page(dev); 1056 if (IS_ERR(dev->priv.uar)) { 1057 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1058 err = PTR_ERR(dev->priv.uar); 1059 return err; 1060 } 1061 1062 mlx5_events_start(dev); 1063 mlx5_pagealloc_start(dev); 1064 1065 err = mlx5_irq_table_create(dev); 1066 if (err) { 1067 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1068 goto err_irq_table; 1069 } 1070 1071 err = mlx5_eq_table_create(dev); 1072 if (err) { 1073 mlx5_core_err(dev, "Failed to create EQs\n"); 1074 goto err_eq_table; 1075 } 1076 1077 err = mlx5_fw_tracer_init(dev->tracer); 1078 if (err) { 1079 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1080 goto err_fw_tracer; 1081 } 1082 1083 mlx5_hv_vhca_init(dev->hv_vhca); 1084 1085 err = mlx5_rsc_dump_init(dev); 1086 if (err) { 1087 mlx5_core_err(dev, "Failed to init Resource dump\n"); 1088 goto err_rsc_dump; 1089 } 1090 1091 err = mlx5_fpga_device_start(dev); 1092 if (err) { 1093 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1094 goto err_fpga_start; 1095 } 1096 1097 err = mlx5_accel_ipsec_init(dev); 1098 if (err) { 1099 mlx5_core_err(dev, "IPSec device start failed %d\n", err); 1100 goto err_ipsec_start; 1101 } 1102 1103 err = mlx5_accel_tls_init(dev); 1104 if (err) { 1105 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1106 goto err_tls_start; 1107 } 1108 1109 err = mlx5_init_fs(dev); 1110 if (err) { 1111 mlx5_core_err(dev, "Failed to init flow steering\n"); 1112 goto err_fs; 1113 } 1114 1115 err = mlx5_core_set_hca_defaults(dev); 1116 if (err) { 1117 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1118 goto err_sriov; 1119 } 1120 1121 err = mlx5_sriov_attach(dev); 1122 if (err) { 1123 mlx5_core_err(dev, "sriov init failed %d\n", err); 1124 goto err_sriov; 1125 } 1126 1127 err = mlx5_ec_init(dev); 1128 if (err) { 1129 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1130 goto err_ec; 1131 } 1132 1133 return 0; 1134 1135 err_ec: 1136 mlx5_sriov_detach(dev); 1137 err_sriov: 1138 mlx5_cleanup_fs(dev); 1139 err_fs: 1140 mlx5_accel_tls_cleanup(dev); 1141 err_tls_start: 1142 mlx5_accel_ipsec_cleanup(dev); 1143 err_ipsec_start: 1144 mlx5_fpga_device_stop(dev); 1145 err_fpga_start: 1146 mlx5_rsc_dump_cleanup(dev); 1147 err_rsc_dump: 1148 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1149 mlx5_fw_tracer_cleanup(dev->tracer); 1150 err_fw_tracer: 1151 mlx5_eq_table_destroy(dev); 1152 err_eq_table: 1153 mlx5_irq_table_destroy(dev); 1154 err_irq_table: 1155 mlx5_pagealloc_stop(dev); 1156 mlx5_events_stop(dev); 1157 mlx5_put_uars_page(dev, dev->priv.uar); 1158 return err; 1159 } 1160 1161 static void mlx5_unload(struct mlx5_core_dev *dev) 1162 { 1163 mlx5_ec_cleanup(dev); 1164 mlx5_sriov_detach(dev); 1165 mlx5_cleanup_fs(dev); 1166 mlx5_accel_ipsec_cleanup(dev); 1167 mlx5_accel_tls_cleanup(dev); 1168 mlx5_fpga_device_stop(dev); 1169 mlx5_rsc_dump_cleanup(dev); 1170 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1171 mlx5_fw_tracer_cleanup(dev->tracer); 1172 mlx5_eq_table_destroy(dev); 1173 mlx5_irq_table_destroy(dev); 1174 mlx5_pagealloc_stop(dev); 1175 mlx5_events_stop(dev); 1176 mlx5_put_uars_page(dev, dev->priv.uar); 1177 } 1178 1179 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1180 { 1181 int err = 0; 1182 1183 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1184 mutex_lock(&dev->intf_state_mutex); 1185 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1186 mlx5_core_warn(dev, "interface is up, NOP\n"); 1187 goto out; 1188 } 1189 /* remove any previous indication of internal error */ 1190 dev->state = MLX5_DEVICE_STATE_UP; 1191 1192 err = mlx5_function_setup(dev, boot); 1193 if (err) 1194 goto out; 1195 1196 if (boot) { 1197 err = mlx5_init_once(dev); 1198 if (err) { 1199 mlx5_core_err(dev, "sw objs init failed\n"); 1200 goto function_teardown; 1201 } 1202 } 1203 1204 err = mlx5_load(dev); 1205 if (err) 1206 goto err_load; 1207 1208 if (boot) { 1209 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1210 if (err) 1211 goto err_devlink_reg; 1212 } 1213 1214 if (mlx5_device_registered(dev)) 1215 mlx5_attach_device(dev); 1216 else 1217 mlx5_register_device(dev); 1218 1219 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1220 out: 1221 mutex_unlock(&dev->intf_state_mutex); 1222 1223 return err; 1224 1225 err_devlink_reg: 1226 mlx5_unload(dev); 1227 err_load: 1228 if (boot) 1229 mlx5_cleanup_once(dev); 1230 function_teardown: 1231 mlx5_function_teardown(dev, boot); 1232 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1233 mutex_unlock(&dev->intf_state_mutex); 1234 1235 return err; 1236 } 1237 1238 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1239 { 1240 if (cleanup) { 1241 mlx5_unregister_device(dev); 1242 mlx5_drain_health_wq(dev); 1243 } 1244 1245 mutex_lock(&dev->intf_state_mutex); 1246 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1247 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1248 __func__); 1249 if (cleanup) 1250 mlx5_cleanup_once(dev); 1251 goto out; 1252 } 1253 1254 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1255 1256 if (mlx5_device_registered(dev)) 1257 mlx5_detach_device(dev); 1258 1259 mlx5_unload(dev); 1260 1261 if (cleanup) 1262 mlx5_cleanup_once(dev); 1263 1264 mlx5_function_teardown(dev, cleanup); 1265 out: 1266 mutex_unlock(&dev->intf_state_mutex); 1267 } 1268 1269 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1270 { 1271 struct mlx5_priv *priv = &dev->priv; 1272 int err; 1273 1274 dev->profile = &profile[profile_idx]; 1275 1276 INIT_LIST_HEAD(&priv->ctx_list); 1277 spin_lock_init(&priv->ctx_lock); 1278 mutex_init(&dev->intf_state_mutex); 1279 1280 mutex_init(&priv->bfregs.reg_head.lock); 1281 mutex_init(&priv->bfregs.wc_head.lock); 1282 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1283 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1284 1285 mutex_init(&priv->alloc_mutex); 1286 mutex_init(&priv->pgdir_mutex); 1287 INIT_LIST_HEAD(&priv->pgdir_list); 1288 1289 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1290 mlx5_debugfs_root); 1291 if (!priv->dbg_root) { 1292 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 1293 return -ENOMEM; 1294 } 1295 1296 err = mlx5_health_init(dev); 1297 if (err) 1298 goto err_health_init; 1299 1300 err = mlx5_pagealloc_init(dev); 1301 if (err) 1302 goto err_pagealloc_init; 1303 1304 return 0; 1305 1306 err_pagealloc_init: 1307 mlx5_health_cleanup(dev); 1308 err_health_init: 1309 debugfs_remove(dev->priv.dbg_root); 1310 1311 return err; 1312 } 1313 1314 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1315 { 1316 mlx5_pagealloc_cleanup(dev); 1317 mlx5_health_cleanup(dev); 1318 debugfs_remove_recursive(dev->priv.dbg_root); 1319 } 1320 1321 #define MLX5_IB_MOD "mlx5_ib" 1322 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1323 { 1324 struct mlx5_core_dev *dev; 1325 struct devlink *devlink; 1326 int err; 1327 1328 devlink = mlx5_devlink_alloc(); 1329 if (!devlink) { 1330 dev_err(&pdev->dev, "devlink alloc failed\n"); 1331 return -ENOMEM; 1332 } 1333 1334 dev = devlink_priv(devlink); 1335 dev->device = &pdev->dev; 1336 dev->pdev = pdev; 1337 1338 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1339 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1340 1341 err = mlx5_mdev_init(dev, prof_sel); 1342 if (err) 1343 goto mdev_init_err; 1344 1345 err = mlx5_pci_init(dev, pdev, id); 1346 if (err) { 1347 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1348 err); 1349 goto pci_init_err; 1350 } 1351 1352 err = mlx5_load_one(dev, true); 1353 if (err) { 1354 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 1355 err); 1356 goto err_load_one; 1357 } 1358 1359 request_module_nowait(MLX5_IB_MOD); 1360 1361 err = mlx5_crdump_enable(dev); 1362 if (err) 1363 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1364 1365 pci_save_state(pdev); 1366 return 0; 1367 1368 err_load_one: 1369 mlx5_pci_close(dev); 1370 pci_init_err: 1371 mlx5_mdev_uninit(dev); 1372 mdev_init_err: 1373 mlx5_devlink_free(devlink); 1374 1375 return err; 1376 } 1377 1378 static void remove_one(struct pci_dev *pdev) 1379 { 1380 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1381 struct devlink *devlink = priv_to_devlink(dev); 1382 1383 mlx5_crdump_disable(dev); 1384 mlx5_devlink_unregister(devlink); 1385 1386 mlx5_unload_one(dev, true); 1387 mlx5_pci_close(dev); 1388 mlx5_mdev_uninit(dev); 1389 mlx5_devlink_free(devlink); 1390 } 1391 1392 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1393 pci_channel_state_t state) 1394 { 1395 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1396 1397 mlx5_core_info(dev, "%s was called\n", __func__); 1398 1399 mlx5_enter_error_state(dev, false); 1400 mlx5_error_sw_reset(dev); 1401 mlx5_unload_one(dev, false); 1402 mlx5_drain_health_wq(dev); 1403 mlx5_pci_disable_device(dev); 1404 1405 return state == pci_channel_io_perm_failure ? 1406 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1407 } 1408 1409 /* wait for the device to show vital signs by waiting 1410 * for the health counter to start counting. 1411 */ 1412 static int wait_vital(struct pci_dev *pdev) 1413 { 1414 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1415 struct mlx5_core_health *health = &dev->priv.health; 1416 const int niter = 100; 1417 u32 last_count = 0; 1418 u32 count; 1419 int i; 1420 1421 for (i = 0; i < niter; i++) { 1422 count = ioread32be(health->health_counter); 1423 if (count && count != 0xffffffff) { 1424 if (last_count && last_count != count) { 1425 mlx5_core_info(dev, 1426 "wait vital counter value 0x%x after %d iterations\n", 1427 count, i); 1428 return 0; 1429 } 1430 last_count = count; 1431 } 1432 msleep(50); 1433 } 1434 1435 return -ETIMEDOUT; 1436 } 1437 1438 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1439 { 1440 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1441 int err; 1442 1443 mlx5_core_info(dev, "%s was called\n", __func__); 1444 1445 err = mlx5_pci_enable_device(dev); 1446 if (err) { 1447 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1448 __func__, err); 1449 return PCI_ERS_RESULT_DISCONNECT; 1450 } 1451 1452 pci_set_master(pdev); 1453 pci_restore_state(pdev); 1454 pci_save_state(pdev); 1455 1456 if (wait_vital(pdev)) { 1457 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1458 return PCI_ERS_RESULT_DISCONNECT; 1459 } 1460 1461 return PCI_ERS_RESULT_RECOVERED; 1462 } 1463 1464 static void mlx5_pci_resume(struct pci_dev *pdev) 1465 { 1466 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1467 int err; 1468 1469 mlx5_core_info(dev, "%s was called\n", __func__); 1470 1471 err = mlx5_load_one(dev, false); 1472 if (err) 1473 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1474 __func__, err); 1475 else 1476 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1477 } 1478 1479 static const struct pci_error_handlers mlx5_err_handler = { 1480 .error_detected = mlx5_pci_err_detected, 1481 .slot_reset = mlx5_pci_slot_reset, 1482 .resume = mlx5_pci_resume 1483 }; 1484 1485 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1486 { 1487 bool fast_teardown = false, force_teardown = false; 1488 int ret = 1; 1489 1490 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1491 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1492 1493 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1494 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1495 1496 if (!fast_teardown && !force_teardown) 1497 return -EOPNOTSUPP; 1498 1499 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1500 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1501 return -EAGAIN; 1502 } 1503 1504 /* Panic tear down fw command will stop the PCI bus communication 1505 * with the HCA, so the health polll is no longer needed. 1506 */ 1507 mlx5_drain_health_wq(dev); 1508 mlx5_stop_health_poll(dev, false); 1509 1510 ret = mlx5_cmd_fast_teardown_hca(dev); 1511 if (!ret) 1512 goto succeed; 1513 1514 ret = mlx5_cmd_force_teardown_hca(dev); 1515 if (!ret) 1516 goto succeed; 1517 1518 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1519 mlx5_start_health_poll(dev); 1520 return ret; 1521 1522 succeed: 1523 mlx5_enter_error_state(dev, true); 1524 1525 /* Some platforms requiring freeing the IRQ's in the shutdown 1526 * flow. If they aren't freed they can't be allocated after 1527 * kexec. There is no need to cleanup the mlx5_core software 1528 * contexts. 1529 */ 1530 mlx5_core_eq_free_irqs(dev); 1531 1532 return 0; 1533 } 1534 1535 static void shutdown(struct pci_dev *pdev) 1536 { 1537 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1538 int err; 1539 1540 mlx5_core_info(dev, "Shutdown was called\n"); 1541 err = mlx5_try_fast_unload(dev); 1542 if (err) 1543 mlx5_unload_one(dev, false); 1544 mlx5_pci_disable_device(dev); 1545 } 1546 1547 static const struct pci_device_id mlx5_core_pci_table[] = { 1548 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1549 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1550 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1551 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1552 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1553 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1554 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1555 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1556 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1557 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1558 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1559 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1560 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1561 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1562 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1563 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1564 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1565 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1566 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1567 { 0, } 1568 }; 1569 1570 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1571 1572 void mlx5_disable_device(struct mlx5_core_dev *dev) 1573 { 1574 mlx5_error_sw_reset(dev); 1575 mlx5_unload_one(dev, false); 1576 } 1577 1578 void mlx5_recover_device(struct mlx5_core_dev *dev) 1579 { 1580 mlx5_pci_disable_device(dev); 1581 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1582 mlx5_pci_resume(dev->pdev); 1583 } 1584 1585 static struct pci_driver mlx5_core_driver = { 1586 .name = DRIVER_NAME, 1587 .id_table = mlx5_core_pci_table, 1588 .probe = init_one, 1589 .remove = remove_one, 1590 .shutdown = shutdown, 1591 .err_handler = &mlx5_err_handler, 1592 .sriov_configure = mlx5_core_sriov_configure, 1593 }; 1594 1595 static void mlx5_core_verify_params(void) 1596 { 1597 if (prof_sel >= ARRAY_SIZE(profile)) { 1598 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1599 prof_sel, 1600 ARRAY_SIZE(profile) - 1, 1601 MLX5_DEFAULT_PROF); 1602 prof_sel = MLX5_DEFAULT_PROF; 1603 } 1604 } 1605 1606 static int __init init(void) 1607 { 1608 int err; 1609 1610 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1611 1612 mlx5_core_verify_params(); 1613 mlx5_accel_ipsec_build_fs_cmds(); 1614 mlx5_register_debugfs(); 1615 1616 err = pci_register_driver(&mlx5_core_driver); 1617 if (err) 1618 goto err_debug; 1619 1620 #ifdef CONFIG_MLX5_CORE_EN 1621 mlx5e_init(); 1622 #endif 1623 1624 return 0; 1625 1626 err_debug: 1627 mlx5_unregister_debugfs(); 1628 return err; 1629 } 1630 1631 static void __exit cleanup(void) 1632 { 1633 #ifdef CONFIG_MLX5_CORE_EN 1634 mlx5e_cleanup(); 1635 #endif 1636 pci_unregister_driver(&mlx5_core_driver); 1637 mlx5_unregister_debugfs(); 1638 } 1639 1640 module_init(init); 1641 module_exit(cleanup); 1642