1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6052ec462eSIlan Tayari #include "lib/mlx5.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 6205564d0aSAviad Yehezkel #include "fpga/ipsec.h" 63bebb23e6SIlan Tayari #include "accel/ipsec.h" 641ae17322SIlya Lesokhin #include "accel/tls.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 7287175120SEran Ben Elisha #include "lib/hv_vhca.h" 7312206b17SAya Levin #include "diag/rsc_dump.h" 74e126ba97SEli Cohen 75e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 77e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 78e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 79e126ba97SEli Cohen 80f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 81f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 82e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 83e126ba97SEli Cohen 849603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 85f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 879603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 889603b61dSJack Morgenstein 898737f818SDaniel Jurgens static u32 sw_owner_id[4]; 908737f818SDaniel Jurgens 91f91e6d89SEran Ben Elisha enum { 92f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 93f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 94f91e6d89SEran Ben Elisha }; 95f91e6d89SEran Ben Elisha 969603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 979603b61dSJack Morgenstein [0] = { 989603b61dSJack Morgenstein .mask = 0, 999603b61dSJack Morgenstein }, 1009603b61dSJack Morgenstein [1] = { 1019603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1029603b61dSJack Morgenstein .log_max_qp = 12, 1039603b61dSJack Morgenstein }, 1049603b61dSJack Morgenstein [2] = { 1059603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1069603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1075f40b4edSMaor Gottlieb .log_max_qp = 18, 1089603b61dSJack Morgenstein .mr_cache[0] = { 1099603b61dSJack Morgenstein .size = 500, 1109603b61dSJack Morgenstein .limit = 250 1119603b61dSJack Morgenstein }, 1129603b61dSJack Morgenstein .mr_cache[1] = { 1139603b61dSJack Morgenstein .size = 500, 1149603b61dSJack Morgenstein .limit = 250 1159603b61dSJack Morgenstein }, 1169603b61dSJack Morgenstein .mr_cache[2] = { 1179603b61dSJack Morgenstein .size = 500, 1189603b61dSJack Morgenstein .limit = 250 1199603b61dSJack Morgenstein }, 1209603b61dSJack Morgenstein .mr_cache[3] = { 1219603b61dSJack Morgenstein .size = 500, 1229603b61dSJack Morgenstein .limit = 250 1239603b61dSJack Morgenstein }, 1249603b61dSJack Morgenstein .mr_cache[4] = { 1259603b61dSJack Morgenstein .size = 500, 1269603b61dSJack Morgenstein .limit = 250 1279603b61dSJack Morgenstein }, 1289603b61dSJack Morgenstein .mr_cache[5] = { 1299603b61dSJack Morgenstein .size = 500, 1309603b61dSJack Morgenstein .limit = 250 1319603b61dSJack Morgenstein }, 1329603b61dSJack Morgenstein .mr_cache[6] = { 1339603b61dSJack Morgenstein .size = 500, 1349603b61dSJack Morgenstein .limit = 250 1359603b61dSJack Morgenstein }, 1369603b61dSJack Morgenstein .mr_cache[7] = { 1379603b61dSJack Morgenstein .size = 500, 1389603b61dSJack Morgenstein .limit = 250 1399603b61dSJack Morgenstein }, 1409603b61dSJack Morgenstein .mr_cache[8] = { 1419603b61dSJack Morgenstein .size = 500, 1429603b61dSJack Morgenstein .limit = 250 1439603b61dSJack Morgenstein }, 1449603b61dSJack Morgenstein .mr_cache[9] = { 1459603b61dSJack Morgenstein .size = 500, 1469603b61dSJack Morgenstein .limit = 250 1479603b61dSJack Morgenstein }, 1489603b61dSJack Morgenstein .mr_cache[10] = { 1499603b61dSJack Morgenstein .size = 500, 1509603b61dSJack Morgenstein .limit = 250 1519603b61dSJack Morgenstein }, 1529603b61dSJack Morgenstein .mr_cache[11] = { 1539603b61dSJack Morgenstein .size = 500, 1549603b61dSJack Morgenstein .limit = 250 1559603b61dSJack Morgenstein }, 1569603b61dSJack Morgenstein .mr_cache[12] = { 1579603b61dSJack Morgenstein .size = 64, 1589603b61dSJack Morgenstein .limit = 32 1599603b61dSJack Morgenstein }, 1609603b61dSJack Morgenstein .mr_cache[13] = { 1619603b61dSJack Morgenstein .size = 32, 1629603b61dSJack Morgenstein .limit = 16 1639603b61dSJack Morgenstein }, 1649603b61dSJack Morgenstein .mr_cache[14] = { 1659603b61dSJack Morgenstein .size = 16, 1669603b61dSJack Morgenstein .limit = 8 1679603b61dSJack Morgenstein }, 1689603b61dSJack Morgenstein .mr_cache[15] = { 1699603b61dSJack Morgenstein .size = 8, 1709603b61dSJack Morgenstein .limit = 4 1719603b61dSJack Morgenstein }, 1729603b61dSJack Morgenstein }, 1739603b61dSJack Morgenstein }; 174e126ba97SEli Cohen 175e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 176e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 177b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 178b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 179e3297246SEli Cohen 180b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 181b8a92577SDaniel Jurgens u32 warn_time_mili) 182e3297246SEli Cohen { 183b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 184e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 185e3297246SEli Cohen int err = 0; 186e3297246SEli Cohen 187b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 188b8a92577SDaniel Jurgens 189e3297246SEli Cohen while (fw_initializing(dev)) { 190e3297246SEli Cohen if (time_after(jiffies, end)) { 191e3297246SEli Cohen err = -EBUSY; 192e3297246SEli Cohen break; 193e3297246SEli Cohen } 194b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 195b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 196b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 197b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 198b8a92577SDaniel Jurgens } 199e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 200e3297246SEli Cohen } 201e3297246SEli Cohen 202e3297246SEli Cohen return err; 203e3297246SEli Cohen } 204e3297246SEli Cohen 205012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 206012e50e1SHuy Nguyen { 207012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 208012e50e1SHuy Nguyen driver_version); 209012e50e1SHuy Nguyen u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 210012e50e1SHuy Nguyen u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 211012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 212012e50e1SHuy Nguyen char *string; 213012e50e1SHuy Nguyen 214012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 215012e50e1SHuy Nguyen return; 216012e50e1SHuy Nguyen 217012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 218012e50e1SHuy Nguyen 219012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 222012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 225012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 226012e50e1SHuy Nguyen 227012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 228012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 229012e50e1SHuy Nguyen 230012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 231012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 232012e50e1SHuy Nguyen 233012e50e1SHuy Nguyen /*Send the command*/ 234012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 235012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 238012e50e1SHuy Nguyen } 239012e50e1SHuy Nguyen 240e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 241e126ba97SEli Cohen { 242e126ba97SEli Cohen int err; 243e126ba97SEli Cohen 244e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 245e126ba97SEli Cohen if (err) { 2461a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 247e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 248e126ba97SEli Cohen if (err) { 2491a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 250e126ba97SEli Cohen return err; 251e126ba97SEli Cohen } 252e126ba97SEli Cohen } 253e126ba97SEli Cohen 254e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 255e126ba97SEli Cohen if (err) { 256e126ba97SEli Cohen dev_warn(&pdev->dev, 2571a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 258e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 259e126ba97SEli Cohen if (err) { 260e126ba97SEli Cohen dev_err(&pdev->dev, 2611a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 262e126ba97SEli Cohen return err; 263e126ba97SEli Cohen } 264e126ba97SEli Cohen } 265e126ba97SEli Cohen 266e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 267e126ba97SEli Cohen return err; 268e126ba97SEli Cohen } 269e126ba97SEli Cohen 27089d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27189d44f0aSMajd Dibbiny { 27289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27389d44f0aSMajd Dibbiny int err = 0; 27489d44f0aSMajd Dibbiny 27589d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27689d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27789d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27889d44f0aSMajd Dibbiny if (!err) 27989d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28089d44f0aSMajd Dibbiny } 28189d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28289d44f0aSMajd Dibbiny 28389d44f0aSMajd Dibbiny return err; 28489d44f0aSMajd Dibbiny } 28589d44f0aSMajd Dibbiny 28689d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28789d44f0aSMajd Dibbiny { 28889d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28989d44f0aSMajd Dibbiny 29089d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29189d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29289d44f0aSMajd Dibbiny pci_disable_device(pdev); 29389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29489d44f0aSMajd Dibbiny } 29589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29689d44f0aSMajd Dibbiny } 29789d44f0aSMajd Dibbiny 298e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 299e126ba97SEli Cohen { 300e126ba97SEli Cohen int err = 0; 301e126ba97SEli Cohen 302e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3031a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 304e126ba97SEli Cohen return -ENODEV; 305e126ba97SEli Cohen } 306e126ba97SEli Cohen 307e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 308e126ba97SEli Cohen if (err) 309e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 310e126ba97SEli Cohen 311e126ba97SEli Cohen return err; 312e126ba97SEli Cohen } 313e126ba97SEli Cohen 314e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 315e126ba97SEli Cohen { 316e126ba97SEli Cohen pci_release_regions(pdev); 317e126ba97SEli Cohen } 318e126ba97SEli Cohen 319bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 320e126ba97SEli Cohen u8 he; 321e126ba97SEli Cohen u8 rsvd[15]; 322e126ba97SEli Cohen }; 323e126ba97SEli Cohen 32487b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32587b8de49SEli Cohen 32687b8de49SEli Cohen enum { 32787b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 328c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 32987b8de49SEli Cohen }; 33087b8de49SEli Cohen 3312974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 332c7a08ac7SEli Cohen { 333c7a08ac7SEli Cohen switch (size) { 334c7a08ac7SEli Cohen case 128: 335c7a08ac7SEli Cohen return 0; 336c7a08ac7SEli Cohen case 256: 337c7a08ac7SEli Cohen return 1; 338c7a08ac7SEli Cohen case 512: 339c7a08ac7SEli Cohen return 2; 340c7a08ac7SEli Cohen case 1024: 341c7a08ac7SEli Cohen return 3; 342c7a08ac7SEli Cohen case 2048: 343c7a08ac7SEli Cohen return 4; 344c7a08ac7SEli Cohen case 4096: 345c7a08ac7SEli Cohen return 5; 346c7a08ac7SEli Cohen default: 3472974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 348c7a08ac7SEli Cohen return 0; 349c7a08ac7SEli Cohen } 350c7a08ac7SEli Cohen } 351c7a08ac7SEli Cohen 352b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 353b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 354938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 355c7a08ac7SEli Cohen { 356b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 357b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 358938fe83cSSaeed Mahameed void *out, *hca_caps; 359938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 360c7a08ac7SEli Cohen int err; 361c7a08ac7SEli Cohen 362b775516bSEli Cohen memset(in, 0, sizeof(in)); 363b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 364c7a08ac7SEli Cohen if (!out) 365c7a08ac7SEli Cohen return -ENOMEM; 366938fe83cSSaeed Mahameed 367b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 368b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 369b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 370c7a08ac7SEli Cohen if (err) { 371938fe83cSSaeed Mahameed mlx5_core_warn(dev, 372938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 373938fe83cSSaeed Mahameed cap_type, cap_mode, err); 374c7a08ac7SEli Cohen goto query_ex; 375c7a08ac7SEli Cohen } 376c7a08ac7SEli Cohen 377938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 378938fe83cSSaeed Mahameed 379938fe83cSSaeed Mahameed switch (cap_mode) { 380938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 381701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 382938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 383938fe83cSSaeed Mahameed break; 384938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 385701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 386938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 387938fe83cSSaeed Mahameed break; 388938fe83cSSaeed Mahameed default: 389938fe83cSSaeed Mahameed mlx5_core_warn(dev, 390938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 391938fe83cSSaeed Mahameed cap_type, cap_mode); 392938fe83cSSaeed Mahameed err = -EINVAL; 393938fe83cSSaeed Mahameed break; 394938fe83cSSaeed Mahameed } 395c7a08ac7SEli Cohen query_ex: 396c7a08ac7SEli Cohen kfree(out); 397c7a08ac7SEli Cohen return err; 398c7a08ac7SEli Cohen } 399c7a08ac7SEli Cohen 400b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 401b06e7de8SLeon Romanovsky { 402b06e7de8SLeon Romanovsky int ret; 403b06e7de8SLeon Romanovsky 404b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 405b06e7de8SLeon Romanovsky if (ret) 406b06e7de8SLeon Romanovsky return ret; 407b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 408b06e7de8SLeon Romanovsky } 409b06e7de8SLeon Romanovsky 410f91e6d89SEran Ben Elisha static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 411c7a08ac7SEli Cohen { 412c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 413c7a08ac7SEli Cohen 414b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 415f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 416c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 417c7a08ac7SEli Cohen } 41887b8de49SEli Cohen 419f91e6d89SEran Ben Elisha static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 420f91e6d89SEran Ben Elisha { 421f91e6d89SEran Ben Elisha void *set_ctx; 422f91e6d89SEran Ben Elisha void *set_hca_cap; 423f91e6d89SEran Ben Elisha int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 424f91e6d89SEran Ben Elisha int req_endianness; 425f91e6d89SEran Ben Elisha int err; 426f91e6d89SEran Ben Elisha 427f91e6d89SEran Ben Elisha if (MLX5_CAP_GEN(dev, atomic)) { 428b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 429f91e6d89SEran Ben Elisha if (err) 430f91e6d89SEran Ben Elisha return err; 431f91e6d89SEran Ben Elisha } else { 432f91e6d89SEran Ben Elisha return 0; 433f91e6d89SEran Ben Elisha } 434f91e6d89SEran Ben Elisha 435f91e6d89SEran Ben Elisha req_endianness = 436f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 437bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 438f91e6d89SEran Ben Elisha 439f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 440f91e6d89SEran Ben Elisha return 0; 441f91e6d89SEran Ben Elisha 442f91e6d89SEran Ben Elisha set_ctx = kzalloc(set_sz, GFP_KERNEL); 443f91e6d89SEran Ben Elisha if (!set_ctx) 444f91e6d89SEran Ben Elisha return -ENOMEM; 445f91e6d89SEran Ben Elisha 446f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 447f91e6d89SEran Ben Elisha 448f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 449bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 450f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 451f91e6d89SEran Ben Elisha 452f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 453f91e6d89SEran Ben Elisha 454f91e6d89SEran Ben Elisha kfree(set_ctx); 455f91e6d89SEran Ben Elisha return err; 456f91e6d89SEran Ben Elisha } 457f91e6d89SEran Ben Elisha 45846861e3eSMoni Shoua static int handle_hca_cap_odp(struct mlx5_core_dev *dev) 45946861e3eSMoni Shoua { 46046861e3eSMoni Shoua void *set_hca_cap; 461224d71ccSLeon Romanovsky void *set_ctx; 462224d71ccSLeon Romanovsky int set_sz; 463fca22e7eSMoni Shoua bool do_set = false; 46446861e3eSMoni Shoua int err; 46546861e3eSMoni Shoua 46637b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46737b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46846861e3eSMoni Shoua return 0; 46946861e3eSMoni Shoua 47046861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 47146861e3eSMoni Shoua if (err) 47246861e3eSMoni Shoua return err; 47346861e3eSMoni Shoua 474224d71ccSLeon Romanovsky set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 47546861e3eSMoni Shoua set_ctx = kzalloc(set_sz, GFP_KERNEL); 47646861e3eSMoni Shoua if (!set_ctx) 47746861e3eSMoni Shoua return -ENOMEM; 47846861e3eSMoni Shoua 47946861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 48046861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 48146861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 48246861e3eSMoni Shoua 483fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 484fca22e7eSMoni Shoua do { \ 485fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 486fca22e7eSMoni Shoua if (_res) { \ 487fca22e7eSMoni Shoua do_set = true; \ 488fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 489fca22e7eSMoni Shoua } \ 490fca22e7eSMoni Shoua } while (0) 49146861e3eSMoni Shoua 492fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 493fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 494fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 495fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 496fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 497fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 498fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 499fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 50000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 50100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 50200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 50300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 50400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 50500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 50646861e3eSMoni Shoua 507fca22e7eSMoni Shoua if (do_set) 508fca22e7eSMoni Shoua err = set_caps(dev, set_ctx, set_sz, 509fca22e7eSMoni Shoua MLX5_SET_HCA_CAP_OP_MOD_ODP); 51046861e3eSMoni Shoua 51146861e3eSMoni Shoua kfree(set_ctx); 512fca22e7eSMoni Shoua 51346861e3eSMoni Shoua return err; 51446861e3eSMoni Shoua } 51546861e3eSMoni Shoua 516e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 517e126ba97SEli Cohen { 518b775516bSEli Cohen void *set_ctx = NULL; 519c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 520c7a08ac7SEli Cohen int err = -ENOMEM; 521b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 522938fe83cSSaeed Mahameed void *set_hca_cap; 523e126ba97SEli Cohen 524b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 525c7a08ac7SEli Cohen if (!set_ctx) 526e126ba97SEli Cohen goto query_ex; 527e126ba97SEli Cohen 528b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 529c7a08ac7SEli Cohen if (err) 530e126ba97SEli Cohen goto query_ex; 531e126ba97SEli Cohen 532938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 533938fe83cSSaeed Mahameed capability); 534701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 535938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 536938fe83cSSaeed Mahameed 537938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 538707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 539938fe83cSSaeed Mahameed 128); 540c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 541938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5422974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 543e126ba97SEli Cohen 544883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 545883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 546883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 547883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 548883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 549883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 550883371c4SNoa Osherovich } 551c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 552938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 553938fe83cSSaeed Mahameed prof->log_max_qp); 554e126ba97SEli Cohen 555938fe83cSSaeed Mahameed /* disable cmdif checksum */ 556938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 557c1868b82SEli Cohen 55891828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 55991828bd8SMajd Dibbiny * than 4K. 56091828bd8SMajd Dibbiny */ 56191828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 562f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 563f502d834SEli Cohen 564fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 565fe1e1876SCarol L Soto 566f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 567f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 568f32f5bd2SDaniel Jurgens set_hca_cap, 569f32f5bd2SDaniel Jurgens cache_line_128byte, 570c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 571f32f5bd2SDaniel Jurgens 572dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 573dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 574dd44572aSMoni Shoua 575c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 576c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 577c4b76d8dSDaniel Jurgens set_hca_cap, 578c4b76d8dSDaniel Jurgens num_vhca_ports, 579c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 580c4b76d8dSDaniel Jurgens 581f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, 582f91e6d89SEran Ben Elisha MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 583e126ba97SEli Cohen 584e126ba97SEli Cohen query_ex: 585e126ba97SEli Cohen kfree(set_ctx); 586e126ba97SEli Cohen return err; 587e126ba97SEli Cohen } 588e126ba97SEli Cohen 58937b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 59037b6bb77SLeon Romanovsky { 59137b6bb77SLeon Romanovsky int err; 59237b6bb77SLeon Romanovsky 59337b6bb77SLeon Romanovsky err = handle_hca_cap(dev); 59437b6bb77SLeon Romanovsky if (err) { 59598a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 59637b6bb77SLeon Romanovsky goto out; 59737b6bb77SLeon Romanovsky } 59837b6bb77SLeon Romanovsky 59937b6bb77SLeon Romanovsky err = handle_hca_cap_atomic(dev); 60037b6bb77SLeon Romanovsky if (err) { 60198a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 60237b6bb77SLeon Romanovsky goto out; 60337b6bb77SLeon Romanovsky } 60437b6bb77SLeon Romanovsky 60537b6bb77SLeon Romanovsky err = handle_hca_cap_odp(dev); 60637b6bb77SLeon Romanovsky if (err) { 60798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 60837b6bb77SLeon Romanovsky goto out; 60937b6bb77SLeon Romanovsky } 61037b6bb77SLeon Romanovsky 61137b6bb77SLeon Romanovsky out: 61237b6bb77SLeon Romanovsky return err; 61337b6bb77SLeon Romanovsky } 61437b6bb77SLeon Romanovsky 615e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 616e126ba97SEli Cohen { 617bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 618bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 619e126ba97SEli Cohen int err; 620e126ba97SEli Cohen 621fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 622fc50db98SEli Cohen return 0; 623fc50db98SEli Cohen 624e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 625e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 626e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 627e126ba97SEli Cohen &he_out, sizeof(he_out), 628e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 629e126ba97SEli Cohen return err; 630e126ba97SEli Cohen } 631e126ba97SEli Cohen 632c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 633c85023e1SHuy Nguyen { 634c85023e1SHuy Nguyen int ret = 0; 635c85023e1SHuy Nguyen 636c85023e1SHuy Nguyen /* Disable local_lb by default */ 6378978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 638c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 639c85023e1SHuy Nguyen 640c85023e1SHuy Nguyen return ret; 641c85023e1SHuy Nguyen } 642c85023e1SHuy Nguyen 6430b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 644cd23b14bSEli Cohen { 645c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 646c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 647cd23b14bSEli Cohen 6480b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6490b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 65022e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 65122e939a9SBodong Wang dev->caps.embedded_cpu); 652c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 653cd23b14bSEli Cohen } 654cd23b14bSEli Cohen 6550b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 656cd23b14bSEli Cohen { 657c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 658c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 659cd23b14bSEli Cohen 6600b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6610b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 66222e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 66322e939a9SBodong Wang dev->caps.embedded_cpu); 664c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 665cd23b14bSEli Cohen } 666cd23b14bSEli Cohen 6674a0475d5SMiroslav Lichvar u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 6684a0475d5SMiroslav Lichvar struct ptp_system_timestamp *sts) 669b0844444SEran Ben Elisha { 670b0844444SEran Ben Elisha u32 timer_h, timer_h1, timer_l; 671b0844444SEran Ben Elisha 672b0844444SEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 6734a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 674b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6754a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 676b0844444SEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 6774a0475d5SMiroslav Lichvar if (timer_h != timer_h1) { 6784a0475d5SMiroslav Lichvar /* wrap around */ 6794a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 680b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6814a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 6824a0475d5SMiroslav Lichvar } 683b0844444SEran Ben Elisha 684a5a1d1c2SThomas Gleixner return (u64)timer_l | (u64)timer_h1 << 32; 685b0844444SEran Ben Elisha } 686b0844444SEran Ben Elisha 687f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 688f62b8bb8SAmir Vadai { 689c4f287c4SSaeed Mahameed u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 690c4f287c4SSaeed Mahameed u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 691f62b8bb8SAmir Vadai u32 sup_issi; 692c4f287c4SSaeed Mahameed int err; 693f62b8bb8SAmir Vadai 694f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 695c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 696f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 697f62b8bb8SAmir Vadai if (err) { 698c4f287c4SSaeed Mahameed u32 syndrome; 699c4f287c4SSaeed Mahameed u8 status; 700c4f287c4SSaeed Mahameed 701c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 702f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 703f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 704f9c14e46SKamal Heib err, status, syndrome); 705f9c14e46SKamal Heib return err; 706f62b8bb8SAmir Vadai } 707f62b8bb8SAmir Vadai 708f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 709f9c14e46SKamal Heib dev->issi = 0; 710f9c14e46SKamal Heib return 0; 711f62b8bb8SAmir Vadai } 712f62b8bb8SAmir Vadai 713f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 714f62b8bb8SAmir Vadai 715f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 716c4f287c4SSaeed Mahameed u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 717c4f287c4SSaeed Mahameed u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 718f62b8bb8SAmir Vadai 719f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 720f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 721c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 722f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 723f62b8bb8SAmir Vadai if (err) { 724f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 725f9c14e46SKamal Heib err); 726f62b8bb8SAmir Vadai return err; 727f62b8bb8SAmir Vadai } 728f62b8bb8SAmir Vadai 729f62b8bb8SAmir Vadai dev->issi = 1; 730f62b8bb8SAmir Vadai 731f62b8bb8SAmir Vadai return 0; 732e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 733f62b8bb8SAmir Vadai return 0; 734f62b8bb8SAmir Vadai } 735f62b8bb8SAmir Vadai 7369eb78923SOr Gerlitz return -EOPNOTSUPP; 737f62b8bb8SAmir Vadai } 738f62b8bb8SAmir Vadai 73911f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 74011f3b84dSSaeed Mahameed const struct pci_device_id *id) 741a31208b1SMajd Dibbiny { 742868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 743a31208b1SMajd Dibbiny int err = 0; 744a31208b1SMajd Dibbiny 745d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 746e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 747e126ba97SEli Cohen 748aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 749311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 750311c7c71SSaeed Mahameed 75189d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 752e126ba97SEli Cohen if (err) { 75398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 75411f3b84dSSaeed Mahameed return err; 755e126ba97SEli Cohen } 756e126ba97SEli Cohen 757e126ba97SEli Cohen err = request_bar(pdev); 758e126ba97SEli Cohen if (err) { 75998a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 760e126ba97SEli Cohen goto err_disable; 761e126ba97SEli Cohen } 762e126ba97SEli Cohen 763e126ba97SEli Cohen pci_set_master(pdev); 764e126ba97SEli Cohen 765e126ba97SEli Cohen err = set_dma_caps(pdev); 766e126ba97SEli Cohen if (err) { 76798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 768e126ba97SEli Cohen goto err_clr_master; 769e126ba97SEli Cohen } 770e126ba97SEli Cohen 771ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 772ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 773ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 774ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 775ce4eee53SMichael Guralnik 776aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 777e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 778e126ba97SEli Cohen if (!dev->iseg) { 779e126ba97SEli Cohen err = -ENOMEM; 78098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 781e126ba97SEli Cohen goto err_clr_master; 782e126ba97SEli Cohen } 783a31208b1SMajd Dibbiny 784b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 785b25bbc2fSAlex Vesker 786a31208b1SMajd Dibbiny return 0; 787a31208b1SMajd Dibbiny 788a31208b1SMajd Dibbiny err_clr_master: 789a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 790a31208b1SMajd Dibbiny release_bar(dev->pdev); 791a31208b1SMajd Dibbiny err_disable: 79289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 793a31208b1SMajd Dibbiny return err; 794a31208b1SMajd Dibbiny } 795a31208b1SMajd Dibbiny 796868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 797a31208b1SMajd Dibbiny { 798a31208b1SMajd Dibbiny iounmap(dev->iseg); 799a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 800a31208b1SMajd Dibbiny release_bar(dev->pdev); 80189d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 802a31208b1SMajd Dibbiny } 803a31208b1SMajd Dibbiny 804868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 80559211bd3SMohamad Haj Yahia { 80659211bd3SMohamad Haj Yahia int err; 80759211bd3SMohamad Haj Yahia 808868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 809868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 81098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 811868bc06bSSaeed Mahameed dev->priv.devcom); 812fadd59fcSAviv Heller 81359211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 81459211bd3SMohamad Haj Yahia if (err) { 81598a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 816fadd59fcSAviv Heller goto err_devcom; 81759211bd3SMohamad Haj Yahia } 81859211bd3SMohamad Haj Yahia 819561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 820561aa15aSYuval Avnery if (err) { 821561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 822561aa15aSYuval Avnery goto err_devcom; 823561aa15aSYuval Avnery } 824561aa15aSYuval Avnery 825f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 82659211bd3SMohamad Haj Yahia if (err) { 82798a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 828561aa15aSYuval Avnery goto err_irq_cleanup; 82959211bd3SMohamad Haj Yahia } 83059211bd3SMohamad Haj Yahia 83169c1280bSSaeed Mahameed err = mlx5_events_init(dev); 83269c1280bSSaeed Mahameed if (err) { 83398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 83469c1280bSSaeed Mahameed goto err_eq_cleanup; 83569c1280bSSaeed Mahameed } 83669c1280bSSaeed Mahameed 8379f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 83859211bd3SMohamad Haj Yahia 83959211bd3SMohamad Haj Yahia mlx5_init_qp_table(dev); 84059211bd3SMohamad Haj Yahia 84152ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 84252ec462eSIlan Tayari 8437c39afb3SFeras Daoud mlx5_init_clock(dev); 8447c39afb3SFeras Daoud 845358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8460ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 847358aa5ceSSaeed Mahameed 84859211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 84959211bd3SMohamad Haj Yahia if (err) { 85098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 85159211bd3SMohamad Haj Yahia goto err_tables_cleanup; 85259211bd3SMohamad Haj Yahia } 85359211bd3SMohamad Haj Yahia 854eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 855eeb66cdbSSaeed Mahameed if (err) { 85698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 857eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 858eeb66cdbSSaeed Mahameed } 859eeb66cdbSSaeed Mahameed 860c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 861c2d6e31aSMohamad Haj Yahia if (err) { 86298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 86386eec50bSBodong Wang goto err_mpfs_cleanup; 86486eec50bSBodong Wang } 86586eec50bSBodong Wang 86686eec50bSBodong Wang err = mlx5_eswitch_init(dev); 86786eec50bSBodong Wang if (err) { 86886eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 86986eec50bSBodong Wang goto err_sriov_cleanup; 870c2d6e31aSMohamad Haj Yahia } 871c2d6e31aSMohamad Haj Yahia 8729410733cSIlan Tayari err = mlx5_fpga_init(dev); 8739410733cSIlan Tayari if (err) { 87498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 87586eec50bSBodong Wang goto err_eswitch_cleanup; 8769410733cSIlan Tayari } 8779410733cSIlan Tayari 878c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 879c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 880c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 881c9b9dcb4SAriel Levkovich 88224406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 88387175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 88412206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 88524406953SFeras Daoud 88659211bd3SMohamad Haj Yahia return 0; 88759211bd3SMohamad Haj Yahia 888c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 889c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 89086eec50bSBodong Wang err_sriov_cleanup: 89186eec50bSBodong Wang mlx5_sriov_cleanup(dev); 892eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 893eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 894c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 895c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 89659211bd3SMohamad Haj Yahia err_tables_cleanup: 8970ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 898358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 89959211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 90002d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 90169c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 90259211bd3SMohamad Haj Yahia err_eq_cleanup: 903f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 904561aa15aSYuval Avnery err_irq_cleanup: 905561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 906fadd59fcSAviv Heller err_devcom: 907fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 90859211bd3SMohamad Haj Yahia 90959211bd3SMohamad Haj Yahia return err; 91059211bd3SMohamad Haj Yahia } 91159211bd3SMohamad Haj Yahia 91259211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 91359211bd3SMohamad Haj Yahia { 91412206b17SAya Levin mlx5_rsc_dump_destroy(dev); 91587175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 91624406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 917c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9189410733cSIlan Tayari mlx5_fpga_cleanup(dev); 919c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 92086eec50bSBodong Wang mlx5_sriov_cleanup(dev); 921eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 92259211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9230ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 924358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9257c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 92652ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 92759211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 92802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 92969c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 930f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 931561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 932fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 93359211bd3SMohamad Haj Yahia } 93459211bd3SMohamad Haj Yahia 935e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 936a31208b1SMajd Dibbiny { 937a31208b1SMajd Dibbiny int err; 938a31208b1SMajd Dibbiny 93998a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 940e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 941e126ba97SEli Cohen 94200c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 94300c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 94400c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 94500c6bcb0STal Gilboa 9466c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9476c780a02SEli Cohen */ 948b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9496c780a02SEli Cohen if (err) { 95098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9516c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 952e161105eSSaeed Mahameed return err; 9536c780a02SEli Cohen } 9546c780a02SEli Cohen 955e126ba97SEli Cohen err = mlx5_cmd_init(dev); 956e126ba97SEli Cohen if (err) { 95798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 958e161105eSSaeed Mahameed return err; 959e126ba97SEli Cohen } 960e126ba97SEli Cohen 961b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 962e3297246SEli Cohen if (err) { 96398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 964e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 96555378a23SMohamad Haj Yahia goto err_cmd_cleanup; 966e3297246SEli Cohen } 967e3297246SEli Cohen 9680b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 969cd23b14bSEli Cohen if (err) { 97098a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 97159211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 972cd23b14bSEli Cohen } 973cd23b14bSEli Cohen 974f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 975f62b8bb8SAmir Vadai if (err) { 97698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 977f62b8bb8SAmir Vadai goto err_disable_hca; 978f62b8bb8SAmir Vadai } 979f62b8bb8SAmir Vadai 980cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 981cd23b14bSEli Cohen if (err) { 98298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 983cd23b14bSEli Cohen goto err_disable_hca; 984cd23b14bSEli Cohen } 985cd23b14bSEli Cohen 986e126ba97SEli Cohen err = set_hca_ctrl(dev); 987e126ba97SEli Cohen if (err) { 98898a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 989cd23b14bSEli Cohen goto reclaim_boot_pages; 990e126ba97SEli Cohen } 991e126ba97SEli Cohen 99237b6bb77SLeon Romanovsky err = set_hca_cap(dev); 993e126ba97SEli Cohen if (err) { 99498a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 99546861e3eSMoni Shoua goto reclaim_boot_pages; 99646861e3eSMoni Shoua } 99746861e3eSMoni Shoua 998cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 999e126ba97SEli Cohen if (err) { 100098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1001cd23b14bSEli Cohen goto reclaim_boot_pages; 1002e126ba97SEli Cohen } 1003e126ba97SEli Cohen 10048737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1005e126ba97SEli Cohen if (err) { 100698a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10070cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1008e126ba97SEli Cohen } 1009e126ba97SEli Cohen 1010012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1011012e50e1SHuy Nguyen 1012e126ba97SEli Cohen mlx5_start_health_poll(dev); 1013e126ba97SEli Cohen 1014bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1015bba1574cSDaniel Jurgens if (err) { 101698a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1017e161105eSSaeed Mahameed goto stop_health; 1018bba1574cSDaniel Jurgens } 1019bba1574cSDaniel Jurgens 1020e161105eSSaeed Mahameed return 0; 1021e161105eSSaeed Mahameed 1022e161105eSSaeed Mahameed stop_health: 1023e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1024e161105eSSaeed Mahameed reclaim_boot_pages: 1025e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1026e161105eSSaeed Mahameed err_disable_hca: 1027e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1028e161105eSSaeed Mahameed err_cmd_cleanup: 1029e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1030e161105eSSaeed Mahameed 1031e161105eSSaeed Mahameed return err; 1032e161105eSSaeed Mahameed } 1033e161105eSSaeed Mahameed 1034e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1035e161105eSSaeed Mahameed { 1036e161105eSSaeed Mahameed int err; 1037e161105eSSaeed Mahameed 1038e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1039e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1040259bbc57SMaor Gottlieb if (err) { 104198a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1042e161105eSSaeed Mahameed return err; 1043e126ba97SEli Cohen } 1044e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1045e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1046e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1047e161105eSSaeed Mahameed 1048e161105eSSaeed Mahameed return 0; 1049259bbc57SMaor Gottlieb } 1050e126ba97SEli Cohen 1051a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1052e161105eSSaeed Mahameed { 1053e161105eSSaeed Mahameed int err; 1054e161105eSSaeed Mahameed 105501187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 105672f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 105798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 105872f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1059a80d1b68SSaeed Mahameed return err; 1060e126ba97SEli Cohen } 1061e126ba97SEli Cohen 106269c1280bSSaeed Mahameed mlx5_events_start(dev); 10630cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10640cf53c12SSaeed Mahameed 1065e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1066e1706e62SYuval Avnery if (err) { 1067e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1068e1706e62SYuval Avnery goto err_irq_table; 1069e1706e62SYuval Avnery } 1070e1706e62SYuval Avnery 1071c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1072e126ba97SEli Cohen if (err) { 107398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1074c8e21b3bSSaeed Mahameed goto err_eq_table; 1075e126ba97SEli Cohen } 1076e126ba97SEli Cohen 107724406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 107824406953SFeras Daoud if (err) { 107998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 108024406953SFeras Daoud goto err_fw_tracer; 108124406953SFeras Daoud } 108224406953SFeras Daoud 108387175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 108487175120SEran Ben Elisha 108512206b17SAya Levin err = mlx5_rsc_dump_init(dev); 108612206b17SAya Levin if (err) { 108712206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 108812206b17SAya Levin goto err_rsc_dump; 108912206b17SAya Levin } 109012206b17SAya Levin 109104e87170SMatan Barak err = mlx5_fpga_device_start(dev); 109204e87170SMatan Barak if (err) { 109398a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 109404e87170SMatan Barak goto err_fpga_start; 109504e87170SMatan Barak } 109604e87170SMatan Barak 109704e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 109804e87170SMatan Barak if (err) { 109998a8e6fcSHuy Nguyen mlx5_core_err(dev, "IPSec device start failed %d\n", err); 110004e87170SMatan Barak goto err_ipsec_start; 110104e87170SMatan Barak } 110204e87170SMatan Barak 11031ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11041ae17322SIlya Lesokhin if (err) { 110598a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11061ae17322SIlya Lesokhin goto err_tls_start; 11071ae17322SIlya Lesokhin } 11081ae17322SIlya Lesokhin 110986d722adSMaor Gottlieb err = mlx5_init_fs(dev); 111086d722adSMaor Gottlieb if (err) { 111198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 111286d722adSMaor Gottlieb goto err_fs; 111386d722adSMaor Gottlieb } 11141466cc5bSYevgeny Petrilin 1115c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1116c85023e1SHuy Nguyen if (err) { 111798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 111887883929SSaeed Mahameed goto err_sriov; 1119c85023e1SHuy Nguyen } 1120c85023e1SHuy Nguyen 1121c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1122fc50db98SEli Cohen if (err) { 112398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sriov init failed %d\n", err); 1124fc50db98SEli Cohen goto err_sriov; 1125fc50db98SEli Cohen } 1126fc50db98SEli Cohen 112722e939a9SBodong Wang err = mlx5_ec_init(dev); 112822e939a9SBodong Wang if (err) { 112998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 113022e939a9SBodong Wang goto err_ec; 113122e939a9SBodong Wang } 113222e939a9SBodong Wang 1133a80d1b68SSaeed Mahameed return 0; 1134a80d1b68SSaeed Mahameed 1135a80d1b68SSaeed Mahameed err_ec: 1136a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1137a80d1b68SSaeed Mahameed err_sriov: 1138a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1139a80d1b68SSaeed Mahameed err_fs: 1140a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1141a80d1b68SSaeed Mahameed err_tls_start: 1142a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1143a80d1b68SSaeed Mahameed err_ipsec_start: 1144a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1145a80d1b68SSaeed Mahameed err_fpga_start: 114612206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 114712206b17SAya Levin err_rsc_dump: 114887175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1149a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1150a80d1b68SSaeed Mahameed err_fw_tracer: 1151a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1152a80d1b68SSaeed Mahameed err_eq_table: 1153e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1154e1706e62SYuval Avnery err_irq_table: 1155a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1156a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1157a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1158a80d1b68SSaeed Mahameed return err; 1159a80d1b68SSaeed Mahameed } 1160a80d1b68SSaeed Mahameed 1161a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1162a80d1b68SSaeed Mahameed { 1163a80d1b68SSaeed Mahameed mlx5_ec_cleanup(dev); 1164a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1165a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1166a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1167a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1168a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 116912206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 117087175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1171a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1172a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1173e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1174a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1175a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1176a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1177a80d1b68SSaeed Mahameed } 1178a80d1b68SSaeed Mahameed 11794383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1180a80d1b68SSaeed Mahameed { 1181a80d1b68SSaeed Mahameed int err = 0; 1182a80d1b68SSaeed Mahameed 1183a80d1b68SSaeed Mahameed dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1184a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1185a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1186a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1187a80d1b68SSaeed Mahameed goto out; 1188a80d1b68SSaeed Mahameed } 1189a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1190a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1191a80d1b68SSaeed Mahameed 1192a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1193a80d1b68SSaeed Mahameed if (err) 1194a80d1b68SSaeed Mahameed goto out; 1195a80d1b68SSaeed Mahameed 1196a80d1b68SSaeed Mahameed if (boot) { 1197a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1198a80d1b68SSaeed Mahameed if (err) { 119998a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1200a80d1b68SSaeed Mahameed goto function_teardown; 1201a80d1b68SSaeed Mahameed } 1202a80d1b68SSaeed Mahameed } 1203a80d1b68SSaeed Mahameed 1204a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1205a80d1b68SSaeed Mahameed if (err) 1206a80d1b68SSaeed Mahameed goto err_load; 1207a80d1b68SSaeed Mahameed 1208a6f3b623SMichael Guralnik if (boot) { 1209a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1210a6f3b623SMichael Guralnik if (err) 1211a6f3b623SMichael Guralnik goto err_devlink_reg; 1212a6f3b623SMichael Guralnik } 1213a6f3b623SMichael Guralnik 1214ecd01db8SParav Pandit if (mlx5_device_registered(dev)) 1215737a234bSMohamad Haj Yahia mlx5_attach_device(dev); 1216ecd01db8SParav Pandit else 1217ecd01db8SParav Pandit mlx5_register_device(dev); 1218a31208b1SMajd Dibbiny 12195fc7197dSMajd Dibbiny set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 122089d44f0aSMajd Dibbiny out: 122189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 122289d44f0aSMajd Dibbiny 1223a80d1b68SSaeed Mahameed return err; 1224e126ba97SEli Cohen 1225a6f3b623SMichael Guralnik err_devlink_reg: 1226a80d1b68SSaeed Mahameed mlx5_unload(dev); 1227a80d1b68SSaeed Mahameed err_load: 122859211bd3SMohamad Haj Yahia if (boot) 122959211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1230e161105eSSaeed Mahameed function_teardown: 1231e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 123289d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 123389d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 123489d44f0aSMajd Dibbiny 1235e126ba97SEli Cohen return err; 1236e126ba97SEli Cohen } 1237e126ba97SEli Cohen 1238f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1239e126ba97SEli Cohen { 12400000a5f2SParav Pandit if (cleanup) { 12410000a5f2SParav Pandit mlx5_unregister_device(dev); 124263cbc552SFeras Daoud mlx5_drain_health_wq(dev); 12430000a5f2SParav Pandit } 1244689a248dSDaniel Jurgens 124589d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 1246b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 124798a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 124889d44f0aSMajd Dibbiny __func__); 124959211bd3SMohamad Haj Yahia if (cleanup) 125059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 125189d44f0aSMajd Dibbiny goto out; 125289d44f0aSMajd Dibbiny } 12536b6adee3SMohamad Haj Yahia 12549ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12559ade8c7cSIlan Tayari 1256737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) 1257737a234bSMohamad Haj Yahia mlx5_detach_device(dev); 1258737a234bSMohamad Haj Yahia 1259a80d1b68SSaeed Mahameed mlx5_unload(dev); 1260a80d1b68SSaeed Mahameed 126159211bd3SMohamad Haj Yahia if (cleanup) 126259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12630cf53c12SSaeed Mahameed 1264e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1265ac6ea6e8SEli Cohen out: 126689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 12679603b61dSJack Morgenstein } 126864613d94SSaeed Mahameed 126927b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12709603b61dSJack Morgenstein { 127111f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12729603b61dSJack Morgenstein int err; 12739603b61dSJack Morgenstein 127411f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12759603b61dSJack Morgenstein 1276364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1277364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 127889d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1279d9aaed83SArtemy Kovalyov 128001187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 128101187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 128201187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 128301187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 128401187175SEli Cohen 128511f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 128611f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 128711f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 128811f3b84dSSaeed Mahameed spin_lock_init(&priv->mkey_lock); 128911f3b84dSSaeed Mahameed 129027b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 129127b942fbSParav Pandit mlx5_debugfs_root); 129211f3b84dSSaeed Mahameed if (!priv->dbg_root) { 129327b942fbSParav Pandit dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 129411f3b84dSSaeed Mahameed return -ENOMEM; 12959603b61dSJack Morgenstein } 12969603b61dSJack Morgenstein 1297ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 129852c368dcSSaeed Mahameed if (err) 129952c368dcSSaeed Mahameed goto err_health_init; 1300ac6ea6e8SEli Cohen 13010cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 13020cf53c12SSaeed Mahameed if (err) 13030cf53c12SSaeed Mahameed goto err_pagealloc_init; 130459211bd3SMohamad Haj Yahia 130511f3b84dSSaeed Mahameed return 0; 130652c368dcSSaeed Mahameed 130752c368dcSSaeed Mahameed err_pagealloc_init: 130852c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 130952c368dcSSaeed Mahameed err_health_init: 131052c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 131152c368dcSSaeed Mahameed 131252c368dcSSaeed Mahameed return err; 131311f3b84dSSaeed Mahameed } 131411f3b84dSSaeed Mahameed 131511f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 131611f3b84dSSaeed Mahameed { 131752c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 131852c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 131911f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 132011f3b84dSSaeed Mahameed } 132111f3b84dSSaeed Mahameed 132211f3b84dSSaeed Mahameed #define MLX5_IB_MOD "mlx5_ib" 132311f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 132411f3b84dSSaeed Mahameed { 132511f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 132611f3b84dSSaeed Mahameed struct devlink *devlink; 132711f3b84dSSaeed Mahameed int err; 132811f3b84dSSaeed Mahameed 13291f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 133011f3b84dSSaeed Mahameed if (!devlink) { 13311f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 133211f3b84dSSaeed Mahameed return -ENOMEM; 133311f3b84dSSaeed Mahameed } 133411f3b84dSSaeed Mahameed 133511f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 133627b942fbSParav Pandit dev->device = &pdev->dev; 133727b942fbSParav Pandit dev->pdev = pdev; 133811f3b84dSSaeed Mahameed 1339386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1340386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1341386e75afSHuy Nguyen 134227b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 134311f3b84dSSaeed Mahameed if (err) 134411f3b84dSSaeed Mahameed goto mdev_init_err; 134511f3b84dSSaeed Mahameed 134611f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 13479603b61dSJack Morgenstein if (err) { 134898a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 134998a8e6fcSHuy Nguyen err); 135011f3b84dSSaeed Mahameed goto pci_init_err; 13519603b61dSJack Morgenstein } 13529603b61dSJack Morgenstein 1353868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13549603b61dSJack Morgenstein if (err) { 135598a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 135698a8e6fcSHuy Nguyen err); 13570cf53c12SSaeed Mahameed goto err_load_one; 13589603b61dSJack Morgenstein } 135959211bd3SMohamad Haj Yahia 1360f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 13619603b61dSJack Morgenstein 13628b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13638b9d8baaSAlex Vesker if (err) 13648b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13658b9d8baaSAlex Vesker 13665d47f6c8SDaniel Jurgens pci_save_state(pdev); 13679603b61dSJack Morgenstein return 0; 13689603b61dSJack Morgenstein 13690cf53c12SSaeed Mahameed err_load_one: 1370868bc06bSSaeed Mahameed mlx5_pci_close(dev); 137111f3b84dSSaeed Mahameed pci_init_err: 137211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 137311f3b84dSSaeed Mahameed mdev_init_err: 13741f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1375a31208b1SMajd Dibbiny 13769603b61dSJack Morgenstein return err; 13779603b61dSJack Morgenstein } 1378a31208b1SMajd Dibbiny 13799603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13809603b61dSJack Morgenstein { 13819603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1382feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 13839603b61dSJack Morgenstein 13848b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 13851f28d776SEran Ben Elisha mlx5_devlink_unregister(devlink); 1386737a234bSMohamad Haj Yahia 1387f999b706SParav Pandit mlx5_unload_one(dev, true); 1388868bc06bSSaeed Mahameed mlx5_pci_close(dev); 138911f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 13901f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 13919603b61dSJack Morgenstein } 13929603b61dSJack Morgenstein 139389d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 139489d44f0aSMajd Dibbiny pci_channel_state_t state) 139589d44f0aSMajd Dibbiny { 139689d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 139789d44f0aSMajd Dibbiny 139898a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 139904c0c1abSMohamad Haj Yahia 14008812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 14013e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1402868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 14035e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 140489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 140505ac2c0bSMohamad Haj Yahia 140689d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 140789d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 140889d44f0aSMajd Dibbiny } 140989d44f0aSMajd Dibbiny 1410d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1411d57847dcSDaniel Jurgens * for the health counter to start counting. 141289d44f0aSMajd Dibbiny */ 1413d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 141489d44f0aSMajd Dibbiny { 141589d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 141689d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 141789d44f0aSMajd Dibbiny const int niter = 100; 1418d57847dcSDaniel Jurgens u32 last_count = 0; 141989d44f0aSMajd Dibbiny u32 count; 142089d44f0aSMajd Dibbiny int i; 142189d44f0aSMajd Dibbiny 142289d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 142389d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 142489d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1425d57847dcSDaniel Jurgens if (last_count && last_count != count) { 142698a8e6fcSHuy Nguyen mlx5_core_info(dev, 142798a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 142898a8e6fcSHuy Nguyen count, i); 1429d57847dcSDaniel Jurgens return 0; 1430d57847dcSDaniel Jurgens } 1431d57847dcSDaniel Jurgens last_count = count; 143289d44f0aSMajd Dibbiny } 143389d44f0aSMajd Dibbiny msleep(50); 143489d44f0aSMajd Dibbiny } 143589d44f0aSMajd Dibbiny 1436d57847dcSDaniel Jurgens return -ETIMEDOUT; 143789d44f0aSMajd Dibbiny } 143889d44f0aSMajd Dibbiny 14391061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14401061c90fSMohamad Haj Yahia { 14411061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14421061c90fSMohamad Haj Yahia int err; 14431061c90fSMohamad Haj Yahia 144498a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14451061c90fSMohamad Haj Yahia 14461061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14471061c90fSMohamad Haj Yahia if (err) { 144898a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 144998a8e6fcSHuy Nguyen __func__, err); 14501061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14511061c90fSMohamad Haj Yahia } 14521061c90fSMohamad Haj Yahia 14531061c90fSMohamad Haj Yahia pci_set_master(pdev); 14541061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14555d47f6c8SDaniel Jurgens pci_save_state(pdev); 14561061c90fSMohamad Haj Yahia 14571061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 145898a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14591061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14601061c90fSMohamad Haj Yahia } 14611061c90fSMohamad Haj Yahia 14621061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 14631061c90fSMohamad Haj Yahia } 14641061c90fSMohamad Haj Yahia 146589d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 146689d44f0aSMajd Dibbiny { 146789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 146889d44f0aSMajd Dibbiny int err; 146989d44f0aSMajd Dibbiny 147098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 147189d44f0aSMajd Dibbiny 1472868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 147389d44f0aSMajd Dibbiny if (err) 147498a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 147598a8e6fcSHuy Nguyen __func__, err); 147689d44f0aSMajd Dibbiny else 147798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 147889d44f0aSMajd Dibbiny } 147989d44f0aSMajd Dibbiny 148089d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 148189d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 148289d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 148389d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 148489d44f0aSMajd Dibbiny }; 148589d44f0aSMajd Dibbiny 14868812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 14878812c24dSMajd Dibbiny { 1488fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1489fcd29ad1SFeras Daoud int ret = 1; 14908812c24dSMajd Dibbiny 1491fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1492fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1493fcd29ad1SFeras Daoud 1494fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1495fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1496fcd29ad1SFeras Daoud 1497fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 14988812c24dSMajd Dibbiny return -EOPNOTSUPP; 14998812c24dSMajd Dibbiny 15008812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 15018812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 15028812c24dSMajd Dibbiny return -EAGAIN; 15038812c24dSMajd Dibbiny } 15048812c24dSMajd Dibbiny 1505d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1506d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1507d2aa060dSHuy Nguyen */ 1508d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 150976d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1510d2aa060dSHuy Nguyen 1511fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1512fcd29ad1SFeras Daoud if (!ret) 1513fcd29ad1SFeras Daoud goto succeed; 1514fcd29ad1SFeras Daoud 15158812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1516fcd29ad1SFeras Daoud if (!ret) 1517fcd29ad1SFeras Daoud goto succeed; 1518fcd29ad1SFeras Daoud 15198812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1520d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 15218812c24dSMajd Dibbiny return ret; 15228812c24dSMajd Dibbiny 1523fcd29ad1SFeras Daoud succeed: 15248812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 15258812c24dSMajd Dibbiny 15261ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 15271ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 15281ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 15291ef903bfSDaniel Jurgens * contexts. 15301ef903bfSDaniel Jurgens */ 15311ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 15321ef903bfSDaniel Jurgens 15338812c24dSMajd Dibbiny return 0; 15348812c24dSMajd Dibbiny } 15358812c24dSMajd Dibbiny 15365fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15375fc7197dSMajd Dibbiny { 15385fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15398812c24dSMajd Dibbiny int err; 15405fc7197dSMajd Dibbiny 154198a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15428812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15438812c24dSMajd Dibbiny if (err) 1544868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15455fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15465fc7197dSMajd Dibbiny } 15475fc7197dSMajd Dibbiny 15489603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1549bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1550fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1551bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1552fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1553bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1554fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 15557092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 155664dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1557d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1558d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1559d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1560d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 156185327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 156285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1563b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1564505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 15652e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 15662e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1567d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 15689603b61dSJack Morgenstein { 0, } 15699603b61dSJack Morgenstein }; 15709603b61dSJack Morgenstein 15719603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 15729603b61dSJack Morgenstein 157304c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 157404c0c1abSMohamad Haj Yahia { 1575b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1576b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 157704c0c1abSMohamad Haj Yahia } 157804c0c1abSMohamad Haj Yahia 157904c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 158004c0c1abSMohamad Haj Yahia { 158104c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 158204c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 158304c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 158404c0c1abSMohamad Haj Yahia } 158504c0c1abSMohamad Haj Yahia 15869603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 15879603b61dSJack Morgenstein .name = DRIVER_NAME, 15889603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 15899603b61dSJack Morgenstein .probe = init_one, 159089d44f0aSMajd Dibbiny .remove = remove_one, 15915fc7197dSMajd Dibbiny .shutdown = shutdown, 1592fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1593fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 15949603b61dSJack Morgenstein }; 1595e126ba97SEli Cohen 1596f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1597f663ad98SKamal Heib { 1598f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1599f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1600f663ad98SKamal Heib prof_sel, 1601f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1602f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1603f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1604f663ad98SKamal Heib } 1605f663ad98SKamal Heib } 1606f663ad98SKamal Heib 1607e126ba97SEli Cohen static int __init init(void) 1608e126ba97SEli Cohen { 1609e126ba97SEli Cohen int err; 1610e126ba97SEli Cohen 16118737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 16128737f818SDaniel Jurgens 1613f663ad98SKamal Heib mlx5_core_verify_params(); 1614c778dd31STariq Toukan mlx5_accel_ipsec_build_fs_cmds(); 1615e126ba97SEli Cohen mlx5_register_debugfs(); 1616e126ba97SEli Cohen 16179603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 16189603b61dSJack Morgenstein if (err) 1619ac6ea6e8SEli Cohen goto err_debug; 16209603b61dSJack Morgenstein 1621f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1622f62b8bb8SAmir Vadai mlx5e_init(); 1623f62b8bb8SAmir Vadai #endif 1624f62b8bb8SAmir Vadai 1625e126ba97SEli Cohen return 0; 1626e126ba97SEli Cohen 1627e126ba97SEli Cohen err_debug: 1628e126ba97SEli Cohen mlx5_unregister_debugfs(); 1629e126ba97SEli Cohen return err; 1630e126ba97SEli Cohen } 1631e126ba97SEli Cohen 1632e126ba97SEli Cohen static void __exit cleanup(void) 1633e126ba97SEli Cohen { 1634f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1635f62b8bb8SAmir Vadai mlx5e_cleanup(); 1636f62b8bb8SAmir Vadai #endif 16379603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1638e126ba97SEli Cohen mlx5_unregister_debugfs(); 1639e126ba97SEli Cohen } 1640e126ba97SEli Cohen 1641e126ba97SEli Cohen module_init(init); 1642e126ba97SEli Cohen module_exit(cleanup); 1643