1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/mlx5/srq.h> 47e126ba97SEli Cohen #include <linux/debugfs.h> 48f66f049fSEli Cohen #include <linux/kmod.h> 4989d44f0aSMajd Dibbiny #include <linux/delay.h> 50b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 51e126ba97SEli Cohen #include "mlx5_core.h" 52e126ba97SEli Cohen 53e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 544ae6c18cSAchiad Shochat MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 55e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 56e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 57e126ba97SEli Cohen 58e126ba97SEli Cohen int mlx5_core_debug_mask; 59e126ba97SEli Cohen module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); 60e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 61e126ba97SEli Cohen 629603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 639603b61dSJack Morgenstein static int prof_sel = MLX5_DEFAULT_PROF; 649603b61dSJack Morgenstein module_param_named(prof_sel, prof_sel, int, 0444); 659603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 669603b61dSJack Morgenstein 679603b61dSJack Morgenstein static LIST_HEAD(intf_list); 689603b61dSJack Morgenstein static LIST_HEAD(dev_list); 699603b61dSJack Morgenstein static DEFINE_MUTEX(intf_mutex); 709603b61dSJack Morgenstein 719603b61dSJack Morgenstein struct mlx5_device_context { 729603b61dSJack Morgenstein struct list_head list; 739603b61dSJack Morgenstein struct mlx5_interface *intf; 749603b61dSJack Morgenstein void *context; 759603b61dSJack Morgenstein }; 769603b61dSJack Morgenstein 77f91e6d89SEran Ben Elisha enum { 78f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 79f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 80f91e6d89SEran Ben Elisha }; 81f91e6d89SEran Ben Elisha 829603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 839603b61dSJack Morgenstein [0] = { 849603b61dSJack Morgenstein .mask = 0, 859603b61dSJack Morgenstein }, 869603b61dSJack Morgenstein [1] = { 879603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 889603b61dSJack Morgenstein .log_max_qp = 12, 899603b61dSJack Morgenstein }, 909603b61dSJack Morgenstein [2] = { 919603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 929603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 939603b61dSJack Morgenstein .log_max_qp = 17, 949603b61dSJack Morgenstein .mr_cache[0] = { 959603b61dSJack Morgenstein .size = 500, 969603b61dSJack Morgenstein .limit = 250 979603b61dSJack Morgenstein }, 989603b61dSJack Morgenstein .mr_cache[1] = { 999603b61dSJack Morgenstein .size = 500, 1009603b61dSJack Morgenstein .limit = 250 1019603b61dSJack Morgenstein }, 1029603b61dSJack Morgenstein .mr_cache[2] = { 1039603b61dSJack Morgenstein .size = 500, 1049603b61dSJack Morgenstein .limit = 250 1059603b61dSJack Morgenstein }, 1069603b61dSJack Morgenstein .mr_cache[3] = { 1079603b61dSJack Morgenstein .size = 500, 1089603b61dSJack Morgenstein .limit = 250 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein .mr_cache[4] = { 1119603b61dSJack Morgenstein .size = 500, 1129603b61dSJack Morgenstein .limit = 250 1139603b61dSJack Morgenstein }, 1149603b61dSJack Morgenstein .mr_cache[5] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[6] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[7] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[8] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[9] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[10] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[11] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[12] = { 1439603b61dSJack Morgenstein .size = 64, 1449603b61dSJack Morgenstein .limit = 32 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[13] = { 1479603b61dSJack Morgenstein .size = 32, 1489603b61dSJack Morgenstein .limit = 16 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[14] = { 1519603b61dSJack Morgenstein .size = 16, 1529603b61dSJack Morgenstein .limit = 8 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[15] = { 1559603b61dSJack Morgenstein .size = 8, 1569603b61dSJack Morgenstein .limit = 4 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein }, 1599603b61dSJack Morgenstein }; 160e126ba97SEli Cohen 161e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 162e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 163e3297246SEli Cohen 164e3297246SEli Cohen static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 165e3297246SEli Cohen { 166e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 167e3297246SEli Cohen int err = 0; 168e3297246SEli Cohen 169e3297246SEli Cohen while (fw_initializing(dev)) { 170e3297246SEli Cohen if (time_after(jiffies, end)) { 171e3297246SEli Cohen err = -EBUSY; 172e3297246SEli Cohen break; 173e3297246SEli Cohen } 174e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 175e3297246SEli Cohen } 176e3297246SEli Cohen 177e3297246SEli Cohen return err; 178e3297246SEli Cohen } 179e3297246SEli Cohen 180e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 181e126ba97SEli Cohen { 182e126ba97SEli Cohen int err; 183e126ba97SEli Cohen 184e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 185e126ba97SEli Cohen if (err) { 1861a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 187e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 188e126ba97SEli Cohen if (err) { 1891a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 190e126ba97SEli Cohen return err; 191e126ba97SEli Cohen } 192e126ba97SEli Cohen } 193e126ba97SEli Cohen 194e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 195e126ba97SEli Cohen if (err) { 196e126ba97SEli Cohen dev_warn(&pdev->dev, 1971a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 198e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 199e126ba97SEli Cohen if (err) { 200e126ba97SEli Cohen dev_err(&pdev->dev, 2011a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 202e126ba97SEli Cohen return err; 203e126ba97SEli Cohen } 204e126ba97SEli Cohen } 205e126ba97SEli Cohen 206e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 207e126ba97SEli Cohen return err; 208e126ba97SEli Cohen } 209e126ba97SEli Cohen 21089d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 21189d44f0aSMajd Dibbiny { 21289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 21389d44f0aSMajd Dibbiny int err = 0; 21489d44f0aSMajd Dibbiny 21589d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 21689d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 21789d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 21889d44f0aSMajd Dibbiny if (!err) 21989d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 22089d44f0aSMajd Dibbiny } 22189d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 22289d44f0aSMajd Dibbiny 22389d44f0aSMajd Dibbiny return err; 22489d44f0aSMajd Dibbiny } 22589d44f0aSMajd Dibbiny 22689d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 22789d44f0aSMajd Dibbiny { 22889d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 22989d44f0aSMajd Dibbiny 23089d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 23189d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 23289d44f0aSMajd Dibbiny pci_disable_device(pdev); 23389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 23489d44f0aSMajd Dibbiny } 23589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 23689d44f0aSMajd Dibbiny } 23789d44f0aSMajd Dibbiny 238e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 239e126ba97SEli Cohen { 240e126ba97SEli Cohen int err = 0; 241e126ba97SEli Cohen 242e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2431a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 244e126ba97SEli Cohen return -ENODEV; 245e126ba97SEli Cohen } 246e126ba97SEli Cohen 247e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 248e126ba97SEli Cohen if (err) 249e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 250e126ba97SEli Cohen 251e126ba97SEli Cohen return err; 252e126ba97SEli Cohen } 253e126ba97SEli Cohen 254e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 255e126ba97SEli Cohen { 256e126ba97SEli Cohen pci_release_regions(pdev); 257e126ba97SEli Cohen } 258e126ba97SEli Cohen 259e126ba97SEli Cohen static int mlx5_enable_msix(struct mlx5_core_dev *dev) 260e126ba97SEli Cohen { 261db058a18SSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 262db058a18SSaeed Mahameed struct mlx5_eq_table *table = &priv->eq_table; 263938fe83cSSaeed Mahameed int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 264e126ba97SEli Cohen int nvec; 265e126ba97SEli Cohen int i; 266e126ba97SEli Cohen 267938fe83cSSaeed Mahameed nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + 268938fe83cSSaeed Mahameed MLX5_EQ_VEC_COMP_BASE; 269e126ba97SEli Cohen nvec = min_t(int, nvec, num_eqs); 270e126ba97SEli Cohen if (nvec <= MLX5_EQ_VEC_COMP_BASE) 271e126ba97SEli Cohen return -ENOMEM; 272e126ba97SEli Cohen 273db058a18SSaeed Mahameed priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); 274db058a18SSaeed Mahameed 275db058a18SSaeed Mahameed priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); 276db058a18SSaeed Mahameed if (!priv->msix_arr || !priv->irq_info) 277db058a18SSaeed Mahameed goto err_free_msix; 278e126ba97SEli Cohen 279e126ba97SEli Cohen for (i = 0; i < nvec; i++) 280db058a18SSaeed Mahameed priv->msix_arr[i].entry = i; 281e126ba97SEli Cohen 282db058a18SSaeed Mahameed nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 2833a9e161aSEli Cohen MLX5_EQ_VEC_COMP_BASE + 1, nvec); 284f3c9407bSAlexander Gordeev if (nvec < 0) 285f3c9407bSAlexander Gordeev return nvec; 286e126ba97SEli Cohen 287f3c9407bSAlexander Gordeev table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 288e126ba97SEli Cohen 289e126ba97SEli Cohen return 0; 290db058a18SSaeed Mahameed 291db058a18SSaeed Mahameed err_free_msix: 292db058a18SSaeed Mahameed kfree(priv->irq_info); 293db058a18SSaeed Mahameed kfree(priv->msix_arr); 294db058a18SSaeed Mahameed return -ENOMEM; 295e126ba97SEli Cohen } 296e126ba97SEli Cohen 297e126ba97SEli Cohen static void mlx5_disable_msix(struct mlx5_core_dev *dev) 298e126ba97SEli Cohen { 299db058a18SSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 300e126ba97SEli Cohen 301e126ba97SEli Cohen pci_disable_msix(dev->pdev); 302db058a18SSaeed Mahameed kfree(priv->irq_info); 303db058a18SSaeed Mahameed kfree(priv->msix_arr); 304e126ba97SEli Cohen } 305e126ba97SEli Cohen 306e126ba97SEli Cohen struct mlx5_reg_host_endianess { 307e126ba97SEli Cohen u8 he; 308e126ba97SEli Cohen u8 rsvd[15]; 309e126ba97SEli Cohen }; 310e126ba97SEli Cohen 31187b8de49SEli Cohen 31287b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 31387b8de49SEli Cohen 31487b8de49SEli Cohen enum { 31587b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 316c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 31787b8de49SEli Cohen }; 31887b8de49SEli Cohen 319c7a08ac7SEli Cohen static u16 to_fw_pkey_sz(u32 size) 320c7a08ac7SEli Cohen { 321c7a08ac7SEli Cohen switch (size) { 322c7a08ac7SEli Cohen case 128: 323c7a08ac7SEli Cohen return 0; 324c7a08ac7SEli Cohen case 256: 325c7a08ac7SEli Cohen return 1; 326c7a08ac7SEli Cohen case 512: 327c7a08ac7SEli Cohen return 2; 328c7a08ac7SEli Cohen case 1024: 329c7a08ac7SEli Cohen return 3; 330c7a08ac7SEli Cohen case 2048: 331c7a08ac7SEli Cohen return 4; 332c7a08ac7SEli Cohen case 4096: 333c7a08ac7SEli Cohen return 5; 334c7a08ac7SEli Cohen default: 335c7a08ac7SEli Cohen pr_warn("invalid pkey table size %d\n", size); 336c7a08ac7SEli Cohen return 0; 337c7a08ac7SEli Cohen } 338c7a08ac7SEli Cohen } 339c7a08ac7SEli Cohen 340938fe83cSSaeed Mahameed int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 341938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 342c7a08ac7SEli Cohen { 343b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 344b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 345938fe83cSSaeed Mahameed void *out, *hca_caps; 346938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 347c7a08ac7SEli Cohen int err; 348c7a08ac7SEli Cohen 349b775516bSEli Cohen memset(in, 0, sizeof(in)); 350b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 351c7a08ac7SEli Cohen if (!out) 352c7a08ac7SEli Cohen return -ENOMEM; 353938fe83cSSaeed Mahameed 354b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 355b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 356b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 357b775516bSEli Cohen if (err) 358b775516bSEli Cohen goto query_ex; 359c7a08ac7SEli Cohen 360b775516bSEli Cohen err = mlx5_cmd_status_to_err_v2(out); 361c7a08ac7SEli Cohen if (err) { 362938fe83cSSaeed Mahameed mlx5_core_warn(dev, 363938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 364938fe83cSSaeed Mahameed cap_type, cap_mode, err); 365c7a08ac7SEli Cohen goto query_ex; 366c7a08ac7SEli Cohen } 367c7a08ac7SEli Cohen 368938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 369938fe83cSSaeed Mahameed 370938fe83cSSaeed Mahameed switch (cap_mode) { 371938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 372938fe83cSSaeed Mahameed memcpy(dev->hca_caps_max[cap_type], hca_caps, 373938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 374938fe83cSSaeed Mahameed break; 375938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 376938fe83cSSaeed Mahameed memcpy(dev->hca_caps_cur[cap_type], hca_caps, 377938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 378938fe83cSSaeed Mahameed break; 379938fe83cSSaeed Mahameed default: 380938fe83cSSaeed Mahameed mlx5_core_warn(dev, 381938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 382938fe83cSSaeed Mahameed cap_type, cap_mode); 383938fe83cSSaeed Mahameed err = -EINVAL; 384938fe83cSSaeed Mahameed break; 385938fe83cSSaeed Mahameed } 386c7a08ac7SEli Cohen query_ex: 387c7a08ac7SEli Cohen kfree(out); 388c7a08ac7SEli Cohen return err; 389c7a08ac7SEli Cohen } 390c7a08ac7SEli Cohen 391f91e6d89SEran Ben Elisha static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 392c7a08ac7SEli Cohen { 393b775516bSEli Cohen u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)]; 394c7a08ac7SEli Cohen int err; 395c7a08ac7SEli Cohen 396b775516bSEli Cohen memset(out, 0, sizeof(out)); 397c7a08ac7SEli Cohen 398b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 399f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 400b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 401c7a08ac7SEli Cohen if (err) 402c7a08ac7SEli Cohen return err; 403c7a08ac7SEli Cohen 404b775516bSEli Cohen err = mlx5_cmd_status_to_err_v2(out); 405c7a08ac7SEli Cohen 406c7a08ac7SEli Cohen return err; 407c7a08ac7SEli Cohen } 40887b8de49SEli Cohen 409f91e6d89SEran Ben Elisha static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 410f91e6d89SEran Ben Elisha { 411f91e6d89SEran Ben Elisha void *set_ctx; 412f91e6d89SEran Ben Elisha void *set_hca_cap; 413f91e6d89SEran Ben Elisha int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 414f91e6d89SEran Ben Elisha int req_endianness; 415f91e6d89SEran Ben Elisha int err; 416f91e6d89SEran Ben Elisha 417f91e6d89SEran Ben Elisha if (MLX5_CAP_GEN(dev, atomic)) { 418f91e6d89SEran Ben Elisha err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC, 419f91e6d89SEran Ben Elisha HCA_CAP_OPMOD_GET_CUR); 420f91e6d89SEran Ben Elisha if (err) 421f91e6d89SEran Ben Elisha return err; 422f91e6d89SEran Ben Elisha } else { 423f91e6d89SEran Ben Elisha return 0; 424f91e6d89SEran Ben Elisha } 425f91e6d89SEran Ben Elisha 426f91e6d89SEran Ben Elisha req_endianness = 427f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 428f91e6d89SEran Ben Elisha supported_atomic_req_8B_endianess_mode_1); 429f91e6d89SEran Ben Elisha 430f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 431f91e6d89SEran Ben Elisha return 0; 432f91e6d89SEran Ben Elisha 433f91e6d89SEran Ben Elisha set_ctx = kzalloc(set_sz, GFP_KERNEL); 434f91e6d89SEran Ben Elisha if (!set_ctx) 435f91e6d89SEran Ben Elisha return -ENOMEM; 436f91e6d89SEran Ben Elisha 437f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 438f91e6d89SEran Ben Elisha 439f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 440f91e6d89SEran Ben Elisha MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 441f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 442f91e6d89SEran Ben Elisha 443f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 444f91e6d89SEran Ben Elisha 445f91e6d89SEran Ben Elisha kfree(set_ctx); 446f91e6d89SEran Ben Elisha return err; 447f91e6d89SEran Ben Elisha } 448f91e6d89SEran Ben Elisha 449e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 450e126ba97SEli Cohen { 451b775516bSEli Cohen void *set_ctx = NULL; 452c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 453c7a08ac7SEli Cohen int err = -ENOMEM; 454b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 455938fe83cSSaeed Mahameed void *set_hca_cap; 456e126ba97SEli Cohen 457b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 458c7a08ac7SEli Cohen if (!set_ctx) 459e126ba97SEli Cohen goto query_ex; 460e126ba97SEli Cohen 461938fe83cSSaeed Mahameed err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX); 462e126ba97SEli Cohen if (err) 463e126ba97SEli Cohen goto query_ex; 464e126ba97SEli Cohen 465938fe83cSSaeed Mahameed err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR); 466c7a08ac7SEli Cohen if (err) 467e126ba97SEli Cohen goto query_ex; 468e126ba97SEli Cohen 469938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 470938fe83cSSaeed Mahameed capability); 471938fe83cSSaeed Mahameed memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 472938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 473938fe83cSSaeed Mahameed 474938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 475707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 476938fe83cSSaeed Mahameed 128); 477c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 478938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 479938fe83cSSaeed Mahameed to_fw_pkey_sz(128)); 480e126ba97SEli Cohen 481c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 482938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 483938fe83cSSaeed Mahameed prof->log_max_qp); 484e126ba97SEli Cohen 485938fe83cSSaeed Mahameed /* disable cmdif checksum */ 486938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 487c1868b82SEli Cohen 488fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 489fe1e1876SCarol L Soto 490f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, 491f91e6d89SEran Ben Elisha MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 492e126ba97SEli Cohen 493e126ba97SEli Cohen query_ex: 494e126ba97SEli Cohen kfree(set_ctx); 495e126ba97SEli Cohen return err; 496e126ba97SEli Cohen } 497e126ba97SEli Cohen 498e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 499e126ba97SEli Cohen { 500e126ba97SEli Cohen struct mlx5_reg_host_endianess he_in; 501e126ba97SEli Cohen struct mlx5_reg_host_endianess he_out; 502e126ba97SEli Cohen int err; 503e126ba97SEli Cohen 504e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 505e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 506e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 507e126ba97SEli Cohen &he_out, sizeof(he_out), 508e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 509e126ba97SEli Cohen return err; 510e126ba97SEli Cohen } 511e126ba97SEli Cohen 512cd23b14bSEli Cohen static int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 513cd23b14bSEli Cohen { 514cd23b14bSEli Cohen int err; 515cd23b14bSEli Cohen struct mlx5_enable_hca_mbox_in in; 516cd23b14bSEli Cohen struct mlx5_enable_hca_mbox_out out; 517cd23b14bSEli Cohen 518cd23b14bSEli Cohen memset(&in, 0, sizeof(in)); 519cd23b14bSEli Cohen memset(&out, 0, sizeof(out)); 520cd23b14bSEli Cohen in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA); 521cd23b14bSEli Cohen err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 522cd23b14bSEli Cohen if (err) 523cd23b14bSEli Cohen return err; 524cd23b14bSEli Cohen 525cd23b14bSEli Cohen if (out.hdr.status) 526cd23b14bSEli Cohen return mlx5_cmd_status_to_err(&out.hdr); 527cd23b14bSEli Cohen 528cd23b14bSEli Cohen return 0; 529cd23b14bSEli Cohen } 530cd23b14bSEli Cohen 531cd23b14bSEli Cohen static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 532cd23b14bSEli Cohen { 533cd23b14bSEli Cohen int err; 534cd23b14bSEli Cohen struct mlx5_disable_hca_mbox_in in; 535cd23b14bSEli Cohen struct mlx5_disable_hca_mbox_out out; 536cd23b14bSEli Cohen 537cd23b14bSEli Cohen memset(&in, 0, sizeof(in)); 538cd23b14bSEli Cohen memset(&out, 0, sizeof(out)); 539cd23b14bSEli Cohen in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA); 540cd23b14bSEli Cohen err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 541cd23b14bSEli Cohen if (err) 542cd23b14bSEli Cohen return err; 543cd23b14bSEli Cohen 544cd23b14bSEli Cohen if (out.hdr.status) 545cd23b14bSEli Cohen return mlx5_cmd_status_to_err(&out.hdr); 546cd23b14bSEli Cohen 547cd23b14bSEli Cohen return 0; 548cd23b14bSEli Cohen } 549cd23b14bSEli Cohen 550db058a18SSaeed Mahameed static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) 551db058a18SSaeed Mahameed { 552db058a18SSaeed Mahameed struct mlx5_priv *priv = &mdev->priv; 553db058a18SSaeed Mahameed struct msix_entry *msix = priv->msix_arr; 554db058a18SSaeed Mahameed int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; 555311c7c71SSaeed Mahameed int numa_node = priv->numa_node; 556db058a18SSaeed Mahameed int err; 557db058a18SSaeed Mahameed 558db058a18SSaeed Mahameed if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { 559db058a18SSaeed Mahameed mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); 560db058a18SSaeed Mahameed return -ENOMEM; 561db058a18SSaeed Mahameed } 562db058a18SSaeed Mahameed 563dda922c8SDavid S. Miller cpumask_set_cpu(cpumask_local_spread(i, numa_node), 564dda922c8SDavid S. Miller priv->irq_info[i].mask); 565db058a18SSaeed Mahameed 566db058a18SSaeed Mahameed err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); 567db058a18SSaeed Mahameed if (err) { 568db058a18SSaeed Mahameed mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", 569db058a18SSaeed Mahameed irq); 570db058a18SSaeed Mahameed goto err_clear_mask; 571db058a18SSaeed Mahameed } 572db058a18SSaeed Mahameed 573db058a18SSaeed Mahameed return 0; 574db058a18SSaeed Mahameed 575db058a18SSaeed Mahameed err_clear_mask: 576db058a18SSaeed Mahameed free_cpumask_var(priv->irq_info[i].mask); 577db058a18SSaeed Mahameed return err; 578db058a18SSaeed Mahameed } 579db058a18SSaeed Mahameed 580db058a18SSaeed Mahameed static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) 581db058a18SSaeed Mahameed { 582db058a18SSaeed Mahameed struct mlx5_priv *priv = &mdev->priv; 583db058a18SSaeed Mahameed struct msix_entry *msix = priv->msix_arr; 584db058a18SSaeed Mahameed int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; 585db058a18SSaeed Mahameed 586db058a18SSaeed Mahameed irq_set_affinity_hint(irq, NULL); 587db058a18SSaeed Mahameed free_cpumask_var(priv->irq_info[i].mask); 588db058a18SSaeed Mahameed } 589db058a18SSaeed Mahameed 590db058a18SSaeed Mahameed static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) 591db058a18SSaeed Mahameed { 592db058a18SSaeed Mahameed int err; 593db058a18SSaeed Mahameed int i; 594db058a18SSaeed Mahameed 595db058a18SSaeed Mahameed for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { 596db058a18SSaeed Mahameed err = mlx5_irq_set_affinity_hint(mdev, i); 597db058a18SSaeed Mahameed if (err) 598db058a18SSaeed Mahameed goto err_out; 599db058a18SSaeed Mahameed } 600db058a18SSaeed Mahameed 601db058a18SSaeed Mahameed return 0; 602db058a18SSaeed Mahameed 603db058a18SSaeed Mahameed err_out: 604db058a18SSaeed Mahameed for (i--; i >= 0; i--) 605db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hint(mdev, i); 606db058a18SSaeed Mahameed 607db058a18SSaeed Mahameed return err; 608db058a18SSaeed Mahameed } 609db058a18SSaeed Mahameed 610db058a18SSaeed Mahameed static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) 611db058a18SSaeed Mahameed { 612db058a18SSaeed Mahameed int i; 613db058a18SSaeed Mahameed 614db058a18SSaeed Mahameed for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) 615db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hint(mdev, i); 616db058a18SSaeed Mahameed } 617db058a18SSaeed Mahameed 618233d05d2SSaeed Mahameed int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 619233d05d2SSaeed Mahameed { 620233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 621233d05d2SSaeed Mahameed struct mlx5_eq *eq, *n; 622233d05d2SSaeed Mahameed int err = -ENOENT; 623233d05d2SSaeed Mahameed 624233d05d2SSaeed Mahameed spin_lock(&table->lock); 625233d05d2SSaeed Mahameed list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 626233d05d2SSaeed Mahameed if (eq->index == vector) { 627233d05d2SSaeed Mahameed *eqn = eq->eqn; 628233d05d2SSaeed Mahameed *irqn = eq->irqn; 629233d05d2SSaeed Mahameed err = 0; 630233d05d2SSaeed Mahameed break; 631233d05d2SSaeed Mahameed } 632233d05d2SSaeed Mahameed } 633233d05d2SSaeed Mahameed spin_unlock(&table->lock); 634233d05d2SSaeed Mahameed 635233d05d2SSaeed Mahameed return err; 636233d05d2SSaeed Mahameed } 637233d05d2SSaeed Mahameed EXPORT_SYMBOL(mlx5_vector2eqn); 638233d05d2SSaeed Mahameed 639233d05d2SSaeed Mahameed static void free_comp_eqs(struct mlx5_core_dev *dev) 640233d05d2SSaeed Mahameed { 641233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 642233d05d2SSaeed Mahameed struct mlx5_eq *eq, *n; 643233d05d2SSaeed Mahameed 644233d05d2SSaeed Mahameed spin_lock(&table->lock); 645233d05d2SSaeed Mahameed list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 646233d05d2SSaeed Mahameed list_del(&eq->list); 647233d05d2SSaeed Mahameed spin_unlock(&table->lock); 648233d05d2SSaeed Mahameed if (mlx5_destroy_unmap_eq(dev, eq)) 649233d05d2SSaeed Mahameed mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 650233d05d2SSaeed Mahameed eq->eqn); 651233d05d2SSaeed Mahameed kfree(eq); 652233d05d2SSaeed Mahameed spin_lock(&table->lock); 653233d05d2SSaeed Mahameed } 654233d05d2SSaeed Mahameed spin_unlock(&table->lock); 655233d05d2SSaeed Mahameed } 656233d05d2SSaeed Mahameed 657233d05d2SSaeed Mahameed static int alloc_comp_eqs(struct mlx5_core_dev *dev) 658233d05d2SSaeed Mahameed { 659233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 660db058a18SSaeed Mahameed char name[MLX5_MAX_IRQ_NAME]; 661233d05d2SSaeed Mahameed struct mlx5_eq *eq; 662233d05d2SSaeed Mahameed int ncomp_vec; 663233d05d2SSaeed Mahameed int nent; 664233d05d2SSaeed Mahameed int err; 665233d05d2SSaeed Mahameed int i; 666233d05d2SSaeed Mahameed 667233d05d2SSaeed Mahameed INIT_LIST_HEAD(&table->comp_eqs_list); 668233d05d2SSaeed Mahameed ncomp_vec = table->num_comp_vectors; 669233d05d2SSaeed Mahameed nent = MLX5_COMP_EQ_SIZE; 670233d05d2SSaeed Mahameed for (i = 0; i < ncomp_vec; i++) { 671233d05d2SSaeed Mahameed eq = kzalloc(sizeof(*eq), GFP_KERNEL); 672233d05d2SSaeed Mahameed if (!eq) { 673233d05d2SSaeed Mahameed err = -ENOMEM; 674233d05d2SSaeed Mahameed goto clean; 675233d05d2SSaeed Mahameed } 676233d05d2SSaeed Mahameed 677db058a18SSaeed Mahameed snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 678233d05d2SSaeed Mahameed err = mlx5_create_map_eq(dev, eq, 679233d05d2SSaeed Mahameed i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 680233d05d2SSaeed Mahameed name, &dev->priv.uuari.uars[0]); 681233d05d2SSaeed Mahameed if (err) { 682233d05d2SSaeed Mahameed kfree(eq); 683233d05d2SSaeed Mahameed goto clean; 684233d05d2SSaeed Mahameed } 685233d05d2SSaeed Mahameed mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 686233d05d2SSaeed Mahameed eq->index = i; 687233d05d2SSaeed Mahameed spin_lock(&table->lock); 688233d05d2SSaeed Mahameed list_add_tail(&eq->list, &table->comp_eqs_list); 689233d05d2SSaeed Mahameed spin_unlock(&table->lock); 690233d05d2SSaeed Mahameed } 691233d05d2SSaeed Mahameed 692233d05d2SSaeed Mahameed return 0; 693233d05d2SSaeed Mahameed 694233d05d2SSaeed Mahameed clean: 695233d05d2SSaeed Mahameed free_comp_eqs(dev); 696233d05d2SSaeed Mahameed return err; 697233d05d2SSaeed Mahameed } 698233d05d2SSaeed Mahameed 699f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 700f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 701f62b8bb8SAmir Vadai { 702f62b8bb8SAmir Vadai u32 query_in[MLX5_ST_SZ_DW(query_issi_in)]; 703f62b8bb8SAmir Vadai u32 query_out[MLX5_ST_SZ_DW(query_issi_out)]; 704f62b8bb8SAmir Vadai u32 set_in[MLX5_ST_SZ_DW(set_issi_in)]; 705f62b8bb8SAmir Vadai u32 set_out[MLX5_ST_SZ_DW(set_issi_out)]; 706f62b8bb8SAmir Vadai int err; 707f62b8bb8SAmir Vadai u32 sup_issi; 708f62b8bb8SAmir Vadai 709f62b8bb8SAmir Vadai memset(query_in, 0, sizeof(query_in)); 710f62b8bb8SAmir Vadai memset(query_out, 0, sizeof(query_out)); 711f62b8bb8SAmir Vadai 712f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 713f62b8bb8SAmir Vadai 714f62b8bb8SAmir Vadai err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in), 715f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 716f62b8bb8SAmir Vadai if (err) { 717f62b8bb8SAmir Vadai if (((struct mlx5_outbox_hdr *)query_out)->status == 718f62b8bb8SAmir Vadai MLX5_CMD_STAT_BAD_OP_ERR) { 719f62b8bb8SAmir Vadai pr_debug("Only ISSI 0 is supported\n"); 720f62b8bb8SAmir Vadai return 0; 721f62b8bb8SAmir Vadai } 722f62b8bb8SAmir Vadai 723f62b8bb8SAmir Vadai pr_err("failed to query ISSI\n"); 724f62b8bb8SAmir Vadai return err; 725f62b8bb8SAmir Vadai } 726f62b8bb8SAmir Vadai 727f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 728f62b8bb8SAmir Vadai 729f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 730f62b8bb8SAmir Vadai memset(set_in, 0, sizeof(set_in)); 731f62b8bb8SAmir Vadai memset(set_out, 0, sizeof(set_out)); 732f62b8bb8SAmir Vadai 733f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 734f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 735f62b8bb8SAmir Vadai 736f62b8bb8SAmir Vadai err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in), 737f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 738f62b8bb8SAmir Vadai if (err) { 739f62b8bb8SAmir Vadai pr_err("failed to set ISSI=1\n"); 740f62b8bb8SAmir Vadai return err; 741f62b8bb8SAmir Vadai } 742f62b8bb8SAmir Vadai 743f62b8bb8SAmir Vadai dev->issi = 1; 744f62b8bb8SAmir Vadai 745f62b8bb8SAmir Vadai return 0; 746e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 747f62b8bb8SAmir Vadai return 0; 748f62b8bb8SAmir Vadai } 749f62b8bb8SAmir Vadai 750f62b8bb8SAmir Vadai return -ENOTSUPP; 751f62b8bb8SAmir Vadai } 752f62b8bb8SAmir Vadai #endif 753f62b8bb8SAmir Vadai 75488a85f99SAchiad Shochat static int map_bf_area(struct mlx5_core_dev *dev) 75588a85f99SAchiad Shochat { 75688a85f99SAchiad Shochat resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 75788a85f99SAchiad Shochat resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 75888a85f99SAchiad Shochat 75988a85f99SAchiad Shochat dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 76088a85f99SAchiad Shochat 76188a85f99SAchiad Shochat return dev->priv.bf_mapping ? 0 : -ENOMEM; 76288a85f99SAchiad Shochat } 76388a85f99SAchiad Shochat 76488a85f99SAchiad Shochat static void unmap_bf_area(struct mlx5_core_dev *dev) 76588a85f99SAchiad Shochat { 76688a85f99SAchiad Shochat if (dev->priv.bf_mapping) 76788a85f99SAchiad Shochat io_mapping_free(dev->priv.bf_mapping); 76888a85f99SAchiad Shochat } 76988a85f99SAchiad Shochat 770a31208b1SMajd Dibbiny static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 771a31208b1SMajd Dibbiny { 772a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 773a31208b1SMajd Dibbiny struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 774a31208b1SMajd Dibbiny 775a31208b1SMajd Dibbiny dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL); 776a31208b1SMajd Dibbiny if (!dev_ctx) 777a31208b1SMajd Dibbiny return; 778a31208b1SMajd Dibbiny 779a31208b1SMajd Dibbiny dev_ctx->intf = intf; 780a31208b1SMajd Dibbiny dev_ctx->context = intf->add(dev); 781a31208b1SMajd Dibbiny 782a31208b1SMajd Dibbiny if (dev_ctx->context) { 783a31208b1SMajd Dibbiny spin_lock_irq(&priv->ctx_lock); 784a31208b1SMajd Dibbiny list_add_tail(&dev_ctx->list, &priv->ctx_list); 785a31208b1SMajd Dibbiny spin_unlock_irq(&priv->ctx_lock); 786a31208b1SMajd Dibbiny } else { 787a31208b1SMajd Dibbiny kfree(dev_ctx); 788a31208b1SMajd Dibbiny } 789a31208b1SMajd Dibbiny } 790a31208b1SMajd Dibbiny 791a31208b1SMajd Dibbiny static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 792a31208b1SMajd Dibbiny { 793a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 794a31208b1SMajd Dibbiny struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 795a31208b1SMajd Dibbiny 796a31208b1SMajd Dibbiny list_for_each_entry(dev_ctx, &priv->ctx_list, list) 797a31208b1SMajd Dibbiny if (dev_ctx->intf == intf) { 798a31208b1SMajd Dibbiny spin_lock_irq(&priv->ctx_lock); 799a31208b1SMajd Dibbiny list_del(&dev_ctx->list); 800a31208b1SMajd Dibbiny spin_unlock_irq(&priv->ctx_lock); 801a31208b1SMajd Dibbiny 802a31208b1SMajd Dibbiny intf->remove(dev, dev_ctx->context); 803a31208b1SMajd Dibbiny kfree(dev_ctx); 804a31208b1SMajd Dibbiny return; 805a31208b1SMajd Dibbiny } 806a31208b1SMajd Dibbiny } 807a31208b1SMajd Dibbiny 808a31208b1SMajd Dibbiny static int mlx5_register_device(struct mlx5_core_dev *dev) 809e126ba97SEli Cohen { 810e126ba97SEli Cohen struct mlx5_priv *priv = &dev->priv; 811a31208b1SMajd Dibbiny struct mlx5_interface *intf; 812e126ba97SEli Cohen 813a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 814a31208b1SMajd Dibbiny list_add_tail(&priv->dev_list, &dev_list); 815a31208b1SMajd Dibbiny list_for_each_entry(intf, &intf_list, list) 816a31208b1SMajd Dibbiny mlx5_add_device(intf, priv); 817a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 818a31208b1SMajd Dibbiny 819a31208b1SMajd Dibbiny return 0; 820a31208b1SMajd Dibbiny } 821a31208b1SMajd Dibbiny 822a31208b1SMajd Dibbiny static void mlx5_unregister_device(struct mlx5_core_dev *dev) 823a31208b1SMajd Dibbiny { 824a31208b1SMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 825a31208b1SMajd Dibbiny struct mlx5_interface *intf; 826a31208b1SMajd Dibbiny 827a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 828a31208b1SMajd Dibbiny list_for_each_entry(intf, &intf_list, list) 829a31208b1SMajd Dibbiny mlx5_remove_device(intf, priv); 830a31208b1SMajd Dibbiny list_del(&priv->dev_list); 831a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 832a31208b1SMajd Dibbiny } 833a31208b1SMajd Dibbiny 834a31208b1SMajd Dibbiny int mlx5_register_interface(struct mlx5_interface *intf) 835a31208b1SMajd Dibbiny { 836a31208b1SMajd Dibbiny struct mlx5_priv *priv; 837a31208b1SMajd Dibbiny 838a31208b1SMajd Dibbiny if (!intf->add || !intf->remove) 839a31208b1SMajd Dibbiny return -EINVAL; 840a31208b1SMajd Dibbiny 841a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 842a31208b1SMajd Dibbiny list_add_tail(&intf->list, &intf_list); 843a31208b1SMajd Dibbiny list_for_each_entry(priv, &dev_list, dev_list) 844a31208b1SMajd Dibbiny mlx5_add_device(intf, priv); 845a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 846a31208b1SMajd Dibbiny 847a31208b1SMajd Dibbiny return 0; 848a31208b1SMajd Dibbiny } 849a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_register_interface); 850a31208b1SMajd Dibbiny 851a31208b1SMajd Dibbiny void mlx5_unregister_interface(struct mlx5_interface *intf) 852a31208b1SMajd Dibbiny { 853a31208b1SMajd Dibbiny struct mlx5_priv *priv; 854a31208b1SMajd Dibbiny 855a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 856a31208b1SMajd Dibbiny list_for_each_entry(priv, &dev_list, dev_list) 857a31208b1SMajd Dibbiny mlx5_remove_device(intf, priv); 858a31208b1SMajd Dibbiny list_del(&intf->list); 859a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 860a31208b1SMajd Dibbiny } 861a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_unregister_interface); 862a31208b1SMajd Dibbiny 863a31208b1SMajd Dibbiny void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 864a31208b1SMajd Dibbiny { 865a31208b1SMajd Dibbiny struct mlx5_priv *priv = &mdev->priv; 866a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 867a31208b1SMajd Dibbiny unsigned long flags; 868a31208b1SMajd Dibbiny void *result = NULL; 869a31208b1SMajd Dibbiny 870a31208b1SMajd Dibbiny spin_lock_irqsave(&priv->ctx_lock, flags); 871a31208b1SMajd Dibbiny 872a31208b1SMajd Dibbiny list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 873a31208b1SMajd Dibbiny if ((dev_ctx->intf->protocol == protocol) && 874a31208b1SMajd Dibbiny dev_ctx->intf->get_dev) { 875a31208b1SMajd Dibbiny result = dev_ctx->intf->get_dev(dev_ctx->context); 876a31208b1SMajd Dibbiny break; 877a31208b1SMajd Dibbiny } 878a31208b1SMajd Dibbiny 879a31208b1SMajd Dibbiny spin_unlock_irqrestore(&priv->ctx_lock, flags); 880a31208b1SMajd Dibbiny 881a31208b1SMajd Dibbiny return result; 882a31208b1SMajd Dibbiny } 883a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_get_protocol_dev); 884a31208b1SMajd Dibbiny 885a31208b1SMajd Dibbiny static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 886a31208b1SMajd Dibbiny { 887a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 888a31208b1SMajd Dibbiny int err = 0; 889a31208b1SMajd Dibbiny 890e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 891e126ba97SEli Cohen strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 892e126ba97SEli Cohen priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 893e126ba97SEli Cohen 894e126ba97SEli Cohen mutex_init(&priv->pgdir_mutex); 895e126ba97SEli Cohen INIT_LIST_HEAD(&priv->pgdir_list); 896e126ba97SEli Cohen spin_lock_init(&priv->mkey_lock); 897e126ba97SEli Cohen 898311c7c71SSaeed Mahameed mutex_init(&priv->alloc_mutex); 899311c7c71SSaeed Mahameed 900311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 901311c7c71SSaeed Mahameed 902e126ba97SEli Cohen priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); 903e126ba97SEli Cohen if (!priv->dbg_root) 904e126ba97SEli Cohen return -ENOMEM; 905e126ba97SEli Cohen 90689d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 907e126ba97SEli Cohen if (err) { 9081a91de28SJoe Perches dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 909e126ba97SEli Cohen goto err_dbg; 910e126ba97SEli Cohen } 911e126ba97SEli Cohen 912e126ba97SEli Cohen err = request_bar(pdev); 913e126ba97SEli Cohen if (err) { 9141a91de28SJoe Perches dev_err(&pdev->dev, "error requesting BARs, aborting\n"); 915e126ba97SEli Cohen goto err_disable; 916e126ba97SEli Cohen } 917e126ba97SEli Cohen 918e126ba97SEli Cohen pci_set_master(pdev); 919e126ba97SEli Cohen 920e126ba97SEli Cohen err = set_dma_caps(pdev); 921e126ba97SEli Cohen if (err) { 922e126ba97SEli Cohen dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); 923e126ba97SEli Cohen goto err_clr_master; 924e126ba97SEli Cohen } 925e126ba97SEli Cohen 926e126ba97SEli Cohen dev->iseg_base = pci_resource_start(dev->pdev, 0); 927e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 928e126ba97SEli Cohen if (!dev->iseg) { 929e126ba97SEli Cohen err = -ENOMEM; 930e126ba97SEli Cohen dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); 931e126ba97SEli Cohen goto err_clr_master; 932e126ba97SEli Cohen } 933a31208b1SMajd Dibbiny 934a31208b1SMajd Dibbiny return 0; 935a31208b1SMajd Dibbiny 936a31208b1SMajd Dibbiny err_clr_master: 937a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 938a31208b1SMajd Dibbiny release_bar(dev->pdev); 939a31208b1SMajd Dibbiny err_disable: 94089d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 941a31208b1SMajd Dibbiny 942a31208b1SMajd Dibbiny err_dbg: 943a31208b1SMajd Dibbiny debugfs_remove(priv->dbg_root); 944a31208b1SMajd Dibbiny return err; 945a31208b1SMajd Dibbiny } 946a31208b1SMajd Dibbiny 947a31208b1SMajd Dibbiny static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 948a31208b1SMajd Dibbiny { 949a31208b1SMajd Dibbiny iounmap(dev->iseg); 950a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 951a31208b1SMajd Dibbiny release_bar(dev->pdev); 95289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 953a31208b1SMajd Dibbiny debugfs_remove(priv->dbg_root); 954a31208b1SMajd Dibbiny } 955a31208b1SMajd Dibbiny 956a31208b1SMajd Dibbiny #define MLX5_IB_MOD "mlx5_ib" 957a31208b1SMajd Dibbiny static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 958a31208b1SMajd Dibbiny { 959a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 960a31208b1SMajd Dibbiny int err; 961a31208b1SMajd Dibbiny 96289d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 96389d44f0aSMajd Dibbiny if (dev->interface_state == MLX5_INTERFACE_STATE_UP) { 96489d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 96589d44f0aSMajd Dibbiny __func__); 96689d44f0aSMajd Dibbiny goto out; 96789d44f0aSMajd Dibbiny } 96889d44f0aSMajd Dibbiny 969e126ba97SEli Cohen dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 970e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 971e126ba97SEli Cohen 97289d44f0aSMajd Dibbiny /* on load removing any previous indication of internal error, device is 97389d44f0aSMajd Dibbiny * up 97489d44f0aSMajd Dibbiny */ 97589d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_UP; 97689d44f0aSMajd Dibbiny 977e126ba97SEli Cohen err = mlx5_cmd_init(dev); 978e126ba97SEli Cohen if (err) { 979e126ba97SEli Cohen dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); 98089d44f0aSMajd Dibbiny goto out_err; 981e126ba97SEli Cohen } 982e126ba97SEli Cohen 983e3297246SEli Cohen err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 984e3297246SEli Cohen if (err) { 985e3297246SEli Cohen dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", 986e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 987e3297246SEli Cohen goto out_err; 988e3297246SEli Cohen } 989e3297246SEli Cohen 990e126ba97SEli Cohen mlx5_pagealloc_init(dev); 991cd23b14bSEli Cohen 992cd23b14bSEli Cohen err = mlx5_core_enable_hca(dev); 993cd23b14bSEli Cohen if (err) { 994cd23b14bSEli Cohen dev_err(&pdev->dev, "enable hca failed\n"); 995cd23b14bSEli Cohen goto err_pagealloc_cleanup; 996cd23b14bSEli Cohen } 997cd23b14bSEli Cohen 998f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 999f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1000f62b8bb8SAmir Vadai if (err) { 1001f62b8bb8SAmir Vadai dev_err(&pdev->dev, "failed to set issi\n"); 1002f62b8bb8SAmir Vadai goto err_disable_hca; 1003f62b8bb8SAmir Vadai } 1004f62b8bb8SAmir Vadai #endif 1005f62b8bb8SAmir Vadai 1006cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1007cd23b14bSEli Cohen if (err) { 1008cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate boot pages\n"); 1009cd23b14bSEli Cohen goto err_disable_hca; 1010cd23b14bSEli Cohen } 1011cd23b14bSEli Cohen 1012e126ba97SEli Cohen err = set_hca_ctrl(dev); 1013e126ba97SEli Cohen if (err) { 1014e126ba97SEli Cohen dev_err(&pdev->dev, "set_hca_ctrl failed\n"); 1015cd23b14bSEli Cohen goto reclaim_boot_pages; 1016e126ba97SEli Cohen } 1017e126ba97SEli Cohen 1018e126ba97SEli Cohen err = handle_hca_cap(dev); 1019e126ba97SEli Cohen if (err) { 1020e126ba97SEli Cohen dev_err(&pdev->dev, "handle_hca_cap failed\n"); 1021cd23b14bSEli Cohen goto reclaim_boot_pages; 1022e126ba97SEli Cohen } 1023e126ba97SEli Cohen 1024f91e6d89SEran Ben Elisha err = handle_hca_cap_atomic(dev); 1025f91e6d89SEran Ben Elisha if (err) { 1026f91e6d89SEran Ben Elisha dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); 1027f91e6d89SEran Ben Elisha goto reclaim_boot_pages; 1028f91e6d89SEran Ben Elisha } 1029f91e6d89SEran Ben Elisha 1030cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1031e126ba97SEli Cohen if (err) { 1032cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate init pages\n"); 1033cd23b14bSEli Cohen goto reclaim_boot_pages; 1034e126ba97SEli Cohen } 1035e126ba97SEli Cohen 1036e126ba97SEli Cohen err = mlx5_pagealloc_start(dev); 1037e126ba97SEli Cohen if (err) { 1038e126ba97SEli Cohen dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); 1039cd23b14bSEli Cohen goto reclaim_boot_pages; 1040e126ba97SEli Cohen } 1041e126ba97SEli Cohen 1042e126ba97SEli Cohen err = mlx5_cmd_init_hca(dev); 1043e126ba97SEli Cohen if (err) { 1044e126ba97SEli Cohen dev_err(&pdev->dev, "init hca failed\n"); 1045e126ba97SEli Cohen goto err_pagealloc_stop; 1046e126ba97SEli Cohen } 1047e126ba97SEli Cohen 1048e126ba97SEli Cohen mlx5_start_health_poll(dev); 1049e126ba97SEli Cohen 1050938fe83cSSaeed Mahameed err = mlx5_query_hca_caps(dev); 1051e126ba97SEli Cohen if (err) { 1052e126ba97SEli Cohen dev_err(&pdev->dev, "query hca failed\n"); 1053e126ba97SEli Cohen goto err_stop_poll; 1054e126ba97SEli Cohen } 1055e126ba97SEli Cohen 1056211e6c80SMajd Dibbiny err = mlx5_query_board_id(dev); 1057e126ba97SEli Cohen if (err) { 1058211e6c80SMajd Dibbiny dev_err(&pdev->dev, "query board id failed\n"); 1059e126ba97SEli Cohen goto err_stop_poll; 1060e126ba97SEli Cohen } 1061e126ba97SEli Cohen 1062e126ba97SEli Cohen err = mlx5_enable_msix(dev); 1063e126ba97SEli Cohen if (err) { 1064e126ba97SEli Cohen dev_err(&pdev->dev, "enable msix failed\n"); 1065e126ba97SEli Cohen goto err_stop_poll; 1066e126ba97SEli Cohen } 1067e126ba97SEli Cohen 1068e126ba97SEli Cohen err = mlx5_eq_init(dev); 1069e126ba97SEli Cohen if (err) { 1070e126ba97SEli Cohen dev_err(&pdev->dev, "failed to initialize eq\n"); 1071e126ba97SEli Cohen goto disable_msix; 1072e126ba97SEli Cohen } 1073e126ba97SEli Cohen 1074e126ba97SEli Cohen err = mlx5_alloc_uuars(dev, &priv->uuari); 1075e126ba97SEli Cohen if (err) { 1076e126ba97SEli Cohen dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); 1077e126ba97SEli Cohen goto err_eq_cleanup; 1078e126ba97SEli Cohen } 1079e126ba97SEli Cohen 1080e126ba97SEli Cohen err = mlx5_start_eqs(dev); 1081e126ba97SEli Cohen if (err) { 1082e126ba97SEli Cohen dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); 1083e126ba97SEli Cohen goto err_free_uar; 1084e126ba97SEli Cohen } 1085e126ba97SEli Cohen 1086233d05d2SSaeed Mahameed err = alloc_comp_eqs(dev); 1087233d05d2SSaeed Mahameed if (err) { 1088233d05d2SSaeed Mahameed dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); 1089233d05d2SSaeed Mahameed goto err_stop_eqs; 1090233d05d2SSaeed Mahameed } 1091233d05d2SSaeed Mahameed 109288a85f99SAchiad Shochat if (map_bf_area(dev)) 109388a85f99SAchiad Shochat dev_err(&pdev->dev, "Failed to map blue flame area\n"); 109488a85f99SAchiad Shochat 1095db058a18SSaeed Mahameed err = mlx5_irq_set_affinity_hints(dev); 1096db058a18SSaeed Mahameed if (err) { 1097db058a18SSaeed Mahameed dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); 109888a85f99SAchiad Shochat goto err_unmap_bf_area; 1099db058a18SSaeed Mahameed } 1100db058a18SSaeed Mahameed 1101e126ba97SEli Cohen MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 1102e126ba97SEli Cohen 1103e126ba97SEli Cohen mlx5_init_cq_table(dev); 1104e126ba97SEli Cohen mlx5_init_qp_table(dev); 1105e126ba97SEli Cohen mlx5_init_srq_table(dev); 11063bcdb17aSSagi Grimberg mlx5_init_mr_table(dev); 1107e126ba97SEli Cohen 1108a31208b1SMajd Dibbiny err = mlx5_register_device(dev); 1109a31208b1SMajd Dibbiny if (err) { 1110a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1111a31208b1SMajd Dibbiny goto err_reg_dev; 1112a31208b1SMajd Dibbiny } 1113a31208b1SMajd Dibbiny 1114a31208b1SMajd Dibbiny err = request_module_nowait(MLX5_IB_MOD); 1115a31208b1SMajd Dibbiny if (err) 1116a31208b1SMajd Dibbiny pr_info("failed request module on %s\n", MLX5_IB_MOD); 1117a31208b1SMajd Dibbiny 111889d44f0aSMajd Dibbiny dev->interface_state = MLX5_INTERFACE_STATE_UP; 111989d44f0aSMajd Dibbiny out: 112089d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 112189d44f0aSMajd Dibbiny 1122e126ba97SEli Cohen return 0; 1123e126ba97SEli Cohen 1124a31208b1SMajd Dibbiny err_reg_dev: 1125a31208b1SMajd Dibbiny mlx5_cleanup_mr_table(dev); 1126a31208b1SMajd Dibbiny mlx5_cleanup_srq_table(dev); 1127a31208b1SMajd Dibbiny mlx5_cleanup_qp_table(dev); 1128a31208b1SMajd Dibbiny mlx5_cleanup_cq_table(dev); 1129a31208b1SMajd Dibbiny mlx5_irq_clear_affinity_hints(dev); 1130a31208b1SMajd Dibbiny 113188a85f99SAchiad Shochat err_unmap_bf_area: 113288a85f99SAchiad Shochat unmap_bf_area(dev); 113388a85f99SAchiad Shochat 1134db058a18SSaeed Mahameed free_comp_eqs(dev); 1135db058a18SSaeed Mahameed 1136233d05d2SSaeed Mahameed err_stop_eqs: 1137233d05d2SSaeed Mahameed mlx5_stop_eqs(dev); 1138233d05d2SSaeed Mahameed 1139e126ba97SEli Cohen err_free_uar: 1140e126ba97SEli Cohen mlx5_free_uuars(dev, &priv->uuari); 1141e126ba97SEli Cohen 1142e126ba97SEli Cohen err_eq_cleanup: 1143e126ba97SEli Cohen mlx5_eq_cleanup(dev); 1144e126ba97SEli Cohen 1145e126ba97SEli Cohen disable_msix: 1146e126ba97SEli Cohen mlx5_disable_msix(dev); 1147e126ba97SEli Cohen 1148e126ba97SEli Cohen err_stop_poll: 1149e126ba97SEli Cohen mlx5_stop_health_poll(dev); 11501bde6e30SEli Cohen if (mlx5_cmd_teardown_hca(dev)) { 11511bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 115289d44f0aSMajd Dibbiny goto out_err; 11531bde6e30SEli Cohen } 1154e126ba97SEli Cohen 1155e126ba97SEli Cohen err_pagealloc_stop: 1156e126ba97SEli Cohen mlx5_pagealloc_stop(dev); 1157e126ba97SEli Cohen 1158cd23b14bSEli Cohen reclaim_boot_pages: 1159e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 1160e126ba97SEli Cohen 1161cd23b14bSEli Cohen err_disable_hca: 1162cd23b14bSEli Cohen mlx5_core_disable_hca(dev); 1163cd23b14bSEli Cohen 1164e126ba97SEli Cohen err_pagealloc_cleanup: 1165e126ba97SEli Cohen mlx5_pagealloc_cleanup(dev); 1166e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 1167e126ba97SEli Cohen 116889d44f0aSMajd Dibbiny out_err: 116989d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 117089d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 117189d44f0aSMajd Dibbiny 1172e126ba97SEli Cohen return err; 1173e126ba97SEli Cohen } 1174e126ba97SEli Cohen 1175a31208b1SMajd Dibbiny static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 1176e126ba97SEli Cohen { 117789d44f0aSMajd Dibbiny int err = 0; 1178e126ba97SEli Cohen 117989d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 118089d44f0aSMajd Dibbiny if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) { 118189d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", 118289d44f0aSMajd Dibbiny __func__); 118389d44f0aSMajd Dibbiny goto out; 118489d44f0aSMajd Dibbiny } 1185a31208b1SMajd Dibbiny mlx5_unregister_device(dev); 1186a31208b1SMajd Dibbiny mlx5_cleanup_mr_table(dev); 1187e126ba97SEli Cohen mlx5_cleanup_srq_table(dev); 1188e126ba97SEli Cohen mlx5_cleanup_qp_table(dev); 1189e126ba97SEli Cohen mlx5_cleanup_cq_table(dev); 1190db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hints(dev); 119188a85f99SAchiad Shochat unmap_bf_area(dev); 1192233d05d2SSaeed Mahameed free_comp_eqs(dev); 1193e126ba97SEli Cohen mlx5_stop_eqs(dev); 1194e126ba97SEli Cohen mlx5_free_uuars(dev, &priv->uuari); 1195e126ba97SEli Cohen mlx5_eq_cleanup(dev); 1196e126ba97SEli Cohen mlx5_disable_msix(dev); 1197e126ba97SEli Cohen mlx5_stop_health_poll(dev); 1198ac6ea6e8SEli Cohen err = mlx5_cmd_teardown_hca(dev); 1199ac6ea6e8SEli Cohen if (err) { 12001bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 1201ac6ea6e8SEli Cohen goto out; 12021bde6e30SEli Cohen } 1203e126ba97SEli Cohen mlx5_pagealloc_stop(dev); 1204e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 1205cd23b14bSEli Cohen mlx5_core_disable_hca(dev); 1206e126ba97SEli Cohen mlx5_pagealloc_cleanup(dev); 1207e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 12089603b61dSJack Morgenstein 1209ac6ea6e8SEli Cohen out: 121089d44f0aSMajd Dibbiny dev->interface_state = MLX5_INTERFACE_STATE_DOWN; 121189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1212ac6ea6e8SEli Cohen return err; 12139603b61dSJack Morgenstein } 121464613d94SSaeed Mahameed 121589d44f0aSMajd Dibbiny void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 12164d2f9bbbSJack Morgenstein unsigned long param) 12179603b61dSJack Morgenstein { 12189603b61dSJack Morgenstein struct mlx5_priv *priv = &dev->priv; 12199603b61dSJack Morgenstein struct mlx5_device_context *dev_ctx; 12209603b61dSJack Morgenstein unsigned long flags; 12219603b61dSJack Morgenstein 12229603b61dSJack Morgenstein spin_lock_irqsave(&priv->ctx_lock, flags); 12239603b61dSJack Morgenstein 12249603b61dSJack Morgenstein list_for_each_entry(dev_ctx, &priv->ctx_list, list) 12259603b61dSJack Morgenstein if (dev_ctx->intf->event) 12264d2f9bbbSJack Morgenstein dev_ctx->intf->event(dev, dev_ctx->context, event, param); 12279603b61dSJack Morgenstein 12289603b61dSJack Morgenstein spin_unlock_irqrestore(&priv->ctx_lock, flags); 12299603b61dSJack Morgenstein } 12309603b61dSJack Morgenstein 12319603b61dSJack Morgenstein struct mlx5_core_event_handler { 12329603b61dSJack Morgenstein void (*event)(struct mlx5_core_dev *dev, 12339603b61dSJack Morgenstein enum mlx5_dev_event event, 12349603b61dSJack Morgenstein void *data); 12359603b61dSJack Morgenstein }; 12369603b61dSJack Morgenstein 1237f66f049fSEli Cohen 12389603b61dSJack Morgenstein static int init_one(struct pci_dev *pdev, 12399603b61dSJack Morgenstein const struct pci_device_id *id) 12409603b61dSJack Morgenstein { 12419603b61dSJack Morgenstein struct mlx5_core_dev *dev; 12429603b61dSJack Morgenstein struct mlx5_priv *priv; 12439603b61dSJack Morgenstein int err; 12449603b61dSJack Morgenstein 12459603b61dSJack Morgenstein dev = kzalloc(sizeof(*dev), GFP_KERNEL); 12469603b61dSJack Morgenstein if (!dev) { 12479603b61dSJack Morgenstein dev_err(&pdev->dev, "kzalloc failed\n"); 12489603b61dSJack Morgenstein return -ENOMEM; 12499603b61dSJack Morgenstein } 12509603b61dSJack Morgenstein priv = &dev->priv; 12519603b61dSJack Morgenstein 12529603b61dSJack Morgenstein pci_set_drvdata(pdev, dev); 12539603b61dSJack Morgenstein 12549603b61dSJack Morgenstein if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) { 12559603b61dSJack Morgenstein pr_warn("selected profile out of range, selecting default (%d)\n", 12569603b61dSJack Morgenstein MLX5_DEFAULT_PROF); 12579603b61dSJack Morgenstein prof_sel = MLX5_DEFAULT_PROF; 12589603b61dSJack Morgenstein } 12599603b61dSJack Morgenstein dev->profile = &profile[prof_sel]; 1260a31208b1SMajd Dibbiny dev->pdev = pdev; 12619603b61dSJack Morgenstein dev->event = mlx5_core_event; 12629603b61dSJack Morgenstein 1263364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1264364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 126589d44f0aSMajd Dibbiny mutex_init(&dev->pci_status_mutex); 126689d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1267a31208b1SMajd Dibbiny err = mlx5_pci_init(dev, priv); 12689603b61dSJack Morgenstein if (err) { 1269a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); 1270a31208b1SMajd Dibbiny goto clean_dev; 12719603b61dSJack Morgenstein } 12729603b61dSJack Morgenstein 1273ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 1274ac6ea6e8SEli Cohen if (err) { 1275ac6ea6e8SEli Cohen dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); 1276ac6ea6e8SEli Cohen goto close_pci; 1277ac6ea6e8SEli Cohen } 1278ac6ea6e8SEli Cohen 1279a31208b1SMajd Dibbiny err = mlx5_load_one(dev, priv); 12809603b61dSJack Morgenstein if (err) { 1281a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); 1282ac6ea6e8SEli Cohen goto clean_health; 12839603b61dSJack Morgenstein } 12849603b61dSJack Morgenstein 12859603b61dSJack Morgenstein return 0; 12869603b61dSJack Morgenstein 1287ac6ea6e8SEli Cohen clean_health: 1288ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1289a31208b1SMajd Dibbiny close_pci: 1290a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1291a31208b1SMajd Dibbiny clean_dev: 1292a31208b1SMajd Dibbiny pci_set_drvdata(pdev, NULL); 12939603b61dSJack Morgenstein kfree(dev); 1294a31208b1SMajd Dibbiny 12959603b61dSJack Morgenstein return err; 12969603b61dSJack Morgenstein } 1297a31208b1SMajd Dibbiny 12989603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 12999603b61dSJack Morgenstein { 13009603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1301a31208b1SMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 13029603b61dSJack Morgenstein 1303a31208b1SMajd Dibbiny if (mlx5_unload_one(dev, priv)) { 1304a31208b1SMajd Dibbiny dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1305ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1306a31208b1SMajd Dibbiny return; 1307a31208b1SMajd Dibbiny } 1308ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1309a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1310a31208b1SMajd Dibbiny pci_set_drvdata(pdev, NULL); 13119603b61dSJack Morgenstein kfree(dev); 13129603b61dSJack Morgenstein } 13139603b61dSJack Morgenstein 131489d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 131589d44f0aSMajd Dibbiny pci_channel_state_t state) 131689d44f0aSMajd Dibbiny { 131789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 131889d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 131989d44f0aSMajd Dibbiny 132089d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 132189d44f0aSMajd Dibbiny mlx5_enter_error_state(dev); 132289d44f0aSMajd Dibbiny mlx5_unload_one(dev, priv); 132389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 132489d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 132589d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 132689d44f0aSMajd Dibbiny } 132789d44f0aSMajd Dibbiny 132889d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 132989d44f0aSMajd Dibbiny { 133089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 133189d44f0aSMajd Dibbiny int err = 0; 133289d44f0aSMajd Dibbiny 133389d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 133489d44f0aSMajd Dibbiny 133589d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 133689d44f0aSMajd Dibbiny if (err) { 133789d44f0aSMajd Dibbiny dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 133889d44f0aSMajd Dibbiny , __func__, err); 133989d44f0aSMajd Dibbiny return PCI_ERS_RESULT_DISCONNECT; 134089d44f0aSMajd Dibbiny } 134189d44f0aSMajd Dibbiny pci_set_master(pdev); 134289d44f0aSMajd Dibbiny pci_set_power_state(pdev, PCI_D0); 134389d44f0aSMajd Dibbiny pci_restore_state(pdev); 134489d44f0aSMajd Dibbiny 134589d44f0aSMajd Dibbiny return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 134689d44f0aSMajd Dibbiny } 134789d44f0aSMajd Dibbiny 134889d44f0aSMajd Dibbiny void mlx5_disable_device(struct mlx5_core_dev *dev) 134989d44f0aSMajd Dibbiny { 135089d44f0aSMajd Dibbiny mlx5_pci_err_detected(dev->pdev, 0); 135189d44f0aSMajd Dibbiny } 135289d44f0aSMajd Dibbiny 135389d44f0aSMajd Dibbiny /* wait for the device to show vital signs. For now we check 135489d44f0aSMajd Dibbiny * that we can read the device ID and that the health buffer 135589d44f0aSMajd Dibbiny * shows a non zero value which is different than 0xffffffff 135689d44f0aSMajd Dibbiny */ 135789d44f0aSMajd Dibbiny static void wait_vital(struct pci_dev *pdev) 135889d44f0aSMajd Dibbiny { 135989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 136089d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 136189d44f0aSMajd Dibbiny const int niter = 100; 136289d44f0aSMajd Dibbiny u32 count; 136389d44f0aSMajd Dibbiny u16 did; 136489d44f0aSMajd Dibbiny int i; 136589d44f0aSMajd Dibbiny 136689d44f0aSMajd Dibbiny /* Wait for firmware to be ready after reset */ 136789d44f0aSMajd Dibbiny msleep(1000); 136889d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 136989d44f0aSMajd Dibbiny if (pci_read_config_word(pdev, 2, &did)) { 137089d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "failed reading config word\n"); 137189d44f0aSMajd Dibbiny break; 137289d44f0aSMajd Dibbiny } 137389d44f0aSMajd Dibbiny if (did == pdev->device) { 137489d44f0aSMajd Dibbiny dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 137589d44f0aSMajd Dibbiny break; 137689d44f0aSMajd Dibbiny } 137789d44f0aSMajd Dibbiny msleep(50); 137889d44f0aSMajd Dibbiny } 137989d44f0aSMajd Dibbiny if (i == niter) 138089d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 138189d44f0aSMajd Dibbiny 138289d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 138389d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 138489d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 138589d44f0aSMajd Dibbiny dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 138689d44f0aSMajd Dibbiny break; 138789d44f0aSMajd Dibbiny } 138889d44f0aSMajd Dibbiny msleep(50); 138989d44f0aSMajd Dibbiny } 139089d44f0aSMajd Dibbiny 139189d44f0aSMajd Dibbiny if (i == niter) 139289d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 139389d44f0aSMajd Dibbiny } 139489d44f0aSMajd Dibbiny 139589d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 139689d44f0aSMajd Dibbiny { 139789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 139889d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 139989d44f0aSMajd Dibbiny int err; 140089d44f0aSMajd Dibbiny 140189d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 140289d44f0aSMajd Dibbiny 140389d44f0aSMajd Dibbiny pci_save_state(pdev); 140489d44f0aSMajd Dibbiny wait_vital(pdev); 140589d44f0aSMajd Dibbiny 140689d44f0aSMajd Dibbiny err = mlx5_load_one(dev, priv); 140789d44f0aSMajd Dibbiny if (err) 140889d44f0aSMajd Dibbiny dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 140989d44f0aSMajd Dibbiny , __func__, err); 141089d44f0aSMajd Dibbiny else 141189d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s: device recovered\n", __func__); 141289d44f0aSMajd Dibbiny } 141389d44f0aSMajd Dibbiny 141489d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 141589d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 141689d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 141789d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 141889d44f0aSMajd Dibbiny }; 141989d44f0aSMajd Dibbiny 14209603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 14211c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ 14221c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */ 14231c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ 14241c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */ 14251c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ 14261c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */ 14279603b61dSJack Morgenstein { 0, } 14289603b61dSJack Morgenstein }; 14299603b61dSJack Morgenstein 14309603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 14319603b61dSJack Morgenstein 14329603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 14339603b61dSJack Morgenstein .name = DRIVER_NAME, 14349603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 14359603b61dSJack Morgenstein .probe = init_one, 143689d44f0aSMajd Dibbiny .remove = remove_one, 143789d44f0aSMajd Dibbiny .err_handler = &mlx5_err_handler 14389603b61dSJack Morgenstein }; 1439e126ba97SEli Cohen 1440e126ba97SEli Cohen static int __init init(void) 1441e126ba97SEli Cohen { 1442e126ba97SEli Cohen int err; 1443e126ba97SEli Cohen 1444e126ba97SEli Cohen mlx5_register_debugfs(); 1445e126ba97SEli Cohen 14469603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 14479603b61dSJack Morgenstein if (err) 1448ac6ea6e8SEli Cohen goto err_debug; 14499603b61dSJack Morgenstein 1450f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1451f62b8bb8SAmir Vadai mlx5e_init(); 1452f62b8bb8SAmir Vadai #endif 1453f62b8bb8SAmir Vadai 1454e126ba97SEli Cohen return 0; 1455e126ba97SEli Cohen 1456e126ba97SEli Cohen err_debug: 1457e126ba97SEli Cohen mlx5_unregister_debugfs(); 1458e126ba97SEli Cohen return err; 1459e126ba97SEli Cohen } 1460e126ba97SEli Cohen 1461e126ba97SEli Cohen static void __exit cleanup(void) 1462e126ba97SEli Cohen { 1463f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1464f62b8bb8SAmir Vadai mlx5e_cleanup(); 1465f62b8bb8SAmir Vadai #endif 14669603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1467e126ba97SEli Cohen mlx5_unregister_debugfs(); 1468e126ba97SEli Cohen } 1469e126ba97SEli Cohen 1470e126ba97SEli Cohen module_init(init); 1471e126ba97SEli Cohen module_exit(cleanup); 1472