1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53907af0f0SLeon Romanovsky #include <linux/version.h> 54feae9087SOr Gerlitz #include <net/devlink.h> 55e126ba97SEli Cohen #include "mlx5_core.h" 56f2f3df55SSaeed Mahameed #include "lib/eq.h" 5716d76083SSaeed Mahameed #include "fs_core.h" 58eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 59073bb189SSaeed Mahameed #include "eswitch.h" 601f28d776SEran Ben Elisha #include "devlink.h" 6138b9f903SMoshe Shemesh #include "fw_reset.h" 6252ec462eSIlan Tayari #include "lib/mlx5.h" 63e29341fbSIlan Tayari #include "fpga/core.h" 6405564d0aSAviad Yehezkel #include "fpga/ipsec.h" 65bebb23e6SIlan Tayari #include "accel/ipsec.h" 661ae17322SIlya Lesokhin #include "accel/tls.h" 677c39afb3SFeras Daoud #include "lib/clock.h" 68358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 690ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 70fadd59fcSAviv Heller #include "lib/devcom.h" 71b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7224406953SFeras Daoud #include "diag/fw_tracer.h" 73591905baSBodong Wang #include "ecpf.h" 7487175120SEran Ben Elisha #include "lib/hv_vhca.h" 7512206b17SAya Levin #include "diag/rsc_dump.h" 76e126ba97SEli Cohen 77e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 80e126ba97SEli Cohen 81f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 82f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84e126ba97SEli Cohen 859603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 86f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 87f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 889603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 899603b61dSJack Morgenstein 908737f818SDaniel Jurgens static u32 sw_owner_id[4]; 918737f818SDaniel Jurgens 92f91e6d89SEran Ben Elisha enum { 93f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 94f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 95f91e6d89SEran Ben Elisha }; 96f91e6d89SEran Ben Elisha 979603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 989603b61dSJack Morgenstein [0] = { 999603b61dSJack Morgenstein .mask = 0, 1009603b61dSJack Morgenstein }, 1019603b61dSJack Morgenstein [1] = { 1029603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1039603b61dSJack Morgenstein .log_max_qp = 12, 1049603b61dSJack Morgenstein }, 1059603b61dSJack Morgenstein [2] = { 1069603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1079603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1085f40b4edSMaor Gottlieb .log_max_qp = 18, 1099603b61dSJack Morgenstein .mr_cache[0] = { 1109603b61dSJack Morgenstein .size = 500, 1119603b61dSJack Morgenstein .limit = 250 1129603b61dSJack Morgenstein }, 1139603b61dSJack Morgenstein .mr_cache[1] = { 1149603b61dSJack Morgenstein .size = 500, 1159603b61dSJack Morgenstein .limit = 250 1169603b61dSJack Morgenstein }, 1179603b61dSJack Morgenstein .mr_cache[2] = { 1189603b61dSJack Morgenstein .size = 500, 1199603b61dSJack Morgenstein .limit = 250 1209603b61dSJack Morgenstein }, 1219603b61dSJack Morgenstein .mr_cache[3] = { 1229603b61dSJack Morgenstein .size = 500, 1239603b61dSJack Morgenstein .limit = 250 1249603b61dSJack Morgenstein }, 1259603b61dSJack Morgenstein .mr_cache[4] = { 1269603b61dSJack Morgenstein .size = 500, 1279603b61dSJack Morgenstein .limit = 250 1289603b61dSJack Morgenstein }, 1299603b61dSJack Morgenstein .mr_cache[5] = { 1309603b61dSJack Morgenstein .size = 500, 1319603b61dSJack Morgenstein .limit = 250 1329603b61dSJack Morgenstein }, 1339603b61dSJack Morgenstein .mr_cache[6] = { 1349603b61dSJack Morgenstein .size = 500, 1359603b61dSJack Morgenstein .limit = 250 1369603b61dSJack Morgenstein }, 1379603b61dSJack Morgenstein .mr_cache[7] = { 1389603b61dSJack Morgenstein .size = 500, 1399603b61dSJack Morgenstein .limit = 250 1409603b61dSJack Morgenstein }, 1419603b61dSJack Morgenstein .mr_cache[8] = { 1429603b61dSJack Morgenstein .size = 500, 1439603b61dSJack Morgenstein .limit = 250 1449603b61dSJack Morgenstein }, 1459603b61dSJack Morgenstein .mr_cache[9] = { 1469603b61dSJack Morgenstein .size = 500, 1479603b61dSJack Morgenstein .limit = 250 1489603b61dSJack Morgenstein }, 1499603b61dSJack Morgenstein .mr_cache[10] = { 1509603b61dSJack Morgenstein .size = 500, 1519603b61dSJack Morgenstein .limit = 250 1529603b61dSJack Morgenstein }, 1539603b61dSJack Morgenstein .mr_cache[11] = { 1549603b61dSJack Morgenstein .size = 500, 1559603b61dSJack Morgenstein .limit = 250 1569603b61dSJack Morgenstein }, 1579603b61dSJack Morgenstein .mr_cache[12] = { 1589603b61dSJack Morgenstein .size = 64, 1599603b61dSJack Morgenstein .limit = 32 1609603b61dSJack Morgenstein }, 1619603b61dSJack Morgenstein .mr_cache[13] = { 1629603b61dSJack Morgenstein .size = 32, 1639603b61dSJack Morgenstein .limit = 16 1649603b61dSJack Morgenstein }, 1659603b61dSJack Morgenstein .mr_cache[14] = { 1669603b61dSJack Morgenstein .size = 16, 1679603b61dSJack Morgenstein .limit = 8 1689603b61dSJack Morgenstein }, 1699603b61dSJack Morgenstein .mr_cache[15] = { 1709603b61dSJack Morgenstein .size = 8, 1719603b61dSJack Morgenstein .limit = 4 1729603b61dSJack Morgenstein }, 1739603b61dSJack Morgenstein }, 1749603b61dSJack Morgenstein }; 175e126ba97SEli Cohen 176e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 177e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 178b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 179b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 180e3297246SEli Cohen 181555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 182555af0c3SParav Pandit { 183555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 184555af0c3SParav Pandit } 185555af0c3SParav Pandit 186b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 187b8a92577SDaniel Jurgens u32 warn_time_mili) 188e3297246SEli Cohen { 189b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 190e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 191e3297246SEli Cohen int err = 0; 192e3297246SEli Cohen 193b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 194b8a92577SDaniel Jurgens 195e3297246SEli Cohen while (fw_initializing(dev)) { 196e3297246SEli Cohen if (time_after(jiffies, end)) { 197e3297246SEli Cohen err = -EBUSY; 198e3297246SEli Cohen break; 199e3297246SEli Cohen } 200b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 201b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 202b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 203b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 204b8a92577SDaniel Jurgens } 205e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 206e3297246SEli Cohen } 207e3297246SEli Cohen 208e3297246SEli Cohen return err; 209e3297246SEli Cohen } 210e3297246SEli Cohen 211012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 212012e50e1SHuy Nguyen { 213012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 214012e50e1SHuy Nguyen driver_version); 2153ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 216012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 217012e50e1SHuy Nguyen char *string; 218012e50e1SHuy Nguyen 219012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 220012e50e1SHuy Nguyen return; 221012e50e1SHuy Nguyen 222012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 225012e50e1SHuy Nguyen 226012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 227012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 228012e50e1SHuy Nguyen 229012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 23017a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 231012e50e1SHuy Nguyen 232012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 233012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 234012e50e1SHuy Nguyen 235012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 236907af0f0SLeon Romanovsky 237907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 238907af0f0SLeon Romanovsky (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff), 239907af0f0SLeon Romanovsky (u16)(LINUX_VERSION_CODE & 0xffff)); 240012e50e1SHuy Nguyen 241012e50e1SHuy Nguyen /*Send the command*/ 242012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 243012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 244012e50e1SHuy Nguyen 2453ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 246012e50e1SHuy Nguyen } 247012e50e1SHuy Nguyen 248e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 249e126ba97SEli Cohen { 250e126ba97SEli Cohen int err; 251e126ba97SEli Cohen 252e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 253e126ba97SEli Cohen if (err) { 2541a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 255e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 256e126ba97SEli Cohen if (err) { 2571a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 258e126ba97SEli Cohen return err; 259e126ba97SEli Cohen } 260e126ba97SEli Cohen } 261e126ba97SEli Cohen 262e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 263e126ba97SEli Cohen if (err) { 264e126ba97SEli Cohen dev_warn(&pdev->dev, 2651a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 266e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 267e126ba97SEli Cohen if (err) { 268e126ba97SEli Cohen dev_err(&pdev->dev, 2691a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 270e126ba97SEli Cohen return err; 271e126ba97SEli Cohen } 272e126ba97SEli Cohen } 273e126ba97SEli Cohen 274e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 275e126ba97SEli Cohen return err; 276e126ba97SEli Cohen } 277e126ba97SEli Cohen 27889d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27989d44f0aSMajd Dibbiny { 28089d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28189d44f0aSMajd Dibbiny int err = 0; 28289d44f0aSMajd Dibbiny 28389d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28489d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 28589d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 28689d44f0aSMajd Dibbiny if (!err) 28789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28889d44f0aSMajd Dibbiny } 28989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29089d44f0aSMajd Dibbiny 29189d44f0aSMajd Dibbiny return err; 29289d44f0aSMajd Dibbiny } 29389d44f0aSMajd Dibbiny 29489d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 29589d44f0aSMajd Dibbiny { 29689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29789d44f0aSMajd Dibbiny 29889d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29989d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 30089d44f0aSMajd Dibbiny pci_disable_device(pdev); 30189d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 30289d44f0aSMajd Dibbiny } 30389d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 30489d44f0aSMajd Dibbiny } 30589d44f0aSMajd Dibbiny 306e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 307e126ba97SEli Cohen { 308e126ba97SEli Cohen int err = 0; 309e126ba97SEli Cohen 310e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3111a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 312e126ba97SEli Cohen return -ENODEV; 313e126ba97SEli Cohen } 314e126ba97SEli Cohen 31517a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 316e126ba97SEli Cohen if (err) 317e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 318e126ba97SEli Cohen 319e126ba97SEli Cohen return err; 320e126ba97SEli Cohen } 321e126ba97SEli Cohen 322e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 323e126ba97SEli Cohen { 324e126ba97SEli Cohen pci_release_regions(pdev); 325e126ba97SEli Cohen } 326e126ba97SEli Cohen 327bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 328e126ba97SEli Cohen u8 he; 329e126ba97SEli Cohen u8 rsvd[15]; 330e126ba97SEli Cohen }; 331e126ba97SEli Cohen 33287b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 33387b8de49SEli Cohen 33487b8de49SEli Cohen enum { 33587b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 336c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 33787b8de49SEli Cohen }; 33887b8de49SEli Cohen 3392974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 340c7a08ac7SEli Cohen { 341c7a08ac7SEli Cohen switch (size) { 342c7a08ac7SEli Cohen case 128: 343c7a08ac7SEli Cohen return 0; 344c7a08ac7SEli Cohen case 256: 345c7a08ac7SEli Cohen return 1; 346c7a08ac7SEli Cohen case 512: 347c7a08ac7SEli Cohen return 2; 348c7a08ac7SEli Cohen case 1024: 349c7a08ac7SEli Cohen return 3; 350c7a08ac7SEli Cohen case 2048: 351c7a08ac7SEli Cohen return 4; 352c7a08ac7SEli Cohen case 4096: 353c7a08ac7SEli Cohen return 5; 354c7a08ac7SEli Cohen default: 3552974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 356c7a08ac7SEli Cohen return 0; 357c7a08ac7SEli Cohen } 358c7a08ac7SEli Cohen } 359c7a08ac7SEli Cohen 360b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 361b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 362938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 363c7a08ac7SEli Cohen { 364b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 365b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 366938fe83cSSaeed Mahameed void *out, *hca_caps; 367938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 368c7a08ac7SEli Cohen int err; 369c7a08ac7SEli Cohen 370b775516bSEli Cohen memset(in, 0, sizeof(in)); 371b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 372c7a08ac7SEli Cohen if (!out) 373c7a08ac7SEli Cohen return -ENOMEM; 374938fe83cSSaeed Mahameed 375b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 376b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3773ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 378c7a08ac7SEli Cohen if (err) { 379938fe83cSSaeed Mahameed mlx5_core_warn(dev, 380938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 381938fe83cSSaeed Mahameed cap_type, cap_mode, err); 382c7a08ac7SEli Cohen goto query_ex; 383c7a08ac7SEli Cohen } 384c7a08ac7SEli Cohen 385938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 386938fe83cSSaeed Mahameed 387938fe83cSSaeed Mahameed switch (cap_mode) { 388938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 389701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 390938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 391938fe83cSSaeed Mahameed break; 392938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 393701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 394938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 395938fe83cSSaeed Mahameed break; 396938fe83cSSaeed Mahameed default: 397938fe83cSSaeed Mahameed mlx5_core_warn(dev, 398938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 399938fe83cSSaeed Mahameed cap_type, cap_mode); 400938fe83cSSaeed Mahameed err = -EINVAL; 401938fe83cSSaeed Mahameed break; 402938fe83cSSaeed Mahameed } 403c7a08ac7SEli Cohen query_ex: 404c7a08ac7SEli Cohen kfree(out); 405c7a08ac7SEli Cohen return err; 406c7a08ac7SEli Cohen } 407c7a08ac7SEli Cohen 408b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 409b06e7de8SLeon Romanovsky { 410b06e7de8SLeon Romanovsky int ret; 411b06e7de8SLeon Romanovsky 412b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 413b06e7de8SLeon Romanovsky if (ret) 414b06e7de8SLeon Romanovsky return ret; 415b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 416b06e7de8SLeon Romanovsky } 417b06e7de8SLeon Romanovsky 418a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 419c7a08ac7SEli Cohen { 420b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 421f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4223ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 423c7a08ac7SEli Cohen } 42487b8de49SEli Cohen 425a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 426f91e6d89SEran Ben Elisha { 427f91e6d89SEran Ben Elisha void *set_hca_cap; 428f91e6d89SEran Ben Elisha int req_endianness; 429f91e6d89SEran Ben Elisha int err; 430f91e6d89SEran Ben Elisha 431a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 432a2a322f4SLeon Romanovsky return 0; 433a2a322f4SLeon Romanovsky 434b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 435f91e6d89SEran Ben Elisha if (err) 436f91e6d89SEran Ben Elisha return err; 437f91e6d89SEran Ben Elisha 438f91e6d89SEran Ben Elisha req_endianness = 439f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 440bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 441f91e6d89SEran Ben Elisha 442f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 443f91e6d89SEran Ben Elisha return 0; 444f91e6d89SEran Ben Elisha 445f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 446f91e6d89SEran Ben Elisha 447f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 448bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 449f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 450f91e6d89SEran Ben Elisha 451a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 452f91e6d89SEran Ben Elisha } 453f91e6d89SEran Ben Elisha 454a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45546861e3eSMoni Shoua { 45646861e3eSMoni Shoua void *set_hca_cap; 457fca22e7eSMoni Shoua bool do_set = false; 45846861e3eSMoni Shoua int err; 45946861e3eSMoni Shoua 46037b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46137b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46246861e3eSMoni Shoua return 0; 46346861e3eSMoni Shoua 46446861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46546861e3eSMoni Shoua if (err) 46646861e3eSMoni Shoua return err; 46746861e3eSMoni Shoua 46846861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 46946861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 47046861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47146861e3eSMoni Shoua 472fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 473fca22e7eSMoni Shoua do { \ 474fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 475fca22e7eSMoni Shoua if (_res) { \ 476fca22e7eSMoni Shoua do_set = true; \ 477fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 478fca22e7eSMoni Shoua } \ 479fca22e7eSMoni Shoua } while (0) 48046861e3eSMoni Shoua 481fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 482fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 488fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 48900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 49000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 49100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 49200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49546861e3eSMoni Shoua 496a2a322f4SLeon Romanovsky if (!do_set) 497a2a322f4SLeon Romanovsky return 0; 49846861e3eSMoni Shoua 499a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 50046861e3eSMoni Shoua } 50146861e3eSMoni Shoua 502a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 503e126ba97SEli Cohen { 504c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 505938fe83cSSaeed Mahameed void *set_hca_cap; 506a2a322f4SLeon Romanovsky int err; 507e126ba97SEli Cohen 508b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 509c7a08ac7SEli Cohen if (err) 510a2a322f4SLeon Romanovsky return err; 511e126ba97SEli Cohen 512938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 513938fe83cSSaeed Mahameed capability); 514701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 515938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 516938fe83cSSaeed Mahameed 517938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 518707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 519938fe83cSSaeed Mahameed 128); 520c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 521938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5222974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 523e126ba97SEli Cohen 524883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 525883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 526883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 527883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 528883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 529883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 530883371c4SNoa Osherovich } 531c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 532938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 533938fe83cSSaeed Mahameed prof->log_max_qp); 534e126ba97SEli Cohen 535938fe83cSSaeed Mahameed /* disable cmdif checksum */ 536938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 537c1868b82SEli Cohen 53891828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 53991828bd8SMajd Dibbiny * than 4K. 54091828bd8SMajd Dibbiny */ 54191828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 542f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 543f502d834SEli Cohen 544fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 545fe1e1876SCarol L Soto 546f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 547f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 548f32f5bd2SDaniel Jurgens set_hca_cap, 549f32f5bd2SDaniel Jurgens cache_line_128byte, 550c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 551f32f5bd2SDaniel Jurgens 552dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 553dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 554dd44572aSMoni Shoua 555e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 556e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 557e7f4d0bcSMoshe Shemesh 558c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 559c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 560c4b76d8dSDaniel Jurgens set_hca_cap, 561c4b76d8dSDaniel Jurgens num_vhca_ports, 562c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 563c4b76d8dSDaniel Jurgens 564c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 565c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 566c6168161SEran Ben Elisha 5674dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 5684dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 5694dca6509SMichael Guralnik 570a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 571e126ba97SEli Cohen } 572cd23b14bSEli Cohen 57359e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 57459e9e8e4SMark Zhang { 57559e9e8e4SMark Zhang void *set_hca_cap; 57659e9e8e4SMark Zhang int err; 57759e9e8e4SMark Zhang 57859e9e8e4SMark Zhang if (!MLX5_CAP_GEN(dev, roce)) 57959e9e8e4SMark Zhang return 0; 58059e9e8e4SMark Zhang 58159e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 58259e9e8e4SMark Zhang if (err) 58359e9e8e4SMark Zhang return err; 58459e9e8e4SMark Zhang 58559e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 58659e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 58759e9e8e4SMark Zhang return 0; 58859e9e8e4SMark Zhang 58959e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 59059e9e8e4SMark Zhang memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 59159e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 59259e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 59359e9e8e4SMark Zhang 59459e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 595e126ba97SEli Cohen return err; 596e126ba97SEli Cohen } 597e126ba97SEli Cohen 59837b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 59937b6bb77SLeon Romanovsky { 600a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 601a2a322f4SLeon Romanovsky void *set_ctx; 60237b6bb77SLeon Romanovsky int err; 60337b6bb77SLeon Romanovsky 604a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 605a2a322f4SLeon Romanovsky if (!set_ctx) 606a2a322f4SLeon Romanovsky return -ENOMEM; 607a2a322f4SLeon Romanovsky 608a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 60937b6bb77SLeon Romanovsky if (err) { 61098a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 61137b6bb77SLeon Romanovsky goto out; 61237b6bb77SLeon Romanovsky } 61337b6bb77SLeon Romanovsky 614a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 615a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 61637b6bb77SLeon Romanovsky if (err) { 61798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 61837b6bb77SLeon Romanovsky goto out; 61937b6bb77SLeon Romanovsky } 62037b6bb77SLeon Romanovsky 621a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 622a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 62337b6bb77SLeon Romanovsky if (err) { 62498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 62537b6bb77SLeon Romanovsky goto out; 62637b6bb77SLeon Romanovsky } 62737b6bb77SLeon Romanovsky 62859e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 62959e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 63059e9e8e4SMark Zhang if (err) { 63159e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 63259e9e8e4SMark Zhang goto out; 63359e9e8e4SMark Zhang } 63459e9e8e4SMark Zhang 63537b6bb77SLeon Romanovsky out: 636a2a322f4SLeon Romanovsky kfree(set_ctx); 63737b6bb77SLeon Romanovsky return err; 63837b6bb77SLeon Romanovsky } 63937b6bb77SLeon Romanovsky 640e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 641e126ba97SEli Cohen { 642bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 643bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 644e126ba97SEli Cohen int err; 645e126ba97SEli Cohen 646fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 647fc50db98SEli Cohen return 0; 648fc50db98SEli Cohen 649e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 650e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 651e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 652e126ba97SEli Cohen &he_out, sizeof(he_out), 653e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 654e126ba97SEli Cohen return err; 655e126ba97SEli Cohen } 656e126ba97SEli Cohen 657c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 658c85023e1SHuy Nguyen { 659c85023e1SHuy Nguyen int ret = 0; 660c85023e1SHuy Nguyen 661c85023e1SHuy Nguyen /* Disable local_lb by default */ 6628978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 663c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 664c85023e1SHuy Nguyen 665c85023e1SHuy Nguyen return ret; 666c85023e1SHuy Nguyen } 667c85023e1SHuy Nguyen 6680b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 669e126ba97SEli Cohen { 6703ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 671e126ba97SEli Cohen 6720b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6730b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 67422e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 67522e939a9SBodong Wang dev->caps.embedded_cpu); 6763ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 677e126ba97SEli Cohen } 678e126ba97SEli Cohen 6790b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 680e126ba97SEli Cohen { 6813ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 682e126ba97SEli Cohen 6830b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6840b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 68522e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 68622e939a9SBodong Wang dev->caps.embedded_cpu); 6873ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 688e126ba97SEli Cohen } 689e126ba97SEli Cohen 690f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 691f62b8bb8SAmir Vadai { 6923ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 6933ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 694f62b8bb8SAmir Vadai u32 sup_issi; 695c4f287c4SSaeed Mahameed int err; 696f62b8bb8SAmir Vadai 697f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 6983ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 699f62b8bb8SAmir Vadai if (err) { 700c4f287c4SSaeed Mahameed u32 syndrome; 701c4f287c4SSaeed Mahameed u8 status; 702c4f287c4SSaeed Mahameed 703c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 704f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 705f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 706f9c14e46SKamal Heib err, status, syndrome); 707f9c14e46SKamal Heib return err; 708f62b8bb8SAmir Vadai } 709f62b8bb8SAmir Vadai 710f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 711f9c14e46SKamal Heib dev->issi = 0; 712f9c14e46SKamal Heib return 0; 713f62b8bb8SAmir Vadai } 714f62b8bb8SAmir Vadai 715f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 716f62b8bb8SAmir Vadai 717f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7183ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 719f62b8bb8SAmir Vadai 720f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 721f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7223ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 723f62b8bb8SAmir Vadai if (err) { 724f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 725f9c14e46SKamal Heib err); 726f62b8bb8SAmir Vadai return err; 727f62b8bb8SAmir Vadai } 728f62b8bb8SAmir Vadai 729f62b8bb8SAmir Vadai dev->issi = 1; 730f62b8bb8SAmir Vadai 731f62b8bb8SAmir Vadai return 0; 732e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 733f62b8bb8SAmir Vadai return 0; 734f62b8bb8SAmir Vadai } 735f62b8bb8SAmir Vadai 7369eb78923SOr Gerlitz return -EOPNOTSUPP; 737f62b8bb8SAmir Vadai } 738f62b8bb8SAmir Vadai 73911f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 74011f3b84dSSaeed Mahameed const struct pci_device_id *id) 741a31208b1SMajd Dibbiny { 742868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 743a31208b1SMajd Dibbiny int err = 0; 744a31208b1SMajd Dibbiny 745d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 746e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 747e126ba97SEli Cohen 748aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 7497be3412aSParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 750311c7c71SSaeed Mahameed 75189d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 752e126ba97SEli Cohen if (err) { 75398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 75411f3b84dSSaeed Mahameed return err; 755e126ba97SEli Cohen } 756e126ba97SEli Cohen 757e126ba97SEli Cohen err = request_bar(pdev); 758e126ba97SEli Cohen if (err) { 75998a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 760e126ba97SEli Cohen goto err_disable; 761e126ba97SEli Cohen } 762e126ba97SEli Cohen 763e126ba97SEli Cohen pci_set_master(pdev); 764e126ba97SEli Cohen 765e126ba97SEli Cohen err = set_dma_caps(pdev); 766e126ba97SEli Cohen if (err) { 76798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 768e126ba97SEli Cohen goto err_clr_master; 769e126ba97SEli Cohen } 770e126ba97SEli Cohen 771ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 772ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 773ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 774ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 775ce4eee53SMichael Guralnik 776aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 777e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 778e126ba97SEli Cohen if (!dev->iseg) { 779e126ba97SEli Cohen err = -ENOMEM; 78098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 781e126ba97SEli Cohen goto err_clr_master; 782e126ba97SEli Cohen } 783a31208b1SMajd Dibbiny 784b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 785c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 786a31208b1SMajd Dibbiny return 0; 787a31208b1SMajd Dibbiny 788a31208b1SMajd Dibbiny err_clr_master: 789a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 790a31208b1SMajd Dibbiny release_bar(dev->pdev); 791a31208b1SMajd Dibbiny err_disable: 79289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 793a31208b1SMajd Dibbiny return err; 794a31208b1SMajd Dibbiny } 795a31208b1SMajd Dibbiny 796868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 797a31208b1SMajd Dibbiny { 79842ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 79942ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 80042ea9f1bSShay Drory * before removing the pci bars 80142ea9f1bSShay Drory */ 80242ea9f1bSShay Drory mlx5_drain_health_wq(dev); 803a31208b1SMajd Dibbiny iounmap(dev->iseg); 804a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 805a31208b1SMajd Dibbiny release_bar(dev->pdev); 80689d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 807a31208b1SMajd Dibbiny } 808a31208b1SMajd Dibbiny 809868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 81059211bd3SMohamad Haj Yahia { 81159211bd3SMohamad Haj Yahia int err; 81259211bd3SMohamad Haj Yahia 813868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 814868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 81598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 816868bc06bSSaeed Mahameed dev->priv.devcom); 817fadd59fcSAviv Heller 81859211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 81959211bd3SMohamad Haj Yahia if (err) { 82098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 821fadd59fcSAviv Heller goto err_devcom; 82259211bd3SMohamad Haj Yahia } 82359211bd3SMohamad Haj Yahia 824561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 825561aa15aSYuval Avnery if (err) { 826561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 827561aa15aSYuval Avnery goto err_devcom; 828561aa15aSYuval Avnery } 829561aa15aSYuval Avnery 830f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 83159211bd3SMohamad Haj Yahia if (err) { 83298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 833561aa15aSYuval Avnery goto err_irq_cleanup; 83459211bd3SMohamad Haj Yahia } 83559211bd3SMohamad Haj Yahia 83669c1280bSSaeed Mahameed err = mlx5_events_init(dev); 83769c1280bSSaeed Mahameed if (err) { 83898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 83969c1280bSSaeed Mahameed goto err_eq_cleanup; 84069c1280bSSaeed Mahameed } 84169c1280bSSaeed Mahameed 84238b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 84338b9f903SMoshe Shemesh if (err) { 84438b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 84538b9f903SMoshe Shemesh goto err_events_cleanup; 84638b9f903SMoshe Shemesh } 84738b9f903SMoshe Shemesh 8489f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 84959211bd3SMohamad Haj Yahia 85052ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 85152ec462eSIlan Tayari 8527c39afb3SFeras Daoud mlx5_init_clock(dev); 8537c39afb3SFeras Daoud 854358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8550ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 856358aa5ceSSaeed Mahameed 85759211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 85859211bd3SMohamad Haj Yahia if (err) { 85998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 86059211bd3SMohamad Haj Yahia goto err_tables_cleanup; 86159211bd3SMohamad Haj Yahia } 86259211bd3SMohamad Haj Yahia 863eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 864eeb66cdbSSaeed Mahameed if (err) { 86598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 866eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 867eeb66cdbSSaeed Mahameed } 868eeb66cdbSSaeed Mahameed 869c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 870c2d6e31aSMohamad Haj Yahia if (err) { 87198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 87286eec50bSBodong Wang goto err_mpfs_cleanup; 87386eec50bSBodong Wang } 87486eec50bSBodong Wang 87586eec50bSBodong Wang err = mlx5_eswitch_init(dev); 87686eec50bSBodong Wang if (err) { 87786eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 87886eec50bSBodong Wang goto err_sriov_cleanup; 879c2d6e31aSMohamad Haj Yahia } 880c2d6e31aSMohamad Haj Yahia 8819410733cSIlan Tayari err = mlx5_fpga_init(dev); 8829410733cSIlan Tayari if (err) { 88398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 88486eec50bSBodong Wang goto err_eswitch_cleanup; 8859410733cSIlan Tayari } 8869410733cSIlan Tayari 887c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 888c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 889c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 890c9b9dcb4SAriel Levkovich 89124406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 89287175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 89312206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 89424406953SFeras Daoud 89559211bd3SMohamad Haj Yahia return 0; 89659211bd3SMohamad Haj Yahia 897c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 898c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 89986eec50bSBodong Wang err_sriov_cleanup: 90086eec50bSBodong Wang mlx5_sriov_cleanup(dev); 901eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 902eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 903c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 904c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 90559211bd3SMohamad Haj Yahia err_tables_cleanup: 9060ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 907358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 90802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 90938b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 91038b9f903SMoshe Shemesh err_events_cleanup: 91169c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 91259211bd3SMohamad Haj Yahia err_eq_cleanup: 913f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 914561aa15aSYuval Avnery err_irq_cleanup: 915561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 916fadd59fcSAviv Heller err_devcom: 917fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 91859211bd3SMohamad Haj Yahia 91959211bd3SMohamad Haj Yahia return err; 92059211bd3SMohamad Haj Yahia } 92159211bd3SMohamad Haj Yahia 92259211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 92359211bd3SMohamad Haj Yahia { 92412206b17SAya Levin mlx5_rsc_dump_destroy(dev); 92587175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 92624406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 927c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9289410733cSIlan Tayari mlx5_fpga_cleanup(dev); 929c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 93086eec50bSBodong Wang mlx5_sriov_cleanup(dev); 931eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 93259211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9330ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 934358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9357c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 93652ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 93702d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 93838b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 93969c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 940f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 941561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 942fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 94359211bd3SMohamad Haj Yahia } 94459211bd3SMohamad Haj Yahia 945e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 946a31208b1SMajd Dibbiny { 947a31208b1SMajd Dibbiny int err; 948a31208b1SMajd Dibbiny 94998a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 950e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 951e126ba97SEli Cohen 95200c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 95300c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 95400c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 95500c6bcb0STal Gilboa 9566c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9576c780a02SEli Cohen */ 958b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9596c780a02SEli Cohen if (err) { 96098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9616c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 962e161105eSSaeed Mahameed return err; 9636c780a02SEli Cohen } 9646c780a02SEli Cohen 965e126ba97SEli Cohen err = mlx5_cmd_init(dev); 966e126ba97SEli Cohen if (err) { 96798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 968e161105eSSaeed Mahameed return err; 969e126ba97SEli Cohen } 970e126ba97SEli Cohen 971b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 972e3297246SEli Cohen if (err) { 97398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 974e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 97555378a23SMohamad Haj Yahia goto err_cmd_cleanup; 976e3297246SEli Cohen } 977e3297246SEli Cohen 978f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 979f7936dddSEran Ben Elisha 9800b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 981cd23b14bSEli Cohen if (err) { 98298a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 98359211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 984cd23b14bSEli Cohen } 985cd23b14bSEli Cohen 986f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 987f62b8bb8SAmir Vadai if (err) { 98898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 989f62b8bb8SAmir Vadai goto err_disable_hca; 990f62b8bb8SAmir Vadai } 991f62b8bb8SAmir Vadai 992cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 993cd23b14bSEli Cohen if (err) { 99498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 995cd23b14bSEli Cohen goto err_disable_hca; 996cd23b14bSEli Cohen } 997cd23b14bSEli Cohen 998e126ba97SEli Cohen err = set_hca_ctrl(dev); 999e126ba97SEli Cohen if (err) { 100098a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1001cd23b14bSEli Cohen goto reclaim_boot_pages; 1002e126ba97SEli Cohen } 1003e126ba97SEli Cohen 100437b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1005e126ba97SEli Cohen if (err) { 100698a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 100746861e3eSMoni Shoua goto reclaim_boot_pages; 100846861e3eSMoni Shoua } 100946861e3eSMoni Shoua 1010cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1011e126ba97SEli Cohen if (err) { 101298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1013cd23b14bSEli Cohen goto reclaim_boot_pages; 1014e126ba97SEli Cohen } 1015e126ba97SEli Cohen 10168737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1017e126ba97SEli Cohen if (err) { 101898a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10190cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1020e126ba97SEli Cohen } 1021e126ba97SEli Cohen 1022012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1023012e50e1SHuy Nguyen 1024e126ba97SEli Cohen mlx5_start_health_poll(dev); 1025e126ba97SEli Cohen 1026bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1027bba1574cSDaniel Jurgens if (err) { 102898a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1029e161105eSSaeed Mahameed goto stop_health; 1030bba1574cSDaniel Jurgens } 1031bba1574cSDaniel Jurgens 1032e161105eSSaeed Mahameed return 0; 1033e161105eSSaeed Mahameed 1034e161105eSSaeed Mahameed stop_health: 1035e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1036e161105eSSaeed Mahameed reclaim_boot_pages: 1037e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1038e161105eSSaeed Mahameed err_disable_hca: 1039e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1040e161105eSSaeed Mahameed err_cmd_cleanup: 1041f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1042e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1043e161105eSSaeed Mahameed 1044e161105eSSaeed Mahameed return err; 1045e161105eSSaeed Mahameed } 1046e161105eSSaeed Mahameed 1047e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1048e161105eSSaeed Mahameed { 1049e161105eSSaeed Mahameed int err; 1050e161105eSSaeed Mahameed 1051e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1052e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1053259bbc57SMaor Gottlieb if (err) { 105498a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1055e161105eSSaeed Mahameed return err; 1056e126ba97SEli Cohen } 1057e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1058e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1059f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1060e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1061e161105eSSaeed Mahameed 1062e161105eSSaeed Mahameed return 0; 1063259bbc57SMaor Gottlieb } 1064e126ba97SEli Cohen 1065a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1066e161105eSSaeed Mahameed { 1067e161105eSSaeed Mahameed int err; 1068e161105eSSaeed Mahameed 106901187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 107072f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 107198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 107272f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1073a80d1b68SSaeed Mahameed return err; 1074e126ba97SEli Cohen } 1075e126ba97SEli Cohen 107669c1280bSSaeed Mahameed mlx5_events_start(dev); 10770cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10780cf53c12SSaeed Mahameed 1079e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1080e1706e62SYuval Avnery if (err) { 1081e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1082e1706e62SYuval Avnery goto err_irq_table; 1083e1706e62SYuval Avnery } 1084e1706e62SYuval Avnery 1085c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1086e126ba97SEli Cohen if (err) { 108798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1088c8e21b3bSSaeed Mahameed goto err_eq_table; 1089e126ba97SEli Cohen } 1090e126ba97SEli Cohen 109124406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 109224406953SFeras Daoud if (err) { 109398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 109424406953SFeras Daoud goto err_fw_tracer; 109524406953SFeras Daoud } 109624406953SFeras Daoud 109738b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 109887175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 109987175120SEran Ben Elisha 110012206b17SAya Levin err = mlx5_rsc_dump_init(dev); 110112206b17SAya Levin if (err) { 110212206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 110312206b17SAya Levin goto err_rsc_dump; 110412206b17SAya Levin } 110512206b17SAya Levin 110604e87170SMatan Barak err = mlx5_fpga_device_start(dev); 110704e87170SMatan Barak if (err) { 110898a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 110904e87170SMatan Barak goto err_fpga_start; 111004e87170SMatan Barak } 111104e87170SMatan Barak 11129a6ad1adSRaed Salem mlx5_accel_ipsec_init(dev); 111304e87170SMatan Barak 11141ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11151ae17322SIlya Lesokhin if (err) { 111698a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11171ae17322SIlya Lesokhin goto err_tls_start; 11181ae17322SIlya Lesokhin } 11191ae17322SIlya Lesokhin 112086d722adSMaor Gottlieb err = mlx5_init_fs(dev); 112186d722adSMaor Gottlieb if (err) { 112298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 112386d722adSMaor Gottlieb goto err_fs; 112486d722adSMaor Gottlieb } 11251466cc5bSYevgeny Petrilin 1126c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1127c85023e1SHuy Nguyen if (err) { 112898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 112987883929SSaeed Mahameed goto err_sriov; 1130c85023e1SHuy Nguyen } 1131c85023e1SHuy Nguyen 113222e939a9SBodong Wang err = mlx5_ec_init(dev); 113322e939a9SBodong Wang if (err) { 113498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 113522e939a9SBodong Wang goto err_ec; 113622e939a9SBodong Wang } 113722e939a9SBodong Wang 11385bef709dSParav Pandit err = mlx5_sriov_attach(dev); 11395bef709dSParav Pandit if (err) { 11405bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 11415bef709dSParav Pandit goto err_sriov; 11425bef709dSParav Pandit } 11435bef709dSParav Pandit 1144a80d1b68SSaeed Mahameed return 0; 1145a80d1b68SSaeed Mahameed 1146a80d1b68SSaeed Mahameed err_sriov: 11475bef709dSParav Pandit mlx5_ec_cleanup(dev); 11485bef709dSParav Pandit err_ec: 1149a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1150a80d1b68SSaeed Mahameed err_fs: 1151a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1152a80d1b68SSaeed Mahameed err_tls_start: 1153a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1154a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1155a80d1b68SSaeed Mahameed err_fpga_start: 115612206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 115712206b17SAya Levin err_rsc_dump: 115887175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 115938b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1160a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1161a80d1b68SSaeed Mahameed err_fw_tracer: 1162a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1163a80d1b68SSaeed Mahameed err_eq_table: 1164e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1165e1706e62SYuval Avnery err_irq_table: 1166a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1167a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1168a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1169a80d1b68SSaeed Mahameed return err; 1170a80d1b68SSaeed Mahameed } 1171a80d1b68SSaeed Mahameed 1172a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1173a80d1b68SSaeed Mahameed { 1174a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 11755bef709dSParav Pandit mlx5_ec_cleanup(dev); 1176a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1177a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1178a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1179a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 118012206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 118187175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 118238b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1183a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1184a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1185e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1186a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1187a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1188a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1189a80d1b68SSaeed Mahameed } 1190a80d1b68SSaeed Mahameed 11914383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1192a80d1b68SSaeed Mahameed { 1193a80d1b68SSaeed Mahameed int err = 0; 1194a80d1b68SSaeed Mahameed 1195a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1196a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1197a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1198a80d1b68SSaeed Mahameed goto out; 1199a80d1b68SSaeed Mahameed } 1200a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1201a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1202a80d1b68SSaeed Mahameed 1203a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1204a80d1b68SSaeed Mahameed if (err) 12054f7400d5SShay Drory goto err_function; 1206a80d1b68SSaeed Mahameed 1207a80d1b68SSaeed Mahameed if (boot) { 1208a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1209a80d1b68SSaeed Mahameed if (err) { 121098a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1211a80d1b68SSaeed Mahameed goto function_teardown; 1212a80d1b68SSaeed Mahameed } 1213a80d1b68SSaeed Mahameed } 1214a80d1b68SSaeed Mahameed 1215a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1216a80d1b68SSaeed Mahameed if (err) 1217a80d1b68SSaeed Mahameed goto err_load; 1218a80d1b68SSaeed Mahameed 121998f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 122098f91c45SParav Pandit 1221a6f3b623SMichael Guralnik if (boot) { 1222a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1223a6f3b623SMichael Guralnik if (err) 1224a6f3b623SMichael Guralnik goto err_devlink_reg; 1225a925b5e3SLeon Romanovsky 1226a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 122798f91c45SParav Pandit } else { 1228a925b5e3SLeon Romanovsky err = mlx5_attach_device(dev); 122998f91c45SParav Pandit } 123089d44f0aSMajd Dibbiny 1231a925b5e3SLeon Romanovsky if (err) 1232a925b5e3SLeon Romanovsky goto err_register; 1233a925b5e3SLeon Romanovsky 12344162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 12354162f58bSParav Pandit return 0; 1236e126ba97SEli Cohen 1237a925b5e3SLeon Romanovsky err_register: 1238a925b5e3SLeon Romanovsky if (boot) 1239a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1240a6f3b623SMichael Guralnik err_devlink_reg: 124198f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1242a80d1b68SSaeed Mahameed mlx5_unload(dev); 1243a80d1b68SSaeed Mahameed err_load: 124459211bd3SMohamad Haj Yahia if (boot) 124559211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1246e161105eSSaeed Mahameed function_teardown: 1247e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 12484f7400d5SShay Drory err_function: 124989d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 12504162f58bSParav Pandit out: 125189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1252e126ba97SEli Cohen return err; 1253e126ba97SEli Cohen } 1254e126ba97SEli Cohen 1255f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1256e126ba97SEli Cohen { 125789d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 125898f91c45SParav Pandit 125998f91c45SParav Pandit if (cleanup) { 126098f91c45SParav Pandit mlx5_unregister_device(dev); 126198f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 126298f91c45SParav Pandit } else { 126398f91c45SParav Pandit mlx5_detach_device(dev); 126498f91c45SParav Pandit } 126598f91c45SParav Pandit 1266b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 126798a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 126889d44f0aSMajd Dibbiny __func__); 126959211bd3SMohamad Haj Yahia if (cleanup) 127059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 127189d44f0aSMajd Dibbiny goto out; 127289d44f0aSMajd Dibbiny } 12736b6adee3SMohamad Haj Yahia 12749ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12759ade8c7cSIlan Tayari 1276a80d1b68SSaeed Mahameed mlx5_unload(dev); 1277a80d1b68SSaeed Mahameed 127859211bd3SMohamad Haj Yahia if (cleanup) 127959211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12800cf53c12SSaeed Mahameed 1281e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1282ac6ea6e8SEli Cohen out: 128389d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 12849603b61dSJack Morgenstein } 128564613d94SSaeed Mahameed 128627b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12879603b61dSJack Morgenstein { 128811f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12899603b61dSJack Morgenstein int err; 12909603b61dSJack Morgenstein 129111f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12929603b61dSJack Morgenstein 1293364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1294364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 129589d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1296d9aaed83SArtemy Kovalyov 129701187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 129801187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 129901187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 130001187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 130101187175SEli Cohen 130211f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 130311f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 130411f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 130511f3b84dSSaeed Mahameed 130627b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 130727b942fbSParav Pandit mlx5_debugfs_root); 1308ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 130952c368dcSSaeed Mahameed if (err) 131052c368dcSSaeed Mahameed goto err_health_init; 1311ac6ea6e8SEli Cohen 13120cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 13130cf53c12SSaeed Mahameed if (err) 13140cf53c12SSaeed Mahameed goto err_pagealloc_init; 131559211bd3SMohamad Haj Yahia 1316a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1317a925b5e3SLeon Romanovsky if (err) 1318a925b5e3SLeon Romanovsky goto err_adev_init; 1319a925b5e3SLeon Romanovsky 132011f3b84dSSaeed Mahameed return 0; 132152c368dcSSaeed Mahameed 1322a925b5e3SLeon Romanovsky err_adev_init: 1323a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 132452c368dcSSaeed Mahameed err_pagealloc_init: 132552c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 132652c368dcSSaeed Mahameed err_health_init: 132752c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1328810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1329810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1330810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1331810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1332810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 133352c368dcSSaeed Mahameed return err; 133411f3b84dSSaeed Mahameed } 133511f3b84dSSaeed Mahameed 133611f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 133711f3b84dSSaeed Mahameed { 1338810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1339810cbb25SParav Pandit 1340a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 134152c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 134252c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 134311f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1344810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1345810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1346810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1347810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1348810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 134911f3b84dSSaeed Mahameed } 135011f3b84dSSaeed Mahameed 135111f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 135211f3b84dSSaeed Mahameed { 135311f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 135411f3b84dSSaeed Mahameed struct devlink *devlink; 135511f3b84dSSaeed Mahameed int err; 135611f3b84dSSaeed Mahameed 13571f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 135811f3b84dSSaeed Mahameed if (!devlink) { 13591f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 136011f3b84dSSaeed Mahameed return -ENOMEM; 136111f3b84dSSaeed Mahameed } 136211f3b84dSSaeed Mahameed 136311f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 136427b942fbSParav Pandit dev->device = &pdev->dev; 136527b942fbSParav Pandit dev->pdev = pdev; 136611f3b84dSSaeed Mahameed 1367386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1368386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1369386e75afSHuy Nguyen 1370a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 13714d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 13724d8be211SLeon Romanovsky err = dev->priv.adev_idx; 13734d8be211SLeon Romanovsky goto adev_init_err; 13744d8be211SLeon Romanovsky } 1375a925b5e3SLeon Romanovsky 137627b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 137711f3b84dSSaeed Mahameed if (err) 137811f3b84dSSaeed Mahameed goto mdev_init_err; 137911f3b84dSSaeed Mahameed 138011f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 13819603b61dSJack Morgenstein if (err) { 138298a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 138398a8e6fcSHuy Nguyen err); 138411f3b84dSSaeed Mahameed goto pci_init_err; 13859603b61dSJack Morgenstein } 13869603b61dSJack Morgenstein 1387868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13889603b61dSJack Morgenstein if (err) { 138998a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 139098a8e6fcSHuy Nguyen err); 13910cf53c12SSaeed Mahameed goto err_load_one; 13929603b61dSJack Morgenstein } 139359211bd3SMohamad Haj Yahia 13948b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13958b9d8baaSAlex Vesker if (err) 13968b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13978b9d8baaSAlex Vesker 13985d47f6c8SDaniel Jurgens pci_save_state(pdev); 1399*d89ddaaeSShay Drory if (!mlx5_core_is_mp_slave(dev)) 140060904cd3SParav Pandit devlink_reload_enable(devlink); 14019603b61dSJack Morgenstein return 0; 14029603b61dSJack Morgenstein 14030cf53c12SSaeed Mahameed err_load_one: 1404868bc06bSSaeed Mahameed mlx5_pci_close(dev); 140511f3b84dSSaeed Mahameed pci_init_err: 140611f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 140711f3b84dSSaeed Mahameed mdev_init_err: 1408a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14094d8be211SLeon Romanovsky adev_init_err: 14101f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1411a31208b1SMajd Dibbiny 14129603b61dSJack Morgenstein return err; 14139603b61dSJack Morgenstein } 1414a31208b1SMajd Dibbiny 14159603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 14169603b61dSJack Morgenstein { 14179603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1418feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 14199603b61dSJack Morgenstein 142060904cd3SParav Pandit devlink_reload_disable(devlink); 14218b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 142241798df9SParav Pandit mlx5_drain_health_wq(dev); 1423f999b706SParav Pandit mlx5_unload_one(dev, true); 1424868bc06bSSaeed Mahameed mlx5_pci_close(dev); 142511f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1426a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14271f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 14289603b61dSJack Morgenstein } 14299603b61dSJack Morgenstein 143089d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 143189d44f0aSMajd Dibbiny pci_channel_state_t state) 143289d44f0aSMajd Dibbiny { 143389d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 143489d44f0aSMajd Dibbiny 143598a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 143604c0c1abSMohamad Haj Yahia 14378812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 14383e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1439868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 14405e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 144189d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 144205ac2c0bSMohamad Haj Yahia 144389d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 144489d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 144589d44f0aSMajd Dibbiny } 144689d44f0aSMajd Dibbiny 1447d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1448d57847dcSDaniel Jurgens * for the health counter to start counting. 144989d44f0aSMajd Dibbiny */ 1450d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 145189d44f0aSMajd Dibbiny { 145289d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 145389d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 145489d44f0aSMajd Dibbiny const int niter = 100; 1455d57847dcSDaniel Jurgens u32 last_count = 0; 145689d44f0aSMajd Dibbiny u32 count; 145789d44f0aSMajd Dibbiny int i; 145889d44f0aSMajd Dibbiny 145989d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 146089d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 146189d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1462d57847dcSDaniel Jurgens if (last_count && last_count != count) { 146398a8e6fcSHuy Nguyen mlx5_core_info(dev, 146498a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 146598a8e6fcSHuy Nguyen count, i); 1466d57847dcSDaniel Jurgens return 0; 1467d57847dcSDaniel Jurgens } 1468d57847dcSDaniel Jurgens last_count = count; 146989d44f0aSMajd Dibbiny } 147089d44f0aSMajd Dibbiny msleep(50); 147189d44f0aSMajd Dibbiny } 147289d44f0aSMajd Dibbiny 1473d57847dcSDaniel Jurgens return -ETIMEDOUT; 147489d44f0aSMajd Dibbiny } 147589d44f0aSMajd Dibbiny 14761061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14771061c90fSMohamad Haj Yahia { 14781061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14791061c90fSMohamad Haj Yahia int err; 14801061c90fSMohamad Haj Yahia 148198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14821061c90fSMohamad Haj Yahia 14831061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14841061c90fSMohamad Haj Yahia if (err) { 148598a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 148698a8e6fcSHuy Nguyen __func__, err); 14871061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14881061c90fSMohamad Haj Yahia } 14891061c90fSMohamad Haj Yahia 14901061c90fSMohamad Haj Yahia pci_set_master(pdev); 14911061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14925d47f6c8SDaniel Jurgens pci_save_state(pdev); 14931061c90fSMohamad Haj Yahia 14941061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 149598a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14961061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14971061c90fSMohamad Haj Yahia } 14981061c90fSMohamad Haj Yahia 14991061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 15001061c90fSMohamad Haj Yahia } 15011061c90fSMohamad Haj Yahia 150289d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 150389d44f0aSMajd Dibbiny { 150489d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 150589d44f0aSMajd Dibbiny int err; 150689d44f0aSMajd Dibbiny 150798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 150889d44f0aSMajd Dibbiny 1509868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 151089d44f0aSMajd Dibbiny if (err) 151198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 151298a8e6fcSHuy Nguyen __func__, err); 151389d44f0aSMajd Dibbiny else 151498a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 151589d44f0aSMajd Dibbiny } 151689d44f0aSMajd Dibbiny 151789d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 151889d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 151989d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 152089d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 152189d44f0aSMajd Dibbiny }; 152289d44f0aSMajd Dibbiny 15238812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 15248812c24dSMajd Dibbiny { 1525fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1526fcd29ad1SFeras Daoud int ret = 1; 15278812c24dSMajd Dibbiny 1528fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1529fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1530fcd29ad1SFeras Daoud 1531fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1532fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1533fcd29ad1SFeras Daoud 1534fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 15358812c24dSMajd Dibbiny return -EOPNOTSUPP; 15368812c24dSMajd Dibbiny 15378812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 15388812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 15398812c24dSMajd Dibbiny return -EAGAIN; 15408812c24dSMajd Dibbiny } 15418812c24dSMajd Dibbiny 1542d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1543d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1544d2aa060dSHuy Nguyen */ 1545d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 154676d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1547d2aa060dSHuy Nguyen 1548fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1549fcd29ad1SFeras Daoud if (!ret) 1550fcd29ad1SFeras Daoud goto succeed; 1551fcd29ad1SFeras Daoud 15528812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1553fcd29ad1SFeras Daoud if (!ret) 1554fcd29ad1SFeras Daoud goto succeed; 1555fcd29ad1SFeras Daoud 15568812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1557d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 15588812c24dSMajd Dibbiny return ret; 15598812c24dSMajd Dibbiny 1560fcd29ad1SFeras Daoud succeed: 15618812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 15628812c24dSMajd Dibbiny 15631ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 15641ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 15651ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 15661ef903bfSDaniel Jurgens * contexts. 15671ef903bfSDaniel Jurgens */ 15681ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 15691ef903bfSDaniel Jurgens 15708812c24dSMajd Dibbiny return 0; 15718812c24dSMajd Dibbiny } 15728812c24dSMajd Dibbiny 15735fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15745fc7197dSMajd Dibbiny { 15755fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15768812c24dSMajd Dibbiny int err; 15775fc7197dSMajd Dibbiny 157898a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15798812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15808812c24dSMajd Dibbiny if (err) 1581868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15825fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15835fc7197dSMajd Dibbiny } 15845fc7197dSMajd Dibbiny 15858fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 15868fc3e29bSMark Bloch { 15878fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15888fc3e29bSMark Bloch 15898fc3e29bSMark Bloch mlx5_unload_one(dev, false); 15908fc3e29bSMark Bloch 15918fc3e29bSMark Bloch return 0; 15928fc3e29bSMark Bloch } 15938fc3e29bSMark Bloch 15948fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 15958fc3e29bSMark Bloch { 15968fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15978fc3e29bSMark Bloch 15988fc3e29bSMark Bloch return mlx5_load_one(dev, false); 15998fc3e29bSMark Bloch } 16008fc3e29bSMark Bloch 16019603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1602bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1603fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1604bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1605fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1606bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1607fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 16087092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 160964dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1610d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1611d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1612d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1613d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 161485327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 161585327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1616b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1617505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 16182e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 16192e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1620d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1621dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 16229603b61dSJack Morgenstein { 0, } 16239603b61dSJack Morgenstein }; 16249603b61dSJack Morgenstein 16259603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 16269603b61dSJack Morgenstein 162704c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 162804c0c1abSMohamad Haj Yahia { 1629b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1630b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 163104c0c1abSMohamad Haj Yahia } 163204c0c1abSMohamad Haj Yahia 163304c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 163404c0c1abSMohamad Haj Yahia { 163504c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 163604c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 163704c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 163804c0c1abSMohamad Haj Yahia } 163904c0c1abSMohamad Haj Yahia 16409603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 164117a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 16429603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 16439603b61dSJack Morgenstein .probe = init_one, 164489d44f0aSMajd Dibbiny .remove = remove_one, 16458fc3e29bSMark Bloch .suspend = mlx5_suspend, 16468fc3e29bSMark Bloch .resume = mlx5_resume, 16475fc7197dSMajd Dibbiny .shutdown = shutdown, 1648fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1649fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 16509603b61dSJack Morgenstein }; 1651e126ba97SEli Cohen 1652f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1653f663ad98SKamal Heib { 1654f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1655f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1656f663ad98SKamal Heib prof_sel, 1657f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1658f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1659f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1660f663ad98SKamal Heib } 1661f663ad98SKamal Heib } 1662f663ad98SKamal Heib 1663e126ba97SEli Cohen static int __init init(void) 1664e126ba97SEli Cohen { 1665e126ba97SEli Cohen int err; 1666e126ba97SEli Cohen 166717a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 166817a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 166917a7612bSLeon Romanovsky 16708737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 16718737f818SDaniel Jurgens 1672f663ad98SKamal Heib mlx5_core_verify_params(); 16739a6ad1adSRaed Salem mlx5_fpga_ipsec_build_fs_cmds(); 1674e126ba97SEli Cohen mlx5_register_debugfs(); 1675e126ba97SEli Cohen 16769603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 16779603b61dSJack Morgenstein if (err) 1678ac6ea6e8SEli Cohen goto err_debug; 16799603b61dSJack Morgenstein 1680f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1681912cebf4SLeon Romanovsky err = mlx5e_init(); 1682912cebf4SLeon Romanovsky if (err) { 1683912cebf4SLeon Romanovsky pci_unregister_driver(&mlx5_core_driver); 1684912cebf4SLeon Romanovsky goto err_debug; 1685912cebf4SLeon Romanovsky } 1686f62b8bb8SAmir Vadai #endif 1687f62b8bb8SAmir Vadai 1688e126ba97SEli Cohen return 0; 1689e126ba97SEli Cohen 1690e126ba97SEli Cohen err_debug: 1691e126ba97SEli Cohen mlx5_unregister_debugfs(); 1692e126ba97SEli Cohen return err; 1693e126ba97SEli Cohen } 1694e126ba97SEli Cohen 1695e126ba97SEli Cohen static void __exit cleanup(void) 1696e126ba97SEli Cohen { 1697f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1698f62b8bb8SAmir Vadai mlx5e_cleanup(); 1699f62b8bb8SAmir Vadai #endif 17009603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1701e126ba97SEli Cohen mlx5_unregister_debugfs(); 1702e126ba97SEli Cohen } 1703e126ba97SEli Cohen 1704e126ba97SEli Cohen module_init(init); 1705e126ba97SEli Cohen module_exit(cleanup); 1706