1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 5952ec462eSIlan Tayari #include "lib/mlx5.h" 60e29341fbSIlan Tayari #include "fpga/core.h" 6105564d0aSAviad Yehezkel #include "fpga/ipsec.h" 62bebb23e6SIlan Tayari #include "accel/ipsec.h" 631ae17322SIlya Lesokhin #include "accel/tls.h" 647c39afb3SFeras Daoud #include "lib/clock.h" 65358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 66fadd59fcSAviv Heller #include "lib/devcom.h" 6724406953SFeras Daoud #include "diag/fw_tracer.h" 68e126ba97SEli Cohen 69e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 70048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 71e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 72e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 73e126ba97SEli Cohen 74f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 75f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 76e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 77e126ba97SEli Cohen 789603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 79f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 80f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 819603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 829603b61dSJack Morgenstein 838737f818SDaniel Jurgens static u32 sw_owner_id[4]; 848737f818SDaniel Jurgens 85f91e6d89SEran Ben Elisha enum { 86f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 87f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 88f91e6d89SEran Ben Elisha }; 89f91e6d89SEran Ben Elisha 909603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 919603b61dSJack Morgenstein [0] = { 929603b61dSJack Morgenstein .mask = 0, 939603b61dSJack Morgenstein }, 949603b61dSJack Morgenstein [1] = { 959603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 969603b61dSJack Morgenstein .log_max_qp = 12, 979603b61dSJack Morgenstein }, 989603b61dSJack Morgenstein [2] = { 999603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1009603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1015f40b4edSMaor Gottlieb .log_max_qp = 18, 1029603b61dSJack Morgenstein .mr_cache[0] = { 1039603b61dSJack Morgenstein .size = 500, 1049603b61dSJack Morgenstein .limit = 250 1059603b61dSJack Morgenstein }, 1069603b61dSJack Morgenstein .mr_cache[1] = { 1079603b61dSJack Morgenstein .size = 500, 1089603b61dSJack Morgenstein .limit = 250 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein .mr_cache[2] = { 1119603b61dSJack Morgenstein .size = 500, 1129603b61dSJack Morgenstein .limit = 250 1139603b61dSJack Morgenstein }, 1149603b61dSJack Morgenstein .mr_cache[3] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[4] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[5] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[6] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[7] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[8] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[9] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[10] = { 1439603b61dSJack Morgenstein .size = 500, 1449603b61dSJack Morgenstein .limit = 250 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[11] = { 1479603b61dSJack Morgenstein .size = 500, 1489603b61dSJack Morgenstein .limit = 250 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[12] = { 1519603b61dSJack Morgenstein .size = 64, 1529603b61dSJack Morgenstein .limit = 32 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[13] = { 1559603b61dSJack Morgenstein .size = 32, 1569603b61dSJack Morgenstein .limit = 16 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein .mr_cache[14] = { 1599603b61dSJack Morgenstein .size = 16, 1609603b61dSJack Morgenstein .limit = 8 1619603b61dSJack Morgenstein }, 1629603b61dSJack Morgenstein .mr_cache[15] = { 1639603b61dSJack Morgenstein .size = 8, 1649603b61dSJack Morgenstein .limit = 4 1659603b61dSJack Morgenstein }, 1667d0cc6edSArtemy Kovalyov .mr_cache[16] = { 1677d0cc6edSArtemy Kovalyov .size = 8, 1687d0cc6edSArtemy Kovalyov .limit = 4 1697d0cc6edSArtemy Kovalyov }, 1707d0cc6edSArtemy Kovalyov .mr_cache[17] = { 1717d0cc6edSArtemy Kovalyov .size = 8, 1727d0cc6edSArtemy Kovalyov .limit = 4 1737d0cc6edSArtemy Kovalyov }, 1747d0cc6edSArtemy Kovalyov .mr_cache[18] = { 1757d0cc6edSArtemy Kovalyov .size = 8, 1767d0cc6edSArtemy Kovalyov .limit = 4 1777d0cc6edSArtemy Kovalyov }, 1787d0cc6edSArtemy Kovalyov .mr_cache[19] = { 1797d0cc6edSArtemy Kovalyov .size = 4, 1807d0cc6edSArtemy Kovalyov .limit = 2 1817d0cc6edSArtemy Kovalyov }, 1827d0cc6edSArtemy Kovalyov .mr_cache[20] = { 1837d0cc6edSArtemy Kovalyov .size = 4, 1847d0cc6edSArtemy Kovalyov .limit = 2 1857d0cc6edSArtemy Kovalyov }, 1869603b61dSJack Morgenstein }, 1879603b61dSJack Morgenstein }; 188e126ba97SEli Cohen 189e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 190e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 1916c780a02SEli Cohen #define FW_PRE_INIT_TIMEOUT_MILI 10000 192e3297246SEli Cohen 193e3297246SEli Cohen static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 194e3297246SEli Cohen { 195e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 196e3297246SEli Cohen int err = 0; 197e3297246SEli Cohen 198e3297246SEli Cohen while (fw_initializing(dev)) { 199e3297246SEli Cohen if (time_after(jiffies, end)) { 200e3297246SEli Cohen err = -EBUSY; 201e3297246SEli Cohen break; 202e3297246SEli Cohen } 203e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 204e3297246SEli Cohen } 205e3297246SEli Cohen 206e3297246SEli Cohen return err; 207e3297246SEli Cohen } 208e3297246SEli Cohen 209012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 210012e50e1SHuy Nguyen { 211012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 212012e50e1SHuy Nguyen driver_version); 213012e50e1SHuy Nguyen u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 214012e50e1SHuy Nguyen u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 215012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 216012e50e1SHuy Nguyen char *string; 217012e50e1SHuy Nguyen 218012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 219012e50e1SHuy Nguyen return; 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 222012e50e1SHuy Nguyen 223012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 224012e50e1SHuy Nguyen 225012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 226012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen /*Send the command*/ 238012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 239012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 240012e50e1SHuy Nguyen 241012e50e1SHuy Nguyen mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 242012e50e1SHuy Nguyen } 243012e50e1SHuy Nguyen 244e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 245e126ba97SEli Cohen { 246e126ba97SEli Cohen int err; 247e126ba97SEli Cohen 248e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 249e126ba97SEli Cohen if (err) { 2501a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 251e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 252e126ba97SEli Cohen if (err) { 2531a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 254e126ba97SEli Cohen return err; 255e126ba97SEli Cohen } 256e126ba97SEli Cohen } 257e126ba97SEli Cohen 258e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 259e126ba97SEli Cohen if (err) { 260e126ba97SEli Cohen dev_warn(&pdev->dev, 2611a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 262e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 263e126ba97SEli Cohen if (err) { 264e126ba97SEli Cohen dev_err(&pdev->dev, 2651a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 266e126ba97SEli Cohen return err; 267e126ba97SEli Cohen } 268e126ba97SEli Cohen } 269e126ba97SEli Cohen 270e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 271e126ba97SEli Cohen return err; 272e126ba97SEli Cohen } 273e126ba97SEli Cohen 27489d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27589d44f0aSMajd Dibbiny { 27689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27789d44f0aSMajd Dibbiny int err = 0; 27889d44f0aSMajd Dibbiny 27989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 28189d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 28289d44f0aSMajd Dibbiny if (!err) 28389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28489d44f0aSMajd Dibbiny } 28589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28689d44f0aSMajd Dibbiny 28789d44f0aSMajd Dibbiny return err; 28889d44f0aSMajd Dibbiny } 28989d44f0aSMajd Dibbiny 29089d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 29189d44f0aSMajd Dibbiny { 29289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29389d44f0aSMajd Dibbiny 29489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29689d44f0aSMajd Dibbiny pci_disable_device(pdev); 29789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29889d44f0aSMajd Dibbiny } 29989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 30089d44f0aSMajd Dibbiny } 30189d44f0aSMajd Dibbiny 302e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 303e126ba97SEli Cohen { 304e126ba97SEli Cohen int err = 0; 305e126ba97SEli Cohen 306e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3071a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 308e126ba97SEli Cohen return -ENODEV; 309e126ba97SEli Cohen } 310e126ba97SEli Cohen 311e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 312e126ba97SEli Cohen if (err) 313e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 314e126ba97SEli Cohen 315e126ba97SEli Cohen return err; 316e126ba97SEli Cohen } 317e126ba97SEli Cohen 318e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 319e126ba97SEli Cohen { 320e126ba97SEli Cohen pci_release_regions(pdev); 321e126ba97SEli Cohen } 322e126ba97SEli Cohen 323bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 324e126ba97SEli Cohen u8 he; 325e126ba97SEli Cohen u8 rsvd[15]; 326e126ba97SEli Cohen }; 327e126ba97SEli Cohen 32887b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32987b8de49SEli Cohen 33087b8de49SEli Cohen enum { 33187b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 332c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 33387b8de49SEli Cohen }; 33487b8de49SEli Cohen 3352974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 336c7a08ac7SEli Cohen { 337c7a08ac7SEli Cohen switch (size) { 338c7a08ac7SEli Cohen case 128: 339c7a08ac7SEli Cohen return 0; 340c7a08ac7SEli Cohen case 256: 341c7a08ac7SEli Cohen return 1; 342c7a08ac7SEli Cohen case 512: 343c7a08ac7SEli Cohen return 2; 344c7a08ac7SEli Cohen case 1024: 345c7a08ac7SEli Cohen return 3; 346c7a08ac7SEli Cohen case 2048: 347c7a08ac7SEli Cohen return 4; 348c7a08ac7SEli Cohen case 4096: 349c7a08ac7SEli Cohen return 5; 350c7a08ac7SEli Cohen default: 3512974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 352c7a08ac7SEli Cohen return 0; 353c7a08ac7SEli Cohen } 354c7a08ac7SEli Cohen } 355c7a08ac7SEli Cohen 356b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 357b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 358938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 359c7a08ac7SEli Cohen { 360b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 361b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 362938fe83cSSaeed Mahameed void *out, *hca_caps; 363938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 364c7a08ac7SEli Cohen int err; 365c7a08ac7SEli Cohen 366b775516bSEli Cohen memset(in, 0, sizeof(in)); 367b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 368c7a08ac7SEli Cohen if (!out) 369c7a08ac7SEli Cohen return -ENOMEM; 370938fe83cSSaeed Mahameed 371b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 372b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 373b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 374c7a08ac7SEli Cohen if (err) { 375938fe83cSSaeed Mahameed mlx5_core_warn(dev, 376938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 377938fe83cSSaeed Mahameed cap_type, cap_mode, err); 378c7a08ac7SEli Cohen goto query_ex; 379c7a08ac7SEli Cohen } 380c7a08ac7SEli Cohen 381938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 382938fe83cSSaeed Mahameed 383938fe83cSSaeed Mahameed switch (cap_mode) { 384938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 385701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 386938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 387938fe83cSSaeed Mahameed break; 388938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 389701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 390938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 391938fe83cSSaeed Mahameed break; 392938fe83cSSaeed Mahameed default: 393938fe83cSSaeed Mahameed mlx5_core_warn(dev, 394938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 395938fe83cSSaeed Mahameed cap_type, cap_mode); 396938fe83cSSaeed Mahameed err = -EINVAL; 397938fe83cSSaeed Mahameed break; 398938fe83cSSaeed Mahameed } 399c7a08ac7SEli Cohen query_ex: 400c7a08ac7SEli Cohen kfree(out); 401c7a08ac7SEli Cohen return err; 402c7a08ac7SEli Cohen } 403c7a08ac7SEli Cohen 404b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 405b06e7de8SLeon Romanovsky { 406b06e7de8SLeon Romanovsky int ret; 407b06e7de8SLeon Romanovsky 408b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 409b06e7de8SLeon Romanovsky if (ret) 410b06e7de8SLeon Romanovsky return ret; 411b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 412b06e7de8SLeon Romanovsky } 413b06e7de8SLeon Romanovsky 414f91e6d89SEran Ben Elisha static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 415c7a08ac7SEli Cohen { 416c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 417c7a08ac7SEli Cohen 418b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 419f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 420c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 421c7a08ac7SEli Cohen } 42287b8de49SEli Cohen 423f91e6d89SEran Ben Elisha static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 424f91e6d89SEran Ben Elisha { 425f91e6d89SEran Ben Elisha void *set_ctx; 426f91e6d89SEran Ben Elisha void *set_hca_cap; 427f91e6d89SEran Ben Elisha int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 428f91e6d89SEran Ben Elisha int req_endianness; 429f91e6d89SEran Ben Elisha int err; 430f91e6d89SEran Ben Elisha 431f91e6d89SEran Ben Elisha if (MLX5_CAP_GEN(dev, atomic)) { 432b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 433f91e6d89SEran Ben Elisha if (err) 434f91e6d89SEran Ben Elisha return err; 435f91e6d89SEran Ben Elisha } else { 436f91e6d89SEran Ben Elisha return 0; 437f91e6d89SEran Ben Elisha } 438f91e6d89SEran Ben Elisha 439f91e6d89SEran Ben Elisha req_endianness = 440f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 441bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 442f91e6d89SEran Ben Elisha 443f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 444f91e6d89SEran Ben Elisha return 0; 445f91e6d89SEran Ben Elisha 446f91e6d89SEran Ben Elisha set_ctx = kzalloc(set_sz, GFP_KERNEL); 447f91e6d89SEran Ben Elisha if (!set_ctx) 448f91e6d89SEran Ben Elisha return -ENOMEM; 449f91e6d89SEran Ben Elisha 450f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 451f91e6d89SEran Ben Elisha 452f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 453bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 454f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 455f91e6d89SEran Ben Elisha 456f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 457f91e6d89SEran Ben Elisha 458f91e6d89SEran Ben Elisha kfree(set_ctx); 459f91e6d89SEran Ben Elisha return err; 460f91e6d89SEran Ben Elisha } 461f91e6d89SEran Ben Elisha 462e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 463e126ba97SEli Cohen { 464b775516bSEli Cohen void *set_ctx = NULL; 465c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 466c7a08ac7SEli Cohen int err = -ENOMEM; 467b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 468938fe83cSSaeed Mahameed void *set_hca_cap; 469e126ba97SEli Cohen 470b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 471c7a08ac7SEli Cohen if (!set_ctx) 472e126ba97SEli Cohen goto query_ex; 473e126ba97SEli Cohen 474b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 475c7a08ac7SEli Cohen if (err) 476e126ba97SEli Cohen goto query_ex; 477e126ba97SEli Cohen 478938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 479938fe83cSSaeed Mahameed capability); 480701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 481938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 482938fe83cSSaeed Mahameed 483938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 484707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 485938fe83cSSaeed Mahameed 128); 486c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 487938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 4882974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 489e126ba97SEli Cohen 490883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 491883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 492883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 493883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 494883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 495883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 496883371c4SNoa Osherovich } 497c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 498938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 499938fe83cSSaeed Mahameed prof->log_max_qp); 500e126ba97SEli Cohen 501938fe83cSSaeed Mahameed /* disable cmdif checksum */ 502938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 503c1868b82SEli Cohen 50491828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 50591828bd8SMajd Dibbiny * than 4K. 50691828bd8SMajd Dibbiny */ 50791828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 508f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 509f502d834SEli Cohen 510fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 511fe1e1876SCarol L Soto 512f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 513f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 514f32f5bd2SDaniel Jurgens set_hca_cap, 515f32f5bd2SDaniel Jurgens cache_line_128byte, 516c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 517f32f5bd2SDaniel Jurgens 518dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 519dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 520dd44572aSMoni Shoua 521c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 522c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 523c4b76d8dSDaniel Jurgens set_hca_cap, 524c4b76d8dSDaniel Jurgens num_vhca_ports, 525c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 526c4b76d8dSDaniel Jurgens 527f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, 528f91e6d89SEran Ben Elisha MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 529e126ba97SEli Cohen 530e126ba97SEli Cohen query_ex: 531e126ba97SEli Cohen kfree(set_ctx); 532e126ba97SEli Cohen return err; 533e126ba97SEli Cohen } 534e126ba97SEli Cohen 535e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 536e126ba97SEli Cohen { 537bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 538bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 539e126ba97SEli Cohen int err; 540e126ba97SEli Cohen 541fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 542fc50db98SEli Cohen return 0; 543fc50db98SEli Cohen 544e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 545e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 546e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 547e126ba97SEli Cohen &he_out, sizeof(he_out), 548e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 549e126ba97SEli Cohen return err; 550e126ba97SEli Cohen } 551e126ba97SEli Cohen 552c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 553c85023e1SHuy Nguyen { 554c85023e1SHuy Nguyen int ret = 0; 555c85023e1SHuy Nguyen 556c85023e1SHuy Nguyen /* Disable local_lb by default */ 5578978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 558c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 559c85023e1SHuy Nguyen 560c85023e1SHuy Nguyen return ret; 561c85023e1SHuy Nguyen } 562c85023e1SHuy Nguyen 5630b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 564cd23b14bSEli Cohen { 565c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 566c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 567cd23b14bSEli Cohen 5680b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 5690b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 570c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 571cd23b14bSEli Cohen } 572cd23b14bSEli Cohen 5730b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 574cd23b14bSEli Cohen { 575c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 576c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 577cd23b14bSEli Cohen 5780b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 5790b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 580c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 581cd23b14bSEli Cohen } 582cd23b14bSEli Cohen 5834a0475d5SMiroslav Lichvar u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 5844a0475d5SMiroslav Lichvar struct ptp_system_timestamp *sts) 585b0844444SEran Ben Elisha { 586b0844444SEran Ben Elisha u32 timer_h, timer_h1, timer_l; 587b0844444SEran Ben Elisha 588b0844444SEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 5894a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 590b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 5914a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 592b0844444SEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 5934a0475d5SMiroslav Lichvar if (timer_h != timer_h1) { 5944a0475d5SMiroslav Lichvar /* wrap around */ 5954a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 596b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 5974a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 5984a0475d5SMiroslav Lichvar } 599b0844444SEran Ben Elisha 600a5a1d1c2SThomas Gleixner return (u64)timer_l | (u64)timer_h1 << 32; 601b0844444SEran Ben Elisha } 602b0844444SEran Ben Elisha 603f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 604f62b8bb8SAmir Vadai { 605c4f287c4SSaeed Mahameed u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 606c4f287c4SSaeed Mahameed u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 607f62b8bb8SAmir Vadai u32 sup_issi; 608c4f287c4SSaeed Mahameed int err; 609f62b8bb8SAmir Vadai 610f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 611c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 612f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 613f62b8bb8SAmir Vadai if (err) { 614c4f287c4SSaeed Mahameed u32 syndrome; 615c4f287c4SSaeed Mahameed u8 status; 616c4f287c4SSaeed Mahameed 617c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 618f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 619f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 620f9c14e46SKamal Heib err, status, syndrome); 621f9c14e46SKamal Heib return err; 622f62b8bb8SAmir Vadai } 623f62b8bb8SAmir Vadai 624f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 625f9c14e46SKamal Heib dev->issi = 0; 626f9c14e46SKamal Heib return 0; 627f62b8bb8SAmir Vadai } 628f62b8bb8SAmir Vadai 629f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 630f62b8bb8SAmir Vadai 631f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 632c4f287c4SSaeed Mahameed u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 633c4f287c4SSaeed Mahameed u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 634f62b8bb8SAmir Vadai 635f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 636f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 637c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 638f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 639f62b8bb8SAmir Vadai if (err) { 640f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 641f9c14e46SKamal Heib err); 642f62b8bb8SAmir Vadai return err; 643f62b8bb8SAmir Vadai } 644f62b8bb8SAmir Vadai 645f62b8bb8SAmir Vadai dev->issi = 1; 646f62b8bb8SAmir Vadai 647f62b8bb8SAmir Vadai return 0; 648e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 649f62b8bb8SAmir Vadai return 0; 650f62b8bb8SAmir Vadai } 651f62b8bb8SAmir Vadai 6529eb78923SOr Gerlitz return -EOPNOTSUPP; 653f62b8bb8SAmir Vadai } 654f62b8bb8SAmir Vadai 655a31208b1SMajd Dibbiny static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 656a31208b1SMajd Dibbiny { 657a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 658a31208b1SMajd Dibbiny int err = 0; 659a31208b1SMajd Dibbiny 660e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 661e126ba97SEli Cohen strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 662e126ba97SEli Cohen priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 663e126ba97SEli Cohen 664e126ba97SEli Cohen mutex_init(&priv->pgdir_mutex); 665e126ba97SEli Cohen INIT_LIST_HEAD(&priv->pgdir_list); 666e126ba97SEli Cohen spin_lock_init(&priv->mkey_lock); 667e126ba97SEli Cohen 668311c7c71SSaeed Mahameed mutex_init(&priv->alloc_mutex); 669311c7c71SSaeed Mahameed 670311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 671311c7c71SSaeed Mahameed 672199fa087SLeon Romanovsky if (mlx5_debugfs_root) 673199fa087SLeon Romanovsky priv->dbg_root = 674199fa087SLeon Romanovsky debugfs_create_dir(pci_name(pdev), mlx5_debugfs_root); 675e126ba97SEli Cohen 67689d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 677e126ba97SEli Cohen if (err) { 6781a91de28SJoe Perches dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 679e126ba97SEli Cohen goto err_dbg; 680e126ba97SEli Cohen } 681e126ba97SEli Cohen 682e126ba97SEli Cohen err = request_bar(pdev); 683e126ba97SEli Cohen if (err) { 6841a91de28SJoe Perches dev_err(&pdev->dev, "error requesting BARs, aborting\n"); 685e126ba97SEli Cohen goto err_disable; 686e126ba97SEli Cohen } 687e126ba97SEli Cohen 688e126ba97SEli Cohen pci_set_master(pdev); 689e126ba97SEli Cohen 690e126ba97SEli Cohen err = set_dma_caps(pdev); 691e126ba97SEli Cohen if (err) { 692e126ba97SEli Cohen dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); 693e126ba97SEli Cohen goto err_clr_master; 694e126ba97SEli Cohen } 695e126ba97SEli Cohen 696ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 697ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 698ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 699ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 700ce4eee53SMichael Guralnik 701e126ba97SEli Cohen dev->iseg_base = pci_resource_start(dev->pdev, 0); 702e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 703e126ba97SEli Cohen if (!dev->iseg) { 704e126ba97SEli Cohen err = -ENOMEM; 705e126ba97SEli Cohen dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); 706e126ba97SEli Cohen goto err_clr_master; 707e126ba97SEli Cohen } 708a31208b1SMajd Dibbiny 709a31208b1SMajd Dibbiny return 0; 710a31208b1SMajd Dibbiny 711a31208b1SMajd Dibbiny err_clr_master: 712a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 713a31208b1SMajd Dibbiny release_bar(dev->pdev); 714a31208b1SMajd Dibbiny err_disable: 71589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 716a31208b1SMajd Dibbiny 717a31208b1SMajd Dibbiny err_dbg: 718a31208b1SMajd Dibbiny debugfs_remove(priv->dbg_root); 719a31208b1SMajd Dibbiny return err; 720a31208b1SMajd Dibbiny } 721a31208b1SMajd Dibbiny 722a31208b1SMajd Dibbiny static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 723a31208b1SMajd Dibbiny { 724a31208b1SMajd Dibbiny iounmap(dev->iseg); 725a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 726a31208b1SMajd Dibbiny release_bar(dev->pdev); 72789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 7285df816e7SJack Morgenstein debugfs_remove_recursive(priv->dbg_root); 729a31208b1SMajd Dibbiny } 730a31208b1SMajd Dibbiny 73159211bd3SMohamad Haj Yahia static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 73259211bd3SMohamad Haj Yahia { 73359211bd3SMohamad Haj Yahia struct pci_dev *pdev = dev->pdev; 73459211bd3SMohamad Haj Yahia int err; 73559211bd3SMohamad Haj Yahia 736fadd59fcSAviv Heller priv->devcom = mlx5_devcom_register_device(dev); 737fadd59fcSAviv Heller if (IS_ERR(priv->devcom)) 738fadd59fcSAviv Heller dev_err(&pdev->dev, "failed to register with devcom (0x%p)\n", 739fadd59fcSAviv Heller priv->devcom); 740fadd59fcSAviv Heller 74159211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 74259211bd3SMohamad Haj Yahia if (err) { 74359211bd3SMohamad Haj Yahia dev_err(&pdev->dev, "query board id failed\n"); 744fadd59fcSAviv Heller goto err_devcom; 74559211bd3SMohamad Haj Yahia } 74659211bd3SMohamad Haj Yahia 747f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 74859211bd3SMohamad Haj Yahia if (err) { 74959211bd3SMohamad Haj Yahia dev_err(&pdev->dev, "failed to initialize eq\n"); 750fadd59fcSAviv Heller goto err_devcom; 75159211bd3SMohamad Haj Yahia } 75259211bd3SMohamad Haj Yahia 75369c1280bSSaeed Mahameed err = mlx5_events_init(dev); 75469c1280bSSaeed Mahameed if (err) { 75569c1280bSSaeed Mahameed dev_err(&pdev->dev, "failed to initialize events\n"); 75669c1280bSSaeed Mahameed goto err_eq_cleanup; 75769c1280bSSaeed Mahameed } 75869c1280bSSaeed Mahameed 75902d92f79SSaeed Mahameed err = mlx5_cq_debugfs_init(dev); 76059211bd3SMohamad Haj Yahia if (err) { 76102d92f79SSaeed Mahameed dev_err(&pdev->dev, "failed to initialize cq debugfs\n"); 76269c1280bSSaeed Mahameed goto err_events_cleanup; 76359211bd3SMohamad Haj Yahia } 76459211bd3SMohamad Haj Yahia 76559211bd3SMohamad Haj Yahia mlx5_init_qp_table(dev); 76659211bd3SMohamad Haj Yahia 76759211bd3SMohamad Haj Yahia mlx5_init_mkey_table(dev); 76859211bd3SMohamad Haj Yahia 76952ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 77052ec462eSIlan Tayari 7717c39afb3SFeras Daoud mlx5_init_clock(dev); 7727c39afb3SFeras Daoud 773358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 774358aa5ceSSaeed Mahameed 77559211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 77659211bd3SMohamad Haj Yahia if (err) { 77759211bd3SMohamad Haj Yahia dev_err(&pdev->dev, "Failed to init rate limiting\n"); 77859211bd3SMohamad Haj Yahia goto err_tables_cleanup; 77959211bd3SMohamad Haj Yahia } 78059211bd3SMohamad Haj Yahia 781eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 782eeb66cdbSSaeed Mahameed if (err) { 783eeb66cdbSSaeed Mahameed dev_err(&pdev->dev, "Failed to init l2 table %d\n", err); 784eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 785eeb66cdbSSaeed Mahameed } 786eeb66cdbSSaeed Mahameed 787c2d6e31aSMohamad Haj Yahia err = mlx5_eswitch_init(dev); 788c2d6e31aSMohamad Haj Yahia if (err) { 789c2d6e31aSMohamad Haj Yahia dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); 790eeb66cdbSSaeed Mahameed goto err_mpfs_cleanup; 791c2d6e31aSMohamad Haj Yahia } 792c2d6e31aSMohamad Haj Yahia 793c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 794c2d6e31aSMohamad Haj Yahia if (err) { 795c2d6e31aSMohamad Haj Yahia dev_err(&pdev->dev, "Failed to init sriov %d\n", err); 796c2d6e31aSMohamad Haj Yahia goto err_eswitch_cleanup; 797c2d6e31aSMohamad Haj Yahia } 798c2d6e31aSMohamad Haj Yahia 7999410733cSIlan Tayari err = mlx5_fpga_init(dev); 8009410733cSIlan Tayari if (err) { 8019410733cSIlan Tayari dev_err(&pdev->dev, "Failed to init fpga device %d\n", err); 8029410733cSIlan Tayari goto err_sriov_cleanup; 8039410733cSIlan Tayari } 8049410733cSIlan Tayari 80524406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 80624406953SFeras Daoud 80759211bd3SMohamad Haj Yahia return 0; 80859211bd3SMohamad Haj Yahia 8099410733cSIlan Tayari err_sriov_cleanup: 8109410733cSIlan Tayari mlx5_sriov_cleanup(dev); 811c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 812c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 813eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 814eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 815c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 816c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 81759211bd3SMohamad Haj Yahia err_tables_cleanup: 818358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 81959211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 82059211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 82102d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 82269c1280bSSaeed Mahameed err_events_cleanup: 82369c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 82459211bd3SMohamad Haj Yahia err_eq_cleanup: 825f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 826fadd59fcSAviv Heller err_devcom: 827fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 82859211bd3SMohamad Haj Yahia 82959211bd3SMohamad Haj Yahia return err; 83059211bd3SMohamad Haj Yahia } 83159211bd3SMohamad Haj Yahia 83259211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 83359211bd3SMohamad Haj Yahia { 83424406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 8359410733cSIlan Tayari mlx5_fpga_cleanup(dev); 836c2d6e31aSMohamad Haj Yahia mlx5_sriov_cleanup(dev); 837c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 838eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 83959211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 840358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 8417c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 84252ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 84359211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 84459211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 84502d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 84669c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 847f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 848fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 84959211bd3SMohamad Haj Yahia } 85059211bd3SMohamad Haj Yahia 85159211bd3SMohamad Haj Yahia static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 85259211bd3SMohamad Haj Yahia bool boot) 853a31208b1SMajd Dibbiny { 854a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 855a31208b1SMajd Dibbiny int err; 856a31208b1SMajd Dibbiny 85789d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 8585fc7197dSMajd Dibbiny if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 85989d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 86089d44f0aSMajd Dibbiny __func__); 86189d44f0aSMajd Dibbiny goto out; 86289d44f0aSMajd Dibbiny } 86389d44f0aSMajd Dibbiny 864e126ba97SEli Cohen dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 865e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 866e126ba97SEli Cohen 86700c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 86800c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 86900c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 87000c6bcb0STal Gilboa 87189d44f0aSMajd Dibbiny /* on load removing any previous indication of internal error, device is 87289d44f0aSMajd Dibbiny * up 87389d44f0aSMajd Dibbiny */ 87489d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_UP; 87589d44f0aSMajd Dibbiny 8766c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 8776c780a02SEli Cohen */ 8786c780a02SEli Cohen err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); 8796c780a02SEli Cohen if (err) { 8806c780a02SEli Cohen dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n", 8816c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 8828ce59b16SGal Pressman goto out_err; 8836c780a02SEli Cohen } 8846c780a02SEli Cohen 885e126ba97SEli Cohen err = mlx5_cmd_init(dev); 886e126ba97SEli Cohen if (err) { 887e126ba97SEli Cohen dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); 88889d44f0aSMajd Dibbiny goto out_err; 889e126ba97SEli Cohen } 890e126ba97SEli Cohen 891e3297246SEli Cohen err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 892e3297246SEli Cohen if (err) { 893e3297246SEli Cohen dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", 894e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 89555378a23SMohamad Haj Yahia goto err_cmd_cleanup; 896e3297246SEli Cohen } 897e3297246SEli Cohen 8980b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 899cd23b14bSEli Cohen if (err) { 900cd23b14bSEli Cohen dev_err(&pdev->dev, "enable hca failed\n"); 90159211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 902cd23b14bSEli Cohen } 903cd23b14bSEli Cohen 904f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 905f62b8bb8SAmir Vadai if (err) { 906f62b8bb8SAmir Vadai dev_err(&pdev->dev, "failed to set issi\n"); 907f62b8bb8SAmir Vadai goto err_disable_hca; 908f62b8bb8SAmir Vadai } 909f62b8bb8SAmir Vadai 910cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 911cd23b14bSEli Cohen if (err) { 912cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate boot pages\n"); 913cd23b14bSEli Cohen goto err_disable_hca; 914cd23b14bSEli Cohen } 915cd23b14bSEli Cohen 916e126ba97SEli Cohen err = set_hca_ctrl(dev); 917e126ba97SEli Cohen if (err) { 918e126ba97SEli Cohen dev_err(&pdev->dev, "set_hca_ctrl failed\n"); 919cd23b14bSEli Cohen goto reclaim_boot_pages; 920e126ba97SEli Cohen } 921e126ba97SEli Cohen 922e126ba97SEli Cohen err = handle_hca_cap(dev); 923e126ba97SEli Cohen if (err) { 924e126ba97SEli Cohen dev_err(&pdev->dev, "handle_hca_cap failed\n"); 925cd23b14bSEli Cohen goto reclaim_boot_pages; 926e126ba97SEli Cohen } 927e126ba97SEli Cohen 928f91e6d89SEran Ben Elisha err = handle_hca_cap_atomic(dev); 929f91e6d89SEran Ben Elisha if (err) { 930f91e6d89SEran Ben Elisha dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); 931f91e6d89SEran Ben Elisha goto reclaim_boot_pages; 932f91e6d89SEran Ben Elisha } 933f91e6d89SEran Ben Elisha 934cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 935e126ba97SEli Cohen if (err) { 936cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate init pages\n"); 937cd23b14bSEli Cohen goto reclaim_boot_pages; 938e126ba97SEli Cohen } 939e126ba97SEli Cohen 9408737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 941e126ba97SEli Cohen if (err) { 942e126ba97SEli Cohen dev_err(&pdev->dev, "init hca failed\n"); 9430cf53c12SSaeed Mahameed goto reclaim_boot_pages; 944e126ba97SEli Cohen } 945e126ba97SEli Cohen 946012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 947012e50e1SHuy Nguyen 948e126ba97SEli Cohen mlx5_start_health_poll(dev); 949e126ba97SEli Cohen 950bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 951bba1574cSDaniel Jurgens if (err) { 952bba1574cSDaniel Jurgens dev_err(&pdev->dev, "query hca failed\n"); 953bba1574cSDaniel Jurgens goto err_stop_poll; 954bba1574cSDaniel Jurgens } 955bba1574cSDaniel Jurgens 956259bbc57SMaor Gottlieb if (boot) { 957259bbc57SMaor Gottlieb err = mlx5_init_once(dev, priv); 958259bbc57SMaor Gottlieb if (err) { 95959211bd3SMohamad Haj Yahia dev_err(&pdev->dev, "sw objs init failed\n"); 960e126ba97SEli Cohen goto err_stop_poll; 961e126ba97SEli Cohen } 962259bbc57SMaor Gottlieb } 963e126ba97SEli Cohen 96401187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 96572f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 966e126ba97SEli Cohen dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); 96772f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 968c8e21b3bSSaeed Mahameed goto err_get_uars; 969e126ba97SEli Cohen } 970e126ba97SEli Cohen 97169c1280bSSaeed Mahameed mlx5_events_start(dev); 9720cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 9730cf53c12SSaeed Mahameed 974c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 975e126ba97SEli Cohen if (err) { 976c8e21b3bSSaeed Mahameed dev_err(&pdev->dev, "Failed to create EQs\n"); 977c8e21b3bSSaeed Mahameed goto err_eq_table; 978e126ba97SEli Cohen } 979e126ba97SEli Cohen 98024406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 98124406953SFeras Daoud if (err) { 98224406953SFeras Daoud dev_err(&pdev->dev, "Failed to init FW tracer\n"); 98324406953SFeras Daoud goto err_fw_tracer; 98424406953SFeras Daoud } 98524406953SFeras Daoud 98604e87170SMatan Barak err = mlx5_fpga_device_start(dev); 98704e87170SMatan Barak if (err) { 98804e87170SMatan Barak dev_err(&pdev->dev, "fpga device start failed %d\n", err); 98904e87170SMatan Barak goto err_fpga_start; 99004e87170SMatan Barak } 99104e87170SMatan Barak 99204e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 99304e87170SMatan Barak if (err) { 99404e87170SMatan Barak dev_err(&pdev->dev, "IPSec device start failed %d\n", err); 99504e87170SMatan Barak goto err_ipsec_start; 99604e87170SMatan Barak } 99704e87170SMatan Barak 9981ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 9991ae17322SIlya Lesokhin if (err) { 10001ae17322SIlya Lesokhin dev_err(&pdev->dev, "TLS device start failed %d\n", err); 10011ae17322SIlya Lesokhin goto err_tls_start; 10021ae17322SIlya Lesokhin } 10031ae17322SIlya Lesokhin 100486d722adSMaor Gottlieb err = mlx5_init_fs(dev); 100586d722adSMaor Gottlieb if (err) { 100686d722adSMaor Gottlieb dev_err(&pdev->dev, "Failed to init flow steering\n"); 100786d722adSMaor Gottlieb goto err_fs; 100886d722adSMaor Gottlieb } 10091466cc5bSYevgeny Petrilin 1010c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1011c85023e1SHuy Nguyen if (err) { 1012c85023e1SHuy Nguyen dev_err(&pdev->dev, "Failed to set hca defaults\n"); 1013c85023e1SHuy Nguyen goto err_fs; 1014c85023e1SHuy Nguyen } 1015c85023e1SHuy Nguyen 1016c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1017fc50db98SEli Cohen if (err) { 1018fc50db98SEli Cohen dev_err(&pdev->dev, "sriov init failed %d\n", err); 1019fc50db98SEli Cohen goto err_sriov; 1020fc50db98SEli Cohen } 1021fc50db98SEli Cohen 1022737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) { 1023737a234bSMohamad Haj Yahia mlx5_attach_device(dev); 1024737a234bSMohamad Haj Yahia } else { 1025a31208b1SMajd Dibbiny err = mlx5_register_device(dev); 1026a31208b1SMajd Dibbiny if (err) { 1027a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1028a31208b1SMajd Dibbiny goto err_reg_dev; 1029a31208b1SMajd Dibbiny } 1030737a234bSMohamad Haj Yahia } 1031a31208b1SMajd Dibbiny 10325fc7197dSMajd Dibbiny set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 103389d44f0aSMajd Dibbiny out: 103489d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 103589d44f0aSMajd Dibbiny 1036e126ba97SEli Cohen return 0; 1037e126ba97SEli Cohen 103859211bd3SMohamad Haj Yahia err_reg_dev: 1039c2d6e31aSMohamad Haj Yahia mlx5_sriov_detach(dev); 1040fc50db98SEli Cohen 104159211bd3SMohamad Haj Yahia err_sriov: 104286d722adSMaor Gottlieb mlx5_cleanup_fs(dev); 104359211bd3SMohamad Haj Yahia 104486d722adSMaor Gottlieb err_fs: 10451ae17322SIlya Lesokhin mlx5_accel_tls_cleanup(dev); 10461ae17322SIlya Lesokhin 10471ae17322SIlya Lesokhin err_tls_start: 104804e87170SMatan Barak mlx5_accel_ipsec_cleanup(dev); 104904e87170SMatan Barak 105004e87170SMatan Barak err_ipsec_start: 105104e87170SMatan Barak mlx5_fpga_device_stop(dev); 105204e87170SMatan Barak 105304e87170SMatan Barak err_fpga_start: 105424406953SFeras Daoud mlx5_fw_tracer_cleanup(dev->tracer); 105524406953SFeras Daoud 105624406953SFeras Daoud err_fw_tracer: 1057c8e21b3bSSaeed Mahameed mlx5_eq_table_destroy(dev); 1058233d05d2SSaeed Mahameed 1059c8e21b3bSSaeed Mahameed err_eq_table: 10600cf53c12SSaeed Mahameed mlx5_pagealloc_stop(dev); 106169c1280bSSaeed Mahameed mlx5_events_stop(dev); 106201187175SEli Cohen mlx5_put_uars_page(dev, priv->uar); 1063e126ba97SEli Cohen 1064c8e21b3bSSaeed Mahameed err_get_uars: 106559211bd3SMohamad Haj Yahia if (boot) 106659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 106759211bd3SMohamad Haj Yahia 1068e126ba97SEli Cohen err_stop_poll: 106976d5581cSJack Morgenstein mlx5_stop_health_poll(dev, boot); 10701bde6e30SEli Cohen if (mlx5_cmd_teardown_hca(dev)) { 10711bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 107289d44f0aSMajd Dibbiny goto out_err; 10731bde6e30SEli Cohen } 1074e126ba97SEli Cohen 1075cd23b14bSEli Cohen reclaim_boot_pages: 1076e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 1077e126ba97SEli Cohen 1078cd23b14bSEli Cohen err_disable_hca: 10790b107106SEli Cohen mlx5_core_disable_hca(dev, 0); 1080cd23b14bSEli Cohen 108159211bd3SMohamad Haj Yahia err_cmd_cleanup: 1082e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 1083e126ba97SEli Cohen 108489d44f0aSMajd Dibbiny out_err: 108589d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 108689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 108789d44f0aSMajd Dibbiny 1088e126ba97SEli Cohen return err; 1089e126ba97SEli Cohen } 1090e126ba97SEli Cohen 109159211bd3SMohamad Haj Yahia static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 109259211bd3SMohamad Haj Yahia bool cleanup) 1093e126ba97SEli Cohen { 109489d44f0aSMajd Dibbiny int err = 0; 1095e126ba97SEli Cohen 10965e44fca5SDaniel Jurgens if (cleanup) 10972a0165a0SMohamad Haj Yahia mlx5_drain_health_recovery(dev); 1098689a248dSDaniel Jurgens 109989d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 1100b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 110189d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", 110289d44f0aSMajd Dibbiny __func__); 110359211bd3SMohamad Haj Yahia if (cleanup) 110459211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 110589d44f0aSMajd Dibbiny goto out; 110689d44f0aSMajd Dibbiny } 11076b6adee3SMohamad Haj Yahia 11089ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 11099ade8c7cSIlan Tayari 1110737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) 1111737a234bSMohamad Haj Yahia mlx5_detach_device(dev); 1112737a234bSMohamad Haj Yahia 1113c2d6e31aSMohamad Haj Yahia mlx5_sriov_detach(dev); 111486d722adSMaor Gottlieb mlx5_cleanup_fs(dev); 111504e87170SMatan Barak mlx5_accel_ipsec_cleanup(dev); 11161ae17322SIlya Lesokhin mlx5_accel_tls_cleanup(dev); 111704e87170SMatan Barak mlx5_fpga_device_stop(dev); 111824406953SFeras Daoud mlx5_fw_tracer_cleanup(dev->tracer); 1119c8e21b3bSSaeed Mahameed mlx5_eq_table_destroy(dev); 11200cf53c12SSaeed Mahameed mlx5_pagealloc_stop(dev); 112169c1280bSSaeed Mahameed mlx5_events_stop(dev); 112201187175SEli Cohen mlx5_put_uars_page(dev, priv->uar); 112359211bd3SMohamad Haj Yahia if (cleanup) 112459211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 112576d5581cSJack Morgenstein mlx5_stop_health_poll(dev, cleanup); 11260cf53c12SSaeed Mahameed 1127ac6ea6e8SEli Cohen err = mlx5_cmd_teardown_hca(dev); 1128ac6ea6e8SEli Cohen if (err) { 11291bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 1130ac6ea6e8SEli Cohen goto out; 11311bde6e30SEli Cohen } 1132e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 11330b107106SEli Cohen mlx5_core_disable_hca(dev, 0); 1134e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 11359603b61dSJack Morgenstein 1136ac6ea6e8SEli Cohen out: 113789d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1138ac6ea6e8SEli Cohen return err; 11399603b61dSJack Morgenstein } 114064613d94SSaeed Mahameed 1141feae9087SOr Gerlitz static const struct devlink_ops mlx5_devlink_ops = { 1142e80541ecSSaeed Mahameed #ifdef CONFIG_MLX5_ESWITCH 1143feae9087SOr Gerlitz .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, 1144feae9087SOr Gerlitz .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, 1145bffaa916SRoi Dayan .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, 1146bffaa916SRoi Dayan .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, 11477768d197SRoi Dayan .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, 11487768d197SRoi Dayan .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, 1149feae9087SOr Gerlitz #endif 1150feae9087SOr Gerlitz }; 1151f66f049fSEli Cohen 115259211bd3SMohamad Haj Yahia #define MLX5_IB_MOD "mlx5_ib" 11539603b61dSJack Morgenstein static int init_one(struct pci_dev *pdev, 11549603b61dSJack Morgenstein const struct pci_device_id *id) 11559603b61dSJack Morgenstein { 11569603b61dSJack Morgenstein struct mlx5_core_dev *dev; 1157feae9087SOr Gerlitz struct devlink *devlink; 11589603b61dSJack Morgenstein struct mlx5_priv *priv; 11599603b61dSJack Morgenstein int err; 11609603b61dSJack Morgenstein 1161feae9087SOr Gerlitz devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); 1162feae9087SOr Gerlitz if (!devlink) { 11639603b61dSJack Morgenstein dev_err(&pdev->dev, "kzalloc failed\n"); 11649603b61dSJack Morgenstein return -ENOMEM; 11659603b61dSJack Morgenstein } 1166feae9087SOr Gerlitz 1167feae9087SOr Gerlitz dev = devlink_priv(devlink); 11689603b61dSJack Morgenstein priv = &dev->priv; 1169fc50db98SEli Cohen priv->pci_dev_data = id->driver_data; 11709603b61dSJack Morgenstein 11719603b61dSJack Morgenstein pci_set_drvdata(pdev, dev); 11729603b61dSJack Morgenstein 11730e97a340SHuy Nguyen dev->pdev = pdev; 11749603b61dSJack Morgenstein dev->profile = &profile[prof_sel]; 11759603b61dSJack Morgenstein 1176364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1177364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 117889d44f0aSMajd Dibbiny mutex_init(&dev->pci_status_mutex); 117989d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1180d9aaed83SArtemy Kovalyov 118101187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 118201187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 118301187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 118401187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 118501187175SEli Cohen 1186a31208b1SMajd Dibbiny err = mlx5_pci_init(dev, priv); 11879603b61dSJack Morgenstein if (err) { 1188a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); 1189d5d284b8SSaeed Mahameed goto clean_dev; 11909603b61dSJack Morgenstein } 11919603b61dSJack Morgenstein 1192ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 1193ac6ea6e8SEli Cohen if (err) { 1194ac6ea6e8SEli Cohen dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); 1195ac6ea6e8SEli Cohen goto close_pci; 1196ac6ea6e8SEli Cohen } 1197ac6ea6e8SEli Cohen 11980cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 11990cf53c12SSaeed Mahameed if (err) 12000cf53c12SSaeed Mahameed goto err_pagealloc_init; 120159211bd3SMohamad Haj Yahia 120259211bd3SMohamad Haj Yahia err = mlx5_load_one(dev, priv, true); 12039603b61dSJack Morgenstein if (err) { 1204a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); 12050cf53c12SSaeed Mahameed goto err_load_one; 12069603b61dSJack Morgenstein } 120759211bd3SMohamad Haj Yahia 1208f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 12099603b61dSJack Morgenstein 1210feae9087SOr Gerlitz err = devlink_register(devlink, &pdev->dev); 1211feae9087SOr Gerlitz if (err) 1212feae9087SOr Gerlitz goto clean_load; 1213feae9087SOr Gerlitz 12145d47f6c8SDaniel Jurgens pci_save_state(pdev); 12159603b61dSJack Morgenstein return 0; 12169603b61dSJack Morgenstein 1217feae9087SOr Gerlitz clean_load: 121859211bd3SMohamad Haj Yahia mlx5_unload_one(dev, priv, true); 12190cf53c12SSaeed Mahameed err_load_one: 122059211bd3SMohamad Haj Yahia mlx5_pagealloc_cleanup(dev); 12210cf53c12SSaeed Mahameed err_pagealloc_init: 1222ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1223a31208b1SMajd Dibbiny close_pci: 1224a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1225a31208b1SMajd Dibbiny clean_dev: 1226feae9087SOr Gerlitz devlink_free(devlink); 1227a31208b1SMajd Dibbiny 12289603b61dSJack Morgenstein return err; 12299603b61dSJack Morgenstein } 1230a31208b1SMajd Dibbiny 12319603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 12329603b61dSJack Morgenstein { 12339603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1234feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 1235a31208b1SMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 12369603b61dSJack Morgenstein 1237feae9087SOr Gerlitz devlink_unregister(devlink); 1238737a234bSMohamad Haj Yahia mlx5_unregister_device(dev); 1239737a234bSMohamad Haj Yahia 124059211bd3SMohamad Haj Yahia if (mlx5_unload_one(dev, priv, true)) { 1241a31208b1SMajd Dibbiny dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1242ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1243a31208b1SMajd Dibbiny return; 1244a31208b1SMajd Dibbiny } 1245737a234bSMohamad Haj Yahia 124659211bd3SMohamad Haj Yahia mlx5_pagealloc_cleanup(dev); 1247ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1248a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1249feae9087SOr Gerlitz devlink_free(devlink); 12509603b61dSJack Morgenstein } 12519603b61dSJack Morgenstein 125289d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 125389d44f0aSMajd Dibbiny pci_channel_state_t state) 125489d44f0aSMajd Dibbiny { 125589d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 125689d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 125789d44f0aSMajd Dibbiny 125889d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 125904c0c1abSMohamad Haj Yahia 12608812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 126159211bd3SMohamad Haj Yahia mlx5_unload_one(dev, priv, false); 12625d47f6c8SDaniel Jurgens /* In case of kernel call drain the health wq */ 126305ac2c0bSMohamad Haj Yahia if (state) { 12645e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 126589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 126605ac2c0bSMohamad Haj Yahia } 126705ac2c0bSMohamad Haj Yahia 126889d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 126989d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 127089d44f0aSMajd Dibbiny } 127189d44f0aSMajd Dibbiny 1272d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1273d57847dcSDaniel Jurgens * for the health counter to start counting. 127489d44f0aSMajd Dibbiny */ 1275d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 127689d44f0aSMajd Dibbiny { 127789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 127889d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 127989d44f0aSMajd Dibbiny const int niter = 100; 1280d57847dcSDaniel Jurgens u32 last_count = 0; 128189d44f0aSMajd Dibbiny u32 count; 128289d44f0aSMajd Dibbiny int i; 128389d44f0aSMajd Dibbiny 128489d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 128589d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 128689d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1287d57847dcSDaniel Jurgens if (last_count && last_count != count) { 128889d44f0aSMajd Dibbiny dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1289d57847dcSDaniel Jurgens return 0; 1290d57847dcSDaniel Jurgens } 1291d57847dcSDaniel Jurgens last_count = count; 129289d44f0aSMajd Dibbiny } 129389d44f0aSMajd Dibbiny msleep(50); 129489d44f0aSMajd Dibbiny } 129589d44f0aSMajd Dibbiny 1296d57847dcSDaniel Jurgens return -ETIMEDOUT; 129789d44f0aSMajd Dibbiny } 129889d44f0aSMajd Dibbiny 12991061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 13001061c90fSMohamad Haj Yahia { 13011061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 13021061c90fSMohamad Haj Yahia int err; 13031061c90fSMohamad Haj Yahia 13041061c90fSMohamad Haj Yahia dev_info(&pdev->dev, "%s was called\n", __func__); 13051061c90fSMohamad Haj Yahia 13061061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 13071061c90fSMohamad Haj Yahia if (err) { 13081061c90fSMohamad Haj Yahia dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 13091061c90fSMohamad Haj Yahia , __func__, err); 13101061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 13111061c90fSMohamad Haj Yahia } 13121061c90fSMohamad Haj Yahia 13131061c90fSMohamad Haj Yahia pci_set_master(pdev); 13141061c90fSMohamad Haj Yahia pci_restore_state(pdev); 13155d47f6c8SDaniel Jurgens pci_save_state(pdev); 13161061c90fSMohamad Haj Yahia 13171061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 13181061c90fSMohamad Haj Yahia dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); 13191061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 13201061c90fSMohamad Haj Yahia } 13211061c90fSMohamad Haj Yahia 13221061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 13231061c90fSMohamad Haj Yahia } 13241061c90fSMohamad Haj Yahia 132589d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 132689d44f0aSMajd Dibbiny { 132789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 132889d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 132989d44f0aSMajd Dibbiny int err; 133089d44f0aSMajd Dibbiny 133189d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 133289d44f0aSMajd Dibbiny 133359211bd3SMohamad Haj Yahia err = mlx5_load_one(dev, priv, false); 133489d44f0aSMajd Dibbiny if (err) 133589d44f0aSMajd Dibbiny dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 133689d44f0aSMajd Dibbiny , __func__, err); 133789d44f0aSMajd Dibbiny else 133889d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s: device recovered\n", __func__); 133989d44f0aSMajd Dibbiny } 134089d44f0aSMajd Dibbiny 134189d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 134289d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 134389d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 134489d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 134589d44f0aSMajd Dibbiny }; 134689d44f0aSMajd Dibbiny 13478812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 13488812c24dSMajd Dibbiny { 1349fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1350fcd29ad1SFeras Daoud int ret = 1; 13518812c24dSMajd Dibbiny 1352fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1353fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1354fcd29ad1SFeras Daoud 1355fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1356fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1357fcd29ad1SFeras Daoud 1358fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 13598812c24dSMajd Dibbiny return -EOPNOTSUPP; 13608812c24dSMajd Dibbiny 13618812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 13628812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 13638812c24dSMajd Dibbiny return -EAGAIN; 13648812c24dSMajd Dibbiny } 13658812c24dSMajd Dibbiny 1366d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1367d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1368d2aa060dSHuy Nguyen */ 1369d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 137076d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1371d2aa060dSHuy Nguyen 1372fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1373fcd29ad1SFeras Daoud if (!ret) 1374fcd29ad1SFeras Daoud goto succeed; 1375fcd29ad1SFeras Daoud 13768812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1377fcd29ad1SFeras Daoud if (!ret) 1378fcd29ad1SFeras Daoud goto succeed; 1379fcd29ad1SFeras Daoud 13808812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1381d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 13828812c24dSMajd Dibbiny return ret; 13838812c24dSMajd Dibbiny 1384fcd29ad1SFeras Daoud succeed: 13858812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 13868812c24dSMajd Dibbiny 13871ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 13881ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 13891ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 13901ef903bfSDaniel Jurgens * contexts. 13911ef903bfSDaniel Jurgens */ 13921ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 13931ef903bfSDaniel Jurgens 13948812c24dSMajd Dibbiny return 0; 13958812c24dSMajd Dibbiny } 13968812c24dSMajd Dibbiny 13975fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 13985fc7197dSMajd Dibbiny { 13995fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14005fc7197dSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 14018812c24dSMajd Dibbiny int err; 14025fc7197dSMajd Dibbiny 14035fc7197dSMajd Dibbiny dev_info(&pdev->dev, "Shutdown was called\n"); 14048812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 14058812c24dSMajd Dibbiny if (err) 140659211bd3SMohamad Haj Yahia mlx5_unload_one(dev, priv, false); 14075fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 14085fc7197dSMajd Dibbiny } 14095fc7197dSMajd Dibbiny 14109603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1411bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1412fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1413bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1414fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1415bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1416fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 14177092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 141864dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1419d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1420d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1421d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1422d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 14232e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 14242e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 14259603b61dSJack Morgenstein { 0, } 14269603b61dSJack Morgenstein }; 14279603b61dSJack Morgenstein 14289603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 14299603b61dSJack Morgenstein 143004c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 143104c0c1abSMohamad Haj Yahia { 143204c0c1abSMohamad Haj Yahia mlx5_pci_err_detected(dev->pdev, 0); 143304c0c1abSMohamad Haj Yahia } 143404c0c1abSMohamad Haj Yahia 143504c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 143604c0c1abSMohamad Haj Yahia { 143704c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 143804c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 143904c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 144004c0c1abSMohamad Haj Yahia } 144104c0c1abSMohamad Haj Yahia 14429603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 14439603b61dSJack Morgenstein .name = DRIVER_NAME, 14449603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 14459603b61dSJack Morgenstein .probe = init_one, 144689d44f0aSMajd Dibbiny .remove = remove_one, 14475fc7197dSMajd Dibbiny .shutdown = shutdown, 1448fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1449fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 14509603b61dSJack Morgenstein }; 1451e126ba97SEli Cohen 1452f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1453f663ad98SKamal Heib { 1454f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1455f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1456f663ad98SKamal Heib prof_sel, 1457f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1458f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1459f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1460f663ad98SKamal Heib } 1461f663ad98SKamal Heib } 1462f663ad98SKamal Heib 1463e126ba97SEli Cohen static int __init init(void) 1464e126ba97SEli Cohen { 1465e126ba97SEli Cohen int err; 1466e126ba97SEli Cohen 14678737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 14688737f818SDaniel Jurgens 1469f663ad98SKamal Heib mlx5_core_verify_params(); 147005564d0aSAviad Yehezkel mlx5_fpga_ipsec_build_fs_cmds(); 1471e126ba97SEli Cohen mlx5_register_debugfs(); 1472e126ba97SEli Cohen 14739603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 14749603b61dSJack Morgenstein if (err) 1475ac6ea6e8SEli Cohen goto err_debug; 14769603b61dSJack Morgenstein 1477f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1478f62b8bb8SAmir Vadai mlx5e_init(); 1479f62b8bb8SAmir Vadai #endif 1480f62b8bb8SAmir Vadai 1481e126ba97SEli Cohen return 0; 1482e126ba97SEli Cohen 1483e126ba97SEli Cohen err_debug: 1484e126ba97SEli Cohen mlx5_unregister_debugfs(); 1485e126ba97SEli Cohen return err; 1486e126ba97SEli Cohen } 1487e126ba97SEli Cohen 1488e126ba97SEli Cohen static void __exit cleanup(void) 1489e126ba97SEli Cohen { 1490f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1491f62b8bb8SAmir Vadai mlx5e_cleanup(); 1492f62b8bb8SAmir Vadai #endif 14939603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1494e126ba97SEli Cohen mlx5_unregister_debugfs(); 1495e126ba97SEli Cohen } 1496e126ba97SEli Cohen 1497e126ba97SEli Cohen module_init(init); 1498e126ba97SEli Cohen module_exit(cleanup); 1499