1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40db058a18SSaeed Mahameed #include <linux/interrupt.h> 41e3297246SEli Cohen #include <linux/delay.h> 42e126ba97SEli Cohen #include <linux/mlx5/driver.h> 43e126ba97SEli Cohen #include <linux/mlx5/cq.h> 44e126ba97SEli Cohen #include <linux/mlx5/qp.h> 45e126ba97SEli Cohen #include <linux/debugfs.h> 46f66f049fSEli Cohen #include <linux/kmod.h> 47b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 48c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 495a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 505a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 515a7b27ebSMaor Gottlieb #endif 52907af0f0SLeon Romanovsky #include <linux/version.h> 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6038b9f903SMoshe Shemesh #include "fw_reset.h" 6152ec462eSIlan Tayari #include "lib/mlx5.h" 625945e1adSAmir Tzin #include "lib/tout.h" 63e29341fbSIlan Tayari #include "fpga/core.h" 64c6e3b421SLeon Romanovsky #include "en_accel/ipsec.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 7287175120SEran Ben Elisha #include "lib/hv_vhca.h" 7312206b17SAya Levin #include "diag/rsc_dump.h" 74f3196bb0SParav Pandit #include "sf/vhca_event.h" 7590d010b8SParav Pandit #include "sf/dev/dev.h" 766a327321SParav Pandit #include "sf/sf.h" 773b43190bSShay Drory #include "mlx5_irq.h" 78e126ba97SEli Cohen 79e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 80048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 81e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 82e126ba97SEli Cohen 83f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 84f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 85e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 86e126ba97SEli Cohen 87f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 88f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 899603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 909603b61dSJack Morgenstein 918737f818SDaniel Jurgens static u32 sw_owner_id[4]; 92dc402cccSYishai Hadas #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 93dc402cccSYishai Hadas static DEFINE_IDA(sw_vhca_ida); 948737f818SDaniel Jurgens 95f91e6d89SEran Ben Elisha enum { 96f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 97f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 98f91e6d89SEran Ben Elisha }; 99f91e6d89SEran Ben Elisha 100f79a609eSMaher Sanalla #define LOG_MAX_SUPPORTED_QPS 0xff 101f79a609eSMaher Sanalla 1029603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1039603b61dSJack Morgenstein [0] = { 1049603b61dSJack Morgenstein .mask = 0, 1059603b61dSJack Morgenstein }, 1069603b61dSJack Morgenstein [1] = { 1079603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1089603b61dSJack Morgenstein .log_max_qp = 12, 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein [2] = { 1119603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1129603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 113f79a609eSMaher Sanalla .log_max_qp = LOG_MAX_SUPPORTED_QPS, 1149603b61dSJack Morgenstein .mr_cache[0] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[1] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[2] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[3] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[4] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[5] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[6] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[7] = { 1439603b61dSJack Morgenstein .size = 500, 1449603b61dSJack Morgenstein .limit = 250 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[8] = { 1479603b61dSJack Morgenstein .size = 500, 1489603b61dSJack Morgenstein .limit = 250 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[9] = { 1519603b61dSJack Morgenstein .size = 500, 1529603b61dSJack Morgenstein .limit = 250 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[10] = { 1559603b61dSJack Morgenstein .size = 500, 1569603b61dSJack Morgenstein .limit = 250 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein .mr_cache[11] = { 1599603b61dSJack Morgenstein .size = 500, 1609603b61dSJack Morgenstein .limit = 250 1619603b61dSJack Morgenstein }, 1629603b61dSJack Morgenstein .mr_cache[12] = { 1639603b61dSJack Morgenstein .size = 64, 1649603b61dSJack Morgenstein .limit = 32 1659603b61dSJack Morgenstein }, 1669603b61dSJack Morgenstein .mr_cache[13] = { 1679603b61dSJack Morgenstein .size = 32, 1689603b61dSJack Morgenstein .limit = 16 1699603b61dSJack Morgenstein }, 1709603b61dSJack Morgenstein .mr_cache[14] = { 1719603b61dSJack Morgenstein .size = 16, 1729603b61dSJack Morgenstein .limit = 8 1739603b61dSJack Morgenstein }, 1749603b61dSJack Morgenstein .mr_cache[15] = { 1759603b61dSJack Morgenstein .size = 8, 1769603b61dSJack Morgenstein .limit = 4 1779603b61dSJack Morgenstein }, 1789603b61dSJack Morgenstein }, 1799603b61dSJack Morgenstein }; 180e126ba97SEli Cohen 181b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 182b8a92577SDaniel Jurgens u32 warn_time_mili) 183e3297246SEli Cohen { 184b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 185e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 186cdfc6ffbSShay Drory u32 fw_initializing; 187e3297246SEli Cohen int err = 0; 188e3297246SEli Cohen 189cdfc6ffbSShay Drory do { 190cdfc6ffbSShay Drory fw_initializing = ioread32be(&dev->iseg->initializing); 191cdfc6ffbSShay Drory if (!(fw_initializing >> 31)) 192cdfc6ffbSShay Drory break; 1938324a02cSGavin Li if (time_after(jiffies, end) || 194*c05d145aSMoshe Shemesh test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 195e3297246SEli Cohen err = -EBUSY; 196e3297246SEli Cohen break; 197e3297246SEli Cohen } 198b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 199cdfc6ffbSShay Drory mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 200cdfc6ffbSShay Drory jiffies_to_msecs(end - warn) / 1000, fw_initializing); 201b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 202b8a92577SDaniel Jurgens } 2035945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 204cdfc6ffbSShay Drory } while (true); 205e3297246SEli Cohen 206e3297246SEli Cohen return err; 207e3297246SEli Cohen } 208e3297246SEli Cohen 209012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 210012e50e1SHuy Nguyen { 211012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 212012e50e1SHuy Nguyen driver_version); 2133ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 214012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 215012e50e1SHuy Nguyen char *string; 216012e50e1SHuy Nguyen 217012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 218012e50e1SHuy Nguyen return; 219012e50e1SHuy Nguyen 220012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 221012e50e1SHuy Nguyen 222012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 225012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 226012e50e1SHuy Nguyen 227012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 22817a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 229012e50e1SHuy Nguyen 230012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 231012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 232012e50e1SHuy Nguyen 233012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 234907af0f0SLeon Romanovsky 235907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 23688a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 23788a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 238012e50e1SHuy Nguyen 239012e50e1SHuy Nguyen /*Send the command*/ 240012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 241012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 242012e50e1SHuy Nguyen 2433ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 244012e50e1SHuy Nguyen } 245012e50e1SHuy Nguyen 246e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 247e126ba97SEli Cohen { 248e126ba97SEli Cohen int err; 249e126ba97SEli Cohen 250eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 251e126ba97SEli Cohen if (err) { 2521a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 253eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 254e126ba97SEli Cohen if (err) { 2551a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 256e126ba97SEli Cohen return err; 257e126ba97SEli Cohen } 258e126ba97SEli Cohen } 259e126ba97SEli Cohen 260e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 261e126ba97SEli Cohen return err; 262e126ba97SEli Cohen } 263e126ba97SEli Cohen 26489d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 26589d44f0aSMajd Dibbiny { 26689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 26789d44f0aSMajd Dibbiny int err = 0; 26889d44f0aSMajd Dibbiny 26989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27189d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27289d44f0aSMajd Dibbiny if (!err) 27389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27489d44f0aSMajd Dibbiny } 27589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 27689d44f0aSMajd Dibbiny 27789d44f0aSMajd Dibbiny return err; 27889d44f0aSMajd Dibbiny } 27989d44f0aSMajd Dibbiny 28089d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28189d44f0aSMajd Dibbiny { 28289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28389d44f0aSMajd Dibbiny 28489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 28689d44f0aSMajd Dibbiny pci_disable_device(pdev); 28789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 28889d44f0aSMajd Dibbiny } 28989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29089d44f0aSMajd Dibbiny } 29189d44f0aSMajd Dibbiny 292e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 293e126ba97SEli Cohen { 294e126ba97SEli Cohen int err = 0; 295e126ba97SEli Cohen 296e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2971a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 298e126ba97SEli Cohen return -ENODEV; 299e126ba97SEli Cohen } 300e126ba97SEli Cohen 30117a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 302e126ba97SEli Cohen if (err) 303e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 304e126ba97SEli Cohen 305e126ba97SEli Cohen return err; 306e126ba97SEli Cohen } 307e126ba97SEli Cohen 308e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 309e126ba97SEli Cohen { 310e126ba97SEli Cohen pci_release_regions(pdev); 311e126ba97SEli Cohen } 312e126ba97SEli Cohen 313bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 314e126ba97SEli Cohen u8 he; 315e126ba97SEli Cohen u8 rsvd[15]; 316e126ba97SEli Cohen }; 317e126ba97SEli Cohen 3182974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 319c7a08ac7SEli Cohen { 320c7a08ac7SEli Cohen switch (size) { 321c7a08ac7SEli Cohen case 128: 322c7a08ac7SEli Cohen return 0; 323c7a08ac7SEli Cohen case 256: 324c7a08ac7SEli Cohen return 1; 325c7a08ac7SEli Cohen case 512: 326c7a08ac7SEli Cohen return 2; 327c7a08ac7SEli Cohen case 1024: 328c7a08ac7SEli Cohen return 3; 329c7a08ac7SEli Cohen case 2048: 330c7a08ac7SEli Cohen return 4; 331c7a08ac7SEli Cohen case 4096: 332c7a08ac7SEli Cohen return 5; 333c7a08ac7SEli Cohen default: 3342974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 335c7a08ac7SEli Cohen return 0; 336c7a08ac7SEli Cohen } 337c7a08ac7SEli Cohen } 338c7a08ac7SEli Cohen 339c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 340c7d4e6abSJiri Pirko { 341c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 342c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev = netdev; 343c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 344c7d4e6abSJiri Pirko netdev); 345c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 346c7d4e6abSJiri Pirko } 347c7d4e6abSJiri Pirko 348c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 349c7d4e6abSJiri Pirko { 350c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 351c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 352c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev); 353c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 354c7d4e6abSJiri Pirko } 355c7d4e6abSJiri Pirko EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 356c7d4e6abSJiri Pirko 357b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 358b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 359938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 360c7a08ac7SEli Cohen { 361b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 362b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 363938fe83cSSaeed Mahameed void *out, *hca_caps; 364938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 365c7a08ac7SEli Cohen int err; 366c7a08ac7SEli Cohen 367b775516bSEli Cohen memset(in, 0, sizeof(in)); 368b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 369c7a08ac7SEli Cohen if (!out) 370c7a08ac7SEli Cohen return -ENOMEM; 371938fe83cSSaeed Mahameed 372b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 373b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3743ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 375c7a08ac7SEli Cohen if (err) { 376938fe83cSSaeed Mahameed mlx5_core_warn(dev, 377938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 378938fe83cSSaeed Mahameed cap_type, cap_mode, err); 379c7a08ac7SEli Cohen goto query_ex; 380c7a08ac7SEli Cohen } 381c7a08ac7SEli Cohen 382938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 383938fe83cSSaeed Mahameed 384938fe83cSSaeed Mahameed switch (cap_mode) { 385938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 38648f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 387938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 388938fe83cSSaeed Mahameed break; 389938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 39048f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 391938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 392938fe83cSSaeed Mahameed break; 393938fe83cSSaeed Mahameed default: 394938fe83cSSaeed Mahameed mlx5_core_warn(dev, 395938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 396938fe83cSSaeed Mahameed cap_type, cap_mode); 397938fe83cSSaeed Mahameed err = -EINVAL; 398938fe83cSSaeed Mahameed break; 399938fe83cSSaeed Mahameed } 400c7a08ac7SEli Cohen query_ex: 401c7a08ac7SEli Cohen kfree(out); 402c7a08ac7SEli Cohen return err; 403c7a08ac7SEli Cohen } 404c7a08ac7SEli Cohen 405b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 406b06e7de8SLeon Romanovsky { 407b06e7de8SLeon Romanovsky int ret; 408b06e7de8SLeon Romanovsky 409b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 410b06e7de8SLeon Romanovsky if (ret) 411b06e7de8SLeon Romanovsky return ret; 412b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 413b06e7de8SLeon Romanovsky } 414b06e7de8SLeon Romanovsky 415a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 416c7a08ac7SEli Cohen { 417b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 418f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4193ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 420c7a08ac7SEli Cohen } 42187b8de49SEli Cohen 422a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 423f91e6d89SEran Ben Elisha { 424f91e6d89SEran Ben Elisha void *set_hca_cap; 425f91e6d89SEran Ben Elisha int req_endianness; 426f91e6d89SEran Ben Elisha int err; 427f91e6d89SEran Ben Elisha 428a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 429a2a322f4SLeon Romanovsky return 0; 430a2a322f4SLeon Romanovsky 431b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 432f91e6d89SEran Ben Elisha if (err) 433f91e6d89SEran Ben Elisha return err; 434f91e6d89SEran Ben Elisha 435f91e6d89SEran Ben Elisha req_endianness = 436f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 437bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 438f91e6d89SEran Ben Elisha 439f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 440f91e6d89SEran Ben Elisha return 0; 441f91e6d89SEran Ben Elisha 442f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 443f91e6d89SEran Ben Elisha 444f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 445bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 446f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 447f91e6d89SEran Ben Elisha 448a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 449f91e6d89SEran Ben Elisha } 450f91e6d89SEran Ben Elisha 451a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45246861e3eSMoni Shoua { 45346861e3eSMoni Shoua void *set_hca_cap; 454fca22e7eSMoni Shoua bool do_set = false; 45546861e3eSMoni Shoua int err; 45646861e3eSMoni Shoua 45737b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 45837b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 45946861e3eSMoni Shoua return 0; 46046861e3eSMoni Shoua 46146861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46246861e3eSMoni Shoua if (err) 46346861e3eSMoni Shoua return err; 46446861e3eSMoni Shoua 46546861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 46648f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 46746861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 46846861e3eSMoni Shoua 469fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 470fca22e7eSMoni Shoua do { \ 471fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 472fca22e7eSMoni Shoua if (_res) { \ 473fca22e7eSMoni Shoua do_set = true; \ 474fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 475fca22e7eSMoni Shoua } \ 476fca22e7eSMoni Shoua } while (0) 47746861e3eSMoni Shoua 478fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 479fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 480fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 481fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 482fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 48600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 48700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 48800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 48900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49246861e3eSMoni Shoua 493a2a322f4SLeon Romanovsky if (!do_set) 494a2a322f4SLeon Romanovsky return 0; 49546861e3eSMoni Shoua 496a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 49746861e3eSMoni Shoua } 49846861e3eSMoni Shoua 4998680a60fSShay Drory static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 5008680a60fSShay Drory { 5018680a60fSShay Drory struct devlink *devlink = priv_to_devlink(dev); 5028680a60fSShay Drory union devlink_param_value val; 5038680a60fSShay Drory int err; 5048680a60fSShay Drory 505075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5068680a60fSShay Drory DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 5078680a60fSShay Drory &val); 5088680a60fSShay Drory if (!err) 5098680a60fSShay Drory return val.vu32; 5108680a60fSShay Drory mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5118680a60fSShay Drory return err; 5128680a60fSShay Drory } 5138680a60fSShay Drory 5149ca05b0fSMaher Sanalla bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 5159ca05b0fSMaher Sanalla { 5169ca05b0fSMaher Sanalla struct devlink *devlink = priv_to_devlink(dev); 5179ca05b0fSMaher Sanalla union devlink_param_value val; 5189ca05b0fSMaher Sanalla int err; 5199ca05b0fSMaher Sanalla 520075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5219ca05b0fSMaher Sanalla DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 5229ca05b0fSMaher Sanalla &val); 5239ca05b0fSMaher Sanalla 5249ca05b0fSMaher Sanalla if (!err) 5259ca05b0fSMaher Sanalla return val.vbool; 5269ca05b0fSMaher Sanalla 5279ca05b0fSMaher Sanalla mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5289ca05b0fSMaher Sanalla return MLX5_CAP_GEN(dev, roce); 5299ca05b0fSMaher Sanalla } 5309ca05b0fSMaher Sanalla EXPORT_SYMBOL(mlx5_is_roce_on); 5319ca05b0fSMaher Sanalla 532dc402cccSYishai Hadas static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 533dc402cccSYishai Hadas { 534dc402cccSYishai Hadas void *set_hca_cap; 535dc402cccSYishai Hadas int err; 536dc402cccSYishai Hadas 537dc402cccSYishai Hadas if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 538dc402cccSYishai Hadas return 0; 539dc402cccSYishai Hadas 540dc402cccSYishai Hadas err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 541dc402cccSYishai Hadas if (err) 542dc402cccSYishai Hadas return err; 543dc402cccSYishai Hadas 544dc402cccSYishai Hadas if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 545dc402cccSYishai Hadas !(dev->priv.sw_vhca_id > 0)) 546dc402cccSYishai Hadas return 0; 547dc402cccSYishai Hadas 548dc402cccSYishai Hadas set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 549dc402cccSYishai Hadas capability); 550dc402cccSYishai Hadas memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 551dc402cccSYishai Hadas MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 552dc402cccSYishai Hadas MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 553dc402cccSYishai Hadas 554dc402cccSYishai Hadas return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 555dc402cccSYishai Hadas } 556dc402cccSYishai Hadas 557a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 558e126ba97SEli Cohen { 5593410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 560938fe83cSSaeed Mahameed void *set_hca_cap; 5618680a60fSShay Drory int max_uc_list; 562a2a322f4SLeon Romanovsky int err; 563e126ba97SEli Cohen 564b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 565c7a08ac7SEli Cohen if (err) 566a2a322f4SLeon Romanovsky return err; 567e126ba97SEli Cohen 568938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 569938fe83cSSaeed Mahameed capability); 57048f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 571938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 572938fe83cSSaeed Mahameed 573938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 574707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 575938fe83cSSaeed Mahameed 128); 576c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 577938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5782974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 579e126ba97SEli Cohen 580883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 581f79a609eSMaher Sanalla if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 582a6e9085dSMaher Sanalla prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 583f79a609eSMaher Sanalla } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 584883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5853410fbcdSMaor Gottlieb prof->log_max_qp, 586883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5873410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 588883371c4SNoa Osherovich } 589c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 590938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 591938fe83cSSaeed Mahameed prof->log_max_qp); 592e126ba97SEli Cohen 593938fe83cSSaeed Mahameed /* disable cmdif checksum */ 594938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 595c1868b82SEli Cohen 59691828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 59791828bd8SMajd Dibbiny * than 4K. 59891828bd8SMajd Dibbiny */ 59991828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 600f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 601f502d834SEli Cohen 602fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 603fe1e1876SCarol L Soto 604f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 605f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 606f32f5bd2SDaniel Jurgens set_hca_cap, 607f32f5bd2SDaniel Jurgens cache_line_128byte, 608c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 609f32f5bd2SDaniel Jurgens 610dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 611dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 612dd44572aSMoni Shoua 613e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 614e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 615e7f4d0bcSMoshe Shemesh 616c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 617c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 618c4b76d8dSDaniel Jurgens set_hca_cap, 619c4b76d8dSDaniel Jurgens num_vhca_ports, 620c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 621c4b76d8dSDaniel Jurgens 622c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 623c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 624c6168161SEran Ben Elisha 6254dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 6264dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 6274dca6509SMichael Guralnik 628f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 629f3196bb0SParav Pandit 630604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 631604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 632604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 633604774adSLeon Romanovsky 634c4ad5f2bSShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 6359ca05b0fSMaher Sanalla MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 6369ca05b0fSMaher Sanalla mlx5_is_roce_on(dev)); 637fbfa97b4SShay Drory 6388680a60fSShay Drory max_uc_list = max_uc_list_get_devlink_param(dev); 6398680a60fSShay Drory if (max_uc_list > 0) 6408680a60fSShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 6418680a60fSShay Drory ilog2(max_uc_list)); 6428680a60fSShay Drory 643a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 644e126ba97SEli Cohen } 645cd23b14bSEli Cohen 646fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 647fbfa97b4SShay Drory * boot process. 648fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 649fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 650fbfa97b4SShay Drory * Hence, the need for this function. 651fbfa97b4SShay Drory * 652fbfa97b4SShay Drory * Returns 653fbfa97b4SShay Drory * True: 654fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 655fbfa97b4SShay Drory * OR: 656fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 657fbfa97b4SShay Drory * 658fbfa97b4SShay Drory * In any other case, return False. 659fbfa97b4SShay Drory */ 660fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 661fbfa97b4SShay Drory { 6629ca05b0fSMaher Sanalla return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 663fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 664fbfa97b4SShay Drory } 665fbfa97b4SShay Drory 66659e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 66759e9e8e4SMark Zhang { 66859e9e8e4SMark Zhang void *set_hca_cap; 66959e9e8e4SMark Zhang int err; 67059e9e8e4SMark Zhang 671fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 67259e9e8e4SMark Zhang return 0; 67359e9e8e4SMark Zhang 67459e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 67559e9e8e4SMark Zhang if (err) 67659e9e8e4SMark Zhang return err; 67759e9e8e4SMark Zhang 67859e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 67959e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 68059e9e8e4SMark Zhang return 0; 68159e9e8e4SMark Zhang 68259e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 68348f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 68459e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 68559e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 68659e9e8e4SMark Zhang 68759e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 688e126ba97SEli Cohen return err; 689e126ba97SEli Cohen } 690e126ba97SEli Cohen 69190b1df74SLiu, Changcheng static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 69290b1df74SLiu, Changcheng void *set_ctx) 69390b1df74SLiu, Changcheng { 69490b1df74SLiu, Changcheng void *set_hca_cap; 69590b1df74SLiu, Changcheng int err; 69690b1df74SLiu, Changcheng 69790b1df74SLiu, Changcheng if (!MLX5_CAP_GEN(dev, port_selection_cap)) 69890b1df74SLiu, Changcheng return 0; 69990b1df74SLiu, Changcheng 70090b1df74SLiu, Changcheng err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 70190b1df74SLiu, Changcheng if (err) 70290b1df74SLiu, Changcheng return err; 70390b1df74SLiu, Changcheng 70490b1df74SLiu, Changcheng if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 70590b1df74SLiu, Changcheng !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 70690b1df74SLiu, Changcheng return 0; 70790b1df74SLiu, Changcheng 70890b1df74SLiu, Changcheng set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 70990b1df74SLiu, Changcheng memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 71090b1df74SLiu, Changcheng MLX5_ST_SZ_BYTES(port_selection_cap)); 71190b1df74SLiu, Changcheng MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 71290b1df74SLiu, Changcheng 71390b1df74SLiu, Changcheng err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION); 71490b1df74SLiu, Changcheng 71590b1df74SLiu, Changcheng return err; 71690b1df74SLiu, Changcheng } 71790b1df74SLiu, Changcheng 71837b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 71937b6bb77SLeon Romanovsky { 720a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 721a2a322f4SLeon Romanovsky void *set_ctx; 72237b6bb77SLeon Romanovsky int err; 72337b6bb77SLeon Romanovsky 724a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 725a2a322f4SLeon Romanovsky if (!set_ctx) 726a2a322f4SLeon Romanovsky return -ENOMEM; 727a2a322f4SLeon Romanovsky 728a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 72937b6bb77SLeon Romanovsky if (err) { 73098a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 73137b6bb77SLeon Romanovsky goto out; 73237b6bb77SLeon Romanovsky } 73337b6bb77SLeon Romanovsky 734a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 735a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 73637b6bb77SLeon Romanovsky if (err) { 73798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 73837b6bb77SLeon Romanovsky goto out; 73937b6bb77SLeon Romanovsky } 74037b6bb77SLeon Romanovsky 741a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 742a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 74337b6bb77SLeon Romanovsky if (err) { 74498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 74537b6bb77SLeon Romanovsky goto out; 74637b6bb77SLeon Romanovsky } 74737b6bb77SLeon Romanovsky 74859e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 74959e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 75059e9e8e4SMark Zhang if (err) { 75159e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 75259e9e8e4SMark Zhang goto out; 75359e9e8e4SMark Zhang } 75459e9e8e4SMark Zhang 755dc402cccSYishai Hadas memset(set_ctx, 0, set_sz); 756dc402cccSYishai Hadas err = handle_hca_cap_2(dev, set_ctx); 757dc402cccSYishai Hadas if (err) { 758dc402cccSYishai Hadas mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 759dc402cccSYishai Hadas goto out; 760dc402cccSYishai Hadas } 761dc402cccSYishai Hadas 76290b1df74SLiu, Changcheng memset(set_ctx, 0, set_sz); 76390b1df74SLiu, Changcheng err = handle_hca_cap_port_selection(dev, set_ctx); 76490b1df74SLiu, Changcheng if (err) { 76590b1df74SLiu, Changcheng mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 76690b1df74SLiu, Changcheng goto out; 76790b1df74SLiu, Changcheng } 76890b1df74SLiu, Changcheng 76937b6bb77SLeon Romanovsky out: 770a2a322f4SLeon Romanovsky kfree(set_ctx); 77137b6bb77SLeon Romanovsky return err; 77237b6bb77SLeon Romanovsky } 77337b6bb77SLeon Romanovsky 774e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 775e126ba97SEli Cohen { 776bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 777bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 778e126ba97SEli Cohen int err; 779e126ba97SEli Cohen 780fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 781fc50db98SEli Cohen return 0; 782fc50db98SEli Cohen 783e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 784e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 785e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 786e126ba97SEli Cohen &he_out, sizeof(he_out), 787e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 788e126ba97SEli Cohen return err; 789e126ba97SEli Cohen } 790e126ba97SEli Cohen 791c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 792c85023e1SHuy Nguyen { 793c85023e1SHuy Nguyen int ret = 0; 794c85023e1SHuy Nguyen 795c85023e1SHuy Nguyen /* Disable local_lb by default */ 7968978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 797c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 798c85023e1SHuy Nguyen 799c85023e1SHuy Nguyen return ret; 800c85023e1SHuy Nguyen } 801c85023e1SHuy Nguyen 8020b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 803e126ba97SEli Cohen { 8043ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 805e126ba97SEli Cohen 8060b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 8070b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 80822e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 80922e939a9SBodong Wang dev->caps.embedded_cpu); 8103ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 811e126ba97SEli Cohen } 812e126ba97SEli Cohen 8130b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 814e126ba97SEli Cohen { 8153ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 816e126ba97SEli Cohen 8170b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 8180b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 81922e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 82022e939a9SBodong Wang dev->caps.embedded_cpu); 8213ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 822e126ba97SEli Cohen } 823e126ba97SEli Cohen 824f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 825f62b8bb8SAmir Vadai { 8263ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 8273ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 828f62b8bb8SAmir Vadai u32 sup_issi; 829c4f287c4SSaeed Mahameed int err; 830f62b8bb8SAmir Vadai 831f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 8323ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 833f62b8bb8SAmir Vadai if (err) { 834605bef00SSaeed Mahameed u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 835605bef00SSaeed Mahameed u8 status = MLX5_GET(query_issi_out, query_out, status); 836c4f287c4SSaeed Mahameed 837f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 838f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 839f9c14e46SKamal Heib err, status, syndrome); 840f9c14e46SKamal Heib return err; 841f62b8bb8SAmir Vadai } 842f62b8bb8SAmir Vadai 843f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 844f9c14e46SKamal Heib dev->issi = 0; 845f9c14e46SKamal Heib return 0; 846f62b8bb8SAmir Vadai } 847f62b8bb8SAmir Vadai 848f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 849f62b8bb8SAmir Vadai 850f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 8513ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 852f62b8bb8SAmir Vadai 853f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 854f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 8553ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 856f62b8bb8SAmir Vadai if (err) { 857f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 858f9c14e46SKamal Heib err); 859f62b8bb8SAmir Vadai return err; 860f62b8bb8SAmir Vadai } 861f62b8bb8SAmir Vadai 862f62b8bb8SAmir Vadai dev->issi = 1; 863f62b8bb8SAmir Vadai 864f62b8bb8SAmir Vadai return 0; 865e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 866f62b8bb8SAmir Vadai return 0; 867f62b8bb8SAmir Vadai } 868f62b8bb8SAmir Vadai 8699eb78923SOr Gerlitz return -EOPNOTSUPP; 870f62b8bb8SAmir Vadai } 871f62b8bb8SAmir Vadai 87211f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 87311f3b84dSSaeed Mahameed const struct pci_device_id *id) 874a31208b1SMajd Dibbiny { 875a31208b1SMajd Dibbiny int err = 0; 876a31208b1SMajd Dibbiny 877d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 878e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 879e126ba97SEli Cohen 880aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 881311c7c71SSaeed Mahameed 88289d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 883e126ba97SEli Cohen if (err) { 88498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 88511f3b84dSSaeed Mahameed return err; 886e126ba97SEli Cohen } 887e126ba97SEli Cohen 888e126ba97SEli Cohen err = request_bar(pdev); 889e126ba97SEli Cohen if (err) { 89098a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 891e126ba97SEli Cohen goto err_disable; 892e126ba97SEli Cohen } 893e126ba97SEli Cohen 894e126ba97SEli Cohen pci_set_master(pdev); 895e126ba97SEli Cohen 896e126ba97SEli Cohen err = set_dma_caps(pdev); 897e126ba97SEli Cohen if (err) { 89898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 899e126ba97SEli Cohen goto err_clr_master; 900e126ba97SEli Cohen } 901e126ba97SEli Cohen 902ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 903ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 904ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 905ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 906ce4eee53SMichael Guralnik 907aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 908e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 909e126ba97SEli Cohen if (!dev->iseg) { 910e126ba97SEli Cohen err = -ENOMEM; 91198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 912e126ba97SEli Cohen goto err_clr_master; 913e126ba97SEli Cohen } 914a31208b1SMajd Dibbiny 915b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 916c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 917a31208b1SMajd Dibbiny return 0; 918a31208b1SMajd Dibbiny 919a31208b1SMajd Dibbiny err_clr_master: 920a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 921a31208b1SMajd Dibbiny release_bar(dev->pdev); 922a31208b1SMajd Dibbiny err_disable: 92389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 924a31208b1SMajd Dibbiny return err; 925a31208b1SMajd Dibbiny } 926a31208b1SMajd Dibbiny 927868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 928a31208b1SMajd Dibbiny { 92942ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 93042ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 93142ea9f1bSShay Drory * before removing the pci bars 93242ea9f1bSShay Drory */ 93342ea9f1bSShay Drory mlx5_drain_health_wq(dev); 934a31208b1SMajd Dibbiny iounmap(dev->iseg); 935a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 936a31208b1SMajd Dibbiny release_bar(dev->pdev); 93789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 938a31208b1SMajd Dibbiny } 939a31208b1SMajd Dibbiny 940868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 94159211bd3SMohamad Haj Yahia { 94259211bd3SMohamad Haj Yahia int err; 94359211bd3SMohamad Haj Yahia 944868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 945868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 94698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 947868bc06bSSaeed Mahameed dev->priv.devcom); 948fadd59fcSAviv Heller 94959211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 95059211bd3SMohamad Haj Yahia if (err) { 95198a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 952fadd59fcSAviv Heller goto err_devcom; 95359211bd3SMohamad Haj Yahia } 95459211bd3SMohamad Haj Yahia 955561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 956561aa15aSYuval Avnery if (err) { 957561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 958561aa15aSYuval Avnery goto err_devcom; 959561aa15aSYuval Avnery } 960561aa15aSYuval Avnery 961f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 96259211bd3SMohamad Haj Yahia if (err) { 96398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 964561aa15aSYuval Avnery goto err_irq_cleanup; 96559211bd3SMohamad Haj Yahia } 96659211bd3SMohamad Haj Yahia 96769c1280bSSaeed Mahameed err = mlx5_events_init(dev); 96869c1280bSSaeed Mahameed if (err) { 96998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 97069c1280bSSaeed Mahameed goto err_eq_cleanup; 97169c1280bSSaeed Mahameed } 97269c1280bSSaeed Mahameed 97338b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 97438b9f903SMoshe Shemesh if (err) { 97538b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 97638b9f903SMoshe Shemesh goto err_events_cleanup; 97738b9f903SMoshe Shemesh } 97838b9f903SMoshe Shemesh 9799f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 98059211bd3SMohamad Haj Yahia 98152ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 98252ec462eSIlan Tayari 9837c39afb3SFeras Daoud mlx5_init_clock(dev); 9847c39afb3SFeras Daoud 985358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 9860ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 987358aa5ceSSaeed Mahameed 98859211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 98959211bd3SMohamad Haj Yahia if (err) { 99098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 99159211bd3SMohamad Haj Yahia goto err_tables_cleanup; 99259211bd3SMohamad Haj Yahia } 99359211bd3SMohamad Haj Yahia 994eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 995eeb66cdbSSaeed Mahameed if (err) { 99698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 997eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 998eeb66cdbSSaeed Mahameed } 999eeb66cdbSSaeed Mahameed 1000c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 1001c2d6e31aSMohamad Haj Yahia if (err) { 100298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 100386eec50bSBodong Wang goto err_mpfs_cleanup; 100486eec50bSBodong Wang } 100586eec50bSBodong Wang 100686eec50bSBodong Wang err = mlx5_eswitch_init(dev); 100786eec50bSBodong Wang if (err) { 100886eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 100986eec50bSBodong Wang goto err_sriov_cleanup; 1010c2d6e31aSMohamad Haj Yahia } 1011c2d6e31aSMohamad Haj Yahia 10129410733cSIlan Tayari err = mlx5_fpga_init(dev); 10139410733cSIlan Tayari if (err) { 101498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 101586eec50bSBodong Wang goto err_eswitch_cleanup; 10169410733cSIlan Tayari } 10179410733cSIlan Tayari 1018f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 1019f3196bb0SParav Pandit if (err) { 1020f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1021f3196bb0SParav Pandit goto err_fpga_cleanup; 1022f3196bb0SParav Pandit } 1023f3196bb0SParav Pandit 10248f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 10258f010541SParav Pandit if (err) { 10268f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 10278f010541SParav Pandit goto err_sf_hw_table_cleanup; 10288f010541SParav Pandit } 10298f010541SParav Pandit 10308f010541SParav Pandit err = mlx5_sf_table_init(dev); 10318f010541SParav Pandit if (err) { 10328f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 10338f010541SParav Pandit goto err_sf_table_cleanup; 10348f010541SParav Pandit } 10358f010541SParav Pandit 1036b3388697SShay Drory err = mlx5_fs_core_alloc(dev); 1037b3388697SShay Drory if (err) { 1038b3388697SShay Drory mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1039b3388697SShay Drory goto err_fs; 1040b3388697SShay Drory } 1041b3388697SShay Drory 1042c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 1043c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 1044c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 1045c9b9dcb4SAriel Levkovich 104624406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 104787175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 104812206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 104924406953SFeras Daoud 105059211bd3SMohamad Haj Yahia return 0; 105159211bd3SMohamad Haj Yahia 1052b3388697SShay Drory err_fs: 1053b3388697SShay Drory mlx5_sf_table_cleanup(dev); 10548f010541SParav Pandit err_sf_table_cleanup: 10558f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 10568f010541SParav Pandit err_sf_hw_table_cleanup: 10578f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 1058f3196bb0SParav Pandit err_fpga_cleanup: 1059f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 1060c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 1061c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 106286eec50bSBodong Wang err_sriov_cleanup: 106386eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1064eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 1065eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 1066c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 1067c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 106859211bd3SMohamad Haj Yahia err_tables_cleanup: 10690ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1070358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 10712a35b2c2SJiri Pirko mlx5_cleanup_clock(dev); 10722a35b2c2SJiri Pirko mlx5_cleanup_reserved_gids(dev); 107302d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 107438b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 107538b9f903SMoshe Shemesh err_events_cleanup: 107669c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 107759211bd3SMohamad Haj Yahia err_eq_cleanup: 1078f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1079561aa15aSYuval Avnery err_irq_cleanup: 1080561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1081fadd59fcSAviv Heller err_devcom: 1082fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 108359211bd3SMohamad Haj Yahia 108459211bd3SMohamad Haj Yahia return err; 108559211bd3SMohamad Haj Yahia } 108659211bd3SMohamad Haj Yahia 108759211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 108859211bd3SMohamad Haj Yahia { 108912206b17SAya Levin mlx5_rsc_dump_destroy(dev); 109087175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 109124406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 1092c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 1093b3388697SShay Drory mlx5_fs_core_free(dev); 10948f010541SParav Pandit mlx5_sf_table_cleanup(dev); 10958f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 1096f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 10979410733cSIlan Tayari mlx5_fpga_cleanup(dev); 1098c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 109986eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1100eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 110159211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 11020ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1103358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 11047c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 110552ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 110602d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 110738b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 110869c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 1109f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1110561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1111fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 111259211bd3SMohamad Haj Yahia } 111359211bd3SMohamad Haj Yahia 11149b98d395SMoshe Shemesh static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1115a31208b1SMajd Dibbiny { 1116a31208b1SMajd Dibbiny int err; 1117a31208b1SMajd Dibbiny 111898a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1119e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 1120e126ba97SEli Cohen 112100c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 112200c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 112300c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 112400c6bcb0STal Gilboa 11256c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 11266c780a02SEli Cohen */ 112737ca95e6SGavin Li err = wait_fw_init(dev, timeout, 11285945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 11296c780a02SEli Cohen if (err) { 11305945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 113137ca95e6SGavin Li timeout); 113276091b0fSAmir Tzin return err; 11336c780a02SEli Cohen } 11346c780a02SEli Cohen 1135e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1136e126ba97SEli Cohen if (err) { 113798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 113876091b0fSAmir Tzin return err; 1139e126ba97SEli Cohen } 1140e126ba97SEli Cohen 11415945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 11425945e1adSAmir Tzin 11435945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1144e3297246SEli Cohen if (err) { 11455945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 11465945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 114755378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1148e3297246SEli Cohen } 1149e3297246SEli Cohen 1150f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1151f7936dddSEran Ben Elisha 11529b98d395SMoshe Shemesh mlx5_start_health_poll(dev); 11539b98d395SMoshe Shemesh 11540b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1155cd23b14bSEli Cohen if (err) { 115698a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 11579b98d395SMoshe Shemesh goto stop_health_poll; 1158cd23b14bSEli Cohen } 1159cd23b14bSEli Cohen 1160f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1161f62b8bb8SAmir Vadai if (err) { 116298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1163f62b8bb8SAmir Vadai goto err_disable_hca; 1164f62b8bb8SAmir Vadai } 1165f62b8bb8SAmir Vadai 1166cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1167cd23b14bSEli Cohen if (err) { 116898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1169cd23b14bSEli Cohen goto err_disable_hca; 1170cd23b14bSEli Cohen } 1171cd23b14bSEli Cohen 117232def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 117332def412SAmir Tzin if (err) { 117432def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 117532def412SAmir Tzin goto reclaim_boot_pages; 117632def412SAmir Tzin } 117732def412SAmir Tzin 1178e126ba97SEli Cohen err = set_hca_ctrl(dev); 1179e126ba97SEli Cohen if (err) { 118098a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1181cd23b14bSEli Cohen goto reclaim_boot_pages; 1182e126ba97SEli Cohen } 1183e126ba97SEli Cohen 118437b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1185e126ba97SEli Cohen if (err) { 118698a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 118746861e3eSMoni Shoua goto reclaim_boot_pages; 118846861e3eSMoni Shoua } 118946861e3eSMoni Shoua 1190cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1191e126ba97SEli Cohen if (err) { 119298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1193cd23b14bSEli Cohen goto reclaim_boot_pages; 1194e126ba97SEli Cohen } 1195e126ba97SEli Cohen 11968737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1197e126ba97SEli Cohen if (err) { 119898a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 11990cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1200e126ba97SEli Cohen } 1201e126ba97SEli Cohen 1202012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1203012e50e1SHuy Nguyen 1204bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1205bba1574cSDaniel Jurgens if (err) { 120698a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1207502e82b9SAya Levin goto reclaim_boot_pages; 1208bba1574cSDaniel Jurgens } 12099b98d395SMoshe Shemesh mlx5_start_health_fw_log_up(dev); 1210502e82b9SAya Levin 1211e161105eSSaeed Mahameed return 0; 1212e161105eSSaeed Mahameed 1213e161105eSSaeed Mahameed reclaim_boot_pages: 1214e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1215e161105eSSaeed Mahameed err_disable_hca: 1216e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 12179b98d395SMoshe Shemesh stop_health_poll: 12189b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1219e161105eSSaeed Mahameed err_cmd_cleanup: 1220f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1221e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1222e161105eSSaeed Mahameed 1223e161105eSSaeed Mahameed return err; 1224e161105eSSaeed Mahameed } 1225e161105eSSaeed Mahameed 1226e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1227e161105eSSaeed Mahameed { 1228e161105eSSaeed Mahameed int err; 1229e161105eSSaeed Mahameed 1230e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1231259bbc57SMaor Gottlieb if (err) { 123298a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1233e161105eSSaeed Mahameed return err; 1234e126ba97SEli Cohen } 1235e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1236e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 12379b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1238f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1239e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1240e161105eSSaeed Mahameed 1241e161105eSSaeed Mahameed return 0; 1242259bbc57SMaor Gottlieb } 1243e126ba97SEli Cohen 1244a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1245e161105eSSaeed Mahameed { 1246e161105eSSaeed Mahameed int err; 1247e161105eSSaeed Mahameed 124801187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 124972f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 125098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 125172f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1252a80d1b68SSaeed Mahameed return err; 1253e126ba97SEli Cohen } 1254e126ba97SEli Cohen 125569c1280bSSaeed Mahameed mlx5_events_start(dev); 12560cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 12570cf53c12SSaeed Mahameed 1258e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1259e1706e62SYuval Avnery if (err) { 1260e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1261e1706e62SYuval Avnery goto err_irq_table; 1262e1706e62SYuval Avnery } 1263e1706e62SYuval Avnery 1264c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1265e126ba97SEli Cohen if (err) { 126698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1267c8e21b3bSSaeed Mahameed goto err_eq_table; 1268e126ba97SEli Cohen } 1269e126ba97SEli Cohen 127024406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 127124406953SFeras Daoud if (err) { 1272f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1273f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1274f62eb932SAya Levin dev->tracer = NULL; 127524406953SFeras Daoud } 127624406953SFeras Daoud 127738b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 127887175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 127987175120SEran Ben Elisha 128012206b17SAya Levin err = mlx5_rsc_dump_init(dev); 128112206b17SAya Levin if (err) { 1282f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1283f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1284f62eb932SAya Levin dev->rsc_dump = NULL; 128512206b17SAya Levin } 128612206b17SAya Levin 128704e87170SMatan Barak err = mlx5_fpga_device_start(dev); 128804e87170SMatan Barak if (err) { 128998a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 129004e87170SMatan Barak goto err_fpga_start; 129104e87170SMatan Barak } 129204e87170SMatan Barak 1293b3388697SShay Drory err = mlx5_fs_core_init(dev); 129486d722adSMaor Gottlieb if (err) { 129598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 129686d722adSMaor Gottlieb goto err_fs; 129786d722adSMaor Gottlieb } 12981466cc5bSYevgeny Petrilin 1299c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1300c85023e1SHuy Nguyen if (err) { 130198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 130294a4b841SLeon Romanovsky goto err_set_hca; 1303c85023e1SHuy Nguyen } 1304c85023e1SHuy Nguyen 1305f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1306f3196bb0SParav Pandit 13076a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 13086a327321SParav Pandit if (err) { 13096a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 13106a327321SParav Pandit goto err_vhca; 13116a327321SParav Pandit } 13126a327321SParav Pandit 131322e939a9SBodong Wang err = mlx5_ec_init(dev); 131422e939a9SBodong Wang if (err) { 131598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 131622e939a9SBodong Wang goto err_ec; 131722e939a9SBodong Wang } 131822e939a9SBodong Wang 1319cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 13205bef709dSParav Pandit err = mlx5_sriov_attach(dev); 13215bef709dSParav Pandit if (err) { 13225bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 13235bef709dSParav Pandit goto err_sriov; 13245bef709dSParav Pandit } 13255bef709dSParav Pandit 132690d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 132790d010b8SParav Pandit 132871b75f0eSMoshe Shemesh err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 132971b75f0eSMoshe Shemesh if (err) 133071b75f0eSMoshe Shemesh goto err_traps_reg; 133171b75f0eSMoshe Shemesh 1332a80d1b68SSaeed Mahameed return 0; 1333a80d1b68SSaeed Mahameed 133471b75f0eSMoshe Shemesh err_traps_reg: 133571b75f0eSMoshe Shemesh mlx5_sf_dev_table_destroy(dev); 133671b75f0eSMoshe Shemesh mlx5_sriov_detach(dev); 1337a80d1b68SSaeed Mahameed err_sriov: 1338cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13395bef709dSParav Pandit mlx5_ec_cleanup(dev); 13405bef709dSParav Pandit err_ec: 13416a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 13426a327321SParav Pandit err_vhca: 1343f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 134494a4b841SLeon Romanovsky err_set_hca: 1345b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1346a80d1b68SSaeed Mahameed err_fs: 1347a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1348a80d1b68SSaeed Mahameed err_fpga_start: 134912206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 135087175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 135138b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1352a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1353a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1354a80d1b68SSaeed Mahameed err_eq_table: 1355e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1356e1706e62SYuval Avnery err_irq_table: 1357a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1358a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1359a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1360a80d1b68SSaeed Mahameed return err; 1361a80d1b68SSaeed Mahameed } 1362a80d1b68SSaeed Mahameed 1363a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1364a80d1b68SSaeed Mahameed { 136571b75f0eSMoshe Shemesh mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 136690d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1367a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1368f019679eSChris Mi mlx5_eswitch_disable(dev->priv.eswitch); 1369cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13705bef709dSParav Pandit mlx5_ec_cleanup(dev); 13716a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1372f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1373b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1374a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 137512206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 137687175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 137738b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1378a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1379a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1380e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1381a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1382a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1383a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1384a80d1b68SSaeed Mahameed } 1385a80d1b68SSaeed Mahameed 13866dea2f7eSLeon Romanovsky int mlx5_init_one(struct mlx5_core_dev *dev) 1387a80d1b68SSaeed Mahameed { 138884a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 1389a80d1b68SSaeed Mahameed int err = 0; 1390a80d1b68SSaeed Mahameed 139184a433a4SMoshe Shemesh devl_lock(devlink); 1392a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1393a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1394a80d1b68SSaeed Mahameed 13959b98d395SMoshe Shemesh err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1396a80d1b68SSaeed Mahameed if (err) 13974f7400d5SShay Drory goto err_function; 1398a80d1b68SSaeed Mahameed 1399a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1400a80d1b68SSaeed Mahameed if (err) { 140198a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1402a80d1b68SSaeed Mahameed goto function_teardown; 1403a80d1b68SSaeed Mahameed } 1404a80d1b68SSaeed Mahameed 1405a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1406a80d1b68SSaeed Mahameed if (err) 1407a80d1b68SSaeed Mahameed goto err_load; 1408a80d1b68SSaeed Mahameed 140998f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 141098f91c45SParav Pandit 1411c8aebff4SJiri Pirko err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1412a6f3b623SMichael Guralnik if (err) 1413c8aebff4SJiri Pirko goto err_devlink_params_reg; 1414a925b5e3SLeon Romanovsky 1415a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1416a925b5e3SLeon Romanovsky if (err) 1417a925b5e3SLeon Romanovsky goto err_register; 1418a925b5e3SLeon Romanovsky 14194162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 142084a433a4SMoshe Shemesh devl_unlock(devlink); 14214162f58bSParav Pandit return 0; 1422e126ba97SEli Cohen 1423a925b5e3SLeon Romanovsky err_register: 1424c8aebff4SJiri Pirko mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1425c8aebff4SJiri Pirko err_devlink_params_reg: 142698f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1427a80d1b68SSaeed Mahameed mlx5_unload(dev); 1428a80d1b68SSaeed Mahameed err_load: 142959211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1430e161105eSSaeed Mahameed function_teardown: 14316dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14324f7400d5SShay Drory err_function: 143389d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 143489d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 143584a433a4SMoshe Shemesh devl_unlock(devlink); 1436e126ba97SEli Cohen return err; 1437e126ba97SEli Cohen } 1438e126ba97SEli Cohen 14396dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1440e126ba97SEli Cohen { 144184a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 144284a433a4SMoshe Shemesh 144384a433a4SMoshe Shemesh devl_lock(devlink); 144489d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 144598f91c45SParav Pandit 144698f91c45SParav Pandit mlx5_unregister_device(dev); 1447c8aebff4SJiri Pirko mlx5_devlink_params_unregister(priv_to_devlink(dev)); 144898f91c45SParav Pandit 1449b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 145098a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 145189d44f0aSMajd Dibbiny __func__); 145259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 145389d44f0aSMajd Dibbiny goto out; 145489d44f0aSMajd Dibbiny } 14556b6adee3SMohamad Haj Yahia 14569ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1457a80d1b68SSaeed Mahameed mlx5_unload(dev); 145859211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 14596dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14606dea2f7eSLeon Romanovsky out: 14616dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 146284a433a4SMoshe Shemesh devl_unlock(devlink); 14636dea2f7eSLeon Romanovsky } 14640cf53c12SSaeed Mahameed 146584a433a4SMoshe Shemesh int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 14666dea2f7eSLeon Romanovsky { 14676dea2f7eSLeon Romanovsky int err = 0; 146837ca95e6SGavin Li u64 timeout; 14696dea2f7eSLeon Romanovsky 147084a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 14716dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 14726dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 14736dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 14746dea2f7eSLeon Romanovsky goto out; 14756dea2f7eSLeon Romanovsky } 14766dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 14776dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 14786dea2f7eSLeon Romanovsky 147937ca95e6SGavin Li if (recovery) 148037ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 148137ca95e6SGavin Li else 148237ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 14839b98d395SMoshe Shemesh err = mlx5_function_setup(dev, false, timeout); 14846dea2f7eSLeon Romanovsky if (err) 14856dea2f7eSLeon Romanovsky goto err_function; 14866dea2f7eSLeon Romanovsky 14876dea2f7eSLeon Romanovsky err = mlx5_load(dev); 14886dea2f7eSLeon Romanovsky if (err) 14896dea2f7eSLeon Romanovsky goto err_load; 14906dea2f7eSLeon Romanovsky 14916dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 14926dea2f7eSLeon Romanovsky 14936dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 14946dea2f7eSLeon Romanovsky if (err) 14956dea2f7eSLeon Romanovsky goto err_attach; 14966dea2f7eSLeon Romanovsky 14976dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 14986dea2f7eSLeon Romanovsky return 0; 14996dea2f7eSLeon Romanovsky 15006dea2f7eSLeon Romanovsky err_attach: 15016dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15026dea2f7eSLeon Romanovsky mlx5_unload(dev); 15036dea2f7eSLeon Romanovsky err_load: 15046dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 15056dea2f7eSLeon Romanovsky err_function: 15066dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 15076dea2f7eSLeon Romanovsky out: 15086dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 15096dea2f7eSLeon Romanovsky return err; 15106dea2f7eSLeon Romanovsky } 15116dea2f7eSLeon Romanovsky 15125977ac39SJiri Pirko int mlx5_load_one(struct mlx5_core_dev *dev) 15136dea2f7eSLeon Romanovsky { 151484a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 151584a433a4SMoshe Shemesh int ret; 151684a433a4SMoshe Shemesh 151784a433a4SMoshe Shemesh devl_lock(devlink); 15185977ac39SJiri Pirko ret = mlx5_load_one_devl_locked(dev, false); 151984a433a4SMoshe Shemesh devl_unlock(devlink); 152084a433a4SMoshe Shemesh return ret; 152184a433a4SMoshe Shemesh } 152284a433a4SMoshe Shemesh 152372ed5d56SJiri Pirko void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 152484a433a4SMoshe Shemesh { 152584a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 15266dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 15276dea2f7eSLeon Romanovsky 152872ed5d56SJiri Pirko mlx5_detach_device(dev, suspend); 15296dea2f7eSLeon Romanovsky 15306dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 15316dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 15326dea2f7eSLeon Romanovsky __func__); 15336dea2f7eSLeon Romanovsky goto out; 15346dea2f7eSLeon Romanovsky } 15356dea2f7eSLeon Romanovsky 15366dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15376dea2f7eSLeon Romanovsky mlx5_unload(dev); 15386dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1539ac6ea6e8SEli Cohen out: 154089d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 15419603b61dSJack Morgenstein } 154264613d94SSaeed Mahameed 154372ed5d56SJiri Pirko void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 154484a433a4SMoshe Shemesh { 154584a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 154684a433a4SMoshe Shemesh 154784a433a4SMoshe Shemesh devl_lock(devlink); 154872ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, suspend); 154984a433a4SMoshe Shemesh devl_unlock(devlink); 155084a433a4SMoshe Shemesh } 155184a433a4SMoshe Shemesh 155248f02eefSParav Pandit static const int types[] = { 155348f02eefSParav Pandit MLX5_CAP_GENERAL, 155448f02eefSParav Pandit MLX5_CAP_GENERAL_2, 155548f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 155648f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 155748f02eefSParav Pandit MLX5_CAP_ODP, 155848f02eefSParav Pandit MLX5_CAP_ATOMIC, 155948f02eefSParav Pandit MLX5_CAP_ROCE, 156048f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 156148f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 156248f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 156348f02eefSParav Pandit MLX5_CAP_ESWITCH, 156448f02eefSParav Pandit MLX5_CAP_VECTOR_CALC, 156548f02eefSParav Pandit MLX5_CAP_QOS, 156648f02eefSParav Pandit MLX5_CAP_DEBUG, 156748f02eefSParav Pandit MLX5_CAP_DEV_MEM, 156848f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 156948f02eefSParav Pandit MLX5_CAP_TLS, 157048f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 157148f02eefSParav Pandit MLX5_CAP_IPSEC, 1572425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 15737025329dSBen Ben-Ishay MLX5_CAP_DEV_SHAMPO, 15748ff0ac5bSLior Nahmanson MLX5_CAP_MACSEC, 157593983863SYishai Hadas MLX5_CAP_ADV_VIRTUALIZATION, 1576fe298bdfSJianbo Liu MLX5_CAP_CRYPTO, 157748f02eefSParav Pandit }; 157848f02eefSParav Pandit 157948f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 158048f02eefSParav Pandit { 158148f02eefSParav Pandit int type; 158248f02eefSParav Pandit int i; 158348f02eefSParav Pandit 158448f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 158548f02eefSParav Pandit type = types[i]; 158648f02eefSParav Pandit kfree(dev->caps.hca[type]); 158748f02eefSParav Pandit } 158848f02eefSParav Pandit } 158948f02eefSParav Pandit 159048f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 159148f02eefSParav Pandit { 159248f02eefSParav Pandit struct mlx5_hca_cap *cap; 159348f02eefSParav Pandit int type; 159448f02eefSParav Pandit int i; 159548f02eefSParav Pandit 159648f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 159748f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 159848f02eefSParav Pandit if (!cap) 159948f02eefSParav Pandit goto err; 160048f02eefSParav Pandit type = types[i]; 160148f02eefSParav Pandit dev->caps.hca[type] = cap; 160248f02eefSParav Pandit } 160348f02eefSParav Pandit 160448f02eefSParav Pandit return 0; 160548f02eefSParav Pandit 160648f02eefSParav Pandit err: 160748f02eefSParav Pandit mlx5_hca_caps_free(dev); 160848f02eefSParav Pandit return -ENOMEM; 160948f02eefSParav Pandit } 161048f02eefSParav Pandit 1611dd3dd726SEli Cohen static int vhca_id_show(struct seq_file *file, void *priv) 1612dd3dd726SEli Cohen { 1613dd3dd726SEli Cohen struct mlx5_core_dev *dev = file->private; 1614dd3dd726SEli Cohen 1615dd3dd726SEli Cohen seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1616dd3dd726SEli Cohen return 0; 1617dd3dd726SEli Cohen } 1618dd3dd726SEli Cohen 1619dd3dd726SEli Cohen DEFINE_SHOW_ATTRIBUTE(vhca_id); 1620dd3dd726SEli Cohen 16211958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 16229603b61dSJack Morgenstein { 162311f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 16249603b61dSJack Morgenstein int err; 16259603b61dSJack Morgenstein 16263410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1627d59b73a6SMoshe Shemesh lockdep_register_key(&dev->lock_key); 162889d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1629d59b73a6SMoshe Shemesh lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1630c7d4e6abSJiri Pirko mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1631d9aaed83SArtemy Kovalyov 163201187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 163301187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 163401187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 163501187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 163601187175SEli Cohen 163711f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 163811f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 163911f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 164011f3b84dSSaeed Mahameed 164144f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 164266771a1cSMoshe Shemesh priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 164327b942fbSParav Pandit mlx5_debugfs_root); 1644dd3dd726SEli Cohen debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 16453d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 16463d347b1bSAya Levin 164776091b0fSAmir Tzin err = mlx5_tout_init(dev); 164876091b0fSAmir Tzin if (err) { 164976091b0fSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 165076091b0fSAmir Tzin goto err_timeout_init; 165176091b0fSAmir Tzin } 165276091b0fSAmir Tzin 1653ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 165452c368dcSSaeed Mahameed if (err) 165552c368dcSSaeed Mahameed goto err_health_init; 1656ac6ea6e8SEli Cohen 16570cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 16580cf53c12SSaeed Mahameed if (err) 16590cf53c12SSaeed Mahameed goto err_pagealloc_init; 166059211bd3SMohamad Haj Yahia 1661a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1662a925b5e3SLeon Romanovsky if (err) 1663a925b5e3SLeon Romanovsky goto err_adev_init; 1664a925b5e3SLeon Romanovsky 166548f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 166648f02eefSParav Pandit if (err) 166748f02eefSParav Pandit goto err_hca_caps; 166848f02eefSParav Pandit 1669dc402cccSYishai Hadas /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1670dc402cccSYishai Hadas * unique id per function which uses mlx5_core. 1671dc402cccSYishai Hadas * Those values are supplied to FW as part of the init HCA command to 1672dc402cccSYishai Hadas * be used by both driver and FW when it's applicable. 1673dc402cccSYishai Hadas */ 1674dc402cccSYishai Hadas dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1675dc402cccSYishai Hadas MAX_SW_VHCA_ID, 1676dc402cccSYishai Hadas GFP_KERNEL); 1677dc402cccSYishai Hadas if (dev->priv.sw_vhca_id < 0) 1678dc402cccSYishai Hadas mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1679dc402cccSYishai Hadas dev->priv.sw_vhca_id); 1680dc402cccSYishai Hadas 168111f3b84dSSaeed Mahameed return 0; 168252c368dcSSaeed Mahameed 168348f02eefSParav Pandit err_hca_caps: 168448f02eefSParav Pandit mlx5_adev_cleanup(dev); 1685a925b5e3SLeon Romanovsky err_adev_init: 1686a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 168752c368dcSSaeed Mahameed err_pagealloc_init: 168852c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 168952c368dcSSaeed Mahameed err_health_init: 169076091b0fSAmir Tzin mlx5_tout_cleanup(dev); 169176091b0fSAmir Tzin err_timeout_init: 169266771a1cSMoshe Shemesh debugfs_remove(dev->priv.dbg.dbg_root); 1693810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1694810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1695810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1696810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1697810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1698d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 169952c368dcSSaeed Mahameed return err; 170011f3b84dSSaeed Mahameed } 170111f3b84dSSaeed Mahameed 17021958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 170311f3b84dSSaeed Mahameed { 1704810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1705810cbb25SParav Pandit 1706dc402cccSYishai Hadas if (priv->sw_vhca_id > 0) 1707dc402cccSYishai Hadas ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1708dc402cccSYishai Hadas 170948f02eefSParav Pandit mlx5_hca_caps_free(dev); 1710a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 171152c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 171252c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 171376091b0fSAmir Tzin mlx5_tout_cleanup(dev); 171466771a1cSMoshe Shemesh debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1715810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1716810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1717810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1718810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1719c7d4e6abSJiri Pirko mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1720810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1721d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 172211f3b84dSSaeed Mahameed } 172311f3b84dSSaeed Mahameed 17246dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 172511f3b84dSSaeed Mahameed { 172611f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 172711f3b84dSSaeed Mahameed struct devlink *devlink; 172811f3b84dSSaeed Mahameed int err; 172911f3b84dSSaeed Mahameed 1730919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 173111f3b84dSSaeed Mahameed if (!devlink) { 17321f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 173311f3b84dSSaeed Mahameed return -ENOMEM; 173411f3b84dSSaeed Mahameed } 173511f3b84dSSaeed Mahameed 173611f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 173727b942fbSParav Pandit dev->device = &pdev->dev; 173827b942fbSParav Pandit dev->pdev = pdev; 173911f3b84dSSaeed Mahameed 1740386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1741386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1742386e75afSHuy Nguyen 1743a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 17444d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 17454d8be211SLeon Romanovsky err = dev->priv.adev_idx; 17464d8be211SLeon Romanovsky goto adev_init_err; 17474d8be211SLeon Romanovsky } 1748a925b5e3SLeon Romanovsky 174927b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 175011f3b84dSSaeed Mahameed if (err) 175111f3b84dSSaeed Mahameed goto mdev_init_err; 175211f3b84dSSaeed Mahameed 175311f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 17549603b61dSJack Morgenstein if (err) { 175598a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 175698a8e6fcSHuy Nguyen err); 175711f3b84dSSaeed Mahameed goto pci_init_err; 17589603b61dSJack Morgenstein } 17599603b61dSJack Morgenstein 17606dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 17619603b61dSJack Morgenstein if (err) { 17626dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 176398a8e6fcSHuy Nguyen err); 17646dea2f7eSLeon Romanovsky goto err_init_one; 17659603b61dSJack Morgenstein } 176659211bd3SMohamad Haj Yahia 17678b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 17688b9d8baaSAlex Vesker if (err) 17698b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 17708b9d8baaSAlex Vesker 17715d47f6c8SDaniel Jurgens pci_save_state(pdev); 177264ea2d0eSLeon Romanovsky devlink_register(devlink); 17739603b61dSJack Morgenstein return 0; 17749603b61dSJack Morgenstein 17756dea2f7eSLeon Romanovsky err_init_one: 1776868bc06bSSaeed Mahameed mlx5_pci_close(dev); 177711f3b84dSSaeed Mahameed pci_init_err: 177811f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 177911f3b84dSSaeed Mahameed mdev_init_err: 1780a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 17814d8be211SLeon Romanovsky adev_init_err: 17821f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1783a31208b1SMajd Dibbiny 17849603b61dSJack Morgenstein return err; 17859603b61dSJack Morgenstein } 1786a31208b1SMajd Dibbiny 17879603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 17889603b61dSJack Morgenstein { 17899603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1790feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 17919603b61dSJack Morgenstein 179216d42d31SShay Drory /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 179316d42d31SShay Drory * fw_reset before unregistering the devlink. 179416d42d31SShay Drory */ 179516d42d31SShay Drory mlx5_drain_fw_reset(dev); 17968324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 179764ea2d0eSLeon Romanovsky devlink_unregister(devlink); 1798143a41d7SYishai Hadas mlx5_sriov_disable(pdev); 17998b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 180041798df9SParav Pandit mlx5_drain_health_wq(dev); 18016dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1802868bc06bSSaeed Mahameed mlx5_pci_close(dev); 180311f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1804a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 18051f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 18069603b61dSJack Morgenstein } 18079603b61dSJack Morgenstein 1808fad1783aSSaeed Mahameed #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1809fad1783aSSaeed Mahameed struct mlx5_core_dev *__dev = (dev); \ 1810fad1783aSSaeed Mahameed mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1811fad1783aSSaeed Mahameed __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1812fad1783aSSaeed Mahameed __dev->pci_status, ##__VA_ARGS__); \ 1813fad1783aSSaeed Mahameed }) 1814fad1783aSSaeed Mahameed 1815fad1783aSSaeed Mahameed static const char *result2str(enum pci_ers_result result) 1816fad1783aSSaeed Mahameed { 1817fad1783aSSaeed Mahameed return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1818fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1819fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1820fad1783aSSaeed Mahameed "unknown"; 1821fad1783aSSaeed Mahameed } 1822fad1783aSSaeed Mahameed 182389d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 182489d44f0aSMajd Dibbiny pci_channel_state_t state) 182589d44f0aSMajd Dibbiny { 182689d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1827fad1783aSSaeed Mahameed enum pci_ers_result res; 182889d44f0aSMajd Dibbiny 1829fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 183004c0c1abSMohamad Haj Yahia 18318812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 18323e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 183372ed5d56SJiri Pirko mlx5_unload_one(dev, true); 18345e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 183589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 183605ac2c0bSMohamad Haj Yahia 1837fad1783aSSaeed Mahameed res = state == pci_channel_io_perm_failure ? 183889d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1839fad1783aSSaeed Mahameed 1840394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 1841394164f9SRoy Novich __func__, dev->state, dev->pci_status, res, result2str(res)); 1842fad1783aSSaeed Mahameed return res; 184389d44f0aSMajd Dibbiny } 184489d44f0aSMajd Dibbiny 1845d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1846d57847dcSDaniel Jurgens * for the health counter to start counting. 184789d44f0aSMajd Dibbiny */ 1848d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 184989d44f0aSMajd Dibbiny { 185089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 185189d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 185289d44f0aSMajd Dibbiny const int niter = 100; 1853d57847dcSDaniel Jurgens u32 last_count = 0; 185489d44f0aSMajd Dibbiny u32 count; 185589d44f0aSMajd Dibbiny int i; 185689d44f0aSMajd Dibbiny 185789d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 185889d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 185989d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1860d57847dcSDaniel Jurgens if (last_count && last_count != count) { 186198a8e6fcSHuy Nguyen mlx5_core_info(dev, 186298a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 186398a8e6fcSHuy Nguyen count, i); 1864d57847dcSDaniel Jurgens return 0; 1865d57847dcSDaniel Jurgens } 1866d57847dcSDaniel Jurgens last_count = count; 186789d44f0aSMajd Dibbiny } 186889d44f0aSMajd Dibbiny msleep(50); 186989d44f0aSMajd Dibbiny } 187089d44f0aSMajd Dibbiny 1871d57847dcSDaniel Jurgens return -ETIMEDOUT; 187289d44f0aSMajd Dibbiny } 187389d44f0aSMajd Dibbiny 18741061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 18751061c90fSMohamad Haj Yahia { 1876fad1783aSSaeed Mahameed enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 18771061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18781061c90fSMohamad Haj Yahia int err; 18791061c90fSMohamad Haj Yahia 1880394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 1881394164f9SRoy Novich __func__, dev->state, dev->pci_status); 18821061c90fSMohamad Haj Yahia 18831061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 18841061c90fSMohamad Haj Yahia if (err) { 188598a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 188698a8e6fcSHuy Nguyen __func__, err); 1887fad1783aSSaeed Mahameed goto out; 18881061c90fSMohamad Haj Yahia } 18891061c90fSMohamad Haj Yahia 18901061c90fSMohamad Haj Yahia pci_set_master(pdev); 18911061c90fSMohamad Haj Yahia pci_restore_state(pdev); 18925d47f6c8SDaniel Jurgens pci_save_state(pdev); 18931061c90fSMohamad Haj Yahia 1894fad1783aSSaeed Mahameed err = wait_vital(pdev); 1895fad1783aSSaeed Mahameed if (err) { 1896fad1783aSSaeed Mahameed mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1897fad1783aSSaeed Mahameed __func__, err); 1898fad1783aSSaeed Mahameed goto out; 18991061c90fSMohamad Haj Yahia } 19001061c90fSMohamad Haj Yahia 1901fad1783aSSaeed Mahameed res = PCI_ERS_RESULT_RECOVERED; 1902fad1783aSSaeed Mahameed out: 1903394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 1904394164f9SRoy Novich __func__, dev->state, dev->pci_status, err, res, result2str(res)); 1905fad1783aSSaeed Mahameed return res; 19061061c90fSMohamad Haj Yahia } 19071061c90fSMohamad Haj Yahia 190889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 190989d44f0aSMajd Dibbiny { 191089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 191189d44f0aSMajd Dibbiny int err; 191289d44f0aSMajd Dibbiny 1913fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, loading driver..\n"); 191489d44f0aSMajd Dibbiny 19155977ac39SJiri Pirko err = mlx5_load_one(dev); 1916416ef713SRoy Novich if (!err) 1917416ef713SRoy Novich devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1918416ef713SRoy Novich DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1919416ef713SRoy Novich 1920fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1921fad1783aSSaeed Mahameed !err ? "recovered" : "Failed"); 192289d44f0aSMajd Dibbiny } 192389d44f0aSMajd Dibbiny 192489d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 192589d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 192689d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 192789d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 192889d44f0aSMajd Dibbiny }; 192989d44f0aSMajd Dibbiny 19308812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 19318812c24dSMajd Dibbiny { 1932fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1933fcd29ad1SFeras Daoud int ret = 1; 19348812c24dSMajd Dibbiny 1935fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1936fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1937fcd29ad1SFeras Daoud 1938fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1939fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1940fcd29ad1SFeras Daoud 1941fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 19428812c24dSMajd Dibbiny return -EOPNOTSUPP; 19438812c24dSMajd Dibbiny 19448812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 19458812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 19468812c24dSMajd Dibbiny return -EAGAIN; 19478812c24dSMajd Dibbiny } 19488812c24dSMajd Dibbiny 1949d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1950b0ea505bSJulia Lawall * with the HCA, so the health poll is no longer needed. 1951d2aa060dSHuy Nguyen */ 1952d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 195376d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1954d2aa060dSHuy Nguyen 1955fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1956fcd29ad1SFeras Daoud if (!ret) 1957fcd29ad1SFeras Daoud goto succeed; 1958fcd29ad1SFeras Daoud 19598812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1960fcd29ad1SFeras Daoud if (!ret) 1961fcd29ad1SFeras Daoud goto succeed; 1962fcd29ad1SFeras Daoud 19638812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1964d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 19658812c24dSMajd Dibbiny return ret; 19668812c24dSMajd Dibbiny 1967fcd29ad1SFeras Daoud succeed: 19688812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 19698812c24dSMajd Dibbiny 19701ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 19711ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 19721ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 19731ef903bfSDaniel Jurgens * contexts. 19741ef903bfSDaniel Jurgens */ 19751ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 19761ef903bfSDaniel Jurgens 19778812c24dSMajd Dibbiny return 0; 19788812c24dSMajd Dibbiny } 19798812c24dSMajd Dibbiny 19805fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 19815fc7197dSMajd Dibbiny { 19825fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19838812c24dSMajd Dibbiny int err; 19845fc7197dSMajd Dibbiny 198598a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 19868324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 19878812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 19888812c24dSMajd Dibbiny if (err) 198972ed5d56SJiri Pirko mlx5_unload_one(dev, false); 19905fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 19915fc7197dSMajd Dibbiny } 19925fc7197dSMajd Dibbiny 19938fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 19948fc3e29bSMark Bloch { 19958fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19968fc3e29bSMark Bloch 199772ed5d56SJiri Pirko mlx5_unload_one(dev, true); 19988fc3e29bSMark Bloch 19998fc3e29bSMark Bloch return 0; 20008fc3e29bSMark Bloch } 20018fc3e29bSMark Bloch 20028fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 20038fc3e29bSMark Bloch { 20048fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 20058fc3e29bSMark Bloch 20065977ac39SJiri Pirko return mlx5_load_one(dev); 20078fc3e29bSMark Bloch } 20088fc3e29bSMark Bloch 20099603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 2010bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2011fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2012bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2013fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2014bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2015fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 20167092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 201764dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2018d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2019d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2020d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2021d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 202285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 202385327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2024b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2025505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2026f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 20272e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 20282e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2029d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2030dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2031f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 20329603b61dSJack Morgenstein { 0, } 20339603b61dSJack Morgenstein }; 20349603b61dSJack Morgenstein 20359603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 20369603b61dSJack Morgenstein 203704c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 203804c0c1abSMohamad Haj Yahia { 2039b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 204072ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, false); 204104c0c1abSMohamad Haj Yahia } 204204c0c1abSMohamad Haj Yahia 2043fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 204404c0c1abSMohamad Haj Yahia { 204533de865fSMoshe Shemesh if (!mlx5_core_is_sf(dev)) { 204604c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 204733de865fSMoshe Shemesh if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 204833de865fSMoshe Shemesh return -EIO; 204933de865fSMoshe Shemesh } 205033de865fSMoshe Shemesh 2051d3dbdc9fSMoshe Shemesh return mlx5_load_one_devl_locked(dev, true); 205204c0c1abSMohamad Haj Yahia } 205304c0c1abSMohamad Haj Yahia 20549603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 205517a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 20569603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 20576dea2f7eSLeon Romanovsky .probe = probe_one, 205889d44f0aSMajd Dibbiny .remove = remove_one, 20598fc3e29bSMark Bloch .suspend = mlx5_suspend, 20608fc3e29bSMark Bloch .resume = mlx5_resume, 20615fc7197dSMajd Dibbiny .shutdown = shutdown, 2062fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 2063fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 2064e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2065e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 20669603b61dSJack Morgenstein }; 2067e126ba97SEli Cohen 20681695b97bSYishai Hadas /** 20691695b97bSYishai Hadas * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 20701695b97bSYishai Hadas * mlx5_core is its driver. 20711695b97bSYishai Hadas * @pdev: The associated PCI device. 20721695b97bSYishai Hadas * 20731695b97bSYishai Hadas * Upon return the interface state lock stay held to let caller uses it safely. 20741695b97bSYishai Hadas * Caller must ensure to use the returned mlx5 device for a narrow window 20751695b97bSYishai Hadas * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 20761695b97bSYishai Hadas * 20771695b97bSYishai Hadas * Return: Pointer to the associated mlx5_core_dev or NULL. 20781695b97bSYishai Hadas */ 20791695b97bSYishai Hadas struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 20801695b97bSYishai Hadas { 20811695b97bSYishai Hadas struct mlx5_core_dev *mdev; 20821695b97bSYishai Hadas 20831695b97bSYishai Hadas mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 20841695b97bSYishai Hadas if (IS_ERR(mdev)) 20851695b97bSYishai Hadas return NULL; 20861695b97bSYishai Hadas 20871695b97bSYishai Hadas mutex_lock(&mdev->intf_state_mutex); 20881695b97bSYishai Hadas if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 20891695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 20901695b97bSYishai Hadas return NULL; 20911695b97bSYishai Hadas } 20921695b97bSYishai Hadas 20931695b97bSYishai Hadas return mdev; 20941695b97bSYishai Hadas } 20951695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_get_core_dev); 20961695b97bSYishai Hadas 20971695b97bSYishai Hadas /** 20981695b97bSYishai Hadas * mlx5_vf_put_core_dev - Put the mlx5 core device back. 20991695b97bSYishai Hadas * @mdev: The mlx5 core device. 21001695b97bSYishai Hadas * 21011695b97bSYishai Hadas * Upon return the interface state lock is unlocked and caller should not 21021695b97bSYishai Hadas * access the mdev any more. 21031695b97bSYishai Hadas */ 21041695b97bSYishai Hadas void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 21051695b97bSYishai Hadas { 21061695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 21071695b97bSYishai Hadas } 21081695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_put_core_dev); 21091695b97bSYishai Hadas 2110f663ad98SKamal Heib static void mlx5_core_verify_params(void) 2111f663ad98SKamal Heib { 2112f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 2113f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2114f663ad98SKamal Heib prof_sel, 2115f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 2116f663ad98SKamal Heib MLX5_DEFAULT_PROF); 2117f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 2118f663ad98SKamal Heib } 2119f663ad98SKamal Heib } 2120f663ad98SKamal Heib 21212c1e1b94SRandy Dunlap static int __init mlx5_init(void) 2122e126ba97SEli Cohen { 2123e126ba97SEli Cohen int err; 2124e126ba97SEli Cohen 212517a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 212617a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 212717a7612bSLeon Romanovsky 21288737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 21298737f818SDaniel Jurgens 2130f663ad98SKamal Heib mlx5_core_verify_params(); 2131e126ba97SEli Cohen mlx5_register_debugfs(); 2132e126ba97SEli Cohen 21338f0d1451SShay Drory err = mlx5e_init(); 21349603b61dSJack Morgenstein if (err) 2135ac6ea6e8SEli Cohen goto err_debug; 21369603b61dSJack Morgenstein 21371958fc2fSParav Pandit err = mlx5_sf_driver_register(); 21381958fc2fSParav Pandit if (err) 21391958fc2fSParav Pandit goto err_sf; 21401958fc2fSParav Pandit 21418f0d1451SShay Drory err = pci_register_driver(&mlx5_core_driver); 2142c633e799SLeon Romanovsky if (err) 21438f0d1451SShay Drory goto err_pci; 2144f62b8bb8SAmir Vadai 2145e126ba97SEli Cohen return 0; 2146e126ba97SEli Cohen 21478f0d1451SShay Drory err_pci: 2148c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 21491958fc2fSParav Pandit err_sf: 21508f0d1451SShay Drory mlx5e_cleanup(); 2151e126ba97SEli Cohen err_debug: 2152e126ba97SEli Cohen mlx5_unregister_debugfs(); 2153e126ba97SEli Cohen return err; 2154e126ba97SEli Cohen } 2155e126ba97SEli Cohen 21562c1e1b94SRandy Dunlap static void __exit mlx5_cleanup(void) 2157e126ba97SEli Cohen { 21589603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 21598f0d1451SShay Drory mlx5_sf_driver_unregister(); 21608f0d1451SShay Drory mlx5e_cleanup(); 2161e126ba97SEli Cohen mlx5_unregister_debugfs(); 2162e126ba97SEli Cohen } 2163e126ba97SEli Cohen 21642c1e1b94SRandy Dunlap module_init(mlx5_init); 21652c1e1b94SRandy Dunlap module_exit(mlx5_cleanup); 2166