1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40db058a18SSaeed Mahameed #include <linux/interrupt.h> 41e3297246SEli Cohen #include <linux/delay.h> 42e126ba97SEli Cohen #include <linux/mlx5/driver.h> 43e126ba97SEli Cohen #include <linux/mlx5/cq.h> 44e126ba97SEli Cohen #include <linux/mlx5/qp.h> 45e126ba97SEli Cohen #include <linux/debugfs.h> 46f66f049fSEli Cohen #include <linux/kmod.h> 47b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 48c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 49907af0f0SLeon Romanovsky #include <linux/version.h> 50feae9087SOr Gerlitz #include <net/devlink.h> 51e126ba97SEli Cohen #include "mlx5_core.h" 52f2f3df55SSaeed Mahameed #include "lib/eq.h" 5316d76083SSaeed Mahameed #include "fs_core.h" 54eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 55073bb189SSaeed Mahameed #include "eswitch.h" 561f28d776SEran Ben Elisha #include "devlink.h" 5738b9f903SMoshe Shemesh #include "fw_reset.h" 5852ec462eSIlan Tayari #include "lib/mlx5.h" 595945e1adSAmir Tzin #include "lib/tout.h" 60e29341fbSIlan Tayari #include "fpga/core.h" 61c6e3b421SLeon Romanovsky #include "en_accel/ipsec.h" 627c39afb3SFeras Daoud #include "lib/clock.h" 63358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 640ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 65fadd59fcSAviv Heller #include "lib/devcom.h" 66b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 6724406953SFeras Daoud #include "diag/fw_tracer.h" 68591905baSBodong Wang #include "ecpf.h" 6987175120SEran Ben Elisha #include "lib/hv_vhca.h" 7012206b17SAya Levin #include "diag/rsc_dump.h" 71f3196bb0SParav Pandit #include "sf/vhca_event.h" 7290d010b8SParav Pandit #include "sf/dev/dev.h" 736a327321SParav Pandit #include "sf/sf.h" 743b43190bSShay Drory #include "mlx5_irq.h" 751f507e80SAdham Faris #include "hwmon.h" 76e126ba97SEli Cohen 77e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 80e126ba97SEli Cohen 81f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 82f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84e126ba97SEli Cohen 85f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 879603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 889603b61dSJack Morgenstein 898737f818SDaniel Jurgens static u32 sw_owner_id[4]; 90dc402cccSYishai Hadas #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 91dc402cccSYishai Hadas static DEFINE_IDA(sw_vhca_ida); 928737f818SDaniel Jurgens 93f91e6d89SEran Ben Elisha enum { 94f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 95f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 96f91e6d89SEran Ben Elisha }; 97f91e6d89SEran Ben Elisha 98f79a609eSMaher Sanalla #define LOG_MAX_SUPPORTED_QPS 0xff 99f79a609eSMaher Sanalla 1009603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1019603b61dSJack Morgenstein [0] = { 1029603b61dSJack Morgenstein .mask = 0, 1039df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 1049603b61dSJack Morgenstein }, 1059603b61dSJack Morgenstein [1] = { 1069603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1079603b61dSJack Morgenstein .log_max_qp = 12, 1089df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 1099df839a7SParav Pandit 1109603b61dSJack Morgenstein }, 1119603b61dSJack Morgenstein [2] = { 1129603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1139603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 114f79a609eSMaher Sanalla .log_max_qp = LOG_MAX_SUPPORTED_QPS, 1159df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 1169603b61dSJack Morgenstein .mr_cache[0] = { 1179603b61dSJack Morgenstein .size = 500, 1189603b61dSJack Morgenstein .limit = 250 1199603b61dSJack Morgenstein }, 1209603b61dSJack Morgenstein .mr_cache[1] = { 1219603b61dSJack Morgenstein .size = 500, 1229603b61dSJack Morgenstein .limit = 250 1239603b61dSJack Morgenstein }, 1249603b61dSJack Morgenstein .mr_cache[2] = { 1259603b61dSJack Morgenstein .size = 500, 1269603b61dSJack Morgenstein .limit = 250 1279603b61dSJack Morgenstein }, 1289603b61dSJack Morgenstein .mr_cache[3] = { 1299603b61dSJack Morgenstein .size = 500, 1309603b61dSJack Morgenstein .limit = 250 1319603b61dSJack Morgenstein }, 1329603b61dSJack Morgenstein .mr_cache[4] = { 1339603b61dSJack Morgenstein .size = 500, 1349603b61dSJack Morgenstein .limit = 250 1359603b61dSJack Morgenstein }, 1369603b61dSJack Morgenstein .mr_cache[5] = { 1379603b61dSJack Morgenstein .size = 500, 1389603b61dSJack Morgenstein .limit = 250 1399603b61dSJack Morgenstein }, 1409603b61dSJack Morgenstein .mr_cache[6] = { 1419603b61dSJack Morgenstein .size = 500, 1429603b61dSJack Morgenstein .limit = 250 1439603b61dSJack Morgenstein }, 1449603b61dSJack Morgenstein .mr_cache[7] = { 1459603b61dSJack Morgenstein .size = 500, 1469603b61dSJack Morgenstein .limit = 250 1479603b61dSJack Morgenstein }, 1489603b61dSJack Morgenstein .mr_cache[8] = { 1499603b61dSJack Morgenstein .size = 500, 1509603b61dSJack Morgenstein .limit = 250 1519603b61dSJack Morgenstein }, 1529603b61dSJack Morgenstein .mr_cache[9] = { 1539603b61dSJack Morgenstein .size = 500, 1549603b61dSJack Morgenstein .limit = 250 1559603b61dSJack Morgenstein }, 1569603b61dSJack Morgenstein .mr_cache[10] = { 1579603b61dSJack Morgenstein .size = 500, 1589603b61dSJack Morgenstein .limit = 250 1599603b61dSJack Morgenstein }, 1609603b61dSJack Morgenstein .mr_cache[11] = { 1619603b61dSJack Morgenstein .size = 500, 1629603b61dSJack Morgenstein .limit = 250 1639603b61dSJack Morgenstein }, 1649603b61dSJack Morgenstein .mr_cache[12] = { 1659603b61dSJack Morgenstein .size = 64, 1669603b61dSJack Morgenstein .limit = 32 1679603b61dSJack Morgenstein }, 1689603b61dSJack Morgenstein .mr_cache[13] = { 1699603b61dSJack Morgenstein .size = 32, 1709603b61dSJack Morgenstein .limit = 16 1719603b61dSJack Morgenstein }, 1729603b61dSJack Morgenstein .mr_cache[14] = { 1739603b61dSJack Morgenstein .size = 16, 1749603b61dSJack Morgenstein .limit = 8 1759603b61dSJack Morgenstein }, 1769603b61dSJack Morgenstein .mr_cache[15] = { 1779603b61dSJack Morgenstein .size = 8, 1789603b61dSJack Morgenstein .limit = 4 1799603b61dSJack Morgenstein }, 1809603b61dSJack Morgenstein }, 1819df839a7SParav Pandit [3] = { 1829df839a7SParav Pandit .mask = MLX5_PROF_MASK_QP_SIZE, 1839df839a7SParav Pandit .log_max_qp = LOG_MAX_SUPPORTED_QPS, 1849df839a7SParav Pandit .num_cmd_caches = 0, 1859df839a7SParav Pandit }, 1869603b61dSJack Morgenstein }; 187e126ba97SEli Cohen 188b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189b8a92577SDaniel Jurgens u32 warn_time_mili) 190e3297246SEli Cohen { 191b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193cdfc6ffbSShay Drory u32 fw_initializing; 194e3297246SEli Cohen int err = 0; 195e3297246SEli Cohen 196cdfc6ffbSShay Drory do { 197cdfc6ffbSShay Drory fw_initializing = ioread32be(&dev->iseg->initializing); 198cdfc6ffbSShay Drory if (!(fw_initializing >> 31)) 199cdfc6ffbSShay Drory break; 2008324a02cSGavin Li if (time_after(jiffies, end) || 201c05d145aSMoshe Shemesh test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 202e3297246SEli Cohen err = -EBUSY; 203e3297246SEli Cohen break; 204e3297246SEli Cohen } 205b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 206cdfc6ffbSShay Drory mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 207cdfc6ffbSShay Drory jiffies_to_msecs(end - warn) / 1000, fw_initializing); 208b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 209b8a92577SDaniel Jurgens } 2105945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 211cdfc6ffbSShay Drory } while (true); 212e3297246SEli Cohen 213e3297246SEli Cohen return err; 214e3297246SEli Cohen } 215e3297246SEli Cohen 216012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 217012e50e1SHuy Nguyen { 218012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 219012e50e1SHuy Nguyen driver_version); 2203ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 221012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 222012e50e1SHuy Nguyen char *string; 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 225012e50e1SHuy Nguyen return; 226012e50e1SHuy Nguyen 227012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 228012e50e1SHuy Nguyen 229012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 23517a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 239012e50e1SHuy Nguyen 240012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 241907af0f0SLeon Romanovsky 242907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 24388a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 24488a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 245012e50e1SHuy Nguyen 246012e50e1SHuy Nguyen /*Send the command*/ 247012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 248012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 249012e50e1SHuy Nguyen 2503ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 251012e50e1SHuy Nguyen } 252012e50e1SHuy Nguyen 253e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 254e126ba97SEli Cohen { 255e126ba97SEli Cohen int err; 256e126ba97SEli Cohen 257eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 258e126ba97SEli Cohen if (err) { 2591a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 260eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 261e126ba97SEli Cohen if (err) { 2621a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 263e126ba97SEli Cohen return err; 264e126ba97SEli Cohen } 265e126ba97SEli Cohen } 266e126ba97SEli Cohen 267e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 268e126ba97SEli Cohen return err; 269e126ba97SEli Cohen } 270e126ba97SEli Cohen 27189d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27289d44f0aSMajd Dibbiny { 27389d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27489d44f0aSMajd Dibbiny int err = 0; 27589d44f0aSMajd Dibbiny 27689d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27789d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27889d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27989d44f0aSMajd Dibbiny if (!err) 28089d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28189d44f0aSMajd Dibbiny } 28289d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28389d44f0aSMajd Dibbiny 28489d44f0aSMajd Dibbiny return err; 28589d44f0aSMajd Dibbiny } 28689d44f0aSMajd Dibbiny 28789d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28889d44f0aSMajd Dibbiny { 28989d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29089d44f0aSMajd Dibbiny 29189d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29289d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29389d44f0aSMajd Dibbiny pci_disable_device(pdev); 29489d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29589d44f0aSMajd Dibbiny } 29689d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29789d44f0aSMajd Dibbiny } 29889d44f0aSMajd Dibbiny 299e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 300e126ba97SEli Cohen { 301e126ba97SEli Cohen int err = 0; 302e126ba97SEli Cohen 303e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3041a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 305e126ba97SEli Cohen return -ENODEV; 306e126ba97SEli Cohen } 307e126ba97SEli Cohen 30817a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 309e126ba97SEli Cohen if (err) 310e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 311e126ba97SEli Cohen 312e126ba97SEli Cohen return err; 313e126ba97SEli Cohen } 314e126ba97SEli Cohen 315e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 316e126ba97SEli Cohen { 317e126ba97SEli Cohen pci_release_regions(pdev); 318e126ba97SEli Cohen } 319e126ba97SEli Cohen 320bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 321e126ba97SEli Cohen u8 he; 322e126ba97SEli Cohen u8 rsvd[15]; 323e126ba97SEli Cohen }; 324e126ba97SEli Cohen 3252974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 326c7a08ac7SEli Cohen { 327c7a08ac7SEli Cohen switch (size) { 328c7a08ac7SEli Cohen case 128: 329c7a08ac7SEli Cohen return 0; 330c7a08ac7SEli Cohen case 256: 331c7a08ac7SEli Cohen return 1; 332c7a08ac7SEli Cohen case 512: 333c7a08ac7SEli Cohen return 2; 334c7a08ac7SEli Cohen case 1024: 335c7a08ac7SEli Cohen return 3; 336c7a08ac7SEli Cohen case 2048: 337c7a08ac7SEli Cohen return 4; 338c7a08ac7SEli Cohen case 4096: 339c7a08ac7SEli Cohen return 5; 340c7a08ac7SEli Cohen default: 3412974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 342c7a08ac7SEli Cohen return 0; 343c7a08ac7SEli Cohen } 344c7a08ac7SEli Cohen } 345c7a08ac7SEli Cohen 346c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 347c7d4e6abSJiri Pirko { 348c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 349c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev = netdev; 350c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351c7d4e6abSJiri Pirko netdev); 352c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353c7d4e6abSJiri Pirko } 354c7d4e6abSJiri Pirko 355c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 356c7d4e6abSJiri Pirko { 357c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 358c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 359c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev); 360c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 361c7d4e6abSJiri Pirko } 362c7d4e6abSJiri Pirko EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 363c7d4e6abSJiri Pirko 364*a41cb591SShay Drory int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 365938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 366c7a08ac7SEli Cohen { 367b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 368b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 369938fe83cSSaeed Mahameed void *out, *hca_caps; 370938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 371c7a08ac7SEli Cohen int err; 372c7a08ac7SEli Cohen 373b775516bSEli Cohen memset(in, 0, sizeof(in)); 374b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 375c7a08ac7SEli Cohen if (!out) 376c7a08ac7SEli Cohen return -ENOMEM; 377938fe83cSSaeed Mahameed 378b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 379b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3803ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 381c7a08ac7SEli Cohen if (err) { 382938fe83cSSaeed Mahameed mlx5_core_warn(dev, 383938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 384938fe83cSSaeed Mahameed cap_type, cap_mode, err); 385c7a08ac7SEli Cohen goto query_ex; 386c7a08ac7SEli Cohen } 387c7a08ac7SEli Cohen 388938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 389938fe83cSSaeed Mahameed 390938fe83cSSaeed Mahameed switch (cap_mode) { 391938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 39248f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 393938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 394938fe83cSSaeed Mahameed break; 395938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 39648f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 397938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 398938fe83cSSaeed Mahameed break; 399938fe83cSSaeed Mahameed default: 400938fe83cSSaeed Mahameed mlx5_core_warn(dev, 401938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 402938fe83cSSaeed Mahameed cap_type, cap_mode); 403938fe83cSSaeed Mahameed err = -EINVAL; 404938fe83cSSaeed Mahameed break; 405938fe83cSSaeed Mahameed } 406c7a08ac7SEli Cohen query_ex: 407c7a08ac7SEli Cohen kfree(out); 408c7a08ac7SEli Cohen return err; 409c7a08ac7SEli Cohen } 410c7a08ac7SEli Cohen 411b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 412b06e7de8SLeon Romanovsky { 413b06e7de8SLeon Romanovsky int ret; 414b06e7de8SLeon Romanovsky 415b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 416b06e7de8SLeon Romanovsky if (ret) 417b06e7de8SLeon Romanovsky return ret; 418b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 419b06e7de8SLeon Romanovsky } 420b06e7de8SLeon Romanovsky 421a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 422c7a08ac7SEli Cohen { 423b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 424f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4253ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 426c7a08ac7SEli Cohen } 42787b8de49SEli Cohen 428a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 429f91e6d89SEran Ben Elisha { 430f91e6d89SEran Ben Elisha void *set_hca_cap; 431f91e6d89SEran Ben Elisha int req_endianness; 432f91e6d89SEran Ben Elisha int err; 433f91e6d89SEran Ben Elisha 434a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 435a2a322f4SLeon Romanovsky return 0; 436a2a322f4SLeon Romanovsky 437b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 438f91e6d89SEran Ben Elisha if (err) 439f91e6d89SEran Ben Elisha return err; 440f91e6d89SEran Ben Elisha 441f91e6d89SEran Ben Elisha req_endianness = 442f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 443bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 444f91e6d89SEran Ben Elisha 445f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 446f91e6d89SEran Ben Elisha return 0; 447f91e6d89SEran Ben Elisha 448f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 449f91e6d89SEran Ben Elisha 450f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 451bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 452f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 453f91e6d89SEran Ben Elisha 454a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 455f91e6d89SEran Ben Elisha } 456f91e6d89SEran Ben Elisha 457a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45846861e3eSMoni Shoua { 45946861e3eSMoni Shoua void *set_hca_cap; 460fca22e7eSMoni Shoua bool do_set = false; 46146861e3eSMoni Shoua int err; 46246861e3eSMoni Shoua 46337b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46437b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46546861e3eSMoni Shoua return 0; 46646861e3eSMoni Shoua 46746861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46846861e3eSMoni Shoua if (err) 46946861e3eSMoni Shoua return err; 47046861e3eSMoni Shoua 47146861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 47248f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 47346861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47446861e3eSMoni Shoua 475fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 476fca22e7eSMoni Shoua do { \ 477fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 478fca22e7eSMoni Shoua if (_res) { \ 479fca22e7eSMoni Shoua do_set = true; \ 480fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 481fca22e7eSMoni Shoua } \ 482fca22e7eSMoni Shoua } while (0) 48346861e3eSMoni Shoua 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 488fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 489fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 490fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 491fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 49200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 49300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 49400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 49500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49846861e3eSMoni Shoua 499a2a322f4SLeon Romanovsky if (!do_set) 500a2a322f4SLeon Romanovsky return 0; 50146861e3eSMoni Shoua 502a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 50346861e3eSMoni Shoua } 50446861e3eSMoni Shoua 5058680a60fSShay Drory static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 5068680a60fSShay Drory { 5078680a60fSShay Drory struct devlink *devlink = priv_to_devlink(dev); 5088680a60fSShay Drory union devlink_param_value val; 5098680a60fSShay Drory int err; 5108680a60fSShay Drory 511075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5128680a60fSShay Drory DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 5138680a60fSShay Drory &val); 5148680a60fSShay Drory if (!err) 5158680a60fSShay Drory return val.vu32; 5168680a60fSShay Drory mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5178680a60fSShay Drory return err; 5188680a60fSShay Drory } 5198680a60fSShay Drory 5209ca05b0fSMaher Sanalla bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 5219ca05b0fSMaher Sanalla { 5229ca05b0fSMaher Sanalla struct devlink *devlink = priv_to_devlink(dev); 5239ca05b0fSMaher Sanalla union devlink_param_value val; 5249ca05b0fSMaher Sanalla int err; 5259ca05b0fSMaher Sanalla 526075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5279ca05b0fSMaher Sanalla DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 5289ca05b0fSMaher Sanalla &val); 5299ca05b0fSMaher Sanalla 5309ca05b0fSMaher Sanalla if (!err) 5319ca05b0fSMaher Sanalla return val.vbool; 5329ca05b0fSMaher Sanalla 5339ca05b0fSMaher Sanalla mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5349ca05b0fSMaher Sanalla return MLX5_CAP_GEN(dev, roce); 5359ca05b0fSMaher Sanalla } 5369ca05b0fSMaher Sanalla EXPORT_SYMBOL(mlx5_is_roce_on); 5379ca05b0fSMaher Sanalla 538dc402cccSYishai Hadas static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 539dc402cccSYishai Hadas { 540dc402cccSYishai Hadas void *set_hca_cap; 541dc402cccSYishai Hadas int err; 542dc402cccSYishai Hadas 543dc402cccSYishai Hadas if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 544dc402cccSYishai Hadas return 0; 545dc402cccSYishai Hadas 546dc402cccSYishai Hadas err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 547dc402cccSYishai Hadas if (err) 548dc402cccSYishai Hadas return err; 549dc402cccSYishai Hadas 550dc402cccSYishai Hadas if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 551dc402cccSYishai Hadas !(dev->priv.sw_vhca_id > 0)) 552dc402cccSYishai Hadas return 0; 553dc402cccSYishai Hadas 554dc402cccSYishai Hadas set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 555dc402cccSYishai Hadas capability); 556dc402cccSYishai Hadas memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 557dc402cccSYishai Hadas MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 558dc402cccSYishai Hadas MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 559dc402cccSYishai Hadas 560dc402cccSYishai Hadas return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 561dc402cccSYishai Hadas } 562dc402cccSYishai Hadas 563a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 564e126ba97SEli Cohen { 5653410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 566938fe83cSSaeed Mahameed void *set_hca_cap; 5678680a60fSShay Drory int max_uc_list; 568a2a322f4SLeon Romanovsky int err; 569e126ba97SEli Cohen 570b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 571c7a08ac7SEli Cohen if (err) 572a2a322f4SLeon Romanovsky return err; 573e126ba97SEli Cohen 574938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 575938fe83cSSaeed Mahameed capability); 57648f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 577938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 578938fe83cSSaeed Mahameed 579938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 580707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 581938fe83cSSaeed Mahameed 128); 582c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 583938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5842974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 585e126ba97SEli Cohen 586883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 587f79a609eSMaher Sanalla if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 588a6e9085dSMaher Sanalla prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 589f79a609eSMaher Sanalla } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 590883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5913410fbcdSMaor Gottlieb prof->log_max_qp, 592883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5933410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 594883371c4SNoa Osherovich } 595c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 596938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 597938fe83cSSaeed Mahameed prof->log_max_qp); 598e126ba97SEli Cohen 599938fe83cSSaeed Mahameed /* disable cmdif checksum */ 600938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 601c1868b82SEli Cohen 60291828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 60391828bd8SMajd Dibbiny * than 4K. 60491828bd8SMajd Dibbiny */ 60591828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 606f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 607f502d834SEli Cohen 608fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 609fe1e1876SCarol L Soto 610f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 611f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 612f32f5bd2SDaniel Jurgens set_hca_cap, 613f32f5bd2SDaniel Jurgens cache_line_128byte, 614c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 615f32f5bd2SDaniel Jurgens 616dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 617dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 618dd44572aSMoni Shoua 619e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 620e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 6217a9770f1SMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload)) 6227a9770f1SMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, 6237a9770f1SMoshe Shemesh pci_sync_for_fw_update_with_driver_unload, 1); 624e7f4d0bcSMoshe Shemesh 625c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 626c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 627c4b76d8dSDaniel Jurgens set_hca_cap, 628c4b76d8dSDaniel Jurgens num_vhca_ports, 629c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 630c4b76d8dSDaniel Jurgens 631c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 632c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 633c6168161SEran Ben Elisha 6344dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 6354dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 6364dca6509SMichael Guralnik 637f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 638f3196bb0SParav Pandit 639604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 640604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 641604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 642604774adSLeon Romanovsky 643c4ad5f2bSShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 6449ca05b0fSMaher Sanalla MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 6459ca05b0fSMaher Sanalla mlx5_is_roce_on(dev)); 646fbfa97b4SShay Drory 6478680a60fSShay Drory max_uc_list = max_uc_list_get_devlink_param(dev); 6488680a60fSShay Drory if (max_uc_list > 0) 6498680a60fSShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 6508680a60fSShay Drory ilog2(max_uc_list)); 6518680a60fSShay Drory 652a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 653e126ba97SEli Cohen } 654cd23b14bSEli Cohen 655fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 656fbfa97b4SShay Drory * boot process. 657fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 658fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 659fbfa97b4SShay Drory * Hence, the need for this function. 660fbfa97b4SShay Drory * 661fbfa97b4SShay Drory * Returns 662fbfa97b4SShay Drory * True: 663fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 664fbfa97b4SShay Drory * OR: 665fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 666fbfa97b4SShay Drory * 667fbfa97b4SShay Drory * In any other case, return False. 668fbfa97b4SShay Drory */ 669fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 670fbfa97b4SShay Drory { 6719ca05b0fSMaher Sanalla return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 672fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 673fbfa97b4SShay Drory } 674fbfa97b4SShay Drory 67559e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 67659e9e8e4SMark Zhang { 67759e9e8e4SMark Zhang void *set_hca_cap; 67859e9e8e4SMark Zhang int err; 67959e9e8e4SMark Zhang 680fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 68159e9e8e4SMark Zhang return 0; 68259e9e8e4SMark Zhang 68359e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 68459e9e8e4SMark Zhang if (err) 68559e9e8e4SMark Zhang return err; 68659e9e8e4SMark Zhang 68759e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 68859e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 68959e9e8e4SMark Zhang return 0; 69059e9e8e4SMark Zhang 69159e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 69248f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 69359e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 69459e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 69559e9e8e4SMark Zhang 696f4244e55SOr Har-Toov if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 697f4244e55SOr Har-Toov MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 698f4244e55SOr Har-Toov 69959e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 700e126ba97SEli Cohen return err; 701e126ba97SEli Cohen } 702e126ba97SEli Cohen 70390b1df74SLiu, Changcheng static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 70490b1df74SLiu, Changcheng void *set_ctx) 70590b1df74SLiu, Changcheng { 70690b1df74SLiu, Changcheng void *set_hca_cap; 70790b1df74SLiu, Changcheng int err; 70890b1df74SLiu, Changcheng 70990b1df74SLiu, Changcheng if (!MLX5_CAP_GEN(dev, port_selection_cap)) 71090b1df74SLiu, Changcheng return 0; 71190b1df74SLiu, Changcheng 71290b1df74SLiu, Changcheng err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 71390b1df74SLiu, Changcheng if (err) 71490b1df74SLiu, Changcheng return err; 71590b1df74SLiu, Changcheng 71690b1df74SLiu, Changcheng if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 71790b1df74SLiu, Changcheng !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 71890b1df74SLiu, Changcheng return 0; 71990b1df74SLiu, Changcheng 72090b1df74SLiu, Changcheng set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 72190b1df74SLiu, Changcheng memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 72290b1df74SLiu, Changcheng MLX5_ST_SZ_BYTES(port_selection_cap)); 72390b1df74SLiu, Changcheng MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 72490b1df74SLiu, Changcheng 725f9c895a7SRoi Dayan err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 72690b1df74SLiu, Changcheng 72790b1df74SLiu, Changcheng return err; 72890b1df74SLiu, Changcheng } 72990b1df74SLiu, Changcheng 73037b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 73137b6bb77SLeon Romanovsky { 732a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 733a2a322f4SLeon Romanovsky void *set_ctx; 73437b6bb77SLeon Romanovsky int err; 73537b6bb77SLeon Romanovsky 736a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 737a2a322f4SLeon Romanovsky if (!set_ctx) 738a2a322f4SLeon Romanovsky return -ENOMEM; 739a2a322f4SLeon Romanovsky 740a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 74137b6bb77SLeon Romanovsky if (err) { 74298a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 74337b6bb77SLeon Romanovsky goto out; 74437b6bb77SLeon Romanovsky } 74537b6bb77SLeon Romanovsky 746a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 747a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 74837b6bb77SLeon Romanovsky if (err) { 74998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 75037b6bb77SLeon Romanovsky goto out; 75137b6bb77SLeon Romanovsky } 75237b6bb77SLeon Romanovsky 753a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 754a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 75537b6bb77SLeon Romanovsky if (err) { 75698a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 75737b6bb77SLeon Romanovsky goto out; 75837b6bb77SLeon Romanovsky } 75937b6bb77SLeon Romanovsky 76059e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 76159e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 76259e9e8e4SMark Zhang if (err) { 76359e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 76459e9e8e4SMark Zhang goto out; 76559e9e8e4SMark Zhang } 76659e9e8e4SMark Zhang 767dc402cccSYishai Hadas memset(set_ctx, 0, set_sz); 768dc402cccSYishai Hadas err = handle_hca_cap_2(dev, set_ctx); 769dc402cccSYishai Hadas if (err) { 770dc402cccSYishai Hadas mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 771dc402cccSYishai Hadas goto out; 772dc402cccSYishai Hadas } 773dc402cccSYishai Hadas 77490b1df74SLiu, Changcheng memset(set_ctx, 0, set_sz); 77590b1df74SLiu, Changcheng err = handle_hca_cap_port_selection(dev, set_ctx); 77690b1df74SLiu, Changcheng if (err) { 77790b1df74SLiu, Changcheng mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 77890b1df74SLiu, Changcheng goto out; 77990b1df74SLiu, Changcheng } 78090b1df74SLiu, Changcheng 78137b6bb77SLeon Romanovsky out: 782a2a322f4SLeon Romanovsky kfree(set_ctx); 78337b6bb77SLeon Romanovsky return err; 78437b6bb77SLeon Romanovsky } 78537b6bb77SLeon Romanovsky 786e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 787e126ba97SEli Cohen { 788bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 789bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 790e126ba97SEli Cohen int err; 791e126ba97SEli Cohen 792fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 793fc50db98SEli Cohen return 0; 794fc50db98SEli Cohen 795e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 796e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 797e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 798e126ba97SEli Cohen &he_out, sizeof(he_out), 799e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 800e126ba97SEli Cohen return err; 801e126ba97SEli Cohen } 802e126ba97SEli Cohen 803c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 804c85023e1SHuy Nguyen { 805c85023e1SHuy Nguyen int ret = 0; 806c85023e1SHuy Nguyen 807c85023e1SHuy Nguyen /* Disable local_lb by default */ 8088978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 809c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 810c85023e1SHuy Nguyen 811c85023e1SHuy Nguyen return ret; 812c85023e1SHuy Nguyen } 813c85023e1SHuy Nguyen 8140b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 815e126ba97SEli Cohen { 8163ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 817e126ba97SEli Cohen 8180b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 8190b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 82022e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 82122e939a9SBodong Wang dev->caps.embedded_cpu); 8223ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 823e126ba97SEli Cohen } 824e126ba97SEli Cohen 8250b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 826e126ba97SEli Cohen { 8273ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 828e126ba97SEli Cohen 8290b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 8300b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 83122e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 83222e939a9SBodong Wang dev->caps.embedded_cpu); 8333ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 834e126ba97SEli Cohen } 835e126ba97SEli Cohen 836f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 837f62b8bb8SAmir Vadai { 8383ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 8393ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 840f62b8bb8SAmir Vadai u32 sup_issi; 841c4f287c4SSaeed Mahameed int err; 842f62b8bb8SAmir Vadai 843f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 8443ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 845f62b8bb8SAmir Vadai if (err) { 846605bef00SSaeed Mahameed u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 847605bef00SSaeed Mahameed u8 status = MLX5_GET(query_issi_out, query_out, status); 848c4f287c4SSaeed Mahameed 849f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 850f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 851f9c14e46SKamal Heib err, status, syndrome); 852f9c14e46SKamal Heib return err; 853f62b8bb8SAmir Vadai } 854f62b8bb8SAmir Vadai 855f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 856f9c14e46SKamal Heib dev->issi = 0; 857f9c14e46SKamal Heib return 0; 858f62b8bb8SAmir Vadai } 859f62b8bb8SAmir Vadai 860f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 861f62b8bb8SAmir Vadai 862f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 8633ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 864f62b8bb8SAmir Vadai 865f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 866f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 8673ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 868f62b8bb8SAmir Vadai if (err) { 869f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 870f9c14e46SKamal Heib err); 871f62b8bb8SAmir Vadai return err; 872f62b8bb8SAmir Vadai } 873f62b8bb8SAmir Vadai 874f62b8bb8SAmir Vadai dev->issi = 1; 875f62b8bb8SAmir Vadai 876f62b8bb8SAmir Vadai return 0; 877e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 878f62b8bb8SAmir Vadai return 0; 879f62b8bb8SAmir Vadai } 880f62b8bb8SAmir Vadai 8819eb78923SOr Gerlitz return -EOPNOTSUPP; 882f62b8bb8SAmir Vadai } 883f62b8bb8SAmir Vadai 88411f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 88511f3b84dSSaeed Mahameed const struct pci_device_id *id) 886a31208b1SMajd Dibbiny { 887a31208b1SMajd Dibbiny int err = 0; 888a31208b1SMajd Dibbiny 889d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 890e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 891e126ba97SEli Cohen 892aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 893311c7c71SSaeed Mahameed 89489d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 895e126ba97SEli Cohen if (err) { 89698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 89711f3b84dSSaeed Mahameed return err; 898e126ba97SEli Cohen } 899e126ba97SEli Cohen 900e126ba97SEli Cohen err = request_bar(pdev); 901e126ba97SEli Cohen if (err) { 90298a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 903e126ba97SEli Cohen goto err_disable; 904e126ba97SEli Cohen } 905e126ba97SEli Cohen 906e126ba97SEli Cohen pci_set_master(pdev); 907e126ba97SEli Cohen 908e126ba97SEli Cohen err = set_dma_caps(pdev); 909e126ba97SEli Cohen if (err) { 91098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 911e126ba97SEli Cohen goto err_clr_master; 912e126ba97SEli Cohen } 913e126ba97SEli Cohen 914ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 915ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 916ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 917ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 918ce4eee53SMichael Guralnik 919aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 920e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 921e126ba97SEli Cohen if (!dev->iseg) { 922e126ba97SEli Cohen err = -ENOMEM; 92398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 924e126ba97SEli Cohen goto err_clr_master; 925e126ba97SEli Cohen } 926a31208b1SMajd Dibbiny 927b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 928a31208b1SMajd Dibbiny return 0; 929a31208b1SMajd Dibbiny 930a31208b1SMajd Dibbiny err_clr_master: 931a31208b1SMajd Dibbiny release_bar(dev->pdev); 932a31208b1SMajd Dibbiny err_disable: 93389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 934a31208b1SMajd Dibbiny return err; 935a31208b1SMajd Dibbiny } 936a31208b1SMajd Dibbiny 937868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 938a31208b1SMajd Dibbiny { 93942ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 94042ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 94142ea9f1bSShay Drory * before removing the pci bars 94242ea9f1bSShay Drory */ 94342ea9f1bSShay Drory mlx5_drain_health_wq(dev); 944a31208b1SMajd Dibbiny iounmap(dev->iseg); 945a31208b1SMajd Dibbiny release_bar(dev->pdev); 94689d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 947a31208b1SMajd Dibbiny } 948a31208b1SMajd Dibbiny 949868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 95059211bd3SMohamad Haj Yahia { 95159211bd3SMohamad Haj Yahia int err; 95259211bd3SMohamad Haj Yahia 95388d162b4SRoi Dayan dev->priv.devc = mlx5_devcom_register_device(dev); 95488d162b4SRoi Dayan if (IS_ERR(dev->priv.devc)) 95588d162b4SRoi Dayan mlx5_core_warn(dev, "failed to register devcom device %ld\n", 95688d162b4SRoi Dayan PTR_ERR(dev->priv.devc)); 957fadd59fcSAviv Heller 95859211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 95959211bd3SMohamad Haj Yahia if (err) { 96098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 961fadd59fcSAviv Heller goto err_devcom; 96259211bd3SMohamad Haj Yahia } 96359211bd3SMohamad Haj Yahia 964561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 965561aa15aSYuval Avnery if (err) { 966561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 967561aa15aSYuval Avnery goto err_devcom; 968561aa15aSYuval Avnery } 969561aa15aSYuval Avnery 970f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 97159211bd3SMohamad Haj Yahia if (err) { 97298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 973561aa15aSYuval Avnery goto err_irq_cleanup; 97459211bd3SMohamad Haj Yahia } 97559211bd3SMohamad Haj Yahia 97669c1280bSSaeed Mahameed err = mlx5_events_init(dev); 97769c1280bSSaeed Mahameed if (err) { 97898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 97969c1280bSSaeed Mahameed goto err_eq_cleanup; 98069c1280bSSaeed Mahameed } 98169c1280bSSaeed Mahameed 98238b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 98338b9f903SMoshe Shemesh if (err) { 98438b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 98538b9f903SMoshe Shemesh goto err_events_cleanup; 98638b9f903SMoshe Shemesh } 98738b9f903SMoshe Shemesh 9889f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 98959211bd3SMohamad Haj Yahia 99052ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 99152ec462eSIlan Tayari 9927c39afb3SFeras Daoud mlx5_init_clock(dev); 9937c39afb3SFeras Daoud 994358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 9950ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 996358aa5ceSSaeed Mahameed 99759211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 99859211bd3SMohamad Haj Yahia if (err) { 99998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 100059211bd3SMohamad Haj Yahia goto err_tables_cleanup; 100159211bd3SMohamad Haj Yahia } 100259211bd3SMohamad Haj Yahia 1003eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 1004eeb66cdbSSaeed Mahameed if (err) { 100598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1006eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 1007eeb66cdbSSaeed Mahameed } 1008eeb66cdbSSaeed Mahameed 1009c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 1010c2d6e31aSMohamad Haj Yahia if (err) { 101198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 101286eec50bSBodong Wang goto err_mpfs_cleanup; 101386eec50bSBodong Wang } 101486eec50bSBodong Wang 101586eec50bSBodong Wang err = mlx5_eswitch_init(dev); 101686eec50bSBodong Wang if (err) { 101786eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 101886eec50bSBodong Wang goto err_sriov_cleanup; 1019c2d6e31aSMohamad Haj Yahia } 1020c2d6e31aSMohamad Haj Yahia 10219410733cSIlan Tayari err = mlx5_fpga_init(dev); 10229410733cSIlan Tayari if (err) { 102398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 102486eec50bSBodong Wang goto err_eswitch_cleanup; 10259410733cSIlan Tayari } 10269410733cSIlan Tayari 1027f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 1028f3196bb0SParav Pandit if (err) { 1029f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1030f3196bb0SParav Pandit goto err_fpga_cleanup; 1031f3196bb0SParav Pandit } 1032f3196bb0SParav Pandit 10338f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 10348f010541SParav Pandit if (err) { 10358f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 10368f010541SParav Pandit goto err_sf_hw_table_cleanup; 10378f010541SParav Pandit } 10388f010541SParav Pandit 10398f010541SParav Pandit err = mlx5_sf_table_init(dev); 10408f010541SParav Pandit if (err) { 10418f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 10428f010541SParav Pandit goto err_sf_table_cleanup; 10438f010541SParav Pandit } 10448f010541SParav Pandit 1045b3388697SShay Drory err = mlx5_fs_core_alloc(dev); 1046b3388697SShay Drory if (err) { 1047b3388697SShay Drory mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1048b3388697SShay Drory goto err_fs; 1049b3388697SShay Drory } 1050b3388697SShay Drory 1051c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 1052c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 1053a6573514SRoi Dayan mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm)); 1054c9b9dcb4SAriel Levkovich 105524406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 105687175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 105712206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 105824406953SFeras Daoud 105959211bd3SMohamad Haj Yahia return 0; 106059211bd3SMohamad Haj Yahia 1061b3388697SShay Drory err_fs: 1062b3388697SShay Drory mlx5_sf_table_cleanup(dev); 10638f010541SParav Pandit err_sf_table_cleanup: 10648f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 10658f010541SParav Pandit err_sf_hw_table_cleanup: 10668f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 1067f3196bb0SParav Pandit err_fpga_cleanup: 1068f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 1069c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 1070c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 107186eec50bSBodong Wang err_sriov_cleanup: 107286eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1073eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 1074eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 1075c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 1076c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 107759211bd3SMohamad Haj Yahia err_tables_cleanup: 10780ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1079358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 10802a35b2c2SJiri Pirko mlx5_cleanup_clock(dev); 10812a35b2c2SJiri Pirko mlx5_cleanup_reserved_gids(dev); 108202d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 108338b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 108438b9f903SMoshe Shemesh err_events_cleanup: 108569c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 108659211bd3SMohamad Haj Yahia err_eq_cleanup: 1087f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1088561aa15aSYuval Avnery err_irq_cleanup: 1089561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1090fadd59fcSAviv Heller err_devcom: 109188d162b4SRoi Dayan mlx5_devcom_unregister_device(dev->priv.devc); 109259211bd3SMohamad Haj Yahia 109359211bd3SMohamad Haj Yahia return err; 109459211bd3SMohamad Haj Yahia } 109559211bd3SMohamad Haj Yahia 109659211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 109759211bd3SMohamad Haj Yahia { 109812206b17SAya Levin mlx5_rsc_dump_destroy(dev); 109987175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 110024406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 1101c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 1102b3388697SShay Drory mlx5_fs_core_free(dev); 11038f010541SParav Pandit mlx5_sf_table_cleanup(dev); 11048f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 1105f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 11069410733cSIlan Tayari mlx5_fpga_cleanup(dev); 1107c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 110886eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1109eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 111059211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 11110ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1112358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 11137c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 111452ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 111502d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 111638b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 111769c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 1118f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1119561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 112088d162b4SRoi Dayan mlx5_devcom_unregister_device(dev->priv.devc); 112159211bd3SMohamad Haj Yahia } 112259211bd3SMohamad Haj Yahia 11232059cf51SShay Drory static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1124a31208b1SMajd Dibbiny { 1125a31208b1SMajd Dibbiny int err; 1126a31208b1SMajd Dibbiny 112798a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1128e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 1129e126ba97SEli Cohen 113000c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 113100c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 113200c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 113300c6bcb0STal Gilboa 11346c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 11356c780a02SEli Cohen */ 113637ca95e6SGavin Li err = wait_fw_init(dev, timeout, 11375945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 11386c780a02SEli Cohen if (err) { 11395945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 114037ca95e6SGavin Li timeout); 114176091b0fSAmir Tzin return err; 11426c780a02SEli Cohen } 11436c780a02SEli Cohen 114406cd555fSShay Drory err = mlx5_cmd_enable(dev); 1145e126ba97SEli Cohen if (err) { 114698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 114776091b0fSAmir Tzin return err; 1148e126ba97SEli Cohen } 1149e126ba97SEli Cohen 11505945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 11515945e1adSAmir Tzin 11525945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1153e3297246SEli Cohen if (err) { 11545945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 11555945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 115655378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1157e3297246SEli Cohen } 1158e3297246SEli Cohen 1159bbfa4b58SMoshe Shemesh dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1160f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1161f7936dddSEran Ben Elisha 11629b98d395SMoshe Shemesh mlx5_start_health_poll(dev); 11639b98d395SMoshe Shemesh 11640b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1165cd23b14bSEli Cohen if (err) { 116698a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 11679b98d395SMoshe Shemesh goto stop_health_poll; 1168cd23b14bSEli Cohen } 1169cd23b14bSEli Cohen 1170f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1171f62b8bb8SAmir Vadai if (err) { 117298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1173f62b8bb8SAmir Vadai goto err_disable_hca; 1174f62b8bb8SAmir Vadai } 1175f62b8bb8SAmir Vadai 1176cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1177cd23b14bSEli Cohen if (err) { 117898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1179cd23b14bSEli Cohen goto err_disable_hca; 1180cd23b14bSEli Cohen } 1181cd23b14bSEli Cohen 118232def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 118332def412SAmir Tzin if (err) { 118432def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 118532def412SAmir Tzin goto reclaim_boot_pages; 118632def412SAmir Tzin } 118732def412SAmir Tzin 1188e161105eSSaeed Mahameed return 0; 1189e161105eSSaeed Mahameed 1190e161105eSSaeed Mahameed reclaim_boot_pages: 1191e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1192e161105eSSaeed Mahameed err_disable_hca: 1193e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 11949b98d395SMoshe Shemesh stop_health_poll: 11959b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1196e161105eSSaeed Mahameed err_cmd_cleanup: 1197f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 119806cd555fSShay Drory mlx5_cmd_disable(dev); 1199e161105eSSaeed Mahameed 1200e161105eSSaeed Mahameed return err; 1201e161105eSSaeed Mahameed } 1202e161105eSSaeed Mahameed 12032059cf51SShay Drory static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot) 12042059cf51SShay Drory { 12052059cf51SShay Drory mlx5_reclaim_startup_pages(dev); 12062059cf51SShay Drory mlx5_core_disable_hca(dev, 0); 12072059cf51SShay Drory mlx5_stop_health_poll(dev, boot); 12082059cf51SShay Drory mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 120906cd555fSShay Drory mlx5_cmd_disable(dev); 12102059cf51SShay Drory } 12112059cf51SShay Drory 12122059cf51SShay Drory static int mlx5_function_open(struct mlx5_core_dev *dev) 12132059cf51SShay Drory { 12142059cf51SShay Drory int err; 12152059cf51SShay Drory 12162059cf51SShay Drory err = set_hca_ctrl(dev); 12172059cf51SShay Drory if (err) { 12182059cf51SShay Drory mlx5_core_err(dev, "set_hca_ctrl failed\n"); 12192059cf51SShay Drory return err; 12202059cf51SShay Drory } 12212059cf51SShay Drory 12222059cf51SShay Drory err = set_hca_cap(dev); 12232059cf51SShay Drory if (err) { 12242059cf51SShay Drory mlx5_core_err(dev, "set_hca_cap failed\n"); 12252059cf51SShay Drory return err; 12262059cf51SShay Drory } 12272059cf51SShay Drory 12282059cf51SShay Drory err = mlx5_satisfy_startup_pages(dev, 0); 12292059cf51SShay Drory if (err) { 12302059cf51SShay Drory mlx5_core_err(dev, "failed to allocate init pages\n"); 12312059cf51SShay Drory return err; 12322059cf51SShay Drory } 12332059cf51SShay Drory 12342059cf51SShay Drory err = mlx5_cmd_init_hca(dev, sw_owner_id); 12352059cf51SShay Drory if (err) { 12362059cf51SShay Drory mlx5_core_err(dev, "init hca failed\n"); 12372059cf51SShay Drory return err; 12382059cf51SShay Drory } 12392059cf51SShay Drory 12402059cf51SShay Drory mlx5_set_driver_version(dev); 12412059cf51SShay Drory 12422059cf51SShay Drory err = mlx5_query_hca_caps(dev); 12432059cf51SShay Drory if (err) { 12442059cf51SShay Drory mlx5_core_err(dev, "query hca failed\n"); 12452059cf51SShay Drory return err; 12462059cf51SShay Drory } 12472059cf51SShay Drory mlx5_start_health_fw_log_up(dev); 12482059cf51SShay Drory return 0; 12492059cf51SShay Drory } 12502059cf51SShay Drory 12512059cf51SShay Drory static int mlx5_function_close(struct mlx5_core_dev *dev) 1252e161105eSSaeed Mahameed { 1253e161105eSSaeed Mahameed int err; 1254e161105eSSaeed Mahameed 1255e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1256259bbc57SMaor Gottlieb if (err) { 125798a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1258e161105eSSaeed Mahameed return err; 1259e126ba97SEli Cohen } 1260e161105eSSaeed Mahameed 1261e161105eSSaeed Mahameed return 0; 1262259bbc57SMaor Gottlieb } 1263e126ba97SEli Cohen 12642059cf51SShay Drory static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 12652059cf51SShay Drory { 12662059cf51SShay Drory int err; 12672059cf51SShay Drory 12682059cf51SShay Drory err = mlx5_function_enable(dev, boot, timeout); 12692059cf51SShay Drory if (err) 12702059cf51SShay Drory return err; 12712059cf51SShay Drory 12722059cf51SShay Drory err = mlx5_function_open(dev); 12732059cf51SShay Drory if (err) 12742059cf51SShay Drory mlx5_function_disable(dev, boot); 12752059cf51SShay Drory return err; 12762059cf51SShay Drory } 12772059cf51SShay Drory 12782059cf51SShay Drory static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 12792059cf51SShay Drory { 12802059cf51SShay Drory int err = mlx5_function_close(dev); 12812059cf51SShay Drory 12822059cf51SShay Drory if (!err) 12832059cf51SShay Drory mlx5_function_disable(dev, boot); 12842059cf51SShay Drory return err; 12852059cf51SShay Drory } 12862059cf51SShay Drory 1287a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1288e161105eSSaeed Mahameed { 1289e161105eSSaeed Mahameed int err; 1290e161105eSSaeed Mahameed 129101187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 129272f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 129398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 129472f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1295a80d1b68SSaeed Mahameed return err; 1296e126ba97SEli Cohen } 1297e126ba97SEli Cohen 129869c1280bSSaeed Mahameed mlx5_events_start(dev); 12990cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 13000cf53c12SSaeed Mahameed 1301e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1302e1706e62SYuval Avnery if (err) { 1303e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1304e1706e62SYuval Avnery goto err_irq_table; 1305e1706e62SYuval Avnery } 1306e1706e62SYuval Avnery 1307c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1308e126ba97SEli Cohen if (err) { 130998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1310c8e21b3bSSaeed Mahameed goto err_eq_table; 1311e126ba97SEli Cohen } 1312e126ba97SEli Cohen 131324406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 131424406953SFeras Daoud if (err) { 1315f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1316f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1317f62eb932SAya Levin dev->tracer = NULL; 131824406953SFeras Daoud } 131924406953SFeras Daoud 132038b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 132187175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 132287175120SEran Ben Elisha 132312206b17SAya Levin err = mlx5_rsc_dump_init(dev); 132412206b17SAya Levin if (err) { 1325f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1326f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1327f62eb932SAya Levin dev->rsc_dump = NULL; 132812206b17SAya Levin } 132912206b17SAya Levin 133004e87170SMatan Barak err = mlx5_fpga_device_start(dev); 133104e87170SMatan Barak if (err) { 133298a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 133304e87170SMatan Barak goto err_fpga_start; 133404e87170SMatan Barak } 133504e87170SMatan Barak 1336b3388697SShay Drory err = mlx5_fs_core_init(dev); 133786d722adSMaor Gottlieb if (err) { 133898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 133986d722adSMaor Gottlieb goto err_fs; 134086d722adSMaor Gottlieb } 13411466cc5bSYevgeny Petrilin 1342c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1343c85023e1SHuy Nguyen if (err) { 134498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 134594a4b841SLeon Romanovsky goto err_set_hca; 1346c85023e1SHuy Nguyen } 1347c85023e1SHuy Nguyen 1348f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1349f3196bb0SParav Pandit 13506a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 13516a327321SParav Pandit if (err) { 13526a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 13536a327321SParav Pandit goto err_vhca; 13546a327321SParav Pandit } 13556a327321SParav Pandit 135622e939a9SBodong Wang err = mlx5_ec_init(dev); 135722e939a9SBodong Wang if (err) { 135898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 135922e939a9SBodong Wang goto err_ec; 136022e939a9SBodong Wang } 136122e939a9SBodong Wang 1362cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 13635bef709dSParav Pandit err = mlx5_sriov_attach(dev); 13645bef709dSParav Pandit if (err) { 13655bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 13665bef709dSParav Pandit goto err_sriov; 13675bef709dSParav Pandit } 13685bef709dSParav Pandit 136990d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 137090d010b8SParav Pandit 137171b75f0eSMoshe Shemesh err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 137271b75f0eSMoshe Shemesh if (err) 137371b75f0eSMoshe Shemesh goto err_traps_reg; 137471b75f0eSMoshe Shemesh 1375a80d1b68SSaeed Mahameed return 0; 1376a80d1b68SSaeed Mahameed 137771b75f0eSMoshe Shemesh err_traps_reg: 137871b75f0eSMoshe Shemesh mlx5_sf_dev_table_destroy(dev); 137971b75f0eSMoshe Shemesh mlx5_sriov_detach(dev); 1380a80d1b68SSaeed Mahameed err_sriov: 1381cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13825bef709dSParav Pandit mlx5_ec_cleanup(dev); 13835bef709dSParav Pandit err_ec: 13846a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 13856a327321SParav Pandit err_vhca: 1386f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 138794a4b841SLeon Romanovsky err_set_hca: 1388b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1389a80d1b68SSaeed Mahameed err_fs: 1390a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1391a80d1b68SSaeed Mahameed err_fpga_start: 139212206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 139387175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 139438b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1395a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1396a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1397a80d1b68SSaeed Mahameed err_eq_table: 1398e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1399e1706e62SYuval Avnery err_irq_table: 1400a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1401a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1402a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1403a80d1b68SSaeed Mahameed return err; 1404a80d1b68SSaeed Mahameed } 1405a80d1b68SSaeed Mahameed 1406a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1407a80d1b68SSaeed Mahameed { 140871b75f0eSMoshe Shemesh mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 140990d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1410f019679eSChris Mi mlx5_eswitch_disable(dev->priv.eswitch); 14117ba930fcSDaniel Jurgens mlx5_sriov_detach(dev); 1412cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 14135bef709dSParav Pandit mlx5_ec_cleanup(dev); 14146a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1415f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1416b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1417a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 141812206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 141987175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 142038b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1421a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1422a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1423e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1424a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1425a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1426a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1427a80d1b68SSaeed Mahameed } 1428a80d1b68SSaeed Mahameed 1429e71383fbSShay Drory int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) 1430a80d1b68SSaeed Mahameed { 1431e71383fbSShay Drory bool light_probe = mlx5_dev_is_lightweight(dev); 1432a80d1b68SSaeed Mahameed int err = 0; 1433a80d1b68SSaeed Mahameed 1434a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1435a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1436a80d1b68SSaeed Mahameed 14379b98d395SMoshe Shemesh err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1438a80d1b68SSaeed Mahameed if (err) 14394f7400d5SShay Drory goto err_function; 1440a80d1b68SSaeed Mahameed 1441a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1442a80d1b68SSaeed Mahameed if (err) { 144398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1444a80d1b68SSaeed Mahameed goto function_teardown; 1445a80d1b68SSaeed Mahameed } 1446a80d1b68SSaeed Mahameed 1447e71383fbSShay Drory /* In case of light_probe, mlx5_devlink is already registered. 1448e71383fbSShay Drory * Hence, don't register devlink again. 1449e71383fbSShay Drory */ 1450e71383fbSShay Drory if (!light_probe) { 1451fe578cbbSEli Cohen err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1452fe578cbbSEli Cohen if (err) 1453fe578cbbSEli Cohen goto err_devlink_params_reg; 1454e71383fbSShay Drory } 1455fe578cbbSEli Cohen 1456a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1457a80d1b68SSaeed Mahameed if (err) 1458a80d1b68SSaeed Mahameed goto err_load; 1459a80d1b68SSaeed Mahameed 146098f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 146198f91c45SParav Pandit 1462a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1463a925b5e3SLeon Romanovsky if (err) 1464a925b5e3SLeon Romanovsky goto err_register; 1465a925b5e3SLeon Romanovsky 14664162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 14674162f58bSParav Pandit return 0; 1468e126ba97SEli Cohen 1469a925b5e3SLeon Romanovsky err_register: 147098f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1471a80d1b68SSaeed Mahameed mlx5_unload(dev); 1472a80d1b68SSaeed Mahameed err_load: 1473e71383fbSShay Drory if (!light_probe) 1474fe578cbbSEli Cohen mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1475fe578cbbSEli Cohen err_devlink_params_reg: 147659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1477e161105eSSaeed Mahameed function_teardown: 14786dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14794f7400d5SShay Drory err_function: 148089d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 148189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1482e71383fbSShay Drory return err; 1483e71383fbSShay Drory } 1484e71383fbSShay Drory 1485e71383fbSShay Drory int mlx5_init_one(struct mlx5_core_dev *dev) 1486e71383fbSShay Drory { 1487e71383fbSShay Drory struct devlink *devlink = priv_to_devlink(dev); 1488e71383fbSShay Drory int err; 1489e71383fbSShay Drory 1490e71383fbSShay Drory devl_lock(devlink); 1491e71383fbSShay Drory err = mlx5_init_one_devl_locked(dev); 149284a433a4SMoshe Shemesh devl_unlock(devlink); 1493e126ba97SEli Cohen return err; 1494e126ba97SEli Cohen } 1495e126ba97SEli Cohen 14966dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1497e126ba97SEli Cohen { 149884a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 149984a433a4SMoshe Shemesh 150084a433a4SMoshe Shemesh devl_lock(devlink); 150189d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 150298f91c45SParav Pandit 150398f91c45SParav Pandit mlx5_unregister_device(dev); 150498f91c45SParav Pandit 1505b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 150698a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 150789d44f0aSMajd Dibbiny __func__); 150853d737dfSShay Drory mlx5_devlink_params_unregister(priv_to_devlink(dev)); 150959211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 151089d44f0aSMajd Dibbiny goto out; 151189d44f0aSMajd Dibbiny } 15126b6adee3SMohamad Haj Yahia 15139ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1514a80d1b68SSaeed Mahameed mlx5_unload(dev); 1515fe578cbbSEli Cohen mlx5_devlink_params_unregister(priv_to_devlink(dev)); 151659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 15176dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 15186dea2f7eSLeon Romanovsky out: 15196dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 152084a433a4SMoshe Shemesh devl_unlock(devlink); 15216dea2f7eSLeon Romanovsky } 15220cf53c12SSaeed Mahameed 152384a433a4SMoshe Shemesh int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 15246dea2f7eSLeon Romanovsky { 15256dea2f7eSLeon Romanovsky int err = 0; 152637ca95e6SGavin Li u64 timeout; 15276dea2f7eSLeon Romanovsky 152884a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 15296dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 15306dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 15316dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 15326dea2f7eSLeon Romanovsky goto out; 15336dea2f7eSLeon Romanovsky } 15346dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 15356dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 15366dea2f7eSLeon Romanovsky 153737ca95e6SGavin Li if (recovery) 153837ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 153937ca95e6SGavin Li else 154037ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 15419b98d395SMoshe Shemesh err = mlx5_function_setup(dev, false, timeout); 15426dea2f7eSLeon Romanovsky if (err) 15436dea2f7eSLeon Romanovsky goto err_function; 15446dea2f7eSLeon Romanovsky 15456dea2f7eSLeon Romanovsky err = mlx5_load(dev); 15466dea2f7eSLeon Romanovsky if (err) 15476dea2f7eSLeon Romanovsky goto err_load; 15486dea2f7eSLeon Romanovsky 15496dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15506dea2f7eSLeon Romanovsky 15516dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 15526dea2f7eSLeon Romanovsky if (err) 15536dea2f7eSLeon Romanovsky goto err_attach; 15546dea2f7eSLeon Romanovsky 15556dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 15566dea2f7eSLeon Romanovsky return 0; 15576dea2f7eSLeon Romanovsky 15586dea2f7eSLeon Romanovsky err_attach: 15596dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15606dea2f7eSLeon Romanovsky mlx5_unload(dev); 15616dea2f7eSLeon Romanovsky err_load: 15626dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 15636dea2f7eSLeon Romanovsky err_function: 15646dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 15656dea2f7eSLeon Romanovsky out: 15666dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 15676dea2f7eSLeon Romanovsky return err; 15686dea2f7eSLeon Romanovsky } 15696dea2f7eSLeon Romanovsky 157021608a2cSMoshe Shemesh int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 15716dea2f7eSLeon Romanovsky { 157284a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 157384a433a4SMoshe Shemesh int ret; 157484a433a4SMoshe Shemesh 157584a433a4SMoshe Shemesh devl_lock(devlink); 157621608a2cSMoshe Shemesh ret = mlx5_load_one_devl_locked(dev, recovery); 157784a433a4SMoshe Shemesh devl_unlock(devlink); 157884a433a4SMoshe Shemesh return ret; 157984a433a4SMoshe Shemesh } 158084a433a4SMoshe Shemesh 158172ed5d56SJiri Pirko void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 158284a433a4SMoshe Shemesh { 158384a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 15846dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 15856dea2f7eSLeon Romanovsky 158672ed5d56SJiri Pirko mlx5_detach_device(dev, suspend); 15876dea2f7eSLeon Romanovsky 15886dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 15896dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 15906dea2f7eSLeon Romanovsky __func__); 15916dea2f7eSLeon Romanovsky goto out; 15926dea2f7eSLeon Romanovsky } 15936dea2f7eSLeon Romanovsky 15946dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15956dea2f7eSLeon Romanovsky mlx5_unload(dev); 15966dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1597ac6ea6e8SEli Cohen out: 159889d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 15999603b61dSJack Morgenstein } 160064613d94SSaeed Mahameed 160172ed5d56SJiri Pirko void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 160284a433a4SMoshe Shemesh { 160384a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 160484a433a4SMoshe Shemesh 160584a433a4SMoshe Shemesh devl_lock(devlink); 160672ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, suspend); 160784a433a4SMoshe Shemesh devl_unlock(devlink); 160884a433a4SMoshe Shemesh } 160984a433a4SMoshe Shemesh 1610e71383fbSShay Drory /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps. 1611e71383fbSShay Drory * A full query of hca_caps will be done when the device will reload. 1612e71383fbSShay Drory */ 1613e71383fbSShay Drory static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev) 1614e71383fbSShay Drory { 1615e71383fbSShay Drory int err; 1616e71383fbSShay Drory 1617e71383fbSShay Drory err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 1618e71383fbSShay Drory if (err) 1619e71383fbSShay Drory return err; 1620e71383fbSShay Drory 1621e71383fbSShay Drory if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 1622*a41cb591SShay Drory err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 1623*a41cb591SShay Drory HCA_CAP_OPMOD_GET_CUR); 1624e71383fbSShay Drory if (err) 1625e71383fbSShay Drory return err; 1626e71383fbSShay Drory } 1627e71383fbSShay Drory 1628e71383fbSShay Drory if (MLX5_CAP_GEN(dev, nic_flow_table) || 1629e71383fbSShay Drory MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 1630*a41cb591SShay Drory err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, 1631*a41cb591SShay Drory HCA_CAP_OPMOD_GET_CUR); 1632e71383fbSShay Drory if (err) 1633e71383fbSShay Drory return err; 1634e71383fbSShay Drory } 1635e71383fbSShay Drory 1636e71383fbSShay Drory if (MLX5_CAP_GEN_64(dev, general_obj_types) & 1637e71383fbSShay Drory MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 1638*a41cb591SShay Drory err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, 1639*a41cb591SShay Drory HCA_CAP_OPMOD_GET_CUR); 1640e71383fbSShay Drory if (err) 1641e71383fbSShay Drory return err; 1642e71383fbSShay Drory } 1643e71383fbSShay Drory 1644e71383fbSShay Drory return 0; 1645e71383fbSShay Drory } 1646e71383fbSShay Drory 1647e71383fbSShay Drory int mlx5_init_one_light(struct mlx5_core_dev *dev) 1648e71383fbSShay Drory { 1649e71383fbSShay Drory struct devlink *devlink = priv_to_devlink(dev); 1650e71383fbSShay Drory int err; 1651e71383fbSShay Drory 1652e71383fbSShay Drory dev->state = MLX5_DEVICE_STATE_UP; 1653e71383fbSShay Drory err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1654e71383fbSShay Drory if (err) { 1655e71383fbSShay Drory mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err); 1656e71383fbSShay Drory goto out; 1657e71383fbSShay Drory } 1658e71383fbSShay Drory 1659e71383fbSShay Drory err = mlx5_query_hca_caps_light(dev); 1660e71383fbSShay Drory if (err) { 1661e71383fbSShay Drory mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err); 1662e71383fbSShay Drory goto query_hca_caps_err; 1663e71383fbSShay Drory } 1664e71383fbSShay Drory 1665e71383fbSShay Drory devl_lock(devlink); 1666e71383fbSShay Drory err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1667e71383fbSShay Drory devl_unlock(devlink); 1668e71383fbSShay Drory if (err) { 1669e71383fbSShay Drory mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); 1670e71383fbSShay Drory goto query_hca_caps_err; 1671e71383fbSShay Drory } 1672e71383fbSShay Drory 1673e71383fbSShay Drory return 0; 1674e71383fbSShay Drory 1675e71383fbSShay Drory query_hca_caps_err: 1676e71383fbSShay Drory mlx5_function_disable(dev, true); 1677e71383fbSShay Drory out: 1678e71383fbSShay Drory dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1679e71383fbSShay Drory return err; 1680e71383fbSShay Drory } 1681e71383fbSShay Drory 1682e71383fbSShay Drory void mlx5_uninit_one_light(struct mlx5_core_dev *dev) 1683e71383fbSShay Drory { 1684e71383fbSShay Drory struct devlink *devlink = priv_to_devlink(dev); 1685e71383fbSShay Drory 1686e71383fbSShay Drory devl_lock(devlink); 1687e71383fbSShay Drory mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1688e71383fbSShay Drory devl_unlock(devlink); 1689e71383fbSShay Drory if (dev->state != MLX5_DEVICE_STATE_UP) 1690e71383fbSShay Drory return; 1691e71383fbSShay Drory mlx5_function_disable(dev, true); 1692e71383fbSShay Drory } 1693e71383fbSShay Drory 1694e71383fbSShay Drory /* xxx_light() function are used in order to configure the device without full 1695e71383fbSShay Drory * init (light init). e.g.: There isn't a point in reload a device to light state. 1696e71383fbSShay Drory * Hence, mlx5_load_one_light() isn't needed. 1697e71383fbSShay Drory */ 1698e71383fbSShay Drory 1699e71383fbSShay Drory void mlx5_unload_one_light(struct mlx5_core_dev *dev) 1700e71383fbSShay Drory { 1701e71383fbSShay Drory if (dev->state != MLX5_DEVICE_STATE_UP) 1702e71383fbSShay Drory return; 1703e71383fbSShay Drory mlx5_function_disable(dev, false); 1704e71383fbSShay Drory dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1705e71383fbSShay Drory } 1706e71383fbSShay Drory 170748f02eefSParav Pandit static const int types[] = { 170848f02eefSParav Pandit MLX5_CAP_GENERAL, 170948f02eefSParav Pandit MLX5_CAP_GENERAL_2, 171048f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 171148f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 171248f02eefSParav Pandit MLX5_CAP_ODP, 171348f02eefSParav Pandit MLX5_CAP_ATOMIC, 171448f02eefSParav Pandit MLX5_CAP_ROCE, 171548f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 171648f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 171748f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 171848f02eefSParav Pandit MLX5_CAP_ESWITCH, 171948f02eefSParav Pandit MLX5_CAP_QOS, 172048f02eefSParav Pandit MLX5_CAP_DEBUG, 172148f02eefSParav Pandit MLX5_CAP_DEV_MEM, 172248f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 172348f02eefSParav Pandit MLX5_CAP_TLS, 172448f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 172548f02eefSParav Pandit MLX5_CAP_IPSEC, 1726425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 17278ff0ac5bSLior Nahmanson MLX5_CAP_MACSEC, 172893983863SYishai Hadas MLX5_CAP_ADV_VIRTUALIZATION, 1729fe298bdfSJianbo Liu MLX5_CAP_CRYPTO, 173048f02eefSParav Pandit }; 173148f02eefSParav Pandit 173248f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 173348f02eefSParav Pandit { 173448f02eefSParav Pandit int type; 173548f02eefSParav Pandit int i; 173648f02eefSParav Pandit 173748f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 173848f02eefSParav Pandit type = types[i]; 173948f02eefSParav Pandit kfree(dev->caps.hca[type]); 174048f02eefSParav Pandit } 174148f02eefSParav Pandit } 174248f02eefSParav Pandit 174348f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 174448f02eefSParav Pandit { 174548f02eefSParav Pandit struct mlx5_hca_cap *cap; 174648f02eefSParav Pandit int type; 174748f02eefSParav Pandit int i; 174848f02eefSParav Pandit 174948f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 175048f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 175148f02eefSParav Pandit if (!cap) 175248f02eefSParav Pandit goto err; 175348f02eefSParav Pandit type = types[i]; 175448f02eefSParav Pandit dev->caps.hca[type] = cap; 175548f02eefSParav Pandit } 175648f02eefSParav Pandit 175748f02eefSParav Pandit return 0; 175848f02eefSParav Pandit 175948f02eefSParav Pandit err: 176048f02eefSParav Pandit mlx5_hca_caps_free(dev); 176148f02eefSParav Pandit return -ENOMEM; 176248f02eefSParav Pandit } 176348f02eefSParav Pandit 1764dd3dd726SEli Cohen static int vhca_id_show(struct seq_file *file, void *priv) 1765dd3dd726SEli Cohen { 1766dd3dd726SEli Cohen struct mlx5_core_dev *dev = file->private; 1767dd3dd726SEli Cohen 1768dd3dd726SEli Cohen seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1769dd3dd726SEli Cohen return 0; 1770dd3dd726SEli Cohen } 1771dd3dd726SEli Cohen 1772dd3dd726SEli Cohen DEFINE_SHOW_ATTRIBUTE(vhca_id); 1773dd3dd726SEli Cohen 17741958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 17759603b61dSJack Morgenstein { 177611f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 17779603b61dSJack Morgenstein int err; 17789603b61dSJack Morgenstein 17793410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1780d59b73a6SMoshe Shemesh lockdep_register_key(&dev->lock_key); 178189d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1782d59b73a6SMoshe Shemesh lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1783c7d4e6abSJiri Pirko mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1784d9aaed83SArtemy Kovalyov 178501187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 178601187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 178701187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 178801187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 178901187175SEli Cohen 179011f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 179111f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 179211f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 179311f3b84dSSaeed Mahameed 179444f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 179566771a1cSMoshe Shemesh priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 179627b942fbSParav Pandit mlx5_debugfs_root); 1797dd3dd726SEli Cohen debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 17983d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 17993d347b1bSAya Levin 180006cd555fSShay Drory err = mlx5_cmd_init(dev); 180106cd555fSShay Drory if (err) { 180206cd555fSShay Drory mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n"); 180306cd555fSShay Drory goto err_cmd_init; 180406cd555fSShay Drory } 180506cd555fSShay Drory 180676091b0fSAmir Tzin err = mlx5_tout_init(dev); 180776091b0fSAmir Tzin if (err) { 180876091b0fSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 180976091b0fSAmir Tzin goto err_timeout_init; 181076091b0fSAmir Tzin } 181176091b0fSAmir Tzin 1812ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 181352c368dcSSaeed Mahameed if (err) 181452c368dcSSaeed Mahameed goto err_health_init; 1815ac6ea6e8SEli Cohen 18160cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 18170cf53c12SSaeed Mahameed if (err) 18180cf53c12SSaeed Mahameed goto err_pagealloc_init; 181959211bd3SMohamad Haj Yahia 1820a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1821a925b5e3SLeon Romanovsky if (err) 1822a925b5e3SLeon Romanovsky goto err_adev_init; 1823a925b5e3SLeon Romanovsky 182448f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 182548f02eefSParav Pandit if (err) 182648f02eefSParav Pandit goto err_hca_caps; 182748f02eefSParav Pandit 1828dc402cccSYishai Hadas /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1829dc402cccSYishai Hadas * unique id per function which uses mlx5_core. 1830dc402cccSYishai Hadas * Those values are supplied to FW as part of the init HCA command to 1831dc402cccSYishai Hadas * be used by both driver and FW when it's applicable. 1832dc402cccSYishai Hadas */ 1833dc402cccSYishai Hadas dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1834dc402cccSYishai Hadas MAX_SW_VHCA_ID, 1835dc402cccSYishai Hadas GFP_KERNEL); 1836dc402cccSYishai Hadas if (dev->priv.sw_vhca_id < 0) 1837dc402cccSYishai Hadas mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1838dc402cccSYishai Hadas dev->priv.sw_vhca_id); 1839dc402cccSYishai Hadas 184011f3b84dSSaeed Mahameed return 0; 184152c368dcSSaeed Mahameed 184248f02eefSParav Pandit err_hca_caps: 184348f02eefSParav Pandit mlx5_adev_cleanup(dev); 1844a925b5e3SLeon Romanovsky err_adev_init: 1845a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 184652c368dcSSaeed Mahameed err_pagealloc_init: 184752c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 184852c368dcSSaeed Mahameed err_health_init: 184976091b0fSAmir Tzin mlx5_tout_cleanup(dev); 185076091b0fSAmir Tzin err_timeout_init: 185106cd555fSShay Drory mlx5_cmd_cleanup(dev); 185206cd555fSShay Drory err_cmd_init: 185366771a1cSMoshe Shemesh debugfs_remove(dev->priv.dbg.dbg_root); 1854810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1855810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1856810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1857810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1858810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1859d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 186052c368dcSSaeed Mahameed return err; 186111f3b84dSSaeed Mahameed } 186211f3b84dSSaeed Mahameed 18631958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 186411f3b84dSSaeed Mahameed { 1865810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1866810cbb25SParav Pandit 1867dc402cccSYishai Hadas if (priv->sw_vhca_id > 0) 1868dc402cccSYishai Hadas ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1869dc402cccSYishai Hadas 187048f02eefSParav Pandit mlx5_hca_caps_free(dev); 1871a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 187252c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 187352c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 187476091b0fSAmir Tzin mlx5_tout_cleanup(dev); 187506cd555fSShay Drory mlx5_cmd_cleanup(dev); 187666771a1cSMoshe Shemesh debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1877810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1878810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1879810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1880810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1881c7d4e6abSJiri Pirko mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1882810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1883d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 188411f3b84dSSaeed Mahameed } 188511f3b84dSSaeed Mahameed 18866dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 188711f3b84dSSaeed Mahameed { 188811f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 188911f3b84dSSaeed Mahameed struct devlink *devlink; 189011f3b84dSSaeed Mahameed int err; 189111f3b84dSSaeed Mahameed 1892919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 189311f3b84dSSaeed Mahameed if (!devlink) { 18941f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 189511f3b84dSSaeed Mahameed return -ENOMEM; 189611f3b84dSSaeed Mahameed } 189711f3b84dSSaeed Mahameed 189811f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 189927b942fbSParav Pandit dev->device = &pdev->dev; 190027b942fbSParav Pandit dev->pdev = pdev; 190111f3b84dSSaeed Mahameed 1902386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1903386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1904386e75afSHuy Nguyen 1905a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 19064d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 19074d8be211SLeon Romanovsky err = dev->priv.adev_idx; 19084d8be211SLeon Romanovsky goto adev_init_err; 19094d8be211SLeon Romanovsky } 1910a925b5e3SLeon Romanovsky 191127b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 191211f3b84dSSaeed Mahameed if (err) 191311f3b84dSSaeed Mahameed goto mdev_init_err; 191411f3b84dSSaeed Mahameed 191511f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 19169603b61dSJack Morgenstein if (err) { 191798a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 191898a8e6fcSHuy Nguyen err); 191911f3b84dSSaeed Mahameed goto pci_init_err; 19209603b61dSJack Morgenstein } 19219603b61dSJack Morgenstein 19226dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 19239603b61dSJack Morgenstein if (err) { 19246dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 192598a8e6fcSHuy Nguyen err); 19266dea2f7eSLeon Romanovsky goto err_init_one; 19279603b61dSJack Morgenstein } 192859211bd3SMohamad Haj Yahia 19298b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 19308b9d8baaSAlex Vesker if (err) 19318b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 19328b9d8baaSAlex Vesker 19331f507e80SAdham Faris err = mlx5_hwmon_dev_register(dev); 1934c1fef618SSandipan Patra if (err) 19351f507e80SAdham Faris mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err); 1936c1fef618SSandipan Patra 19375d47f6c8SDaniel Jurgens pci_save_state(pdev); 193864ea2d0eSLeon Romanovsky devlink_register(devlink); 19399603b61dSJack Morgenstein return 0; 19409603b61dSJack Morgenstein 19416dea2f7eSLeon Romanovsky err_init_one: 1942868bc06bSSaeed Mahameed mlx5_pci_close(dev); 194311f3b84dSSaeed Mahameed pci_init_err: 194411f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 194511f3b84dSSaeed Mahameed mdev_init_err: 1946a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 19474d8be211SLeon Romanovsky adev_init_err: 19481f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1949a31208b1SMajd Dibbiny 19509603b61dSJack Morgenstein return err; 19519603b61dSJack Morgenstein } 1952a31208b1SMajd Dibbiny 19539603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 19549603b61dSJack Morgenstein { 19559603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1956feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 19579603b61dSJack Morgenstein 1958031a163fSShay Drory set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1959824c8dc4SShay Drory /* mlx5_drain_fw_reset() and mlx5_drain_health_wq() are using 1960824c8dc4SShay Drory * devlink notify APIs. 1961824c8dc4SShay Drory * Hence, we must drain them before unregistering the devlink. 196216d42d31SShay Drory */ 196316d42d31SShay Drory mlx5_drain_fw_reset(dev); 1964824c8dc4SShay Drory mlx5_drain_health_wq(dev); 196564ea2d0eSLeon Romanovsky devlink_unregister(devlink); 19666d98f314SDaniel Jurgens mlx5_sriov_disable(pdev, false); 19671f507e80SAdham Faris mlx5_hwmon_dev_unregister(dev); 19688b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 19696dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1970868bc06bSSaeed Mahameed mlx5_pci_close(dev); 197111f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1972a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 19731f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 19749603b61dSJack Morgenstein } 19759603b61dSJack Morgenstein 1976fad1783aSSaeed Mahameed #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1977fad1783aSSaeed Mahameed struct mlx5_core_dev *__dev = (dev); \ 1978fad1783aSSaeed Mahameed mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1979fad1783aSSaeed Mahameed __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1980fad1783aSSaeed Mahameed __dev->pci_status, ##__VA_ARGS__); \ 1981fad1783aSSaeed Mahameed }) 1982fad1783aSSaeed Mahameed 1983fad1783aSSaeed Mahameed static const char *result2str(enum pci_ers_result result) 1984fad1783aSSaeed Mahameed { 1985fad1783aSSaeed Mahameed return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1986fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1987fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1988fad1783aSSaeed Mahameed "unknown"; 1989fad1783aSSaeed Mahameed } 1990fad1783aSSaeed Mahameed 199189d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 199289d44f0aSMajd Dibbiny pci_channel_state_t state) 199389d44f0aSMajd Dibbiny { 199489d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1995fad1783aSSaeed Mahameed enum pci_ers_result res; 199689d44f0aSMajd Dibbiny 1997fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 199804c0c1abSMohamad Haj Yahia 19998812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 20003e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 2001aab8e1a2SMoshe Shemesh mlx5_unload_one(dev, false); 20025e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 200389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 200405ac2c0bSMohamad Haj Yahia 2005fad1783aSSaeed Mahameed res = state == pci_channel_io_perm_failure ? 200689d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2007fad1783aSSaeed Mahameed 2008394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 2009394164f9SRoy Novich __func__, dev->state, dev->pci_status, res, result2str(res)); 2010fad1783aSSaeed Mahameed return res; 201189d44f0aSMajd Dibbiny } 201289d44f0aSMajd Dibbiny 2013d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 2014d57847dcSDaniel Jurgens * for the health counter to start counting. 201589d44f0aSMajd Dibbiny */ 2016d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 201789d44f0aSMajd Dibbiny { 201889d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 201989d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 202089d44f0aSMajd Dibbiny const int niter = 100; 2021d57847dcSDaniel Jurgens u32 last_count = 0; 202289d44f0aSMajd Dibbiny u32 count; 202389d44f0aSMajd Dibbiny int i; 202489d44f0aSMajd Dibbiny 202589d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 202689d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 202789d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 2028d57847dcSDaniel Jurgens if (last_count && last_count != count) { 202998a8e6fcSHuy Nguyen mlx5_core_info(dev, 203098a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 203198a8e6fcSHuy Nguyen count, i); 2032d57847dcSDaniel Jurgens return 0; 2033d57847dcSDaniel Jurgens } 2034d57847dcSDaniel Jurgens last_count = count; 203589d44f0aSMajd Dibbiny } 203689d44f0aSMajd Dibbiny msleep(50); 203789d44f0aSMajd Dibbiny } 203889d44f0aSMajd Dibbiny 2039d57847dcSDaniel Jurgens return -ETIMEDOUT; 204089d44f0aSMajd Dibbiny } 204189d44f0aSMajd Dibbiny 20421061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 20431061c90fSMohamad Haj Yahia { 2044fad1783aSSaeed Mahameed enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 20451061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 20461061c90fSMohamad Haj Yahia int err; 20471061c90fSMohamad Haj Yahia 2048394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 2049394164f9SRoy Novich __func__, dev->state, dev->pci_status); 20501061c90fSMohamad Haj Yahia 20511061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 20521061c90fSMohamad Haj Yahia if (err) { 205398a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 205498a8e6fcSHuy Nguyen __func__, err); 2055fad1783aSSaeed Mahameed goto out; 20561061c90fSMohamad Haj Yahia } 20571061c90fSMohamad Haj Yahia 20581061c90fSMohamad Haj Yahia pci_set_master(pdev); 20591061c90fSMohamad Haj Yahia pci_restore_state(pdev); 20605d47f6c8SDaniel Jurgens pci_save_state(pdev); 20611061c90fSMohamad Haj Yahia 2062fad1783aSSaeed Mahameed err = wait_vital(pdev); 2063fad1783aSSaeed Mahameed if (err) { 2064fad1783aSSaeed Mahameed mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 2065fad1783aSSaeed Mahameed __func__, err); 2066fad1783aSSaeed Mahameed goto out; 20671061c90fSMohamad Haj Yahia } 20681061c90fSMohamad Haj Yahia 2069fad1783aSSaeed Mahameed res = PCI_ERS_RESULT_RECOVERED; 2070fad1783aSSaeed Mahameed out: 2071394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 2072394164f9SRoy Novich __func__, dev->state, dev->pci_status, err, res, result2str(res)); 2073fad1783aSSaeed Mahameed return res; 20741061c90fSMohamad Haj Yahia } 20751061c90fSMohamad Haj Yahia 207689d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 207789d44f0aSMajd Dibbiny { 207889d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 207989d44f0aSMajd Dibbiny int err; 208089d44f0aSMajd Dibbiny 2081fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, loading driver..\n"); 208289d44f0aSMajd Dibbiny 208321608a2cSMoshe Shemesh err = mlx5_load_one(dev, false); 208421608a2cSMoshe Shemesh 2085416ef713SRoy Novich if (!err) 2086416ef713SRoy Novich devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 2087416ef713SRoy Novich DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 2088416ef713SRoy Novich 2089fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 2090fad1783aSSaeed Mahameed !err ? "recovered" : "Failed"); 209189d44f0aSMajd Dibbiny } 209289d44f0aSMajd Dibbiny 209389d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 209489d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 209589d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 209689d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 209789d44f0aSMajd Dibbiny }; 209889d44f0aSMajd Dibbiny 20998812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 21008812c24dSMajd Dibbiny { 2101fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 2102fcd29ad1SFeras Daoud int ret = 1; 21038812c24dSMajd Dibbiny 2104fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2105fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2106fcd29ad1SFeras Daoud 2107fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2108fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2109fcd29ad1SFeras Daoud 2110fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 21118812c24dSMajd Dibbiny return -EOPNOTSUPP; 21128812c24dSMajd Dibbiny 21138812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 21148812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 21158812c24dSMajd Dibbiny return -EAGAIN; 21168812c24dSMajd Dibbiny } 21178812c24dSMajd Dibbiny 2118d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 2119b0ea505bSJulia Lawall * with the HCA, so the health poll is no longer needed. 2120d2aa060dSHuy Nguyen */ 2121d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 212276d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 2123d2aa060dSHuy Nguyen 2124fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 2125fcd29ad1SFeras Daoud if (!ret) 2126fcd29ad1SFeras Daoud goto succeed; 2127fcd29ad1SFeras Daoud 21288812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 2129fcd29ad1SFeras Daoud if (!ret) 2130fcd29ad1SFeras Daoud goto succeed; 2131fcd29ad1SFeras Daoud 21328812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 2133d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 21348812c24dSMajd Dibbiny return ret; 21358812c24dSMajd Dibbiny 2136fcd29ad1SFeras Daoud succeed: 21378812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 21388812c24dSMajd Dibbiny 21391ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 21401ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 21411ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 21421ef903bfSDaniel Jurgens * contexts. 21431ef903bfSDaniel Jurgens */ 21441ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 21451ef903bfSDaniel Jurgens 21468812c24dSMajd Dibbiny return 0; 21478812c24dSMajd Dibbiny } 21488812c24dSMajd Dibbiny 21495fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 21505fc7197dSMajd Dibbiny { 21515fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 21528812c24dSMajd Dibbiny int err; 21535fc7197dSMajd Dibbiny 215498a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 21558324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 21568812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 21578812c24dSMajd Dibbiny if (err) 215872ed5d56SJiri Pirko mlx5_unload_one(dev, false); 21595fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 21605fc7197dSMajd Dibbiny } 21615fc7197dSMajd Dibbiny 21628fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 21638fc3e29bSMark Bloch { 21648fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 21658fc3e29bSMark Bloch 216672ed5d56SJiri Pirko mlx5_unload_one(dev, true); 21678fc3e29bSMark Bloch 21688fc3e29bSMark Bloch return 0; 21698fc3e29bSMark Bloch } 21708fc3e29bSMark Bloch 21718fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 21728fc3e29bSMark Bloch { 21738fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 21748fc3e29bSMark Bloch 217521608a2cSMoshe Shemesh return mlx5_load_one(dev, false); 21768fc3e29bSMark Bloch } 21778fc3e29bSMark Bloch 21789603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 2179bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2180fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2181bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2182fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2183bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2184fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 21857092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 218664dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2187d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2188d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2189d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2190d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 219185327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 219285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2193b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2194505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2195f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 21962e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 21972e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2198d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2199dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2200f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 22019603b61dSJack Morgenstein { 0, } 22029603b61dSJack Morgenstein }; 22039603b61dSJack Morgenstein 22049603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 22059603b61dSJack Morgenstein 220604c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 220704c0c1abSMohamad Haj Yahia { 2208b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 220972ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, false); 221004c0c1abSMohamad Haj Yahia } 221104c0c1abSMohamad Haj Yahia 2212fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 221304c0c1abSMohamad Haj Yahia { 221433de865fSMoshe Shemesh if (!mlx5_core_is_sf(dev)) { 221504c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 221633de865fSMoshe Shemesh if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 221733de865fSMoshe Shemesh return -EIO; 221833de865fSMoshe Shemesh } 221933de865fSMoshe Shemesh 2220d3dbdc9fSMoshe Shemesh return mlx5_load_one_devl_locked(dev, true); 222104c0c1abSMohamad Haj Yahia } 222204c0c1abSMohamad Haj Yahia 22239603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 222417a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 22259603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 22266dea2f7eSLeon Romanovsky .probe = probe_one, 222789d44f0aSMajd Dibbiny .remove = remove_one, 22288fc3e29bSMark Bloch .suspend = mlx5_suspend, 22298fc3e29bSMark Bloch .resume = mlx5_resume, 22305fc7197dSMajd Dibbiny .shutdown = shutdown, 2231fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 2232fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 2233e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2234e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 22359603b61dSJack Morgenstein }; 2236e126ba97SEli Cohen 22371695b97bSYishai Hadas /** 22381695b97bSYishai Hadas * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 22391695b97bSYishai Hadas * mlx5_core is its driver. 22401695b97bSYishai Hadas * @pdev: The associated PCI device. 22411695b97bSYishai Hadas * 22421695b97bSYishai Hadas * Upon return the interface state lock stay held to let caller uses it safely. 22431695b97bSYishai Hadas * Caller must ensure to use the returned mlx5 device for a narrow window 22441695b97bSYishai Hadas * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 22451695b97bSYishai Hadas * 22461695b97bSYishai Hadas * Return: Pointer to the associated mlx5_core_dev or NULL. 22471695b97bSYishai Hadas */ 22481695b97bSYishai Hadas struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 22491695b97bSYishai Hadas { 22501695b97bSYishai Hadas struct mlx5_core_dev *mdev; 22511695b97bSYishai Hadas 22521695b97bSYishai Hadas mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 22531695b97bSYishai Hadas if (IS_ERR(mdev)) 22541695b97bSYishai Hadas return NULL; 22551695b97bSYishai Hadas 22561695b97bSYishai Hadas mutex_lock(&mdev->intf_state_mutex); 22571695b97bSYishai Hadas if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 22581695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 22591695b97bSYishai Hadas return NULL; 22601695b97bSYishai Hadas } 22611695b97bSYishai Hadas 22621695b97bSYishai Hadas return mdev; 22631695b97bSYishai Hadas } 22641695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_get_core_dev); 22651695b97bSYishai Hadas 22661695b97bSYishai Hadas /** 22671695b97bSYishai Hadas * mlx5_vf_put_core_dev - Put the mlx5 core device back. 22681695b97bSYishai Hadas * @mdev: The mlx5 core device. 22691695b97bSYishai Hadas * 22701695b97bSYishai Hadas * Upon return the interface state lock is unlocked and caller should not 22711695b97bSYishai Hadas * access the mdev any more. 22721695b97bSYishai Hadas */ 22731695b97bSYishai Hadas void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 22741695b97bSYishai Hadas { 22751695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 22761695b97bSYishai Hadas } 22771695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_put_core_dev); 22781695b97bSYishai Hadas 2279f663ad98SKamal Heib static void mlx5_core_verify_params(void) 2280f663ad98SKamal Heib { 2281f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 2282f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2283f663ad98SKamal Heib prof_sel, 2284f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 2285f663ad98SKamal Heib MLX5_DEFAULT_PROF); 2286f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 2287f663ad98SKamal Heib } 2288f663ad98SKamal Heib } 2289f663ad98SKamal Heib 22902c1e1b94SRandy Dunlap static int __init mlx5_init(void) 2291e126ba97SEli Cohen { 2292e126ba97SEli Cohen int err; 2293e126ba97SEli Cohen 229417a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 229517a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 229617a7612bSLeon Romanovsky 22978737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 22988737f818SDaniel Jurgens 2299f663ad98SKamal Heib mlx5_core_verify_params(); 2300e126ba97SEli Cohen mlx5_register_debugfs(); 2301e126ba97SEli Cohen 23028f0d1451SShay Drory err = mlx5e_init(); 23039603b61dSJack Morgenstein if (err) 2304ac6ea6e8SEli Cohen goto err_debug; 23059603b61dSJack Morgenstein 23061958fc2fSParav Pandit err = mlx5_sf_driver_register(); 23071958fc2fSParav Pandit if (err) 23081958fc2fSParav Pandit goto err_sf; 23091958fc2fSParav Pandit 23108f0d1451SShay Drory err = pci_register_driver(&mlx5_core_driver); 2311c633e799SLeon Romanovsky if (err) 23128f0d1451SShay Drory goto err_pci; 2313f62b8bb8SAmir Vadai 2314e126ba97SEli Cohen return 0; 2315e126ba97SEli Cohen 23168f0d1451SShay Drory err_pci: 2317c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 23181958fc2fSParav Pandit err_sf: 23198f0d1451SShay Drory mlx5e_cleanup(); 2320e126ba97SEli Cohen err_debug: 2321e126ba97SEli Cohen mlx5_unregister_debugfs(); 2322e126ba97SEli Cohen return err; 2323e126ba97SEli Cohen } 2324e126ba97SEli Cohen 23252c1e1b94SRandy Dunlap static void __exit mlx5_cleanup(void) 2326e126ba97SEli Cohen { 23279603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 23288f0d1451SShay Drory mlx5_sf_driver_unregister(); 23298f0d1451SShay Drory mlx5e_cleanup(); 2330e126ba97SEli Cohen mlx5_unregister_debugfs(); 2331e126ba97SEli Cohen } 2332e126ba97SEli Cohen 23332c1e1b94SRandy Dunlap module_init(mlx5_init); 23342c1e1b94SRandy Dunlap module_exit(mlx5_cleanup); 2335