1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40db058a18SSaeed Mahameed #include <linux/interrupt.h> 41e3297246SEli Cohen #include <linux/delay.h> 42e126ba97SEli Cohen #include <linux/mlx5/driver.h> 43e126ba97SEli Cohen #include <linux/mlx5/cq.h> 44e126ba97SEli Cohen #include <linux/mlx5/qp.h> 45e126ba97SEli Cohen #include <linux/debugfs.h> 46f66f049fSEli Cohen #include <linux/kmod.h> 47b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 48c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 49907af0f0SLeon Romanovsky #include <linux/version.h> 50feae9087SOr Gerlitz #include <net/devlink.h> 51e126ba97SEli Cohen #include "mlx5_core.h" 52c1fef618SSandipan Patra #include "thermal.h" 53f2f3df55SSaeed Mahameed #include "lib/eq.h" 5416d76083SSaeed Mahameed #include "fs_core.h" 55eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 56073bb189SSaeed Mahameed #include "eswitch.h" 571f28d776SEran Ben Elisha #include "devlink.h" 5838b9f903SMoshe Shemesh #include "fw_reset.h" 5952ec462eSIlan Tayari #include "lib/mlx5.h" 605945e1adSAmir Tzin #include "lib/tout.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 62c6e3b421SLeon Romanovsky #include "en_accel/ipsec.h" 637c39afb3SFeras Daoud #include "lib/clock.h" 64358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 650ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 66fadd59fcSAviv Heller #include "lib/devcom.h" 67b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 6824406953SFeras Daoud #include "diag/fw_tracer.h" 69591905baSBodong Wang #include "ecpf.h" 7087175120SEran Ben Elisha #include "lib/hv_vhca.h" 7112206b17SAya Levin #include "diag/rsc_dump.h" 72f3196bb0SParav Pandit #include "sf/vhca_event.h" 7390d010b8SParav Pandit #include "sf/dev/dev.h" 746a327321SParav Pandit #include "sf/sf.h" 753b43190bSShay Drory #include "mlx5_irq.h" 76e126ba97SEli Cohen 77e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 78048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 79e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 80e126ba97SEli Cohen 81f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 82f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 83e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 84e126ba97SEli Cohen 85f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 879603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 889603b61dSJack Morgenstein 898737f818SDaniel Jurgens static u32 sw_owner_id[4]; 90dc402cccSYishai Hadas #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 91dc402cccSYishai Hadas static DEFINE_IDA(sw_vhca_ida); 928737f818SDaniel Jurgens 93f91e6d89SEran Ben Elisha enum { 94f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 95f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 96f91e6d89SEran Ben Elisha }; 97f91e6d89SEran Ben Elisha 98f79a609eSMaher Sanalla #define LOG_MAX_SUPPORTED_QPS 0xff 99f79a609eSMaher Sanalla 1009603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1019603b61dSJack Morgenstein [0] = { 1029603b61dSJack Morgenstein .mask = 0, 103*9df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 1049603b61dSJack Morgenstein }, 1059603b61dSJack Morgenstein [1] = { 1069603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1079603b61dSJack Morgenstein .log_max_qp = 12, 108*9df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 109*9df839a7SParav Pandit 1109603b61dSJack Morgenstein }, 1119603b61dSJack Morgenstein [2] = { 1129603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1139603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 114f79a609eSMaher Sanalla .log_max_qp = LOG_MAX_SUPPORTED_QPS, 115*9df839a7SParav Pandit .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 1169603b61dSJack Morgenstein .mr_cache[0] = { 1179603b61dSJack Morgenstein .size = 500, 1189603b61dSJack Morgenstein .limit = 250 1199603b61dSJack Morgenstein }, 1209603b61dSJack Morgenstein .mr_cache[1] = { 1219603b61dSJack Morgenstein .size = 500, 1229603b61dSJack Morgenstein .limit = 250 1239603b61dSJack Morgenstein }, 1249603b61dSJack Morgenstein .mr_cache[2] = { 1259603b61dSJack Morgenstein .size = 500, 1269603b61dSJack Morgenstein .limit = 250 1279603b61dSJack Morgenstein }, 1289603b61dSJack Morgenstein .mr_cache[3] = { 1299603b61dSJack Morgenstein .size = 500, 1309603b61dSJack Morgenstein .limit = 250 1319603b61dSJack Morgenstein }, 1329603b61dSJack Morgenstein .mr_cache[4] = { 1339603b61dSJack Morgenstein .size = 500, 1349603b61dSJack Morgenstein .limit = 250 1359603b61dSJack Morgenstein }, 1369603b61dSJack Morgenstein .mr_cache[5] = { 1379603b61dSJack Morgenstein .size = 500, 1389603b61dSJack Morgenstein .limit = 250 1399603b61dSJack Morgenstein }, 1409603b61dSJack Morgenstein .mr_cache[6] = { 1419603b61dSJack Morgenstein .size = 500, 1429603b61dSJack Morgenstein .limit = 250 1439603b61dSJack Morgenstein }, 1449603b61dSJack Morgenstein .mr_cache[7] = { 1459603b61dSJack Morgenstein .size = 500, 1469603b61dSJack Morgenstein .limit = 250 1479603b61dSJack Morgenstein }, 1489603b61dSJack Morgenstein .mr_cache[8] = { 1499603b61dSJack Morgenstein .size = 500, 1509603b61dSJack Morgenstein .limit = 250 1519603b61dSJack Morgenstein }, 1529603b61dSJack Morgenstein .mr_cache[9] = { 1539603b61dSJack Morgenstein .size = 500, 1549603b61dSJack Morgenstein .limit = 250 1559603b61dSJack Morgenstein }, 1569603b61dSJack Morgenstein .mr_cache[10] = { 1579603b61dSJack Morgenstein .size = 500, 1589603b61dSJack Morgenstein .limit = 250 1599603b61dSJack Morgenstein }, 1609603b61dSJack Morgenstein .mr_cache[11] = { 1619603b61dSJack Morgenstein .size = 500, 1629603b61dSJack Morgenstein .limit = 250 1639603b61dSJack Morgenstein }, 1649603b61dSJack Morgenstein .mr_cache[12] = { 1659603b61dSJack Morgenstein .size = 64, 1669603b61dSJack Morgenstein .limit = 32 1679603b61dSJack Morgenstein }, 1689603b61dSJack Morgenstein .mr_cache[13] = { 1699603b61dSJack Morgenstein .size = 32, 1709603b61dSJack Morgenstein .limit = 16 1719603b61dSJack Morgenstein }, 1729603b61dSJack Morgenstein .mr_cache[14] = { 1739603b61dSJack Morgenstein .size = 16, 1749603b61dSJack Morgenstein .limit = 8 1759603b61dSJack Morgenstein }, 1769603b61dSJack Morgenstein .mr_cache[15] = { 1779603b61dSJack Morgenstein .size = 8, 1789603b61dSJack Morgenstein .limit = 4 1799603b61dSJack Morgenstein }, 1809603b61dSJack Morgenstein }, 181*9df839a7SParav Pandit [3] = { 182*9df839a7SParav Pandit .mask = MLX5_PROF_MASK_QP_SIZE, 183*9df839a7SParav Pandit .log_max_qp = LOG_MAX_SUPPORTED_QPS, 184*9df839a7SParav Pandit .num_cmd_caches = 0, 185*9df839a7SParav Pandit }, 1869603b61dSJack Morgenstein }; 187e126ba97SEli Cohen 188b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189b8a92577SDaniel Jurgens u32 warn_time_mili) 190e3297246SEli Cohen { 191b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193cdfc6ffbSShay Drory u32 fw_initializing; 194e3297246SEli Cohen int err = 0; 195e3297246SEli Cohen 196cdfc6ffbSShay Drory do { 197cdfc6ffbSShay Drory fw_initializing = ioread32be(&dev->iseg->initializing); 198cdfc6ffbSShay Drory if (!(fw_initializing >> 31)) 199cdfc6ffbSShay Drory break; 2008324a02cSGavin Li if (time_after(jiffies, end) || 201c05d145aSMoshe Shemesh test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 202e3297246SEli Cohen err = -EBUSY; 203e3297246SEli Cohen break; 204e3297246SEli Cohen } 205b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 206cdfc6ffbSShay Drory mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 207cdfc6ffbSShay Drory jiffies_to_msecs(end - warn) / 1000, fw_initializing); 208b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 209b8a92577SDaniel Jurgens } 2105945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 211cdfc6ffbSShay Drory } while (true); 212e3297246SEli Cohen 213e3297246SEli Cohen return err; 214e3297246SEli Cohen } 215e3297246SEli Cohen 216012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 217012e50e1SHuy Nguyen { 218012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 219012e50e1SHuy Nguyen driver_version); 2203ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 221012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 222012e50e1SHuy Nguyen char *string; 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 225012e50e1SHuy Nguyen return; 226012e50e1SHuy Nguyen 227012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 228012e50e1SHuy Nguyen 229012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 23517a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 239012e50e1SHuy Nguyen 240012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 241907af0f0SLeon Romanovsky 242907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 24388a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 24488a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 245012e50e1SHuy Nguyen 246012e50e1SHuy Nguyen /*Send the command*/ 247012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 248012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 249012e50e1SHuy Nguyen 2503ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 251012e50e1SHuy Nguyen } 252012e50e1SHuy Nguyen 253e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 254e126ba97SEli Cohen { 255e126ba97SEli Cohen int err; 256e126ba97SEli Cohen 257eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 258e126ba97SEli Cohen if (err) { 2591a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 260eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 261e126ba97SEli Cohen if (err) { 2621a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 263e126ba97SEli Cohen return err; 264e126ba97SEli Cohen } 265e126ba97SEli Cohen } 266e126ba97SEli Cohen 267e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 268e126ba97SEli Cohen return err; 269e126ba97SEli Cohen } 270e126ba97SEli Cohen 27189d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27289d44f0aSMajd Dibbiny { 27389d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27489d44f0aSMajd Dibbiny int err = 0; 27589d44f0aSMajd Dibbiny 27689d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27789d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27889d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27989d44f0aSMajd Dibbiny if (!err) 28089d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28189d44f0aSMajd Dibbiny } 28289d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28389d44f0aSMajd Dibbiny 28489d44f0aSMajd Dibbiny return err; 28589d44f0aSMajd Dibbiny } 28689d44f0aSMajd Dibbiny 28789d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28889d44f0aSMajd Dibbiny { 28989d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29089d44f0aSMajd Dibbiny 29189d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29289d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29389d44f0aSMajd Dibbiny pci_disable_device(pdev); 29489d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29589d44f0aSMajd Dibbiny } 29689d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29789d44f0aSMajd Dibbiny } 29889d44f0aSMajd Dibbiny 299e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 300e126ba97SEli Cohen { 301e126ba97SEli Cohen int err = 0; 302e126ba97SEli Cohen 303e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3041a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 305e126ba97SEli Cohen return -ENODEV; 306e126ba97SEli Cohen } 307e126ba97SEli Cohen 30817a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 309e126ba97SEli Cohen if (err) 310e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 311e126ba97SEli Cohen 312e126ba97SEli Cohen return err; 313e126ba97SEli Cohen } 314e126ba97SEli Cohen 315e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 316e126ba97SEli Cohen { 317e126ba97SEli Cohen pci_release_regions(pdev); 318e126ba97SEli Cohen } 319e126ba97SEli Cohen 320bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 321e126ba97SEli Cohen u8 he; 322e126ba97SEli Cohen u8 rsvd[15]; 323e126ba97SEli Cohen }; 324e126ba97SEli Cohen 3252974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 326c7a08ac7SEli Cohen { 327c7a08ac7SEli Cohen switch (size) { 328c7a08ac7SEli Cohen case 128: 329c7a08ac7SEli Cohen return 0; 330c7a08ac7SEli Cohen case 256: 331c7a08ac7SEli Cohen return 1; 332c7a08ac7SEli Cohen case 512: 333c7a08ac7SEli Cohen return 2; 334c7a08ac7SEli Cohen case 1024: 335c7a08ac7SEli Cohen return 3; 336c7a08ac7SEli Cohen case 2048: 337c7a08ac7SEli Cohen return 4; 338c7a08ac7SEli Cohen case 4096: 339c7a08ac7SEli Cohen return 5; 340c7a08ac7SEli Cohen default: 3412974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 342c7a08ac7SEli Cohen return 0; 343c7a08ac7SEli Cohen } 344c7a08ac7SEli Cohen } 345c7a08ac7SEli Cohen 346c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 347c7d4e6abSJiri Pirko { 348c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 349c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev = netdev; 350c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351c7d4e6abSJiri Pirko netdev); 352c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353c7d4e6abSJiri Pirko } 354c7d4e6abSJiri Pirko 355c7d4e6abSJiri Pirko void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 356c7d4e6abSJiri Pirko { 357c7d4e6abSJiri Pirko mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 358c7d4e6abSJiri Pirko mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 359c7d4e6abSJiri Pirko dev->mlx5e_res.uplink_netdev); 360c7d4e6abSJiri Pirko mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 361c7d4e6abSJiri Pirko } 362c7d4e6abSJiri Pirko EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 363c7d4e6abSJiri Pirko 364b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 365b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 366938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 367c7a08ac7SEli Cohen { 368b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 369b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 370938fe83cSSaeed Mahameed void *out, *hca_caps; 371938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 372c7a08ac7SEli Cohen int err; 373c7a08ac7SEli Cohen 374b775516bSEli Cohen memset(in, 0, sizeof(in)); 375b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 376c7a08ac7SEli Cohen if (!out) 377c7a08ac7SEli Cohen return -ENOMEM; 378938fe83cSSaeed Mahameed 379b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 380b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3813ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 382c7a08ac7SEli Cohen if (err) { 383938fe83cSSaeed Mahameed mlx5_core_warn(dev, 384938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 385938fe83cSSaeed Mahameed cap_type, cap_mode, err); 386c7a08ac7SEli Cohen goto query_ex; 387c7a08ac7SEli Cohen } 388c7a08ac7SEli Cohen 389938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 390938fe83cSSaeed Mahameed 391938fe83cSSaeed Mahameed switch (cap_mode) { 392938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 39348f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 394938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 395938fe83cSSaeed Mahameed break; 396938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 39748f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 398938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 399938fe83cSSaeed Mahameed break; 400938fe83cSSaeed Mahameed default: 401938fe83cSSaeed Mahameed mlx5_core_warn(dev, 402938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 403938fe83cSSaeed Mahameed cap_type, cap_mode); 404938fe83cSSaeed Mahameed err = -EINVAL; 405938fe83cSSaeed Mahameed break; 406938fe83cSSaeed Mahameed } 407c7a08ac7SEli Cohen query_ex: 408c7a08ac7SEli Cohen kfree(out); 409c7a08ac7SEli Cohen return err; 410c7a08ac7SEli Cohen } 411c7a08ac7SEli Cohen 412b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 413b06e7de8SLeon Romanovsky { 414b06e7de8SLeon Romanovsky int ret; 415b06e7de8SLeon Romanovsky 416b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 417b06e7de8SLeon Romanovsky if (ret) 418b06e7de8SLeon Romanovsky return ret; 419b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 420b06e7de8SLeon Romanovsky } 421b06e7de8SLeon Romanovsky 422a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 423c7a08ac7SEli Cohen { 424b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 425f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4263ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 427c7a08ac7SEli Cohen } 42887b8de49SEli Cohen 429a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 430f91e6d89SEran Ben Elisha { 431f91e6d89SEran Ben Elisha void *set_hca_cap; 432f91e6d89SEran Ben Elisha int req_endianness; 433f91e6d89SEran Ben Elisha int err; 434f91e6d89SEran Ben Elisha 435a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 436a2a322f4SLeon Romanovsky return 0; 437a2a322f4SLeon Romanovsky 438b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 439f91e6d89SEran Ben Elisha if (err) 440f91e6d89SEran Ben Elisha return err; 441f91e6d89SEran Ben Elisha 442f91e6d89SEran Ben Elisha req_endianness = 443f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 444bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 445f91e6d89SEran Ben Elisha 446f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 447f91e6d89SEran Ben Elisha return 0; 448f91e6d89SEran Ben Elisha 449f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 450f91e6d89SEran Ben Elisha 451f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 452bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 453f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 454f91e6d89SEran Ben Elisha 455a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 456f91e6d89SEran Ben Elisha } 457f91e6d89SEran Ben Elisha 458a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45946861e3eSMoni Shoua { 46046861e3eSMoni Shoua void *set_hca_cap; 461fca22e7eSMoni Shoua bool do_set = false; 46246861e3eSMoni Shoua int err; 46346861e3eSMoni Shoua 46437b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46537b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46646861e3eSMoni Shoua return 0; 46746861e3eSMoni Shoua 46846861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46946861e3eSMoni Shoua if (err) 47046861e3eSMoni Shoua return err; 47146861e3eSMoni Shoua 47246861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 47348f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 47446861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47546861e3eSMoni Shoua 476fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 477fca22e7eSMoni Shoua do { \ 478fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 479fca22e7eSMoni Shoua if (_res) { \ 480fca22e7eSMoni Shoua do_set = true; \ 481fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 482fca22e7eSMoni Shoua } \ 483fca22e7eSMoni Shoua } while (0) 48446861e3eSMoni Shoua 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 488fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 489fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 490fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 491fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 492fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 49300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 49400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 49500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 49600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49946861e3eSMoni Shoua 500a2a322f4SLeon Romanovsky if (!do_set) 501a2a322f4SLeon Romanovsky return 0; 50246861e3eSMoni Shoua 503a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 50446861e3eSMoni Shoua } 50546861e3eSMoni Shoua 5068680a60fSShay Drory static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 5078680a60fSShay Drory { 5088680a60fSShay Drory struct devlink *devlink = priv_to_devlink(dev); 5098680a60fSShay Drory union devlink_param_value val; 5108680a60fSShay Drory int err; 5118680a60fSShay Drory 512075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5138680a60fSShay Drory DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 5148680a60fSShay Drory &val); 5158680a60fSShay Drory if (!err) 5168680a60fSShay Drory return val.vu32; 5178680a60fSShay Drory mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5188680a60fSShay Drory return err; 5198680a60fSShay Drory } 5208680a60fSShay Drory 5219ca05b0fSMaher Sanalla bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 5229ca05b0fSMaher Sanalla { 5239ca05b0fSMaher Sanalla struct devlink *devlink = priv_to_devlink(dev); 5249ca05b0fSMaher Sanalla union devlink_param_value val; 5259ca05b0fSMaher Sanalla int err; 5269ca05b0fSMaher Sanalla 527075935f0SJiri Pirko err = devl_param_driverinit_value_get(devlink, 5289ca05b0fSMaher Sanalla DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 5299ca05b0fSMaher Sanalla &val); 5309ca05b0fSMaher Sanalla 5319ca05b0fSMaher Sanalla if (!err) 5329ca05b0fSMaher Sanalla return val.vbool; 5339ca05b0fSMaher Sanalla 5349ca05b0fSMaher Sanalla mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5359ca05b0fSMaher Sanalla return MLX5_CAP_GEN(dev, roce); 5369ca05b0fSMaher Sanalla } 5379ca05b0fSMaher Sanalla EXPORT_SYMBOL(mlx5_is_roce_on); 5389ca05b0fSMaher Sanalla 539dc402cccSYishai Hadas static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 540dc402cccSYishai Hadas { 541dc402cccSYishai Hadas void *set_hca_cap; 542dc402cccSYishai Hadas int err; 543dc402cccSYishai Hadas 544dc402cccSYishai Hadas if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 545dc402cccSYishai Hadas return 0; 546dc402cccSYishai Hadas 547dc402cccSYishai Hadas err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 548dc402cccSYishai Hadas if (err) 549dc402cccSYishai Hadas return err; 550dc402cccSYishai Hadas 551dc402cccSYishai Hadas if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 552dc402cccSYishai Hadas !(dev->priv.sw_vhca_id > 0)) 553dc402cccSYishai Hadas return 0; 554dc402cccSYishai Hadas 555dc402cccSYishai Hadas set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 556dc402cccSYishai Hadas capability); 557dc402cccSYishai Hadas memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 558dc402cccSYishai Hadas MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 559dc402cccSYishai Hadas MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 560dc402cccSYishai Hadas 561dc402cccSYishai Hadas return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 562dc402cccSYishai Hadas } 563dc402cccSYishai Hadas 564a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 565e126ba97SEli Cohen { 5663410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 567938fe83cSSaeed Mahameed void *set_hca_cap; 5688680a60fSShay Drory int max_uc_list; 569a2a322f4SLeon Romanovsky int err; 570e126ba97SEli Cohen 571b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 572c7a08ac7SEli Cohen if (err) 573a2a322f4SLeon Romanovsky return err; 574e126ba97SEli Cohen 575938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 576938fe83cSSaeed Mahameed capability); 57748f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 578938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 579938fe83cSSaeed Mahameed 580938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 581707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 582938fe83cSSaeed Mahameed 128); 583c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 584938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5852974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 586e126ba97SEli Cohen 587883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 588f79a609eSMaher Sanalla if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 589a6e9085dSMaher Sanalla prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 590f79a609eSMaher Sanalla } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 591883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5923410fbcdSMaor Gottlieb prof->log_max_qp, 593883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5943410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 595883371c4SNoa Osherovich } 596c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 597938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 598938fe83cSSaeed Mahameed prof->log_max_qp); 599e126ba97SEli Cohen 600938fe83cSSaeed Mahameed /* disable cmdif checksum */ 601938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 602c1868b82SEli Cohen 60391828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 60491828bd8SMajd Dibbiny * than 4K. 60591828bd8SMajd Dibbiny */ 60691828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 607f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 608f502d834SEli Cohen 609fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 610fe1e1876SCarol L Soto 611f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 612f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 613f32f5bd2SDaniel Jurgens set_hca_cap, 614f32f5bd2SDaniel Jurgens cache_line_128byte, 615c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 616f32f5bd2SDaniel Jurgens 617dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 618dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 619dd44572aSMoni Shoua 620e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 621e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 622e7f4d0bcSMoshe Shemesh 623c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 624c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 625c4b76d8dSDaniel Jurgens set_hca_cap, 626c4b76d8dSDaniel Jurgens num_vhca_ports, 627c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 628c4b76d8dSDaniel Jurgens 629c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 630c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 631c6168161SEran Ben Elisha 6324dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 6334dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 6344dca6509SMichael Guralnik 635f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 636f3196bb0SParav Pandit 637604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 638604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 639604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 640604774adSLeon Romanovsky 641c4ad5f2bSShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 6429ca05b0fSMaher Sanalla MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 6439ca05b0fSMaher Sanalla mlx5_is_roce_on(dev)); 644fbfa97b4SShay Drory 6458680a60fSShay Drory max_uc_list = max_uc_list_get_devlink_param(dev); 6468680a60fSShay Drory if (max_uc_list > 0) 6478680a60fSShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 6488680a60fSShay Drory ilog2(max_uc_list)); 6498680a60fSShay Drory 650a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 651e126ba97SEli Cohen } 652cd23b14bSEli Cohen 653fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 654fbfa97b4SShay Drory * boot process. 655fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 656fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 657fbfa97b4SShay Drory * Hence, the need for this function. 658fbfa97b4SShay Drory * 659fbfa97b4SShay Drory * Returns 660fbfa97b4SShay Drory * True: 661fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 662fbfa97b4SShay Drory * OR: 663fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 664fbfa97b4SShay Drory * 665fbfa97b4SShay Drory * In any other case, return False. 666fbfa97b4SShay Drory */ 667fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 668fbfa97b4SShay Drory { 6699ca05b0fSMaher Sanalla return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 670fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 671fbfa97b4SShay Drory } 672fbfa97b4SShay Drory 67359e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 67459e9e8e4SMark Zhang { 67559e9e8e4SMark Zhang void *set_hca_cap; 67659e9e8e4SMark Zhang int err; 67759e9e8e4SMark Zhang 678fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 67959e9e8e4SMark Zhang return 0; 68059e9e8e4SMark Zhang 68159e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 68259e9e8e4SMark Zhang if (err) 68359e9e8e4SMark Zhang return err; 68459e9e8e4SMark Zhang 68559e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 68659e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 68759e9e8e4SMark Zhang return 0; 68859e9e8e4SMark Zhang 68959e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 69048f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 69159e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 69259e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 69359e9e8e4SMark Zhang 69459e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 695e126ba97SEli Cohen return err; 696e126ba97SEli Cohen } 697e126ba97SEli Cohen 69890b1df74SLiu, Changcheng static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 69990b1df74SLiu, Changcheng void *set_ctx) 70090b1df74SLiu, Changcheng { 70190b1df74SLiu, Changcheng void *set_hca_cap; 70290b1df74SLiu, Changcheng int err; 70390b1df74SLiu, Changcheng 70490b1df74SLiu, Changcheng if (!MLX5_CAP_GEN(dev, port_selection_cap)) 70590b1df74SLiu, Changcheng return 0; 70690b1df74SLiu, Changcheng 70790b1df74SLiu, Changcheng err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 70890b1df74SLiu, Changcheng if (err) 70990b1df74SLiu, Changcheng return err; 71090b1df74SLiu, Changcheng 71190b1df74SLiu, Changcheng if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 71290b1df74SLiu, Changcheng !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 71390b1df74SLiu, Changcheng return 0; 71490b1df74SLiu, Changcheng 71590b1df74SLiu, Changcheng set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 71690b1df74SLiu, Changcheng memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 71790b1df74SLiu, Changcheng MLX5_ST_SZ_BYTES(port_selection_cap)); 71890b1df74SLiu, Changcheng MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 71990b1df74SLiu, Changcheng 72090b1df74SLiu, Changcheng err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION); 72190b1df74SLiu, Changcheng 72290b1df74SLiu, Changcheng return err; 72390b1df74SLiu, Changcheng } 72490b1df74SLiu, Changcheng 72537b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 72637b6bb77SLeon Romanovsky { 727a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 728a2a322f4SLeon Romanovsky void *set_ctx; 72937b6bb77SLeon Romanovsky int err; 73037b6bb77SLeon Romanovsky 731a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 732a2a322f4SLeon Romanovsky if (!set_ctx) 733a2a322f4SLeon Romanovsky return -ENOMEM; 734a2a322f4SLeon Romanovsky 735a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 73637b6bb77SLeon Romanovsky if (err) { 73798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 73837b6bb77SLeon Romanovsky goto out; 73937b6bb77SLeon Romanovsky } 74037b6bb77SLeon Romanovsky 741a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 742a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 74337b6bb77SLeon Romanovsky if (err) { 74498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 74537b6bb77SLeon Romanovsky goto out; 74637b6bb77SLeon Romanovsky } 74737b6bb77SLeon Romanovsky 748a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 749a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 75037b6bb77SLeon Romanovsky if (err) { 75198a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 75237b6bb77SLeon Romanovsky goto out; 75337b6bb77SLeon Romanovsky } 75437b6bb77SLeon Romanovsky 75559e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 75659e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 75759e9e8e4SMark Zhang if (err) { 75859e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 75959e9e8e4SMark Zhang goto out; 76059e9e8e4SMark Zhang } 76159e9e8e4SMark Zhang 762dc402cccSYishai Hadas memset(set_ctx, 0, set_sz); 763dc402cccSYishai Hadas err = handle_hca_cap_2(dev, set_ctx); 764dc402cccSYishai Hadas if (err) { 765dc402cccSYishai Hadas mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 766dc402cccSYishai Hadas goto out; 767dc402cccSYishai Hadas } 768dc402cccSYishai Hadas 76990b1df74SLiu, Changcheng memset(set_ctx, 0, set_sz); 77090b1df74SLiu, Changcheng err = handle_hca_cap_port_selection(dev, set_ctx); 77190b1df74SLiu, Changcheng if (err) { 77290b1df74SLiu, Changcheng mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 77390b1df74SLiu, Changcheng goto out; 77490b1df74SLiu, Changcheng } 77590b1df74SLiu, Changcheng 77637b6bb77SLeon Romanovsky out: 777a2a322f4SLeon Romanovsky kfree(set_ctx); 77837b6bb77SLeon Romanovsky return err; 77937b6bb77SLeon Romanovsky } 78037b6bb77SLeon Romanovsky 781e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 782e126ba97SEli Cohen { 783bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 784bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 785e126ba97SEli Cohen int err; 786e126ba97SEli Cohen 787fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 788fc50db98SEli Cohen return 0; 789fc50db98SEli Cohen 790e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 791e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 792e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 793e126ba97SEli Cohen &he_out, sizeof(he_out), 794e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 795e126ba97SEli Cohen return err; 796e126ba97SEli Cohen } 797e126ba97SEli Cohen 798c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 799c85023e1SHuy Nguyen { 800c85023e1SHuy Nguyen int ret = 0; 801c85023e1SHuy Nguyen 802c85023e1SHuy Nguyen /* Disable local_lb by default */ 8038978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 804c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 805c85023e1SHuy Nguyen 806c85023e1SHuy Nguyen return ret; 807c85023e1SHuy Nguyen } 808c85023e1SHuy Nguyen 8090b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 810e126ba97SEli Cohen { 8113ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 812e126ba97SEli Cohen 8130b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 8140b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 81522e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 81622e939a9SBodong Wang dev->caps.embedded_cpu); 8173ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 818e126ba97SEli Cohen } 819e126ba97SEli Cohen 8200b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 821e126ba97SEli Cohen { 8223ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 823e126ba97SEli Cohen 8240b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 8250b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 82622e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 82722e939a9SBodong Wang dev->caps.embedded_cpu); 8283ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 829e126ba97SEli Cohen } 830e126ba97SEli Cohen 831f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 832f62b8bb8SAmir Vadai { 8333ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 8343ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 835f62b8bb8SAmir Vadai u32 sup_issi; 836c4f287c4SSaeed Mahameed int err; 837f62b8bb8SAmir Vadai 838f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 8393ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 840f62b8bb8SAmir Vadai if (err) { 841605bef00SSaeed Mahameed u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 842605bef00SSaeed Mahameed u8 status = MLX5_GET(query_issi_out, query_out, status); 843c4f287c4SSaeed Mahameed 844f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 845f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 846f9c14e46SKamal Heib err, status, syndrome); 847f9c14e46SKamal Heib return err; 848f62b8bb8SAmir Vadai } 849f62b8bb8SAmir Vadai 850f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 851f9c14e46SKamal Heib dev->issi = 0; 852f9c14e46SKamal Heib return 0; 853f62b8bb8SAmir Vadai } 854f62b8bb8SAmir Vadai 855f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 856f62b8bb8SAmir Vadai 857f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 8583ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 859f62b8bb8SAmir Vadai 860f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 861f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 8623ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 863f62b8bb8SAmir Vadai if (err) { 864f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 865f9c14e46SKamal Heib err); 866f62b8bb8SAmir Vadai return err; 867f62b8bb8SAmir Vadai } 868f62b8bb8SAmir Vadai 869f62b8bb8SAmir Vadai dev->issi = 1; 870f62b8bb8SAmir Vadai 871f62b8bb8SAmir Vadai return 0; 872e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 873f62b8bb8SAmir Vadai return 0; 874f62b8bb8SAmir Vadai } 875f62b8bb8SAmir Vadai 8769eb78923SOr Gerlitz return -EOPNOTSUPP; 877f62b8bb8SAmir Vadai } 878f62b8bb8SAmir Vadai 87911f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 88011f3b84dSSaeed Mahameed const struct pci_device_id *id) 881a31208b1SMajd Dibbiny { 882a31208b1SMajd Dibbiny int err = 0; 883a31208b1SMajd Dibbiny 884d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 885e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 886e126ba97SEli Cohen 887aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 888311c7c71SSaeed Mahameed 88989d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 890e126ba97SEli Cohen if (err) { 89198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 89211f3b84dSSaeed Mahameed return err; 893e126ba97SEli Cohen } 894e126ba97SEli Cohen 895e126ba97SEli Cohen err = request_bar(pdev); 896e126ba97SEli Cohen if (err) { 89798a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 898e126ba97SEli Cohen goto err_disable; 899e126ba97SEli Cohen } 900e126ba97SEli Cohen 901e126ba97SEli Cohen pci_set_master(pdev); 902e126ba97SEli Cohen 903e126ba97SEli Cohen err = set_dma_caps(pdev); 904e126ba97SEli Cohen if (err) { 90598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 906e126ba97SEli Cohen goto err_clr_master; 907e126ba97SEli Cohen } 908e126ba97SEli Cohen 909ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 910ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 911ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 912ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 913ce4eee53SMichael Guralnik 914aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 915e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 916e126ba97SEli Cohen if (!dev->iseg) { 917e126ba97SEli Cohen err = -ENOMEM; 91898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 919e126ba97SEli Cohen goto err_clr_master; 920e126ba97SEli Cohen } 921a31208b1SMajd Dibbiny 922b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 923c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 924a31208b1SMajd Dibbiny return 0; 925a31208b1SMajd Dibbiny 926a31208b1SMajd Dibbiny err_clr_master: 927a31208b1SMajd Dibbiny release_bar(dev->pdev); 928a31208b1SMajd Dibbiny err_disable: 92989d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 930a31208b1SMajd Dibbiny return err; 931a31208b1SMajd Dibbiny } 932a31208b1SMajd Dibbiny 933868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 934a31208b1SMajd Dibbiny { 93542ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 93642ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 93742ea9f1bSShay Drory * before removing the pci bars 93842ea9f1bSShay Drory */ 93942ea9f1bSShay Drory mlx5_drain_health_wq(dev); 940a31208b1SMajd Dibbiny iounmap(dev->iseg); 941a31208b1SMajd Dibbiny release_bar(dev->pdev); 94289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 943a31208b1SMajd Dibbiny } 944a31208b1SMajd Dibbiny 945868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 94659211bd3SMohamad Haj Yahia { 94759211bd3SMohamad Haj Yahia int err; 94859211bd3SMohamad Haj Yahia 949868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 950868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 95198a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 952868bc06bSSaeed Mahameed dev->priv.devcom); 953fadd59fcSAviv Heller 95459211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 95559211bd3SMohamad Haj Yahia if (err) { 95698a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 957fadd59fcSAviv Heller goto err_devcom; 95859211bd3SMohamad Haj Yahia } 95959211bd3SMohamad Haj Yahia 960561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 961561aa15aSYuval Avnery if (err) { 962561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 963561aa15aSYuval Avnery goto err_devcom; 964561aa15aSYuval Avnery } 965561aa15aSYuval Avnery 966f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 96759211bd3SMohamad Haj Yahia if (err) { 96898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 969561aa15aSYuval Avnery goto err_irq_cleanup; 97059211bd3SMohamad Haj Yahia } 97159211bd3SMohamad Haj Yahia 97269c1280bSSaeed Mahameed err = mlx5_events_init(dev); 97369c1280bSSaeed Mahameed if (err) { 97498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 97569c1280bSSaeed Mahameed goto err_eq_cleanup; 97669c1280bSSaeed Mahameed } 97769c1280bSSaeed Mahameed 97838b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 97938b9f903SMoshe Shemesh if (err) { 98038b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 98138b9f903SMoshe Shemesh goto err_events_cleanup; 98238b9f903SMoshe Shemesh } 98338b9f903SMoshe Shemesh 9849f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 98559211bd3SMohamad Haj Yahia 98652ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 98752ec462eSIlan Tayari 9887c39afb3SFeras Daoud mlx5_init_clock(dev); 9897c39afb3SFeras Daoud 990358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 9910ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 992358aa5ceSSaeed Mahameed 99359211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 99459211bd3SMohamad Haj Yahia if (err) { 99598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 99659211bd3SMohamad Haj Yahia goto err_tables_cleanup; 99759211bd3SMohamad Haj Yahia } 99859211bd3SMohamad Haj Yahia 999eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 1000eeb66cdbSSaeed Mahameed if (err) { 100198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1002eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 1003eeb66cdbSSaeed Mahameed } 1004eeb66cdbSSaeed Mahameed 1005c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 1006c2d6e31aSMohamad Haj Yahia if (err) { 100798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 100886eec50bSBodong Wang goto err_mpfs_cleanup; 100986eec50bSBodong Wang } 101086eec50bSBodong Wang 101186eec50bSBodong Wang err = mlx5_eswitch_init(dev); 101286eec50bSBodong Wang if (err) { 101386eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 101486eec50bSBodong Wang goto err_sriov_cleanup; 1015c2d6e31aSMohamad Haj Yahia } 1016c2d6e31aSMohamad Haj Yahia 10179410733cSIlan Tayari err = mlx5_fpga_init(dev); 10189410733cSIlan Tayari if (err) { 101998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 102086eec50bSBodong Wang goto err_eswitch_cleanup; 10219410733cSIlan Tayari } 10229410733cSIlan Tayari 1023f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 1024f3196bb0SParav Pandit if (err) { 1025f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1026f3196bb0SParav Pandit goto err_fpga_cleanup; 1027f3196bb0SParav Pandit } 1028f3196bb0SParav Pandit 10298f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 10308f010541SParav Pandit if (err) { 10318f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 10328f010541SParav Pandit goto err_sf_hw_table_cleanup; 10338f010541SParav Pandit } 10348f010541SParav Pandit 10358f010541SParav Pandit err = mlx5_sf_table_init(dev); 10368f010541SParav Pandit if (err) { 10378f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 10388f010541SParav Pandit goto err_sf_table_cleanup; 10398f010541SParav Pandit } 10408f010541SParav Pandit 1041b3388697SShay Drory err = mlx5_fs_core_alloc(dev); 1042b3388697SShay Drory if (err) { 1043b3388697SShay Drory mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1044b3388697SShay Drory goto err_fs; 1045b3388697SShay Drory } 1046b3388697SShay Drory 1047c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 1048c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 1049c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 1050c9b9dcb4SAriel Levkovich 105124406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 105287175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 105312206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 105424406953SFeras Daoud 105559211bd3SMohamad Haj Yahia return 0; 105659211bd3SMohamad Haj Yahia 1057b3388697SShay Drory err_fs: 1058b3388697SShay Drory mlx5_sf_table_cleanup(dev); 10598f010541SParav Pandit err_sf_table_cleanup: 10608f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 10618f010541SParav Pandit err_sf_hw_table_cleanup: 10628f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 1063f3196bb0SParav Pandit err_fpga_cleanup: 1064f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 1065c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 1066c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 106786eec50bSBodong Wang err_sriov_cleanup: 106886eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1069eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 1070eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 1071c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 1072c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 107359211bd3SMohamad Haj Yahia err_tables_cleanup: 10740ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1075358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 10762a35b2c2SJiri Pirko mlx5_cleanup_clock(dev); 10772a35b2c2SJiri Pirko mlx5_cleanup_reserved_gids(dev); 107802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 107938b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 108038b9f903SMoshe Shemesh err_events_cleanup: 108169c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 108259211bd3SMohamad Haj Yahia err_eq_cleanup: 1083f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1084561aa15aSYuval Avnery err_irq_cleanup: 1085561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1086fadd59fcSAviv Heller err_devcom: 1087fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 108859211bd3SMohamad Haj Yahia 108959211bd3SMohamad Haj Yahia return err; 109059211bd3SMohamad Haj Yahia } 109159211bd3SMohamad Haj Yahia 109259211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 109359211bd3SMohamad Haj Yahia { 109412206b17SAya Levin mlx5_rsc_dump_destroy(dev); 109587175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 109624406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 1097c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 1098b3388697SShay Drory mlx5_fs_core_free(dev); 10998f010541SParav Pandit mlx5_sf_table_cleanup(dev); 11008f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 1101f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 11029410733cSIlan Tayari mlx5_fpga_cleanup(dev); 1103c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 110486eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1105eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 110659211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 11070ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1108358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 11097c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 111052ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 111102d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 111238b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 111369c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 1114f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1115561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1116fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 111759211bd3SMohamad Haj Yahia } 111859211bd3SMohamad Haj Yahia 11199b98d395SMoshe Shemesh static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1120a31208b1SMajd Dibbiny { 1121a31208b1SMajd Dibbiny int err; 1122a31208b1SMajd Dibbiny 112398a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1124e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 1125e126ba97SEli Cohen 112600c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 112700c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 112800c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 112900c6bcb0STal Gilboa 11306c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 11316c780a02SEli Cohen */ 113237ca95e6SGavin Li err = wait_fw_init(dev, timeout, 11335945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 11346c780a02SEli Cohen if (err) { 11355945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 113637ca95e6SGavin Li timeout); 113776091b0fSAmir Tzin return err; 11386c780a02SEli Cohen } 11396c780a02SEli Cohen 1140e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1141e126ba97SEli Cohen if (err) { 114298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 114376091b0fSAmir Tzin return err; 1144e126ba97SEli Cohen } 1145e126ba97SEli Cohen 11465945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 11475945e1adSAmir Tzin 11485945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1149e3297246SEli Cohen if (err) { 11505945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 11515945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 115255378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1153e3297246SEli Cohen } 1154e3297246SEli Cohen 1155f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1156f7936dddSEran Ben Elisha 11579b98d395SMoshe Shemesh mlx5_start_health_poll(dev); 11589b98d395SMoshe Shemesh 11590b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1160cd23b14bSEli Cohen if (err) { 116198a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 11629b98d395SMoshe Shemesh goto stop_health_poll; 1163cd23b14bSEli Cohen } 1164cd23b14bSEli Cohen 1165f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1166f62b8bb8SAmir Vadai if (err) { 116798a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1168f62b8bb8SAmir Vadai goto err_disable_hca; 1169f62b8bb8SAmir Vadai } 1170f62b8bb8SAmir Vadai 1171cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1172cd23b14bSEli Cohen if (err) { 117398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1174cd23b14bSEli Cohen goto err_disable_hca; 1175cd23b14bSEli Cohen } 1176cd23b14bSEli Cohen 117732def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 117832def412SAmir Tzin if (err) { 117932def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 118032def412SAmir Tzin goto reclaim_boot_pages; 118132def412SAmir Tzin } 118232def412SAmir Tzin 1183e126ba97SEli Cohen err = set_hca_ctrl(dev); 1184e126ba97SEli Cohen if (err) { 118598a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1186cd23b14bSEli Cohen goto reclaim_boot_pages; 1187e126ba97SEli Cohen } 1188e126ba97SEli Cohen 118937b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1190e126ba97SEli Cohen if (err) { 119198a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 119246861e3eSMoni Shoua goto reclaim_boot_pages; 119346861e3eSMoni Shoua } 119446861e3eSMoni Shoua 1195cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1196e126ba97SEli Cohen if (err) { 119798a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1198cd23b14bSEli Cohen goto reclaim_boot_pages; 1199e126ba97SEli Cohen } 1200e126ba97SEli Cohen 12018737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1202e126ba97SEli Cohen if (err) { 120398a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 12040cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1205e126ba97SEli Cohen } 1206e126ba97SEli Cohen 1207012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1208012e50e1SHuy Nguyen 1209bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1210bba1574cSDaniel Jurgens if (err) { 121198a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1212502e82b9SAya Levin goto reclaim_boot_pages; 1213bba1574cSDaniel Jurgens } 12149b98d395SMoshe Shemesh mlx5_start_health_fw_log_up(dev); 1215502e82b9SAya Levin 1216e161105eSSaeed Mahameed return 0; 1217e161105eSSaeed Mahameed 1218e161105eSSaeed Mahameed reclaim_boot_pages: 1219e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1220e161105eSSaeed Mahameed err_disable_hca: 1221e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 12229b98d395SMoshe Shemesh stop_health_poll: 12239b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1224e161105eSSaeed Mahameed err_cmd_cleanup: 1225f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1226e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1227e161105eSSaeed Mahameed 1228e161105eSSaeed Mahameed return err; 1229e161105eSSaeed Mahameed } 1230e161105eSSaeed Mahameed 1231e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1232e161105eSSaeed Mahameed { 1233e161105eSSaeed Mahameed int err; 1234e161105eSSaeed Mahameed 1235e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1236259bbc57SMaor Gottlieb if (err) { 123798a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1238e161105eSSaeed Mahameed return err; 1239e126ba97SEli Cohen } 1240e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1241e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 12429b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1243f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1244e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1245e161105eSSaeed Mahameed 1246e161105eSSaeed Mahameed return 0; 1247259bbc57SMaor Gottlieb } 1248e126ba97SEli Cohen 1249a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1250e161105eSSaeed Mahameed { 1251e161105eSSaeed Mahameed int err; 1252e161105eSSaeed Mahameed 125301187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 125472f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 125598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 125672f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1257a80d1b68SSaeed Mahameed return err; 1258e126ba97SEli Cohen } 1259e126ba97SEli Cohen 126069c1280bSSaeed Mahameed mlx5_events_start(dev); 12610cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 12620cf53c12SSaeed Mahameed 1263e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1264e1706e62SYuval Avnery if (err) { 1265e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1266e1706e62SYuval Avnery goto err_irq_table; 1267e1706e62SYuval Avnery } 1268e1706e62SYuval Avnery 1269c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1270e126ba97SEli Cohen if (err) { 127198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1272c8e21b3bSSaeed Mahameed goto err_eq_table; 1273e126ba97SEli Cohen } 1274e126ba97SEli Cohen 127524406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 127624406953SFeras Daoud if (err) { 1277f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1278f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1279f62eb932SAya Levin dev->tracer = NULL; 128024406953SFeras Daoud } 128124406953SFeras Daoud 128238b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 128387175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 128487175120SEran Ben Elisha 128512206b17SAya Levin err = mlx5_rsc_dump_init(dev); 128612206b17SAya Levin if (err) { 1287f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1288f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1289f62eb932SAya Levin dev->rsc_dump = NULL; 129012206b17SAya Levin } 129112206b17SAya Levin 129204e87170SMatan Barak err = mlx5_fpga_device_start(dev); 129304e87170SMatan Barak if (err) { 129498a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 129504e87170SMatan Barak goto err_fpga_start; 129604e87170SMatan Barak } 129704e87170SMatan Barak 1298b3388697SShay Drory err = mlx5_fs_core_init(dev); 129986d722adSMaor Gottlieb if (err) { 130098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 130186d722adSMaor Gottlieb goto err_fs; 130286d722adSMaor Gottlieb } 13031466cc5bSYevgeny Petrilin 1304c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1305c85023e1SHuy Nguyen if (err) { 130698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 130794a4b841SLeon Romanovsky goto err_set_hca; 1308c85023e1SHuy Nguyen } 1309c85023e1SHuy Nguyen 1310f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1311f3196bb0SParav Pandit 13126a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 13136a327321SParav Pandit if (err) { 13146a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 13156a327321SParav Pandit goto err_vhca; 13166a327321SParav Pandit } 13176a327321SParav Pandit 131822e939a9SBodong Wang err = mlx5_ec_init(dev); 131922e939a9SBodong Wang if (err) { 132098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 132122e939a9SBodong Wang goto err_ec; 132222e939a9SBodong Wang } 132322e939a9SBodong Wang 1324cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 13255bef709dSParav Pandit err = mlx5_sriov_attach(dev); 13265bef709dSParav Pandit if (err) { 13275bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 13285bef709dSParav Pandit goto err_sriov; 13295bef709dSParav Pandit } 13305bef709dSParav Pandit 133190d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 133290d010b8SParav Pandit 133371b75f0eSMoshe Shemesh err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 133471b75f0eSMoshe Shemesh if (err) 133571b75f0eSMoshe Shemesh goto err_traps_reg; 133671b75f0eSMoshe Shemesh 1337a80d1b68SSaeed Mahameed return 0; 1338a80d1b68SSaeed Mahameed 133971b75f0eSMoshe Shemesh err_traps_reg: 134071b75f0eSMoshe Shemesh mlx5_sf_dev_table_destroy(dev); 134171b75f0eSMoshe Shemesh mlx5_sriov_detach(dev); 1342a80d1b68SSaeed Mahameed err_sriov: 1343cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13445bef709dSParav Pandit mlx5_ec_cleanup(dev); 13455bef709dSParav Pandit err_ec: 13466a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 13476a327321SParav Pandit err_vhca: 1348f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 134994a4b841SLeon Romanovsky err_set_hca: 1350b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1351a80d1b68SSaeed Mahameed err_fs: 1352a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1353a80d1b68SSaeed Mahameed err_fpga_start: 135412206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 135587175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 135638b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1357a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1358a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1359a80d1b68SSaeed Mahameed err_eq_table: 1360e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1361e1706e62SYuval Avnery err_irq_table: 1362a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1363a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1364a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1365a80d1b68SSaeed Mahameed return err; 1366a80d1b68SSaeed Mahameed } 1367a80d1b68SSaeed Mahameed 1368a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1369a80d1b68SSaeed Mahameed { 137071b75f0eSMoshe Shemesh mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 137190d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1372f019679eSChris Mi mlx5_eswitch_disable(dev->priv.eswitch); 13737ba930fcSDaniel Jurgens mlx5_sriov_detach(dev); 1374cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13755bef709dSParav Pandit mlx5_ec_cleanup(dev); 13766a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1377f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1378b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1379a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 138012206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 138187175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 138238b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1383a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1384a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1385e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1386a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1387a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1388a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1389a80d1b68SSaeed Mahameed } 1390a80d1b68SSaeed Mahameed 13916dea2f7eSLeon Romanovsky int mlx5_init_one(struct mlx5_core_dev *dev) 1392a80d1b68SSaeed Mahameed { 139384a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 1394a80d1b68SSaeed Mahameed int err = 0; 1395a80d1b68SSaeed Mahameed 139684a433a4SMoshe Shemesh devl_lock(devlink); 1397a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1398a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1399a80d1b68SSaeed Mahameed 14009b98d395SMoshe Shemesh err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1401a80d1b68SSaeed Mahameed if (err) 14024f7400d5SShay Drory goto err_function; 1403a80d1b68SSaeed Mahameed 1404a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1405a80d1b68SSaeed Mahameed if (err) { 140698a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1407a80d1b68SSaeed Mahameed goto function_teardown; 1408a80d1b68SSaeed Mahameed } 1409a80d1b68SSaeed Mahameed 1410fe578cbbSEli Cohen err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1411fe578cbbSEli Cohen if (err) 1412fe578cbbSEli Cohen goto err_devlink_params_reg; 1413fe578cbbSEli Cohen 1414a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1415a80d1b68SSaeed Mahameed if (err) 1416a80d1b68SSaeed Mahameed goto err_load; 1417a80d1b68SSaeed Mahameed 141898f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 141998f91c45SParav Pandit 1420a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1421a925b5e3SLeon Romanovsky if (err) 1422a925b5e3SLeon Romanovsky goto err_register; 1423a925b5e3SLeon Romanovsky 14244162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 142584a433a4SMoshe Shemesh devl_unlock(devlink); 14264162f58bSParav Pandit return 0; 1427e126ba97SEli Cohen 1428a925b5e3SLeon Romanovsky err_register: 142998f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1430a80d1b68SSaeed Mahameed mlx5_unload(dev); 1431a80d1b68SSaeed Mahameed err_load: 1432fe578cbbSEli Cohen mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1433fe578cbbSEli Cohen err_devlink_params_reg: 143459211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1435e161105eSSaeed Mahameed function_teardown: 14366dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14374f7400d5SShay Drory err_function: 143889d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 143989d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 144084a433a4SMoshe Shemesh devl_unlock(devlink); 1441e126ba97SEli Cohen return err; 1442e126ba97SEli Cohen } 1443e126ba97SEli Cohen 14446dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1445e126ba97SEli Cohen { 144684a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 144784a433a4SMoshe Shemesh 144884a433a4SMoshe Shemesh devl_lock(devlink); 144989d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 145098f91c45SParav Pandit 145198f91c45SParav Pandit mlx5_unregister_device(dev); 145298f91c45SParav Pandit 1453b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 145498a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 145589d44f0aSMajd Dibbiny __func__); 145659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 145789d44f0aSMajd Dibbiny goto out; 145889d44f0aSMajd Dibbiny } 14596b6adee3SMohamad Haj Yahia 14609ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1461a80d1b68SSaeed Mahameed mlx5_unload(dev); 1462fe578cbbSEli Cohen mlx5_devlink_params_unregister(priv_to_devlink(dev)); 146359211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 14646dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14656dea2f7eSLeon Romanovsky out: 14666dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 146784a433a4SMoshe Shemesh devl_unlock(devlink); 14686dea2f7eSLeon Romanovsky } 14690cf53c12SSaeed Mahameed 147084a433a4SMoshe Shemesh int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 14716dea2f7eSLeon Romanovsky { 14726dea2f7eSLeon Romanovsky int err = 0; 147337ca95e6SGavin Li u64 timeout; 14746dea2f7eSLeon Romanovsky 147584a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 14766dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 14776dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 14786dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 14796dea2f7eSLeon Romanovsky goto out; 14806dea2f7eSLeon Romanovsky } 14816dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 14826dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 14836dea2f7eSLeon Romanovsky 148437ca95e6SGavin Li if (recovery) 148537ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 148637ca95e6SGavin Li else 148737ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 14889b98d395SMoshe Shemesh err = mlx5_function_setup(dev, false, timeout); 14896dea2f7eSLeon Romanovsky if (err) 14906dea2f7eSLeon Romanovsky goto err_function; 14916dea2f7eSLeon Romanovsky 14926dea2f7eSLeon Romanovsky err = mlx5_load(dev); 14936dea2f7eSLeon Romanovsky if (err) 14946dea2f7eSLeon Romanovsky goto err_load; 14956dea2f7eSLeon Romanovsky 14966dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 14976dea2f7eSLeon Romanovsky 14986dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 14996dea2f7eSLeon Romanovsky if (err) 15006dea2f7eSLeon Romanovsky goto err_attach; 15016dea2f7eSLeon Romanovsky 15026dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 15036dea2f7eSLeon Romanovsky return 0; 15046dea2f7eSLeon Romanovsky 15056dea2f7eSLeon Romanovsky err_attach: 15066dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15076dea2f7eSLeon Romanovsky mlx5_unload(dev); 15086dea2f7eSLeon Romanovsky err_load: 15096dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 15106dea2f7eSLeon Romanovsky err_function: 15116dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 15126dea2f7eSLeon Romanovsky out: 15136dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 15146dea2f7eSLeon Romanovsky return err; 15156dea2f7eSLeon Romanovsky } 15166dea2f7eSLeon Romanovsky 15175977ac39SJiri Pirko int mlx5_load_one(struct mlx5_core_dev *dev) 15186dea2f7eSLeon Romanovsky { 151984a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 152084a433a4SMoshe Shemesh int ret; 152184a433a4SMoshe Shemesh 152284a433a4SMoshe Shemesh devl_lock(devlink); 15235977ac39SJiri Pirko ret = mlx5_load_one_devl_locked(dev, false); 152484a433a4SMoshe Shemesh devl_unlock(devlink); 152584a433a4SMoshe Shemesh return ret; 152684a433a4SMoshe Shemesh } 152784a433a4SMoshe Shemesh 152872ed5d56SJiri Pirko void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 152984a433a4SMoshe Shemesh { 153084a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 15316dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 15326dea2f7eSLeon Romanovsky 153372ed5d56SJiri Pirko mlx5_detach_device(dev, suspend); 15346dea2f7eSLeon Romanovsky 15356dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 15366dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 15376dea2f7eSLeon Romanovsky __func__); 15386dea2f7eSLeon Romanovsky goto out; 15396dea2f7eSLeon Romanovsky } 15406dea2f7eSLeon Romanovsky 15416dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15426dea2f7eSLeon Romanovsky mlx5_unload(dev); 15436dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1544ac6ea6e8SEli Cohen out: 154589d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 15469603b61dSJack Morgenstein } 154764613d94SSaeed Mahameed 154872ed5d56SJiri Pirko void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 154984a433a4SMoshe Shemesh { 155084a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 155184a433a4SMoshe Shemesh 155284a433a4SMoshe Shemesh devl_lock(devlink); 155372ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, suspend); 155484a433a4SMoshe Shemesh devl_unlock(devlink); 155584a433a4SMoshe Shemesh } 155684a433a4SMoshe Shemesh 155748f02eefSParav Pandit static const int types[] = { 155848f02eefSParav Pandit MLX5_CAP_GENERAL, 155948f02eefSParav Pandit MLX5_CAP_GENERAL_2, 156048f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 156148f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 156248f02eefSParav Pandit MLX5_CAP_ODP, 156348f02eefSParav Pandit MLX5_CAP_ATOMIC, 156448f02eefSParav Pandit MLX5_CAP_ROCE, 156548f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 156648f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 156748f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 156848f02eefSParav Pandit MLX5_CAP_ESWITCH, 156948f02eefSParav Pandit MLX5_CAP_VECTOR_CALC, 157048f02eefSParav Pandit MLX5_CAP_QOS, 157148f02eefSParav Pandit MLX5_CAP_DEBUG, 157248f02eefSParav Pandit MLX5_CAP_DEV_MEM, 157348f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 157448f02eefSParav Pandit MLX5_CAP_TLS, 157548f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 157648f02eefSParav Pandit MLX5_CAP_IPSEC, 1577425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 15787025329dSBen Ben-Ishay MLX5_CAP_DEV_SHAMPO, 15798ff0ac5bSLior Nahmanson MLX5_CAP_MACSEC, 158093983863SYishai Hadas MLX5_CAP_ADV_VIRTUALIZATION, 1581fe298bdfSJianbo Liu MLX5_CAP_CRYPTO, 158248f02eefSParav Pandit }; 158348f02eefSParav Pandit 158448f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 158548f02eefSParav Pandit { 158648f02eefSParav Pandit int type; 158748f02eefSParav Pandit int i; 158848f02eefSParav Pandit 158948f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 159048f02eefSParav Pandit type = types[i]; 159148f02eefSParav Pandit kfree(dev->caps.hca[type]); 159248f02eefSParav Pandit } 159348f02eefSParav Pandit } 159448f02eefSParav Pandit 159548f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 159648f02eefSParav Pandit { 159748f02eefSParav Pandit struct mlx5_hca_cap *cap; 159848f02eefSParav Pandit int type; 159948f02eefSParav Pandit int i; 160048f02eefSParav Pandit 160148f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 160248f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 160348f02eefSParav Pandit if (!cap) 160448f02eefSParav Pandit goto err; 160548f02eefSParav Pandit type = types[i]; 160648f02eefSParav Pandit dev->caps.hca[type] = cap; 160748f02eefSParav Pandit } 160848f02eefSParav Pandit 160948f02eefSParav Pandit return 0; 161048f02eefSParav Pandit 161148f02eefSParav Pandit err: 161248f02eefSParav Pandit mlx5_hca_caps_free(dev); 161348f02eefSParav Pandit return -ENOMEM; 161448f02eefSParav Pandit } 161548f02eefSParav Pandit 1616dd3dd726SEli Cohen static int vhca_id_show(struct seq_file *file, void *priv) 1617dd3dd726SEli Cohen { 1618dd3dd726SEli Cohen struct mlx5_core_dev *dev = file->private; 1619dd3dd726SEli Cohen 1620dd3dd726SEli Cohen seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1621dd3dd726SEli Cohen return 0; 1622dd3dd726SEli Cohen } 1623dd3dd726SEli Cohen 1624dd3dd726SEli Cohen DEFINE_SHOW_ATTRIBUTE(vhca_id); 1625dd3dd726SEli Cohen 16261958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 16279603b61dSJack Morgenstein { 162811f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 16299603b61dSJack Morgenstein int err; 16309603b61dSJack Morgenstein 16313410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1632d59b73a6SMoshe Shemesh lockdep_register_key(&dev->lock_key); 163389d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1634d59b73a6SMoshe Shemesh lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1635c7d4e6abSJiri Pirko mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1636d9aaed83SArtemy Kovalyov 163701187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 163801187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 163901187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 164001187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 164101187175SEli Cohen 164211f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 164311f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 164411f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 164511f3b84dSSaeed Mahameed 164644f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 164766771a1cSMoshe Shemesh priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 164827b942fbSParav Pandit mlx5_debugfs_root); 1649dd3dd726SEli Cohen debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 16503d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 16513d347b1bSAya Levin 165276091b0fSAmir Tzin err = mlx5_tout_init(dev); 165376091b0fSAmir Tzin if (err) { 165476091b0fSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 165576091b0fSAmir Tzin goto err_timeout_init; 165676091b0fSAmir Tzin } 165776091b0fSAmir Tzin 1658ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 165952c368dcSSaeed Mahameed if (err) 166052c368dcSSaeed Mahameed goto err_health_init; 1661ac6ea6e8SEli Cohen 16620cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 16630cf53c12SSaeed Mahameed if (err) 16640cf53c12SSaeed Mahameed goto err_pagealloc_init; 166559211bd3SMohamad Haj Yahia 1666a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1667a925b5e3SLeon Romanovsky if (err) 1668a925b5e3SLeon Romanovsky goto err_adev_init; 1669a925b5e3SLeon Romanovsky 167048f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 167148f02eefSParav Pandit if (err) 167248f02eefSParav Pandit goto err_hca_caps; 167348f02eefSParav Pandit 1674dc402cccSYishai Hadas /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1675dc402cccSYishai Hadas * unique id per function which uses mlx5_core. 1676dc402cccSYishai Hadas * Those values are supplied to FW as part of the init HCA command to 1677dc402cccSYishai Hadas * be used by both driver and FW when it's applicable. 1678dc402cccSYishai Hadas */ 1679dc402cccSYishai Hadas dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1680dc402cccSYishai Hadas MAX_SW_VHCA_ID, 1681dc402cccSYishai Hadas GFP_KERNEL); 1682dc402cccSYishai Hadas if (dev->priv.sw_vhca_id < 0) 1683dc402cccSYishai Hadas mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1684dc402cccSYishai Hadas dev->priv.sw_vhca_id); 1685dc402cccSYishai Hadas 168611f3b84dSSaeed Mahameed return 0; 168752c368dcSSaeed Mahameed 168848f02eefSParav Pandit err_hca_caps: 168948f02eefSParav Pandit mlx5_adev_cleanup(dev); 1690a925b5e3SLeon Romanovsky err_adev_init: 1691a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 169252c368dcSSaeed Mahameed err_pagealloc_init: 169352c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 169452c368dcSSaeed Mahameed err_health_init: 169576091b0fSAmir Tzin mlx5_tout_cleanup(dev); 169676091b0fSAmir Tzin err_timeout_init: 169766771a1cSMoshe Shemesh debugfs_remove(dev->priv.dbg.dbg_root); 1698810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1699810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1700810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1701810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1702810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1703d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 170452c368dcSSaeed Mahameed return err; 170511f3b84dSSaeed Mahameed } 170611f3b84dSSaeed Mahameed 17071958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 170811f3b84dSSaeed Mahameed { 1709810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1710810cbb25SParav Pandit 1711dc402cccSYishai Hadas if (priv->sw_vhca_id > 0) 1712dc402cccSYishai Hadas ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1713dc402cccSYishai Hadas 171448f02eefSParav Pandit mlx5_hca_caps_free(dev); 1715a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 171652c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 171752c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 171876091b0fSAmir Tzin mlx5_tout_cleanup(dev); 171966771a1cSMoshe Shemesh debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1720810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1721810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1722810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1723810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1724c7d4e6abSJiri Pirko mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1725810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1726d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 172711f3b84dSSaeed Mahameed } 172811f3b84dSSaeed Mahameed 17296dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 173011f3b84dSSaeed Mahameed { 173111f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 173211f3b84dSSaeed Mahameed struct devlink *devlink; 173311f3b84dSSaeed Mahameed int err; 173411f3b84dSSaeed Mahameed 1735919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 173611f3b84dSSaeed Mahameed if (!devlink) { 17371f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 173811f3b84dSSaeed Mahameed return -ENOMEM; 173911f3b84dSSaeed Mahameed } 174011f3b84dSSaeed Mahameed 174111f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 174227b942fbSParav Pandit dev->device = &pdev->dev; 174327b942fbSParav Pandit dev->pdev = pdev; 174411f3b84dSSaeed Mahameed 1745386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1746386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1747386e75afSHuy Nguyen 1748a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 17494d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 17504d8be211SLeon Romanovsky err = dev->priv.adev_idx; 17514d8be211SLeon Romanovsky goto adev_init_err; 17524d8be211SLeon Romanovsky } 1753a925b5e3SLeon Romanovsky 175427b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 175511f3b84dSSaeed Mahameed if (err) 175611f3b84dSSaeed Mahameed goto mdev_init_err; 175711f3b84dSSaeed Mahameed 175811f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 17599603b61dSJack Morgenstein if (err) { 176098a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 176198a8e6fcSHuy Nguyen err); 176211f3b84dSSaeed Mahameed goto pci_init_err; 17639603b61dSJack Morgenstein } 17649603b61dSJack Morgenstein 17656dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 17669603b61dSJack Morgenstein if (err) { 17676dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 176898a8e6fcSHuy Nguyen err); 17696dea2f7eSLeon Romanovsky goto err_init_one; 17709603b61dSJack Morgenstein } 177159211bd3SMohamad Haj Yahia 17728b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 17738b9d8baaSAlex Vesker if (err) 17748b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 17758b9d8baaSAlex Vesker 1776c1fef618SSandipan Patra err = mlx5_thermal_init(dev); 1777c1fef618SSandipan Patra if (err) 1778c1fef618SSandipan Patra dev_err(&pdev->dev, "mlx5_thermal_init failed with error code %d\n", err); 1779c1fef618SSandipan Patra 17805d47f6c8SDaniel Jurgens pci_save_state(pdev); 178164ea2d0eSLeon Romanovsky devlink_register(devlink); 17829603b61dSJack Morgenstein return 0; 17839603b61dSJack Morgenstein 17846dea2f7eSLeon Romanovsky err_init_one: 1785868bc06bSSaeed Mahameed mlx5_pci_close(dev); 178611f3b84dSSaeed Mahameed pci_init_err: 178711f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 178811f3b84dSSaeed Mahameed mdev_init_err: 1789a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 17904d8be211SLeon Romanovsky adev_init_err: 17911f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1792a31208b1SMajd Dibbiny 17939603b61dSJack Morgenstein return err; 17949603b61dSJack Morgenstein } 1795a31208b1SMajd Dibbiny 17969603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 17979603b61dSJack Morgenstein { 17989603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1799feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 18009603b61dSJack Morgenstein 1801031a163fSShay Drory set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 180216d42d31SShay Drory /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 180316d42d31SShay Drory * fw_reset before unregistering the devlink. 180416d42d31SShay Drory */ 180516d42d31SShay Drory mlx5_drain_fw_reset(dev); 180664ea2d0eSLeon Romanovsky devlink_unregister(devlink); 1807143a41d7SYishai Hadas mlx5_sriov_disable(pdev); 1808c1fef618SSandipan Patra mlx5_thermal_uninit(dev); 18098b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 181041798df9SParav Pandit mlx5_drain_health_wq(dev); 18116dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1812868bc06bSSaeed Mahameed mlx5_pci_close(dev); 181311f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1814a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 18151f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 18169603b61dSJack Morgenstein } 18179603b61dSJack Morgenstein 1818fad1783aSSaeed Mahameed #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1819fad1783aSSaeed Mahameed struct mlx5_core_dev *__dev = (dev); \ 1820fad1783aSSaeed Mahameed mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1821fad1783aSSaeed Mahameed __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1822fad1783aSSaeed Mahameed __dev->pci_status, ##__VA_ARGS__); \ 1823fad1783aSSaeed Mahameed }) 1824fad1783aSSaeed Mahameed 1825fad1783aSSaeed Mahameed static const char *result2str(enum pci_ers_result result) 1826fad1783aSSaeed Mahameed { 1827fad1783aSSaeed Mahameed return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1828fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1829fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1830fad1783aSSaeed Mahameed "unknown"; 1831fad1783aSSaeed Mahameed } 1832fad1783aSSaeed Mahameed 183389d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 183489d44f0aSMajd Dibbiny pci_channel_state_t state) 183589d44f0aSMajd Dibbiny { 183689d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1837fad1783aSSaeed Mahameed enum pci_ers_result res; 183889d44f0aSMajd Dibbiny 1839fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 184004c0c1abSMohamad Haj Yahia 18418812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 18423e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 184372ed5d56SJiri Pirko mlx5_unload_one(dev, true); 18445e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 184589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 184605ac2c0bSMohamad Haj Yahia 1847fad1783aSSaeed Mahameed res = state == pci_channel_io_perm_failure ? 184889d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1849fad1783aSSaeed Mahameed 1850394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 1851394164f9SRoy Novich __func__, dev->state, dev->pci_status, res, result2str(res)); 1852fad1783aSSaeed Mahameed return res; 185389d44f0aSMajd Dibbiny } 185489d44f0aSMajd Dibbiny 1855d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1856d57847dcSDaniel Jurgens * for the health counter to start counting. 185789d44f0aSMajd Dibbiny */ 1858d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 185989d44f0aSMajd Dibbiny { 186089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 186189d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 186289d44f0aSMajd Dibbiny const int niter = 100; 1863d57847dcSDaniel Jurgens u32 last_count = 0; 186489d44f0aSMajd Dibbiny u32 count; 186589d44f0aSMajd Dibbiny int i; 186689d44f0aSMajd Dibbiny 186789d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 186889d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 186989d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1870d57847dcSDaniel Jurgens if (last_count && last_count != count) { 187198a8e6fcSHuy Nguyen mlx5_core_info(dev, 187298a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 187398a8e6fcSHuy Nguyen count, i); 1874d57847dcSDaniel Jurgens return 0; 1875d57847dcSDaniel Jurgens } 1876d57847dcSDaniel Jurgens last_count = count; 187789d44f0aSMajd Dibbiny } 187889d44f0aSMajd Dibbiny msleep(50); 187989d44f0aSMajd Dibbiny } 188089d44f0aSMajd Dibbiny 1881d57847dcSDaniel Jurgens return -ETIMEDOUT; 188289d44f0aSMajd Dibbiny } 188389d44f0aSMajd Dibbiny 18841061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 18851061c90fSMohamad Haj Yahia { 1886fad1783aSSaeed Mahameed enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 18871061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18881061c90fSMohamad Haj Yahia int err; 18891061c90fSMohamad Haj Yahia 1890394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 1891394164f9SRoy Novich __func__, dev->state, dev->pci_status); 18921061c90fSMohamad Haj Yahia 18931061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 18941061c90fSMohamad Haj Yahia if (err) { 189598a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 189698a8e6fcSHuy Nguyen __func__, err); 1897fad1783aSSaeed Mahameed goto out; 18981061c90fSMohamad Haj Yahia } 18991061c90fSMohamad Haj Yahia 19001061c90fSMohamad Haj Yahia pci_set_master(pdev); 19011061c90fSMohamad Haj Yahia pci_restore_state(pdev); 19025d47f6c8SDaniel Jurgens pci_save_state(pdev); 19031061c90fSMohamad Haj Yahia 1904fad1783aSSaeed Mahameed err = wait_vital(pdev); 1905fad1783aSSaeed Mahameed if (err) { 1906fad1783aSSaeed Mahameed mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1907fad1783aSSaeed Mahameed __func__, err); 1908fad1783aSSaeed Mahameed goto out; 19091061c90fSMohamad Haj Yahia } 19101061c90fSMohamad Haj Yahia 1911fad1783aSSaeed Mahameed res = PCI_ERS_RESULT_RECOVERED; 1912fad1783aSSaeed Mahameed out: 1913394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 1914394164f9SRoy Novich __func__, dev->state, dev->pci_status, err, res, result2str(res)); 1915fad1783aSSaeed Mahameed return res; 19161061c90fSMohamad Haj Yahia } 19171061c90fSMohamad Haj Yahia 191889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 191989d44f0aSMajd Dibbiny { 192089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 192189d44f0aSMajd Dibbiny int err; 192289d44f0aSMajd Dibbiny 1923fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, loading driver..\n"); 192489d44f0aSMajd Dibbiny 19255977ac39SJiri Pirko err = mlx5_load_one(dev); 1926416ef713SRoy Novich if (!err) 1927416ef713SRoy Novich devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1928416ef713SRoy Novich DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1929416ef713SRoy Novich 1930fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1931fad1783aSSaeed Mahameed !err ? "recovered" : "Failed"); 193289d44f0aSMajd Dibbiny } 193389d44f0aSMajd Dibbiny 193489d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 193589d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 193689d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 193789d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 193889d44f0aSMajd Dibbiny }; 193989d44f0aSMajd Dibbiny 19408812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 19418812c24dSMajd Dibbiny { 1942fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1943fcd29ad1SFeras Daoud int ret = 1; 19448812c24dSMajd Dibbiny 1945fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1946fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1947fcd29ad1SFeras Daoud 1948fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1949fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1950fcd29ad1SFeras Daoud 1951fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 19528812c24dSMajd Dibbiny return -EOPNOTSUPP; 19538812c24dSMajd Dibbiny 19548812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 19558812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 19568812c24dSMajd Dibbiny return -EAGAIN; 19578812c24dSMajd Dibbiny } 19588812c24dSMajd Dibbiny 1959d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1960b0ea505bSJulia Lawall * with the HCA, so the health poll is no longer needed. 1961d2aa060dSHuy Nguyen */ 1962d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 196376d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1964d2aa060dSHuy Nguyen 1965fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1966fcd29ad1SFeras Daoud if (!ret) 1967fcd29ad1SFeras Daoud goto succeed; 1968fcd29ad1SFeras Daoud 19698812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1970fcd29ad1SFeras Daoud if (!ret) 1971fcd29ad1SFeras Daoud goto succeed; 1972fcd29ad1SFeras Daoud 19738812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1974d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 19758812c24dSMajd Dibbiny return ret; 19768812c24dSMajd Dibbiny 1977fcd29ad1SFeras Daoud succeed: 19788812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 19798812c24dSMajd Dibbiny 19801ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 19811ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 19821ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 19831ef903bfSDaniel Jurgens * contexts. 19841ef903bfSDaniel Jurgens */ 19851ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 19861ef903bfSDaniel Jurgens 19878812c24dSMajd Dibbiny return 0; 19888812c24dSMajd Dibbiny } 19898812c24dSMajd Dibbiny 19905fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 19915fc7197dSMajd Dibbiny { 19925fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19938812c24dSMajd Dibbiny int err; 19945fc7197dSMajd Dibbiny 199598a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 19968324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 19978812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 19988812c24dSMajd Dibbiny if (err) 199972ed5d56SJiri Pirko mlx5_unload_one(dev, false); 20005fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 20015fc7197dSMajd Dibbiny } 20025fc7197dSMajd Dibbiny 20038fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 20048fc3e29bSMark Bloch { 20058fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 20068fc3e29bSMark Bloch 200772ed5d56SJiri Pirko mlx5_unload_one(dev, true); 20088fc3e29bSMark Bloch 20098fc3e29bSMark Bloch return 0; 20108fc3e29bSMark Bloch } 20118fc3e29bSMark Bloch 20128fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 20138fc3e29bSMark Bloch { 20148fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 20158fc3e29bSMark Bloch 20165977ac39SJiri Pirko return mlx5_load_one(dev); 20178fc3e29bSMark Bloch } 20188fc3e29bSMark Bloch 20199603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 2020bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2021fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2022bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2023fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2024bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2025fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 20267092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 202764dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2028d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2029d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2030d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2031d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 203285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 203385327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2034b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2035505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2036f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 20372e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 20382e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2039d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2040dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2041f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 20429603b61dSJack Morgenstein { 0, } 20439603b61dSJack Morgenstein }; 20449603b61dSJack Morgenstein 20459603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 20469603b61dSJack Morgenstein 204704c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 204804c0c1abSMohamad Haj Yahia { 2049b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 205072ed5d56SJiri Pirko mlx5_unload_one_devl_locked(dev, false); 205104c0c1abSMohamad Haj Yahia } 205204c0c1abSMohamad Haj Yahia 2053fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 205404c0c1abSMohamad Haj Yahia { 205533de865fSMoshe Shemesh if (!mlx5_core_is_sf(dev)) { 205604c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 205733de865fSMoshe Shemesh if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 205833de865fSMoshe Shemesh return -EIO; 205933de865fSMoshe Shemesh } 206033de865fSMoshe Shemesh 2061d3dbdc9fSMoshe Shemesh return mlx5_load_one_devl_locked(dev, true); 206204c0c1abSMohamad Haj Yahia } 206304c0c1abSMohamad Haj Yahia 20649603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 206517a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 20669603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 20676dea2f7eSLeon Romanovsky .probe = probe_one, 206889d44f0aSMajd Dibbiny .remove = remove_one, 20698fc3e29bSMark Bloch .suspend = mlx5_suspend, 20708fc3e29bSMark Bloch .resume = mlx5_resume, 20715fc7197dSMajd Dibbiny .shutdown = shutdown, 2072fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 2073fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 2074e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2075e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 20769603b61dSJack Morgenstein }; 2077e126ba97SEli Cohen 20781695b97bSYishai Hadas /** 20791695b97bSYishai Hadas * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 20801695b97bSYishai Hadas * mlx5_core is its driver. 20811695b97bSYishai Hadas * @pdev: The associated PCI device. 20821695b97bSYishai Hadas * 20831695b97bSYishai Hadas * Upon return the interface state lock stay held to let caller uses it safely. 20841695b97bSYishai Hadas * Caller must ensure to use the returned mlx5 device for a narrow window 20851695b97bSYishai Hadas * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 20861695b97bSYishai Hadas * 20871695b97bSYishai Hadas * Return: Pointer to the associated mlx5_core_dev or NULL. 20881695b97bSYishai Hadas */ 20891695b97bSYishai Hadas struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 20901695b97bSYishai Hadas { 20911695b97bSYishai Hadas struct mlx5_core_dev *mdev; 20921695b97bSYishai Hadas 20931695b97bSYishai Hadas mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 20941695b97bSYishai Hadas if (IS_ERR(mdev)) 20951695b97bSYishai Hadas return NULL; 20961695b97bSYishai Hadas 20971695b97bSYishai Hadas mutex_lock(&mdev->intf_state_mutex); 20981695b97bSYishai Hadas if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 20991695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 21001695b97bSYishai Hadas return NULL; 21011695b97bSYishai Hadas } 21021695b97bSYishai Hadas 21031695b97bSYishai Hadas return mdev; 21041695b97bSYishai Hadas } 21051695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_get_core_dev); 21061695b97bSYishai Hadas 21071695b97bSYishai Hadas /** 21081695b97bSYishai Hadas * mlx5_vf_put_core_dev - Put the mlx5 core device back. 21091695b97bSYishai Hadas * @mdev: The mlx5 core device. 21101695b97bSYishai Hadas * 21111695b97bSYishai Hadas * Upon return the interface state lock is unlocked and caller should not 21121695b97bSYishai Hadas * access the mdev any more. 21131695b97bSYishai Hadas */ 21141695b97bSYishai Hadas void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 21151695b97bSYishai Hadas { 21161695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 21171695b97bSYishai Hadas } 21181695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_put_core_dev); 21191695b97bSYishai Hadas 2120f663ad98SKamal Heib static void mlx5_core_verify_params(void) 2121f663ad98SKamal Heib { 2122f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 2123f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2124f663ad98SKamal Heib prof_sel, 2125f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 2126f663ad98SKamal Heib MLX5_DEFAULT_PROF); 2127f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 2128f663ad98SKamal Heib } 2129f663ad98SKamal Heib } 2130f663ad98SKamal Heib 21312c1e1b94SRandy Dunlap static int __init mlx5_init(void) 2132e126ba97SEli Cohen { 2133e126ba97SEli Cohen int err; 2134e126ba97SEli Cohen 213517a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 213617a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 213717a7612bSLeon Romanovsky 21388737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 21398737f818SDaniel Jurgens 2140f663ad98SKamal Heib mlx5_core_verify_params(); 2141e126ba97SEli Cohen mlx5_register_debugfs(); 2142e126ba97SEli Cohen 21438f0d1451SShay Drory err = mlx5e_init(); 21449603b61dSJack Morgenstein if (err) 2145ac6ea6e8SEli Cohen goto err_debug; 21469603b61dSJack Morgenstein 21471958fc2fSParav Pandit err = mlx5_sf_driver_register(); 21481958fc2fSParav Pandit if (err) 21491958fc2fSParav Pandit goto err_sf; 21501958fc2fSParav Pandit 21518f0d1451SShay Drory err = pci_register_driver(&mlx5_core_driver); 2152c633e799SLeon Romanovsky if (err) 21538f0d1451SShay Drory goto err_pci; 2154f62b8bb8SAmir Vadai 2155e126ba97SEli Cohen return 0; 2156e126ba97SEli Cohen 21578f0d1451SShay Drory err_pci: 2158c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 21591958fc2fSParav Pandit err_sf: 21608f0d1451SShay Drory mlx5e_cleanup(); 2161e126ba97SEli Cohen err_debug: 2162e126ba97SEli Cohen mlx5_unregister_debugfs(); 2163e126ba97SEli Cohen return err; 2164e126ba97SEli Cohen } 2165e126ba97SEli Cohen 21662c1e1b94SRandy Dunlap static void __exit mlx5_cleanup(void) 2167e126ba97SEli Cohen { 21689603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 21698f0d1451SShay Drory mlx5_sf_driver_unregister(); 21708f0d1451SShay Drory mlx5e_cleanup(); 2171e126ba97SEli Cohen mlx5_unregister_debugfs(); 2172e126ba97SEli Cohen } 2173e126ba97SEli Cohen 21742c1e1b94SRandy Dunlap module_init(mlx5_init); 21752c1e1b94SRandy Dunlap module_exit(mlx5_cleanup); 2176