1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6052ec462eSIlan Tayari #include "lib/mlx5.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 6205564d0aSAviad Yehezkel #include "fpga/ipsec.h" 63bebb23e6SIlan Tayari #include "accel/ipsec.h" 641ae17322SIlya Lesokhin #include "accel/tls.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 7287175120SEran Ben Elisha #include "lib/hv_vhca.h" 7312206b17SAya Levin #include "diag/rsc_dump.h" 74e126ba97SEli Cohen 75e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 77e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 78e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 79e126ba97SEli Cohen 80f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 81f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 82e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 83e126ba97SEli Cohen 849603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 85f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 879603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 889603b61dSJack Morgenstein 898737f818SDaniel Jurgens static u32 sw_owner_id[4]; 908737f818SDaniel Jurgens 91f91e6d89SEran Ben Elisha enum { 92f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 93f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 94f91e6d89SEran Ben Elisha }; 95f91e6d89SEran Ben Elisha 969603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 979603b61dSJack Morgenstein [0] = { 989603b61dSJack Morgenstein .mask = 0, 999603b61dSJack Morgenstein }, 1009603b61dSJack Morgenstein [1] = { 1019603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1029603b61dSJack Morgenstein .log_max_qp = 12, 1039603b61dSJack Morgenstein }, 1049603b61dSJack Morgenstein [2] = { 1059603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1069603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1075f40b4edSMaor Gottlieb .log_max_qp = 18, 1089603b61dSJack Morgenstein .mr_cache[0] = { 1099603b61dSJack Morgenstein .size = 500, 1109603b61dSJack Morgenstein .limit = 250 1119603b61dSJack Morgenstein }, 1129603b61dSJack Morgenstein .mr_cache[1] = { 1139603b61dSJack Morgenstein .size = 500, 1149603b61dSJack Morgenstein .limit = 250 1159603b61dSJack Morgenstein }, 1169603b61dSJack Morgenstein .mr_cache[2] = { 1179603b61dSJack Morgenstein .size = 500, 1189603b61dSJack Morgenstein .limit = 250 1199603b61dSJack Morgenstein }, 1209603b61dSJack Morgenstein .mr_cache[3] = { 1219603b61dSJack Morgenstein .size = 500, 1229603b61dSJack Morgenstein .limit = 250 1239603b61dSJack Morgenstein }, 1249603b61dSJack Morgenstein .mr_cache[4] = { 1259603b61dSJack Morgenstein .size = 500, 1269603b61dSJack Morgenstein .limit = 250 1279603b61dSJack Morgenstein }, 1289603b61dSJack Morgenstein .mr_cache[5] = { 1299603b61dSJack Morgenstein .size = 500, 1309603b61dSJack Morgenstein .limit = 250 1319603b61dSJack Morgenstein }, 1329603b61dSJack Morgenstein .mr_cache[6] = { 1339603b61dSJack Morgenstein .size = 500, 1349603b61dSJack Morgenstein .limit = 250 1359603b61dSJack Morgenstein }, 1369603b61dSJack Morgenstein .mr_cache[7] = { 1379603b61dSJack Morgenstein .size = 500, 1389603b61dSJack Morgenstein .limit = 250 1399603b61dSJack Morgenstein }, 1409603b61dSJack Morgenstein .mr_cache[8] = { 1419603b61dSJack Morgenstein .size = 500, 1429603b61dSJack Morgenstein .limit = 250 1439603b61dSJack Morgenstein }, 1449603b61dSJack Morgenstein .mr_cache[9] = { 1459603b61dSJack Morgenstein .size = 500, 1469603b61dSJack Morgenstein .limit = 250 1479603b61dSJack Morgenstein }, 1489603b61dSJack Morgenstein .mr_cache[10] = { 1499603b61dSJack Morgenstein .size = 500, 1509603b61dSJack Morgenstein .limit = 250 1519603b61dSJack Morgenstein }, 1529603b61dSJack Morgenstein .mr_cache[11] = { 1539603b61dSJack Morgenstein .size = 500, 1549603b61dSJack Morgenstein .limit = 250 1559603b61dSJack Morgenstein }, 1569603b61dSJack Morgenstein .mr_cache[12] = { 1579603b61dSJack Morgenstein .size = 64, 1589603b61dSJack Morgenstein .limit = 32 1599603b61dSJack Morgenstein }, 1609603b61dSJack Morgenstein .mr_cache[13] = { 1619603b61dSJack Morgenstein .size = 32, 1629603b61dSJack Morgenstein .limit = 16 1639603b61dSJack Morgenstein }, 1649603b61dSJack Morgenstein .mr_cache[14] = { 1659603b61dSJack Morgenstein .size = 16, 1669603b61dSJack Morgenstein .limit = 8 1679603b61dSJack Morgenstein }, 1689603b61dSJack Morgenstein .mr_cache[15] = { 1699603b61dSJack Morgenstein .size = 8, 1709603b61dSJack Morgenstein .limit = 4 1719603b61dSJack Morgenstein }, 1729603b61dSJack Morgenstein }, 1739603b61dSJack Morgenstein }; 174e126ba97SEli Cohen 175e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 176e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 177b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 178b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 179e3297246SEli Cohen 180555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 181555af0c3SParav Pandit { 182555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 183555af0c3SParav Pandit } 184555af0c3SParav Pandit 185b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 186b8a92577SDaniel Jurgens u32 warn_time_mili) 187e3297246SEli Cohen { 188b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 189e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 190e3297246SEli Cohen int err = 0; 191e3297246SEli Cohen 192b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 193b8a92577SDaniel Jurgens 194e3297246SEli Cohen while (fw_initializing(dev)) { 195e3297246SEli Cohen if (time_after(jiffies, end)) { 196e3297246SEli Cohen err = -EBUSY; 197e3297246SEli Cohen break; 198e3297246SEli Cohen } 199b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 200b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 201b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 202b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 203b8a92577SDaniel Jurgens } 204e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 205e3297246SEli Cohen } 206e3297246SEli Cohen 207e3297246SEli Cohen return err; 208e3297246SEli Cohen } 209e3297246SEli Cohen 210012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 211012e50e1SHuy Nguyen { 212012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 213012e50e1SHuy Nguyen driver_version); 2143ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 215012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 216012e50e1SHuy Nguyen char *string; 217012e50e1SHuy Nguyen 218012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 219012e50e1SHuy Nguyen return; 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 222012e50e1SHuy Nguyen 223012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 224012e50e1SHuy Nguyen 225012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 226012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen /*Send the command*/ 238012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 239012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 240012e50e1SHuy Nguyen 2413ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 242012e50e1SHuy Nguyen } 243012e50e1SHuy Nguyen 244e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 245e126ba97SEli Cohen { 246e126ba97SEli Cohen int err; 247e126ba97SEli Cohen 248e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 249e126ba97SEli Cohen if (err) { 2501a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 251e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 252e126ba97SEli Cohen if (err) { 2531a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 254e126ba97SEli Cohen return err; 255e126ba97SEli Cohen } 256e126ba97SEli Cohen } 257e126ba97SEli Cohen 258e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 259e126ba97SEli Cohen if (err) { 260e126ba97SEli Cohen dev_warn(&pdev->dev, 2611a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 262e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 263e126ba97SEli Cohen if (err) { 264e126ba97SEli Cohen dev_err(&pdev->dev, 2651a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 266e126ba97SEli Cohen return err; 267e126ba97SEli Cohen } 268e126ba97SEli Cohen } 269e126ba97SEli Cohen 270e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 271e126ba97SEli Cohen return err; 272e126ba97SEli Cohen } 273e126ba97SEli Cohen 27489d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27589d44f0aSMajd Dibbiny { 27689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27789d44f0aSMajd Dibbiny int err = 0; 27889d44f0aSMajd Dibbiny 27989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 28189d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 28289d44f0aSMajd Dibbiny if (!err) 28389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 28489d44f0aSMajd Dibbiny } 28589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28689d44f0aSMajd Dibbiny 28789d44f0aSMajd Dibbiny return err; 28889d44f0aSMajd Dibbiny } 28989d44f0aSMajd Dibbiny 29089d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 29189d44f0aSMajd Dibbiny { 29289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29389d44f0aSMajd Dibbiny 29489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29689d44f0aSMajd Dibbiny pci_disable_device(pdev); 29789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29889d44f0aSMajd Dibbiny } 29989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 30089d44f0aSMajd Dibbiny } 30189d44f0aSMajd Dibbiny 302e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 303e126ba97SEli Cohen { 304e126ba97SEli Cohen int err = 0; 305e126ba97SEli Cohen 306e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3071a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 308e126ba97SEli Cohen return -ENODEV; 309e126ba97SEli Cohen } 310e126ba97SEli Cohen 311e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 312e126ba97SEli Cohen if (err) 313e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 314e126ba97SEli Cohen 315e126ba97SEli Cohen return err; 316e126ba97SEli Cohen } 317e126ba97SEli Cohen 318e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 319e126ba97SEli Cohen { 320e126ba97SEli Cohen pci_release_regions(pdev); 321e126ba97SEli Cohen } 322e126ba97SEli Cohen 323bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 324e126ba97SEli Cohen u8 he; 325e126ba97SEli Cohen u8 rsvd[15]; 326e126ba97SEli Cohen }; 327e126ba97SEli Cohen 32887b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32987b8de49SEli Cohen 33087b8de49SEli Cohen enum { 33187b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 332c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 33387b8de49SEli Cohen }; 33487b8de49SEli Cohen 3352974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 336c7a08ac7SEli Cohen { 337c7a08ac7SEli Cohen switch (size) { 338c7a08ac7SEli Cohen case 128: 339c7a08ac7SEli Cohen return 0; 340c7a08ac7SEli Cohen case 256: 341c7a08ac7SEli Cohen return 1; 342c7a08ac7SEli Cohen case 512: 343c7a08ac7SEli Cohen return 2; 344c7a08ac7SEli Cohen case 1024: 345c7a08ac7SEli Cohen return 3; 346c7a08ac7SEli Cohen case 2048: 347c7a08ac7SEli Cohen return 4; 348c7a08ac7SEli Cohen case 4096: 349c7a08ac7SEli Cohen return 5; 350c7a08ac7SEli Cohen default: 3512974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 352c7a08ac7SEli Cohen return 0; 353c7a08ac7SEli Cohen } 354c7a08ac7SEli Cohen } 355c7a08ac7SEli Cohen 356b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 357b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 358938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 359c7a08ac7SEli Cohen { 360b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 361b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 362938fe83cSSaeed Mahameed void *out, *hca_caps; 363938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 364c7a08ac7SEli Cohen int err; 365c7a08ac7SEli Cohen 366b775516bSEli Cohen memset(in, 0, sizeof(in)); 367b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 368c7a08ac7SEli Cohen if (!out) 369c7a08ac7SEli Cohen return -ENOMEM; 370938fe83cSSaeed Mahameed 371b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 372b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3733ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 374c7a08ac7SEli Cohen if (err) { 375938fe83cSSaeed Mahameed mlx5_core_warn(dev, 376938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 377938fe83cSSaeed Mahameed cap_type, cap_mode, err); 378c7a08ac7SEli Cohen goto query_ex; 379c7a08ac7SEli Cohen } 380c7a08ac7SEli Cohen 381938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 382938fe83cSSaeed Mahameed 383938fe83cSSaeed Mahameed switch (cap_mode) { 384938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 385701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 386938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 387938fe83cSSaeed Mahameed break; 388938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 389701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 390938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 391938fe83cSSaeed Mahameed break; 392938fe83cSSaeed Mahameed default: 393938fe83cSSaeed Mahameed mlx5_core_warn(dev, 394938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 395938fe83cSSaeed Mahameed cap_type, cap_mode); 396938fe83cSSaeed Mahameed err = -EINVAL; 397938fe83cSSaeed Mahameed break; 398938fe83cSSaeed Mahameed } 399c7a08ac7SEli Cohen query_ex: 400c7a08ac7SEli Cohen kfree(out); 401c7a08ac7SEli Cohen return err; 402c7a08ac7SEli Cohen } 403c7a08ac7SEli Cohen 404b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 405b06e7de8SLeon Romanovsky { 406b06e7de8SLeon Romanovsky int ret; 407b06e7de8SLeon Romanovsky 408b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 409b06e7de8SLeon Romanovsky if (ret) 410b06e7de8SLeon Romanovsky return ret; 411b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 412b06e7de8SLeon Romanovsky } 413b06e7de8SLeon Romanovsky 414a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 415c7a08ac7SEli Cohen { 416b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 417f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4183ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 419c7a08ac7SEli Cohen } 42087b8de49SEli Cohen 421a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 422f91e6d89SEran Ben Elisha { 423f91e6d89SEran Ben Elisha void *set_hca_cap; 424f91e6d89SEran Ben Elisha int req_endianness; 425f91e6d89SEran Ben Elisha int err; 426f91e6d89SEran Ben Elisha 427a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 428a2a322f4SLeon Romanovsky return 0; 429a2a322f4SLeon Romanovsky 430b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 431f91e6d89SEran Ben Elisha if (err) 432f91e6d89SEran Ben Elisha return err; 433f91e6d89SEran Ben Elisha 434f91e6d89SEran Ben Elisha req_endianness = 435f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 436bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 437f91e6d89SEran Ben Elisha 438f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 439f91e6d89SEran Ben Elisha return 0; 440f91e6d89SEran Ben Elisha 441f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 442f91e6d89SEran Ben Elisha 443f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 444bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 445f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 446f91e6d89SEran Ben Elisha 447a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 448f91e6d89SEran Ben Elisha } 449f91e6d89SEran Ben Elisha 450a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45146861e3eSMoni Shoua { 45246861e3eSMoni Shoua void *set_hca_cap; 453fca22e7eSMoni Shoua bool do_set = false; 45446861e3eSMoni Shoua int err; 45546861e3eSMoni Shoua 45637b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 45737b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 45846861e3eSMoni Shoua return 0; 45946861e3eSMoni Shoua 46046861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46146861e3eSMoni Shoua if (err) 46246861e3eSMoni Shoua return err; 46346861e3eSMoni Shoua 46446861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 46546861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 46646861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 46746861e3eSMoni Shoua 468fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 469fca22e7eSMoni Shoua do { \ 470fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 471fca22e7eSMoni Shoua if (_res) { \ 472fca22e7eSMoni Shoua do_set = true; \ 473fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 474fca22e7eSMoni Shoua } \ 475fca22e7eSMoni Shoua } while (0) 47646861e3eSMoni Shoua 477fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 478fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 479fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 480fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 481fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 482fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 48500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 48600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 48700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 48800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 48900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49146861e3eSMoni Shoua 492a2a322f4SLeon Romanovsky if (!do_set) 493a2a322f4SLeon Romanovsky return 0; 49446861e3eSMoni Shoua 495a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 49646861e3eSMoni Shoua } 49746861e3eSMoni Shoua 498a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 499e126ba97SEli Cohen { 500c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 501938fe83cSSaeed Mahameed void *set_hca_cap; 502a2a322f4SLeon Romanovsky int err; 503e126ba97SEli Cohen 504b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 505c7a08ac7SEli Cohen if (err) 506a2a322f4SLeon Romanovsky return err; 507e126ba97SEli Cohen 508938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 509938fe83cSSaeed Mahameed capability); 510701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 511938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 512938fe83cSSaeed Mahameed 513938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 514707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 515938fe83cSSaeed Mahameed 128); 516c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 517938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5182974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 519e126ba97SEli Cohen 520883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 521883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 522883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 523883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 524883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 525883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 526883371c4SNoa Osherovich } 527c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 528938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 529938fe83cSSaeed Mahameed prof->log_max_qp); 530e126ba97SEli Cohen 531938fe83cSSaeed Mahameed /* disable cmdif checksum */ 532938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 533c1868b82SEli Cohen 53491828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 53591828bd8SMajd Dibbiny * than 4K. 53691828bd8SMajd Dibbiny */ 53791828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 538f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 539f502d834SEli Cohen 540fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 541fe1e1876SCarol L Soto 542f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 543f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 544f32f5bd2SDaniel Jurgens set_hca_cap, 545f32f5bd2SDaniel Jurgens cache_line_128byte, 546c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 547f32f5bd2SDaniel Jurgens 548dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 549dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 550dd44572aSMoni Shoua 551c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 552c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 553c4b76d8dSDaniel Jurgens set_hca_cap, 554c4b76d8dSDaniel Jurgens num_vhca_ports, 555c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 556c4b76d8dSDaniel Jurgens 557c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 558c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 559c6168161SEran Ben Elisha 560a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 561e126ba97SEli Cohen } 562cd23b14bSEli Cohen 56359e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 56459e9e8e4SMark Zhang { 56559e9e8e4SMark Zhang void *set_hca_cap; 56659e9e8e4SMark Zhang int err; 56759e9e8e4SMark Zhang 56859e9e8e4SMark Zhang if (!MLX5_CAP_GEN(dev, roce)) 56959e9e8e4SMark Zhang return 0; 57059e9e8e4SMark Zhang 57159e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 57259e9e8e4SMark Zhang if (err) 57359e9e8e4SMark Zhang return err; 57459e9e8e4SMark Zhang 57559e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 57659e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 57759e9e8e4SMark Zhang return 0; 57859e9e8e4SMark Zhang 57959e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 58059e9e8e4SMark Zhang memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 58159e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 58259e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 58359e9e8e4SMark Zhang 58459e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 585e126ba97SEli Cohen return err; 586e126ba97SEli Cohen } 587e126ba97SEli Cohen 58837b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 58937b6bb77SLeon Romanovsky { 590a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 591a2a322f4SLeon Romanovsky void *set_ctx; 59237b6bb77SLeon Romanovsky int err; 59337b6bb77SLeon Romanovsky 594a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 595a2a322f4SLeon Romanovsky if (!set_ctx) 596a2a322f4SLeon Romanovsky return -ENOMEM; 597a2a322f4SLeon Romanovsky 598a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 59937b6bb77SLeon Romanovsky if (err) { 60098a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 60137b6bb77SLeon Romanovsky goto out; 60237b6bb77SLeon Romanovsky } 60337b6bb77SLeon Romanovsky 604a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 605a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 60637b6bb77SLeon Romanovsky if (err) { 60798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 60837b6bb77SLeon Romanovsky goto out; 60937b6bb77SLeon Romanovsky } 61037b6bb77SLeon Romanovsky 611a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 612a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 61337b6bb77SLeon Romanovsky if (err) { 61498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 61537b6bb77SLeon Romanovsky goto out; 61637b6bb77SLeon Romanovsky } 61737b6bb77SLeon Romanovsky 61859e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 61959e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 62059e9e8e4SMark Zhang if (err) { 62159e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 62259e9e8e4SMark Zhang goto out; 62359e9e8e4SMark Zhang } 62459e9e8e4SMark Zhang 62537b6bb77SLeon Romanovsky out: 626a2a322f4SLeon Romanovsky kfree(set_ctx); 62737b6bb77SLeon Romanovsky return err; 62837b6bb77SLeon Romanovsky } 62937b6bb77SLeon Romanovsky 630e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 631e126ba97SEli Cohen { 632bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 633bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 634e126ba97SEli Cohen int err; 635e126ba97SEli Cohen 636fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 637fc50db98SEli Cohen return 0; 638fc50db98SEli Cohen 639e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 640e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 641e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 642e126ba97SEli Cohen &he_out, sizeof(he_out), 643e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 644e126ba97SEli Cohen return err; 645e126ba97SEli Cohen } 646e126ba97SEli Cohen 647c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 648c85023e1SHuy Nguyen { 649c85023e1SHuy Nguyen int ret = 0; 650c85023e1SHuy Nguyen 651c85023e1SHuy Nguyen /* Disable local_lb by default */ 6528978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 653c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 654c85023e1SHuy Nguyen 655c85023e1SHuy Nguyen return ret; 656c85023e1SHuy Nguyen } 657c85023e1SHuy Nguyen 6580b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 659e126ba97SEli Cohen { 6603ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 661e126ba97SEli Cohen 6620b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6630b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 66422e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 66522e939a9SBodong Wang dev->caps.embedded_cpu); 6663ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 667e126ba97SEli Cohen } 668e126ba97SEli Cohen 6690b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 670e126ba97SEli Cohen { 6713ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 672e126ba97SEli Cohen 6730b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6740b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 67522e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 67622e939a9SBodong Wang dev->caps.embedded_cpu); 6773ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 678e126ba97SEli Cohen } 679e126ba97SEli Cohen 680f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 681f62b8bb8SAmir Vadai { 6823ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 6833ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 684f62b8bb8SAmir Vadai u32 sup_issi; 685c4f287c4SSaeed Mahameed int err; 686f62b8bb8SAmir Vadai 687f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 6883ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 689f62b8bb8SAmir Vadai if (err) { 690c4f287c4SSaeed Mahameed u32 syndrome; 691c4f287c4SSaeed Mahameed u8 status; 692c4f287c4SSaeed Mahameed 693c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 694f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 695f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 696f9c14e46SKamal Heib err, status, syndrome); 697f9c14e46SKamal Heib return err; 698f62b8bb8SAmir Vadai } 699f62b8bb8SAmir Vadai 700f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 701f9c14e46SKamal Heib dev->issi = 0; 702f9c14e46SKamal Heib return 0; 703f62b8bb8SAmir Vadai } 704f62b8bb8SAmir Vadai 705f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 706f62b8bb8SAmir Vadai 707f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7083ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 709f62b8bb8SAmir Vadai 710f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 711f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7123ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 713f62b8bb8SAmir Vadai if (err) { 714f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 715f9c14e46SKamal Heib err); 716f62b8bb8SAmir Vadai return err; 717f62b8bb8SAmir Vadai } 718f62b8bb8SAmir Vadai 719f62b8bb8SAmir Vadai dev->issi = 1; 720f62b8bb8SAmir Vadai 721f62b8bb8SAmir Vadai return 0; 722e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 723f62b8bb8SAmir Vadai return 0; 724f62b8bb8SAmir Vadai } 725f62b8bb8SAmir Vadai 7269eb78923SOr Gerlitz return -EOPNOTSUPP; 727f62b8bb8SAmir Vadai } 728f62b8bb8SAmir Vadai 72911f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 73011f3b84dSSaeed Mahameed const struct pci_device_id *id) 731a31208b1SMajd Dibbiny { 732868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 733a31208b1SMajd Dibbiny int err = 0; 734a31208b1SMajd Dibbiny 735d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 736e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 737e126ba97SEli Cohen 738aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 739311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 740311c7c71SSaeed Mahameed 74189d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 742e126ba97SEli Cohen if (err) { 74398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 74411f3b84dSSaeed Mahameed return err; 745e126ba97SEli Cohen } 746e126ba97SEli Cohen 747e126ba97SEli Cohen err = request_bar(pdev); 748e126ba97SEli Cohen if (err) { 74998a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 750e126ba97SEli Cohen goto err_disable; 751e126ba97SEli Cohen } 752e126ba97SEli Cohen 753e126ba97SEli Cohen pci_set_master(pdev); 754e126ba97SEli Cohen 755e126ba97SEli Cohen err = set_dma_caps(pdev); 756e126ba97SEli Cohen if (err) { 75798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 758e126ba97SEli Cohen goto err_clr_master; 759e126ba97SEli Cohen } 760e126ba97SEli Cohen 761ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 762ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 763ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 764ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 765ce4eee53SMichael Guralnik 766aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 767e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 768e126ba97SEli Cohen if (!dev->iseg) { 769e126ba97SEli Cohen err = -ENOMEM; 77098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 771e126ba97SEli Cohen goto err_clr_master; 772e126ba97SEli Cohen } 773a31208b1SMajd Dibbiny 774b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 775c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 776a31208b1SMajd Dibbiny return 0; 777a31208b1SMajd Dibbiny 778a31208b1SMajd Dibbiny err_clr_master: 779a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 780a31208b1SMajd Dibbiny release_bar(dev->pdev); 781a31208b1SMajd Dibbiny err_disable: 78289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 783a31208b1SMajd Dibbiny return err; 784a31208b1SMajd Dibbiny } 785a31208b1SMajd Dibbiny 786868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 787a31208b1SMajd Dibbiny { 78842ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 78942ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 79042ea9f1bSShay Drory * before removing the pci bars 79142ea9f1bSShay Drory */ 79242ea9f1bSShay Drory mlx5_drain_health_wq(dev); 793a31208b1SMajd Dibbiny iounmap(dev->iseg); 794a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 795a31208b1SMajd Dibbiny release_bar(dev->pdev); 79689d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 797a31208b1SMajd Dibbiny } 798a31208b1SMajd Dibbiny 799868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 80059211bd3SMohamad Haj Yahia { 80159211bd3SMohamad Haj Yahia int err; 80259211bd3SMohamad Haj Yahia 803868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 804868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 80598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 806868bc06bSSaeed Mahameed dev->priv.devcom); 807fadd59fcSAviv Heller 80859211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 80959211bd3SMohamad Haj Yahia if (err) { 81098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 811fadd59fcSAviv Heller goto err_devcom; 81259211bd3SMohamad Haj Yahia } 81359211bd3SMohamad Haj Yahia 814561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 815561aa15aSYuval Avnery if (err) { 816561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 817561aa15aSYuval Avnery goto err_devcom; 818561aa15aSYuval Avnery } 819561aa15aSYuval Avnery 820f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 82159211bd3SMohamad Haj Yahia if (err) { 82298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 823561aa15aSYuval Avnery goto err_irq_cleanup; 82459211bd3SMohamad Haj Yahia } 82559211bd3SMohamad Haj Yahia 82669c1280bSSaeed Mahameed err = mlx5_events_init(dev); 82769c1280bSSaeed Mahameed if (err) { 82898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 82969c1280bSSaeed Mahameed goto err_eq_cleanup; 83069c1280bSSaeed Mahameed } 83169c1280bSSaeed Mahameed 8329f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 83359211bd3SMohamad Haj Yahia 83452ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 83552ec462eSIlan Tayari 8367c39afb3SFeras Daoud mlx5_init_clock(dev); 8377c39afb3SFeras Daoud 838358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8390ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 840358aa5ceSSaeed Mahameed 84159211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 84259211bd3SMohamad Haj Yahia if (err) { 84398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 84459211bd3SMohamad Haj Yahia goto err_tables_cleanup; 84559211bd3SMohamad Haj Yahia } 84659211bd3SMohamad Haj Yahia 847eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 848eeb66cdbSSaeed Mahameed if (err) { 84998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 850eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 851eeb66cdbSSaeed Mahameed } 852eeb66cdbSSaeed Mahameed 853c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 854c2d6e31aSMohamad Haj Yahia if (err) { 85598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 85686eec50bSBodong Wang goto err_mpfs_cleanup; 85786eec50bSBodong Wang } 85886eec50bSBodong Wang 85986eec50bSBodong Wang err = mlx5_eswitch_init(dev); 86086eec50bSBodong Wang if (err) { 86186eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 86286eec50bSBodong Wang goto err_sriov_cleanup; 863c2d6e31aSMohamad Haj Yahia } 864c2d6e31aSMohamad Haj Yahia 8659410733cSIlan Tayari err = mlx5_fpga_init(dev); 8669410733cSIlan Tayari if (err) { 86798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 86886eec50bSBodong Wang goto err_eswitch_cleanup; 8699410733cSIlan Tayari } 8709410733cSIlan Tayari 871c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 872c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 873c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 874c9b9dcb4SAriel Levkovich 87524406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 87687175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 87712206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 87824406953SFeras Daoud 87959211bd3SMohamad Haj Yahia return 0; 88059211bd3SMohamad Haj Yahia 881c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 882c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 88386eec50bSBodong Wang err_sriov_cleanup: 88486eec50bSBodong Wang mlx5_sriov_cleanup(dev); 885eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 886eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 887c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 888c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 88959211bd3SMohamad Haj Yahia err_tables_cleanup: 8900ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 891358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 89202d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 89369c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 89459211bd3SMohamad Haj Yahia err_eq_cleanup: 895f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 896561aa15aSYuval Avnery err_irq_cleanup: 897561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 898fadd59fcSAviv Heller err_devcom: 899fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 90059211bd3SMohamad Haj Yahia 90159211bd3SMohamad Haj Yahia return err; 90259211bd3SMohamad Haj Yahia } 90359211bd3SMohamad Haj Yahia 90459211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 90559211bd3SMohamad Haj Yahia { 90612206b17SAya Levin mlx5_rsc_dump_destroy(dev); 90787175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 90824406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 909c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9109410733cSIlan Tayari mlx5_fpga_cleanup(dev); 911c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 91286eec50bSBodong Wang mlx5_sriov_cleanup(dev); 913eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 91459211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9150ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 916358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9177c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 91852ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 91902d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 92069c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 921f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 922561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 923fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 92459211bd3SMohamad Haj Yahia } 92559211bd3SMohamad Haj Yahia 926e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 927a31208b1SMajd Dibbiny { 928a31208b1SMajd Dibbiny int err; 929a31208b1SMajd Dibbiny 93098a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 931e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 932e126ba97SEli Cohen 93300c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 93400c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 93500c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 93600c6bcb0STal Gilboa 9376c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9386c780a02SEli Cohen */ 939b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9406c780a02SEli Cohen if (err) { 94198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9426c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 943e161105eSSaeed Mahameed return err; 9446c780a02SEli Cohen } 9456c780a02SEli Cohen 946e126ba97SEli Cohen err = mlx5_cmd_init(dev); 947e126ba97SEli Cohen if (err) { 94898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 949e161105eSSaeed Mahameed return err; 950e126ba97SEli Cohen } 951e126ba97SEli Cohen 952b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 953e3297246SEli Cohen if (err) { 95498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 955e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 95655378a23SMohamad Haj Yahia goto err_cmd_cleanup; 957e3297246SEli Cohen } 958e3297246SEli Cohen 959f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 960f7936dddSEran Ben Elisha 9610b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 962cd23b14bSEli Cohen if (err) { 96398a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 96459211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 965cd23b14bSEli Cohen } 966cd23b14bSEli Cohen 967f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 968f62b8bb8SAmir Vadai if (err) { 96998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 970f62b8bb8SAmir Vadai goto err_disable_hca; 971f62b8bb8SAmir Vadai } 972f62b8bb8SAmir Vadai 973cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 974cd23b14bSEli Cohen if (err) { 97598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 976cd23b14bSEli Cohen goto err_disable_hca; 977cd23b14bSEli Cohen } 978cd23b14bSEli Cohen 979e126ba97SEli Cohen err = set_hca_ctrl(dev); 980e126ba97SEli Cohen if (err) { 98198a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 982cd23b14bSEli Cohen goto reclaim_boot_pages; 983e126ba97SEli Cohen } 984e126ba97SEli Cohen 98537b6bb77SLeon Romanovsky err = set_hca_cap(dev); 986e126ba97SEli Cohen if (err) { 98798a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 98846861e3eSMoni Shoua goto reclaim_boot_pages; 98946861e3eSMoni Shoua } 99046861e3eSMoni Shoua 991cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 992e126ba97SEli Cohen if (err) { 99398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 994cd23b14bSEli Cohen goto reclaim_boot_pages; 995e126ba97SEli Cohen } 996e126ba97SEli Cohen 9978737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 998e126ba97SEli Cohen if (err) { 99998a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10000cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1001e126ba97SEli Cohen } 1002e126ba97SEli Cohen 1003012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1004012e50e1SHuy Nguyen 1005e126ba97SEli Cohen mlx5_start_health_poll(dev); 1006e126ba97SEli Cohen 1007bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1008bba1574cSDaniel Jurgens if (err) { 100998a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1010e161105eSSaeed Mahameed goto stop_health; 1011bba1574cSDaniel Jurgens } 1012bba1574cSDaniel Jurgens 1013e161105eSSaeed Mahameed return 0; 1014e161105eSSaeed Mahameed 1015e161105eSSaeed Mahameed stop_health: 1016e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1017e161105eSSaeed Mahameed reclaim_boot_pages: 1018e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1019e161105eSSaeed Mahameed err_disable_hca: 1020e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1021e161105eSSaeed Mahameed err_cmd_cleanup: 1022f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1023e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1024e161105eSSaeed Mahameed 1025e161105eSSaeed Mahameed return err; 1026e161105eSSaeed Mahameed } 1027e161105eSSaeed Mahameed 1028e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1029e161105eSSaeed Mahameed { 1030e161105eSSaeed Mahameed int err; 1031e161105eSSaeed Mahameed 1032e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1033e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1034259bbc57SMaor Gottlieb if (err) { 103598a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1036e161105eSSaeed Mahameed return err; 1037e126ba97SEli Cohen } 1038e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1039e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1040f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1041e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1042e161105eSSaeed Mahameed 1043e161105eSSaeed Mahameed return 0; 1044259bbc57SMaor Gottlieb } 1045e126ba97SEli Cohen 1046a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1047e161105eSSaeed Mahameed { 1048e161105eSSaeed Mahameed int err; 1049e161105eSSaeed Mahameed 105001187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 105172f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 105298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 105372f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1054a80d1b68SSaeed Mahameed return err; 1055e126ba97SEli Cohen } 1056e126ba97SEli Cohen 105769c1280bSSaeed Mahameed mlx5_events_start(dev); 10580cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10590cf53c12SSaeed Mahameed 1060e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1061e1706e62SYuval Avnery if (err) { 1062e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1063e1706e62SYuval Avnery goto err_irq_table; 1064e1706e62SYuval Avnery } 1065e1706e62SYuval Avnery 1066c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1067e126ba97SEli Cohen if (err) { 106898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1069c8e21b3bSSaeed Mahameed goto err_eq_table; 1070e126ba97SEli Cohen } 1071e126ba97SEli Cohen 107224406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 107324406953SFeras Daoud if (err) { 107498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 107524406953SFeras Daoud goto err_fw_tracer; 107624406953SFeras Daoud } 107724406953SFeras Daoud 107887175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 107987175120SEran Ben Elisha 108012206b17SAya Levin err = mlx5_rsc_dump_init(dev); 108112206b17SAya Levin if (err) { 108212206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 108312206b17SAya Levin goto err_rsc_dump; 108412206b17SAya Levin } 108512206b17SAya Levin 108604e87170SMatan Barak err = mlx5_fpga_device_start(dev); 108704e87170SMatan Barak if (err) { 108898a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 108904e87170SMatan Barak goto err_fpga_start; 109004e87170SMatan Barak } 109104e87170SMatan Barak 109204e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 109304e87170SMatan Barak if (err) { 109498a8e6fcSHuy Nguyen mlx5_core_err(dev, "IPSec device start failed %d\n", err); 109504e87170SMatan Barak goto err_ipsec_start; 109604e87170SMatan Barak } 109704e87170SMatan Barak 10981ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 10991ae17322SIlya Lesokhin if (err) { 110098a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11011ae17322SIlya Lesokhin goto err_tls_start; 11021ae17322SIlya Lesokhin } 11031ae17322SIlya Lesokhin 110486d722adSMaor Gottlieb err = mlx5_init_fs(dev); 110586d722adSMaor Gottlieb if (err) { 110698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 110786d722adSMaor Gottlieb goto err_fs; 110886d722adSMaor Gottlieb } 11091466cc5bSYevgeny Petrilin 1110c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1111c85023e1SHuy Nguyen if (err) { 111298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 111387883929SSaeed Mahameed goto err_sriov; 1114c85023e1SHuy Nguyen } 1115c85023e1SHuy Nguyen 1116c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1117fc50db98SEli Cohen if (err) { 111898a8e6fcSHuy Nguyen mlx5_core_err(dev, "sriov init failed %d\n", err); 1119fc50db98SEli Cohen goto err_sriov; 1120fc50db98SEli Cohen } 1121fc50db98SEli Cohen 112222e939a9SBodong Wang err = mlx5_ec_init(dev); 112322e939a9SBodong Wang if (err) { 112498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 112522e939a9SBodong Wang goto err_ec; 112622e939a9SBodong Wang } 112722e939a9SBodong Wang 1128a80d1b68SSaeed Mahameed return 0; 1129a80d1b68SSaeed Mahameed 1130a80d1b68SSaeed Mahameed err_ec: 1131a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1132a80d1b68SSaeed Mahameed err_sriov: 1133a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1134a80d1b68SSaeed Mahameed err_fs: 1135a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1136a80d1b68SSaeed Mahameed err_tls_start: 1137a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1138a80d1b68SSaeed Mahameed err_ipsec_start: 1139a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1140a80d1b68SSaeed Mahameed err_fpga_start: 114112206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 114212206b17SAya Levin err_rsc_dump: 114387175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1144a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1145a80d1b68SSaeed Mahameed err_fw_tracer: 1146a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1147a80d1b68SSaeed Mahameed err_eq_table: 1148e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1149e1706e62SYuval Avnery err_irq_table: 1150a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1151a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1152a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1153a80d1b68SSaeed Mahameed return err; 1154a80d1b68SSaeed Mahameed } 1155a80d1b68SSaeed Mahameed 1156a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1157a80d1b68SSaeed Mahameed { 1158a80d1b68SSaeed Mahameed mlx5_ec_cleanup(dev); 1159a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1160a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1161a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1162a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1163a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 116412206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 116587175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1166a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1167a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1168e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1169a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1170a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1171a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1172a80d1b68SSaeed Mahameed } 1173a80d1b68SSaeed Mahameed 11744383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1175a80d1b68SSaeed Mahameed { 1176a80d1b68SSaeed Mahameed int err = 0; 1177a80d1b68SSaeed Mahameed 1178a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1179a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1180a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1181a80d1b68SSaeed Mahameed goto out; 1182a80d1b68SSaeed Mahameed } 1183a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1184a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1185a80d1b68SSaeed Mahameed 1186a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1187a80d1b68SSaeed Mahameed if (err) 11884f7400d5SShay Drory goto err_function; 1189a80d1b68SSaeed Mahameed 1190a80d1b68SSaeed Mahameed if (boot) { 1191a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1192a80d1b68SSaeed Mahameed if (err) { 119398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1194a80d1b68SSaeed Mahameed goto function_teardown; 1195a80d1b68SSaeed Mahameed } 1196a80d1b68SSaeed Mahameed } 1197a80d1b68SSaeed Mahameed 1198a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1199a80d1b68SSaeed Mahameed if (err) 1200a80d1b68SSaeed Mahameed goto err_load; 1201a80d1b68SSaeed Mahameed 120298f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 120398f91c45SParav Pandit 1204a6f3b623SMichael Guralnik if (boot) { 1205a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1206a6f3b623SMichael Guralnik if (err) 1207a6f3b623SMichael Guralnik goto err_devlink_reg; 1208ecd01db8SParav Pandit mlx5_register_device(dev); 120998f91c45SParav Pandit } else { 121098f91c45SParav Pandit mlx5_attach_device(dev); 121198f91c45SParav Pandit } 121289d44f0aSMajd Dibbiny 12134162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 12144162f58bSParav Pandit return 0; 1215e126ba97SEli Cohen 1216a6f3b623SMichael Guralnik err_devlink_reg: 121798f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1218a80d1b68SSaeed Mahameed mlx5_unload(dev); 1219a80d1b68SSaeed Mahameed err_load: 122059211bd3SMohamad Haj Yahia if (boot) 122159211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1222e161105eSSaeed Mahameed function_teardown: 1223e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 12244f7400d5SShay Drory err_function: 122589d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 12264162f58bSParav Pandit out: 122789d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1228e126ba97SEli Cohen return err; 1229e126ba97SEli Cohen } 1230e126ba97SEli Cohen 1231f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1232e126ba97SEli Cohen { 123389d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 123498f91c45SParav Pandit 123598f91c45SParav Pandit if (cleanup) { 123698f91c45SParav Pandit mlx5_unregister_device(dev); 123798f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 123898f91c45SParav Pandit } else { 123998f91c45SParav Pandit mlx5_detach_device(dev); 124098f91c45SParav Pandit } 124198f91c45SParav Pandit 1242b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 124398a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 124489d44f0aSMajd Dibbiny __func__); 124559211bd3SMohamad Haj Yahia if (cleanup) 124659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 124789d44f0aSMajd Dibbiny goto out; 124889d44f0aSMajd Dibbiny } 12496b6adee3SMohamad Haj Yahia 12509ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12519ade8c7cSIlan Tayari 1252a80d1b68SSaeed Mahameed mlx5_unload(dev); 1253a80d1b68SSaeed Mahameed 125459211bd3SMohamad Haj Yahia if (cleanup) 125559211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12560cf53c12SSaeed Mahameed 1257e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1258ac6ea6e8SEli Cohen out: 125989d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 12609603b61dSJack Morgenstein } 126164613d94SSaeed Mahameed 126227b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12639603b61dSJack Morgenstein { 126411f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12659603b61dSJack Morgenstein int err; 12669603b61dSJack Morgenstein 126711f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12689603b61dSJack Morgenstein 1269364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1270364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 127189d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1272d9aaed83SArtemy Kovalyov 127301187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 127401187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 127501187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 127601187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 127701187175SEli Cohen 127811f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 127911f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 128011f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 128111f3b84dSSaeed Mahameed 128227b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 128327b942fbSParav Pandit mlx5_debugfs_root); 128411f3b84dSSaeed Mahameed if (!priv->dbg_root) { 128527b942fbSParav Pandit dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 1286810cbb25SParav Pandit goto err_dbg_root; 12879603b61dSJack Morgenstein } 12889603b61dSJack Morgenstein 1289ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 129052c368dcSSaeed Mahameed if (err) 129152c368dcSSaeed Mahameed goto err_health_init; 1292ac6ea6e8SEli Cohen 12930cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 12940cf53c12SSaeed Mahameed if (err) 12950cf53c12SSaeed Mahameed goto err_pagealloc_init; 129659211bd3SMohamad Haj Yahia 129711f3b84dSSaeed Mahameed return 0; 129852c368dcSSaeed Mahameed 129952c368dcSSaeed Mahameed err_pagealloc_init: 130052c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 130152c368dcSSaeed Mahameed err_health_init: 130252c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1303810cbb25SParav Pandit err_dbg_root: 1304810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1305810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1306810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1307810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1308810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 130952c368dcSSaeed Mahameed return err; 131011f3b84dSSaeed Mahameed } 131111f3b84dSSaeed Mahameed 131211f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 131311f3b84dSSaeed Mahameed { 1314810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1315810cbb25SParav Pandit 131652c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 131752c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 131811f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1319810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1320810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1321810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1322810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1323810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 132411f3b84dSSaeed Mahameed } 132511f3b84dSSaeed Mahameed 132611f3b84dSSaeed Mahameed #define MLX5_IB_MOD "mlx5_ib" 132711f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 132811f3b84dSSaeed Mahameed { 132911f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 133011f3b84dSSaeed Mahameed struct devlink *devlink; 133111f3b84dSSaeed Mahameed int err; 133211f3b84dSSaeed Mahameed 13331f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 133411f3b84dSSaeed Mahameed if (!devlink) { 13351f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 133611f3b84dSSaeed Mahameed return -ENOMEM; 133711f3b84dSSaeed Mahameed } 133811f3b84dSSaeed Mahameed 133911f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 134027b942fbSParav Pandit dev->device = &pdev->dev; 134127b942fbSParav Pandit dev->pdev = pdev; 134211f3b84dSSaeed Mahameed 1343386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1344386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1345386e75afSHuy Nguyen 134627b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 134711f3b84dSSaeed Mahameed if (err) 134811f3b84dSSaeed Mahameed goto mdev_init_err; 134911f3b84dSSaeed Mahameed 135011f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 13519603b61dSJack Morgenstein if (err) { 135298a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 135398a8e6fcSHuy Nguyen err); 135411f3b84dSSaeed Mahameed goto pci_init_err; 13559603b61dSJack Morgenstein } 13569603b61dSJack Morgenstein 1357868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13589603b61dSJack Morgenstein if (err) { 135998a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 136098a8e6fcSHuy Nguyen err); 13610cf53c12SSaeed Mahameed goto err_load_one; 13629603b61dSJack Morgenstein } 136359211bd3SMohamad Haj Yahia 1364f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 13659603b61dSJack Morgenstein 13668b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13678b9d8baaSAlex Vesker if (err) 13688b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13698b9d8baaSAlex Vesker 13705d47f6c8SDaniel Jurgens pci_save_state(pdev); 137160904cd3SParav Pandit devlink_reload_enable(devlink); 13729603b61dSJack Morgenstein return 0; 13739603b61dSJack Morgenstein 13740cf53c12SSaeed Mahameed err_load_one: 1375868bc06bSSaeed Mahameed mlx5_pci_close(dev); 137611f3b84dSSaeed Mahameed pci_init_err: 137711f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 137811f3b84dSSaeed Mahameed mdev_init_err: 13791f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1380a31208b1SMajd Dibbiny 13819603b61dSJack Morgenstein return err; 13829603b61dSJack Morgenstein } 1383a31208b1SMajd Dibbiny 13849603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13859603b61dSJack Morgenstein { 13869603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1387feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 13889603b61dSJack Morgenstein 138960904cd3SParav Pandit devlink_reload_disable(devlink); 13908b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 139141798df9SParav Pandit mlx5_drain_health_wq(dev); 1392f999b706SParav Pandit mlx5_unload_one(dev, true); 1393868bc06bSSaeed Mahameed mlx5_pci_close(dev); 139411f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 13951f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 13969603b61dSJack Morgenstein } 13979603b61dSJack Morgenstein 139889d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 139989d44f0aSMajd Dibbiny pci_channel_state_t state) 140089d44f0aSMajd Dibbiny { 140189d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 140289d44f0aSMajd Dibbiny 140398a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 140404c0c1abSMohamad Haj Yahia 14058812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 14063e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1407868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 14085e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 140989d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 141005ac2c0bSMohamad Haj Yahia 141189d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 141289d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 141389d44f0aSMajd Dibbiny } 141489d44f0aSMajd Dibbiny 1415d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1416d57847dcSDaniel Jurgens * for the health counter to start counting. 141789d44f0aSMajd Dibbiny */ 1418d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 141989d44f0aSMajd Dibbiny { 142089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 142189d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 142289d44f0aSMajd Dibbiny const int niter = 100; 1423d57847dcSDaniel Jurgens u32 last_count = 0; 142489d44f0aSMajd Dibbiny u32 count; 142589d44f0aSMajd Dibbiny int i; 142689d44f0aSMajd Dibbiny 142789d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 142889d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 142989d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1430d57847dcSDaniel Jurgens if (last_count && last_count != count) { 143198a8e6fcSHuy Nguyen mlx5_core_info(dev, 143298a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 143398a8e6fcSHuy Nguyen count, i); 1434d57847dcSDaniel Jurgens return 0; 1435d57847dcSDaniel Jurgens } 1436d57847dcSDaniel Jurgens last_count = count; 143789d44f0aSMajd Dibbiny } 143889d44f0aSMajd Dibbiny msleep(50); 143989d44f0aSMajd Dibbiny } 144089d44f0aSMajd Dibbiny 1441d57847dcSDaniel Jurgens return -ETIMEDOUT; 144289d44f0aSMajd Dibbiny } 144389d44f0aSMajd Dibbiny 14441061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14451061c90fSMohamad Haj Yahia { 14461061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14471061c90fSMohamad Haj Yahia int err; 14481061c90fSMohamad Haj Yahia 144998a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14501061c90fSMohamad Haj Yahia 14511061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14521061c90fSMohamad Haj Yahia if (err) { 145398a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 145498a8e6fcSHuy Nguyen __func__, err); 14551061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14561061c90fSMohamad Haj Yahia } 14571061c90fSMohamad Haj Yahia 14581061c90fSMohamad Haj Yahia pci_set_master(pdev); 14591061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14605d47f6c8SDaniel Jurgens pci_save_state(pdev); 14611061c90fSMohamad Haj Yahia 14621061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 146398a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14641061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14651061c90fSMohamad Haj Yahia } 14661061c90fSMohamad Haj Yahia 14671061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 14681061c90fSMohamad Haj Yahia } 14691061c90fSMohamad Haj Yahia 147089d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 147189d44f0aSMajd Dibbiny { 147289d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 147389d44f0aSMajd Dibbiny int err; 147489d44f0aSMajd Dibbiny 147598a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 147689d44f0aSMajd Dibbiny 1477868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 147889d44f0aSMajd Dibbiny if (err) 147998a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 148098a8e6fcSHuy Nguyen __func__, err); 148189d44f0aSMajd Dibbiny else 148298a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 148389d44f0aSMajd Dibbiny } 148489d44f0aSMajd Dibbiny 148589d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 148689d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 148789d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 148889d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 148989d44f0aSMajd Dibbiny }; 149089d44f0aSMajd Dibbiny 14918812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 14928812c24dSMajd Dibbiny { 1493fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1494fcd29ad1SFeras Daoud int ret = 1; 14958812c24dSMajd Dibbiny 1496fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1497fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1498fcd29ad1SFeras Daoud 1499fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1500fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1501fcd29ad1SFeras Daoud 1502fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 15038812c24dSMajd Dibbiny return -EOPNOTSUPP; 15048812c24dSMajd Dibbiny 15058812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 15068812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 15078812c24dSMajd Dibbiny return -EAGAIN; 15088812c24dSMajd Dibbiny } 15098812c24dSMajd Dibbiny 1510d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1511d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1512d2aa060dSHuy Nguyen */ 1513d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 151476d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1515d2aa060dSHuy Nguyen 1516fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1517fcd29ad1SFeras Daoud if (!ret) 1518fcd29ad1SFeras Daoud goto succeed; 1519fcd29ad1SFeras Daoud 15208812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1521fcd29ad1SFeras Daoud if (!ret) 1522fcd29ad1SFeras Daoud goto succeed; 1523fcd29ad1SFeras Daoud 15248812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1525d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 15268812c24dSMajd Dibbiny return ret; 15278812c24dSMajd Dibbiny 1528fcd29ad1SFeras Daoud succeed: 15298812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 15308812c24dSMajd Dibbiny 15311ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 15321ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 15331ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 15341ef903bfSDaniel Jurgens * contexts. 15351ef903bfSDaniel Jurgens */ 15361ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 15371ef903bfSDaniel Jurgens 15388812c24dSMajd Dibbiny return 0; 15398812c24dSMajd Dibbiny } 15408812c24dSMajd Dibbiny 15415fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15425fc7197dSMajd Dibbiny { 15435fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15448812c24dSMajd Dibbiny int err; 15455fc7197dSMajd Dibbiny 154698a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15478812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15488812c24dSMajd Dibbiny if (err) 1549868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15505fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15515fc7197dSMajd Dibbiny } 15525fc7197dSMajd Dibbiny 15538fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 15548fc3e29bSMark Bloch { 15558fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15568fc3e29bSMark Bloch 15578fc3e29bSMark Bloch mlx5_unload_one(dev, false); 15588fc3e29bSMark Bloch 15598fc3e29bSMark Bloch return 0; 15608fc3e29bSMark Bloch } 15618fc3e29bSMark Bloch 15628fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 15638fc3e29bSMark Bloch { 15648fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15658fc3e29bSMark Bloch 15668fc3e29bSMark Bloch return mlx5_load_one(dev, false); 15678fc3e29bSMark Bloch } 15688fc3e29bSMark Bloch 15699603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1570bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1571fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1572bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1573fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1574bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1575fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 15767092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 157764dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1578d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1579d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1580d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1581d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 158285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 158385327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1584b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1585505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 15862e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 15872e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1588d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 15899603b61dSJack Morgenstein { 0, } 15909603b61dSJack Morgenstein }; 15919603b61dSJack Morgenstein 15929603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 15939603b61dSJack Morgenstein 159404c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 159504c0c1abSMohamad Haj Yahia { 1596b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1597b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 159804c0c1abSMohamad Haj Yahia } 159904c0c1abSMohamad Haj Yahia 160004c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 160104c0c1abSMohamad Haj Yahia { 160204c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 160304c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 160404c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 160504c0c1abSMohamad Haj Yahia } 160604c0c1abSMohamad Haj Yahia 16079603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 16089603b61dSJack Morgenstein .name = DRIVER_NAME, 16099603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 16109603b61dSJack Morgenstein .probe = init_one, 161189d44f0aSMajd Dibbiny .remove = remove_one, 16128fc3e29bSMark Bloch .suspend = mlx5_suspend, 16138fc3e29bSMark Bloch .resume = mlx5_resume, 16145fc7197dSMajd Dibbiny .shutdown = shutdown, 1615fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1616fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 16179603b61dSJack Morgenstein }; 1618e126ba97SEli Cohen 1619f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1620f663ad98SKamal Heib { 1621f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1622f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1623f663ad98SKamal Heib prof_sel, 1624f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1625f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1626f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1627f663ad98SKamal Heib } 1628f663ad98SKamal Heib } 1629f663ad98SKamal Heib 1630e126ba97SEli Cohen static int __init init(void) 1631e126ba97SEli Cohen { 1632e126ba97SEli Cohen int err; 1633e126ba97SEli Cohen 16348737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 16358737f818SDaniel Jurgens 1636f663ad98SKamal Heib mlx5_core_verify_params(); 1637c778dd31STariq Toukan mlx5_accel_ipsec_build_fs_cmds(); 1638e126ba97SEli Cohen mlx5_register_debugfs(); 1639e126ba97SEli Cohen 16409603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 16419603b61dSJack Morgenstein if (err) 1642ac6ea6e8SEli Cohen goto err_debug; 16439603b61dSJack Morgenstein 1644f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1645f62b8bb8SAmir Vadai mlx5e_init(); 1646f62b8bb8SAmir Vadai #endif 1647f62b8bb8SAmir Vadai 1648e126ba97SEli Cohen return 0; 1649e126ba97SEli Cohen 1650e126ba97SEli Cohen err_debug: 1651e126ba97SEli Cohen mlx5_unregister_debugfs(); 1652e126ba97SEli Cohen return err; 1653e126ba97SEli Cohen } 1654e126ba97SEli Cohen 1655e126ba97SEli Cohen static void __exit cleanup(void) 1656e126ba97SEli Cohen { 1657f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1658f62b8bb8SAmir Vadai mlx5e_cleanup(); 1659f62b8bb8SAmir Vadai #endif 16609603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1661e126ba97SEli Cohen mlx5_unregister_debugfs(); 1662e126ba97SEli Cohen } 1663e126ba97SEli Cohen 1664e126ba97SEli Cohen module_init(init); 1665e126ba97SEli Cohen module_exit(cleanup); 1666