1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40db058a18SSaeed Mahameed #include <linux/interrupt.h> 41e3297246SEli Cohen #include <linux/delay.h> 42e126ba97SEli Cohen #include <linux/mlx5/driver.h> 43e126ba97SEli Cohen #include <linux/mlx5/cq.h> 44e126ba97SEli Cohen #include <linux/mlx5/qp.h> 45e126ba97SEli Cohen #include <linux/debugfs.h> 46f66f049fSEli Cohen #include <linux/kmod.h> 47b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 48c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 495a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 505a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 515a7b27ebSMaor Gottlieb #endif 52907af0f0SLeon Romanovsky #include <linux/version.h> 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6038b9f903SMoshe Shemesh #include "fw_reset.h" 6152ec462eSIlan Tayari #include "lib/mlx5.h" 625945e1adSAmir Tzin #include "lib/tout.h" 63e29341fbSIlan Tayari #include "fpga/core.h" 64c6e3b421SLeon Romanovsky #include "en_accel/ipsec.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 7287175120SEran Ben Elisha #include "lib/hv_vhca.h" 7312206b17SAya Levin #include "diag/rsc_dump.h" 74f3196bb0SParav Pandit #include "sf/vhca_event.h" 7590d010b8SParav Pandit #include "sf/dev/dev.h" 766a327321SParav Pandit #include "sf/sf.h" 773b43190bSShay Drory #include "mlx5_irq.h" 78e126ba97SEli Cohen 79e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 80048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 81e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 82e126ba97SEli Cohen 83f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 84f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 85e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 86e126ba97SEli Cohen 87f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 88f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 899603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 909603b61dSJack Morgenstein 918737f818SDaniel Jurgens static u32 sw_owner_id[4]; 92dc402cccSYishai Hadas #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 93dc402cccSYishai Hadas static DEFINE_IDA(sw_vhca_ida); 948737f818SDaniel Jurgens 95f91e6d89SEran Ben Elisha enum { 96f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 97f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 98f91e6d89SEran Ben Elisha }; 99f91e6d89SEran Ben Elisha 100f79a609eSMaher Sanalla #define LOG_MAX_SUPPORTED_QPS 0xff 101f79a609eSMaher Sanalla 1029603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1039603b61dSJack Morgenstein [0] = { 1049603b61dSJack Morgenstein .mask = 0, 1059603b61dSJack Morgenstein }, 1069603b61dSJack Morgenstein [1] = { 1079603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1089603b61dSJack Morgenstein .log_max_qp = 12, 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein [2] = { 1119603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1129603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 113f79a609eSMaher Sanalla .log_max_qp = LOG_MAX_SUPPORTED_QPS, 1149603b61dSJack Morgenstein .mr_cache[0] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[1] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[2] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[3] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[4] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[5] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[6] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[7] = { 1439603b61dSJack Morgenstein .size = 500, 1449603b61dSJack Morgenstein .limit = 250 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[8] = { 1479603b61dSJack Morgenstein .size = 500, 1489603b61dSJack Morgenstein .limit = 250 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[9] = { 1519603b61dSJack Morgenstein .size = 500, 1529603b61dSJack Morgenstein .limit = 250 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[10] = { 1559603b61dSJack Morgenstein .size = 500, 1569603b61dSJack Morgenstein .limit = 250 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein .mr_cache[11] = { 1599603b61dSJack Morgenstein .size = 500, 1609603b61dSJack Morgenstein .limit = 250 1619603b61dSJack Morgenstein }, 1629603b61dSJack Morgenstein .mr_cache[12] = { 1639603b61dSJack Morgenstein .size = 64, 1649603b61dSJack Morgenstein .limit = 32 1659603b61dSJack Morgenstein }, 1669603b61dSJack Morgenstein .mr_cache[13] = { 1679603b61dSJack Morgenstein .size = 32, 1689603b61dSJack Morgenstein .limit = 16 1699603b61dSJack Morgenstein }, 1709603b61dSJack Morgenstein .mr_cache[14] = { 1719603b61dSJack Morgenstein .size = 16, 1729603b61dSJack Morgenstein .limit = 8 1739603b61dSJack Morgenstein }, 1749603b61dSJack Morgenstein .mr_cache[15] = { 1759603b61dSJack Morgenstein .size = 8, 1769603b61dSJack Morgenstein .limit = 4 1779603b61dSJack Morgenstein }, 1789603b61dSJack Morgenstein }, 1799603b61dSJack Morgenstein }; 180e126ba97SEli Cohen 181b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 182b8a92577SDaniel Jurgens u32 warn_time_mili) 183e3297246SEli Cohen { 184b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 185e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 186cdfc6ffbSShay Drory u32 fw_initializing; 187e3297246SEli Cohen int err = 0; 188e3297246SEli Cohen 189cdfc6ffbSShay Drory do { 190cdfc6ffbSShay Drory fw_initializing = ioread32be(&dev->iseg->initializing); 191cdfc6ffbSShay Drory if (!(fw_initializing >> 31)) 192cdfc6ffbSShay Drory break; 1938324a02cSGavin Li if (time_after(jiffies, end) || 1948324a02cSGavin Li test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 195e3297246SEli Cohen err = -EBUSY; 196e3297246SEli Cohen break; 197e3297246SEli Cohen } 198b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 199cdfc6ffbSShay Drory mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", 200cdfc6ffbSShay Drory jiffies_to_msecs(end - warn) / 1000, fw_initializing); 201b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 202b8a92577SDaniel Jurgens } 2035945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 204cdfc6ffbSShay Drory } while (true); 205e3297246SEli Cohen 206e3297246SEli Cohen return err; 207e3297246SEli Cohen } 208e3297246SEli Cohen 209012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 210012e50e1SHuy Nguyen { 211012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 212012e50e1SHuy Nguyen driver_version); 2133ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 214012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 215012e50e1SHuy Nguyen char *string; 216012e50e1SHuy Nguyen 217012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 218012e50e1SHuy Nguyen return; 219012e50e1SHuy Nguyen 220012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 221012e50e1SHuy Nguyen 222012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 225012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 226012e50e1SHuy Nguyen 227012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 22817a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 229012e50e1SHuy Nguyen 230012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 231012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 232012e50e1SHuy Nguyen 233012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 234907af0f0SLeon Romanovsky 235907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 23688a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 23788a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 238012e50e1SHuy Nguyen 239012e50e1SHuy Nguyen /*Send the command*/ 240012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 241012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 242012e50e1SHuy Nguyen 2433ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 244012e50e1SHuy Nguyen } 245012e50e1SHuy Nguyen 246e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 247e126ba97SEli Cohen { 248e126ba97SEli Cohen int err; 249e126ba97SEli Cohen 250eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 251e126ba97SEli Cohen if (err) { 2521a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 253eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 254e126ba97SEli Cohen if (err) { 2551a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 256e126ba97SEli Cohen return err; 257e126ba97SEli Cohen } 258e126ba97SEli Cohen } 259e126ba97SEli Cohen 260e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 261e126ba97SEli Cohen return err; 262e126ba97SEli Cohen } 263e126ba97SEli Cohen 26489d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 26589d44f0aSMajd Dibbiny { 26689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 26789d44f0aSMajd Dibbiny int err = 0; 26889d44f0aSMajd Dibbiny 26989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27189d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27289d44f0aSMajd Dibbiny if (!err) 27389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27489d44f0aSMajd Dibbiny } 27589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 27689d44f0aSMajd Dibbiny 27789d44f0aSMajd Dibbiny return err; 27889d44f0aSMajd Dibbiny } 27989d44f0aSMajd Dibbiny 28089d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28189d44f0aSMajd Dibbiny { 28289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28389d44f0aSMajd Dibbiny 28489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 28689d44f0aSMajd Dibbiny pci_disable_device(pdev); 28789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 28889d44f0aSMajd Dibbiny } 28989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29089d44f0aSMajd Dibbiny } 29189d44f0aSMajd Dibbiny 292e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 293e126ba97SEli Cohen { 294e126ba97SEli Cohen int err = 0; 295e126ba97SEli Cohen 296e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2971a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 298e126ba97SEli Cohen return -ENODEV; 299e126ba97SEli Cohen } 300e126ba97SEli Cohen 30117a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 302e126ba97SEli Cohen if (err) 303e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 304e126ba97SEli Cohen 305e126ba97SEli Cohen return err; 306e126ba97SEli Cohen } 307e126ba97SEli Cohen 308e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 309e126ba97SEli Cohen { 310e126ba97SEli Cohen pci_release_regions(pdev); 311e126ba97SEli Cohen } 312e126ba97SEli Cohen 313bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 314e126ba97SEli Cohen u8 he; 315e126ba97SEli Cohen u8 rsvd[15]; 316e126ba97SEli Cohen }; 317e126ba97SEli Cohen 3182974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 319c7a08ac7SEli Cohen { 320c7a08ac7SEli Cohen switch (size) { 321c7a08ac7SEli Cohen case 128: 322c7a08ac7SEli Cohen return 0; 323c7a08ac7SEli Cohen case 256: 324c7a08ac7SEli Cohen return 1; 325c7a08ac7SEli Cohen case 512: 326c7a08ac7SEli Cohen return 2; 327c7a08ac7SEli Cohen case 1024: 328c7a08ac7SEli Cohen return 3; 329c7a08ac7SEli Cohen case 2048: 330c7a08ac7SEli Cohen return 4; 331c7a08ac7SEli Cohen case 4096: 332c7a08ac7SEli Cohen return 5; 333c7a08ac7SEli Cohen default: 3342974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 335c7a08ac7SEli Cohen return 0; 336c7a08ac7SEli Cohen } 337c7a08ac7SEli Cohen } 338c7a08ac7SEli Cohen 339b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 340b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 341938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 342c7a08ac7SEli Cohen { 343b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 344b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 345938fe83cSSaeed Mahameed void *out, *hca_caps; 346938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 347c7a08ac7SEli Cohen int err; 348c7a08ac7SEli Cohen 349b775516bSEli Cohen memset(in, 0, sizeof(in)); 350b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 351c7a08ac7SEli Cohen if (!out) 352c7a08ac7SEli Cohen return -ENOMEM; 353938fe83cSSaeed Mahameed 354b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 355b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3563ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 357c7a08ac7SEli Cohen if (err) { 358938fe83cSSaeed Mahameed mlx5_core_warn(dev, 359938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 360938fe83cSSaeed Mahameed cap_type, cap_mode, err); 361c7a08ac7SEli Cohen goto query_ex; 362c7a08ac7SEli Cohen } 363c7a08ac7SEli Cohen 364938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 365938fe83cSSaeed Mahameed 366938fe83cSSaeed Mahameed switch (cap_mode) { 367938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 36848f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 369938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 370938fe83cSSaeed Mahameed break; 371938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 37248f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 373938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 374938fe83cSSaeed Mahameed break; 375938fe83cSSaeed Mahameed default: 376938fe83cSSaeed Mahameed mlx5_core_warn(dev, 377938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 378938fe83cSSaeed Mahameed cap_type, cap_mode); 379938fe83cSSaeed Mahameed err = -EINVAL; 380938fe83cSSaeed Mahameed break; 381938fe83cSSaeed Mahameed } 382c7a08ac7SEli Cohen query_ex: 383c7a08ac7SEli Cohen kfree(out); 384c7a08ac7SEli Cohen return err; 385c7a08ac7SEli Cohen } 386c7a08ac7SEli Cohen 387b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 388b06e7de8SLeon Romanovsky { 389b06e7de8SLeon Romanovsky int ret; 390b06e7de8SLeon Romanovsky 391b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 392b06e7de8SLeon Romanovsky if (ret) 393b06e7de8SLeon Romanovsky return ret; 394b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 395b06e7de8SLeon Romanovsky } 396b06e7de8SLeon Romanovsky 397a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 398c7a08ac7SEli Cohen { 399b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 400f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4013ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 402c7a08ac7SEli Cohen } 40387b8de49SEli Cohen 404a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 405f91e6d89SEran Ben Elisha { 406f91e6d89SEran Ben Elisha void *set_hca_cap; 407f91e6d89SEran Ben Elisha int req_endianness; 408f91e6d89SEran Ben Elisha int err; 409f91e6d89SEran Ben Elisha 410a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 411a2a322f4SLeon Romanovsky return 0; 412a2a322f4SLeon Romanovsky 413b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 414f91e6d89SEran Ben Elisha if (err) 415f91e6d89SEran Ben Elisha return err; 416f91e6d89SEran Ben Elisha 417f91e6d89SEran Ben Elisha req_endianness = 418f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 419bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 420f91e6d89SEran Ben Elisha 421f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 422f91e6d89SEran Ben Elisha return 0; 423f91e6d89SEran Ben Elisha 424f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 425f91e6d89SEran Ben Elisha 426f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 427bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 428f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 429f91e6d89SEran Ben Elisha 430a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 431f91e6d89SEran Ben Elisha } 432f91e6d89SEran Ben Elisha 433a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 43446861e3eSMoni Shoua { 43546861e3eSMoni Shoua void *set_hca_cap; 436fca22e7eSMoni Shoua bool do_set = false; 43746861e3eSMoni Shoua int err; 43846861e3eSMoni Shoua 43937b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 44037b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 44146861e3eSMoni Shoua return 0; 44246861e3eSMoni Shoua 44346861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 44446861e3eSMoni Shoua if (err) 44546861e3eSMoni Shoua return err; 44646861e3eSMoni Shoua 44746861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 44848f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 44946861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 45046861e3eSMoni Shoua 451fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 452fca22e7eSMoni Shoua do { \ 453fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 454fca22e7eSMoni Shoua if (_res) { \ 455fca22e7eSMoni Shoua do_set = true; \ 456fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 457fca22e7eSMoni Shoua } \ 458fca22e7eSMoni Shoua } while (0) 45946861e3eSMoni Shoua 460fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 461fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 462fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 463fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 464fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 465fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 466fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 467fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 46800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 46900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 47000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 47100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 47200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 47300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 47446861e3eSMoni Shoua 475a2a322f4SLeon Romanovsky if (!do_set) 476a2a322f4SLeon Romanovsky return 0; 47746861e3eSMoni Shoua 478a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 47946861e3eSMoni Shoua } 48046861e3eSMoni Shoua 4818680a60fSShay Drory static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 4828680a60fSShay Drory { 4838680a60fSShay Drory struct devlink *devlink = priv_to_devlink(dev); 4848680a60fSShay Drory union devlink_param_value val; 4858680a60fSShay Drory int err; 4868680a60fSShay Drory 4878680a60fSShay Drory err = devlink_param_driverinit_value_get(devlink, 4888680a60fSShay Drory DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 4898680a60fSShay Drory &val); 4908680a60fSShay Drory if (!err) 4918680a60fSShay Drory return val.vu32; 4928680a60fSShay Drory mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 4938680a60fSShay Drory return err; 4948680a60fSShay Drory } 4958680a60fSShay Drory 4969ca05b0fSMaher Sanalla bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 4979ca05b0fSMaher Sanalla { 4989ca05b0fSMaher Sanalla struct devlink *devlink = priv_to_devlink(dev); 4999ca05b0fSMaher Sanalla union devlink_param_value val; 5009ca05b0fSMaher Sanalla int err; 5019ca05b0fSMaher Sanalla 5029ca05b0fSMaher Sanalla err = devlink_param_driverinit_value_get(devlink, 5039ca05b0fSMaher Sanalla DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 5049ca05b0fSMaher Sanalla &val); 5059ca05b0fSMaher Sanalla 5069ca05b0fSMaher Sanalla if (!err) 5079ca05b0fSMaher Sanalla return val.vbool; 5089ca05b0fSMaher Sanalla 5099ca05b0fSMaher Sanalla mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5109ca05b0fSMaher Sanalla return MLX5_CAP_GEN(dev, roce); 5119ca05b0fSMaher Sanalla } 5129ca05b0fSMaher Sanalla EXPORT_SYMBOL(mlx5_is_roce_on); 5139ca05b0fSMaher Sanalla 514dc402cccSYishai Hadas static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 515dc402cccSYishai Hadas { 516dc402cccSYishai Hadas void *set_hca_cap; 517dc402cccSYishai Hadas int err; 518dc402cccSYishai Hadas 519dc402cccSYishai Hadas if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 520dc402cccSYishai Hadas return 0; 521dc402cccSYishai Hadas 522dc402cccSYishai Hadas err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 523dc402cccSYishai Hadas if (err) 524dc402cccSYishai Hadas return err; 525dc402cccSYishai Hadas 526dc402cccSYishai Hadas if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 527dc402cccSYishai Hadas !(dev->priv.sw_vhca_id > 0)) 528dc402cccSYishai Hadas return 0; 529dc402cccSYishai Hadas 530dc402cccSYishai Hadas set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 531dc402cccSYishai Hadas capability); 532dc402cccSYishai Hadas memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 533dc402cccSYishai Hadas MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 534dc402cccSYishai Hadas MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 535dc402cccSYishai Hadas 536dc402cccSYishai Hadas return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 537dc402cccSYishai Hadas } 538dc402cccSYishai Hadas 539a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 540e126ba97SEli Cohen { 5413410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 542938fe83cSSaeed Mahameed void *set_hca_cap; 5438680a60fSShay Drory int max_uc_list; 544a2a322f4SLeon Romanovsky int err; 545e126ba97SEli Cohen 546b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 547c7a08ac7SEli Cohen if (err) 548a2a322f4SLeon Romanovsky return err; 549e126ba97SEli Cohen 550938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 551938fe83cSSaeed Mahameed capability); 55248f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 553938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 554938fe83cSSaeed Mahameed 555938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 556707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 557938fe83cSSaeed Mahameed 128); 558c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 559938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5602974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 561e126ba97SEli Cohen 562883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 563f79a609eSMaher Sanalla if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 564a6e9085dSMaher Sanalla prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 565f79a609eSMaher Sanalla } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 566883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5673410fbcdSMaor Gottlieb prof->log_max_qp, 568883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5693410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 570883371c4SNoa Osherovich } 571c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 572938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 573938fe83cSSaeed Mahameed prof->log_max_qp); 574e126ba97SEli Cohen 575938fe83cSSaeed Mahameed /* disable cmdif checksum */ 576938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 577c1868b82SEli Cohen 57891828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 57991828bd8SMajd Dibbiny * than 4K. 58091828bd8SMajd Dibbiny */ 58191828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 582f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 583f502d834SEli Cohen 584fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 585fe1e1876SCarol L Soto 586f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 587f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 588f32f5bd2SDaniel Jurgens set_hca_cap, 589f32f5bd2SDaniel Jurgens cache_line_128byte, 590c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 591f32f5bd2SDaniel Jurgens 592dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 593dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 594dd44572aSMoni Shoua 595e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 596e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 597e7f4d0bcSMoshe Shemesh 598c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 599c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 600c4b76d8dSDaniel Jurgens set_hca_cap, 601c4b76d8dSDaniel Jurgens num_vhca_ports, 602c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 603c4b76d8dSDaniel Jurgens 604c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 605c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 606c6168161SEran Ben Elisha 6074dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 6084dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 6094dca6509SMichael Guralnik 610f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 611f3196bb0SParav Pandit 612604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 613604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 614604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 615604774adSLeon Romanovsky 616c4ad5f2bSShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 6179ca05b0fSMaher Sanalla MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 6189ca05b0fSMaher Sanalla mlx5_is_roce_on(dev)); 619fbfa97b4SShay Drory 6208680a60fSShay Drory max_uc_list = max_uc_list_get_devlink_param(dev); 6218680a60fSShay Drory if (max_uc_list > 0) 6228680a60fSShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 6238680a60fSShay Drory ilog2(max_uc_list)); 6248680a60fSShay Drory 625a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 626e126ba97SEli Cohen } 627cd23b14bSEli Cohen 628fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 629fbfa97b4SShay Drory * boot process. 630fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 631fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 632fbfa97b4SShay Drory * Hence, the need for this function. 633fbfa97b4SShay Drory * 634fbfa97b4SShay Drory * Returns 635fbfa97b4SShay Drory * True: 636fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 637fbfa97b4SShay Drory * OR: 638fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 639fbfa97b4SShay Drory * 640fbfa97b4SShay Drory * In any other case, return False. 641fbfa97b4SShay Drory */ 642fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 643fbfa97b4SShay Drory { 6449ca05b0fSMaher Sanalla return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 645fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 646fbfa97b4SShay Drory } 647fbfa97b4SShay Drory 64859e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 64959e9e8e4SMark Zhang { 65059e9e8e4SMark Zhang void *set_hca_cap; 65159e9e8e4SMark Zhang int err; 65259e9e8e4SMark Zhang 653fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 65459e9e8e4SMark Zhang return 0; 65559e9e8e4SMark Zhang 65659e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 65759e9e8e4SMark Zhang if (err) 65859e9e8e4SMark Zhang return err; 65959e9e8e4SMark Zhang 66059e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 66159e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 66259e9e8e4SMark Zhang return 0; 66359e9e8e4SMark Zhang 66459e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 66548f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 66659e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 66759e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 66859e9e8e4SMark Zhang 66959e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 670e126ba97SEli Cohen return err; 671e126ba97SEli Cohen } 672e126ba97SEli Cohen 67390b1df74SLiu, Changcheng static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 67490b1df74SLiu, Changcheng void *set_ctx) 67590b1df74SLiu, Changcheng { 67690b1df74SLiu, Changcheng void *set_hca_cap; 67790b1df74SLiu, Changcheng int err; 67890b1df74SLiu, Changcheng 67990b1df74SLiu, Changcheng if (!MLX5_CAP_GEN(dev, port_selection_cap)) 68090b1df74SLiu, Changcheng return 0; 68190b1df74SLiu, Changcheng 68290b1df74SLiu, Changcheng err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 68390b1df74SLiu, Changcheng if (err) 68490b1df74SLiu, Changcheng return err; 68590b1df74SLiu, Changcheng 68690b1df74SLiu, Changcheng if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 68790b1df74SLiu, Changcheng !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 68890b1df74SLiu, Changcheng return 0; 68990b1df74SLiu, Changcheng 69090b1df74SLiu, Changcheng set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 69190b1df74SLiu, Changcheng memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 69290b1df74SLiu, Changcheng MLX5_ST_SZ_BYTES(port_selection_cap)); 69390b1df74SLiu, Changcheng MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 69490b1df74SLiu, Changcheng 69590b1df74SLiu, Changcheng err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION); 69690b1df74SLiu, Changcheng 69790b1df74SLiu, Changcheng return err; 69890b1df74SLiu, Changcheng } 69990b1df74SLiu, Changcheng 70037b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 70137b6bb77SLeon Romanovsky { 702a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 703a2a322f4SLeon Romanovsky void *set_ctx; 70437b6bb77SLeon Romanovsky int err; 70537b6bb77SLeon Romanovsky 706a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 707a2a322f4SLeon Romanovsky if (!set_ctx) 708a2a322f4SLeon Romanovsky return -ENOMEM; 709a2a322f4SLeon Romanovsky 710a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 71137b6bb77SLeon Romanovsky if (err) { 71298a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 71337b6bb77SLeon Romanovsky goto out; 71437b6bb77SLeon Romanovsky } 71537b6bb77SLeon Romanovsky 716a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 717a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 71837b6bb77SLeon Romanovsky if (err) { 71998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 72037b6bb77SLeon Romanovsky goto out; 72137b6bb77SLeon Romanovsky } 72237b6bb77SLeon Romanovsky 723a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 724a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 72537b6bb77SLeon Romanovsky if (err) { 72698a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 72737b6bb77SLeon Romanovsky goto out; 72837b6bb77SLeon Romanovsky } 72937b6bb77SLeon Romanovsky 73059e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 73159e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 73259e9e8e4SMark Zhang if (err) { 73359e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 73459e9e8e4SMark Zhang goto out; 73559e9e8e4SMark Zhang } 73659e9e8e4SMark Zhang 737dc402cccSYishai Hadas memset(set_ctx, 0, set_sz); 738dc402cccSYishai Hadas err = handle_hca_cap_2(dev, set_ctx); 739dc402cccSYishai Hadas if (err) { 740dc402cccSYishai Hadas mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 741dc402cccSYishai Hadas goto out; 742dc402cccSYishai Hadas } 743dc402cccSYishai Hadas 74490b1df74SLiu, Changcheng memset(set_ctx, 0, set_sz); 74590b1df74SLiu, Changcheng err = handle_hca_cap_port_selection(dev, set_ctx); 74690b1df74SLiu, Changcheng if (err) { 74790b1df74SLiu, Changcheng mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 74890b1df74SLiu, Changcheng goto out; 74990b1df74SLiu, Changcheng } 75090b1df74SLiu, Changcheng 75137b6bb77SLeon Romanovsky out: 752a2a322f4SLeon Romanovsky kfree(set_ctx); 75337b6bb77SLeon Romanovsky return err; 75437b6bb77SLeon Romanovsky } 75537b6bb77SLeon Romanovsky 756e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 757e126ba97SEli Cohen { 758bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 759bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 760e126ba97SEli Cohen int err; 761e126ba97SEli Cohen 762fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 763fc50db98SEli Cohen return 0; 764fc50db98SEli Cohen 765e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 766e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 767e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 768e126ba97SEli Cohen &he_out, sizeof(he_out), 769e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 770e126ba97SEli Cohen return err; 771e126ba97SEli Cohen } 772e126ba97SEli Cohen 773c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 774c85023e1SHuy Nguyen { 775c85023e1SHuy Nguyen int ret = 0; 776c85023e1SHuy Nguyen 777c85023e1SHuy Nguyen /* Disable local_lb by default */ 7788978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 779c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 780c85023e1SHuy Nguyen 781c85023e1SHuy Nguyen return ret; 782c85023e1SHuy Nguyen } 783c85023e1SHuy Nguyen 7840b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 785e126ba97SEli Cohen { 7863ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 787e126ba97SEli Cohen 7880b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 7890b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 79022e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 79122e939a9SBodong Wang dev->caps.embedded_cpu); 7923ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 793e126ba97SEli Cohen } 794e126ba97SEli Cohen 7950b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 796e126ba97SEli Cohen { 7973ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 798e126ba97SEli Cohen 7990b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 8000b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 80122e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 80222e939a9SBodong Wang dev->caps.embedded_cpu); 8033ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 804e126ba97SEli Cohen } 805e126ba97SEli Cohen 806f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 807f62b8bb8SAmir Vadai { 8083ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 8093ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 810f62b8bb8SAmir Vadai u32 sup_issi; 811c4f287c4SSaeed Mahameed int err; 812f62b8bb8SAmir Vadai 813f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 8143ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 815f62b8bb8SAmir Vadai if (err) { 816605bef00SSaeed Mahameed u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 817605bef00SSaeed Mahameed u8 status = MLX5_GET(query_issi_out, query_out, status); 818c4f287c4SSaeed Mahameed 819f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 820f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 821f9c14e46SKamal Heib err, status, syndrome); 822f9c14e46SKamal Heib return err; 823f62b8bb8SAmir Vadai } 824f62b8bb8SAmir Vadai 825f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 826f9c14e46SKamal Heib dev->issi = 0; 827f9c14e46SKamal Heib return 0; 828f62b8bb8SAmir Vadai } 829f62b8bb8SAmir Vadai 830f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 831f62b8bb8SAmir Vadai 832f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 8333ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 834f62b8bb8SAmir Vadai 835f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 836f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 8373ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 838f62b8bb8SAmir Vadai if (err) { 839f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 840f9c14e46SKamal Heib err); 841f62b8bb8SAmir Vadai return err; 842f62b8bb8SAmir Vadai } 843f62b8bb8SAmir Vadai 844f62b8bb8SAmir Vadai dev->issi = 1; 845f62b8bb8SAmir Vadai 846f62b8bb8SAmir Vadai return 0; 847e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 848f62b8bb8SAmir Vadai return 0; 849f62b8bb8SAmir Vadai } 850f62b8bb8SAmir Vadai 8519eb78923SOr Gerlitz return -EOPNOTSUPP; 852f62b8bb8SAmir Vadai } 853f62b8bb8SAmir Vadai 85411f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 85511f3b84dSSaeed Mahameed const struct pci_device_id *id) 856a31208b1SMajd Dibbiny { 857a31208b1SMajd Dibbiny int err = 0; 858a31208b1SMajd Dibbiny 859d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 860e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 861e126ba97SEli Cohen 862aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 863311c7c71SSaeed Mahameed 86489d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 865e126ba97SEli Cohen if (err) { 86698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 86711f3b84dSSaeed Mahameed return err; 868e126ba97SEli Cohen } 869e126ba97SEli Cohen 870e126ba97SEli Cohen err = request_bar(pdev); 871e126ba97SEli Cohen if (err) { 87298a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 873e126ba97SEli Cohen goto err_disable; 874e126ba97SEli Cohen } 875e126ba97SEli Cohen 876e126ba97SEli Cohen pci_set_master(pdev); 877e126ba97SEli Cohen 878e126ba97SEli Cohen err = set_dma_caps(pdev); 879e126ba97SEli Cohen if (err) { 88098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 881e126ba97SEli Cohen goto err_clr_master; 882e126ba97SEli Cohen } 883e126ba97SEli Cohen 884ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 885ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 886ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 887ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 888ce4eee53SMichael Guralnik 889aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 890e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 891e126ba97SEli Cohen if (!dev->iseg) { 892e126ba97SEli Cohen err = -ENOMEM; 89398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 894e126ba97SEli Cohen goto err_clr_master; 895e126ba97SEli Cohen } 896a31208b1SMajd Dibbiny 897b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 898c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 899a31208b1SMajd Dibbiny return 0; 900a31208b1SMajd Dibbiny 901a31208b1SMajd Dibbiny err_clr_master: 902a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 903a31208b1SMajd Dibbiny release_bar(dev->pdev); 904a31208b1SMajd Dibbiny err_disable: 90589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 906a31208b1SMajd Dibbiny return err; 907a31208b1SMajd Dibbiny } 908a31208b1SMajd Dibbiny 909868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 910a31208b1SMajd Dibbiny { 91142ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 91242ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 91342ea9f1bSShay Drory * before removing the pci bars 91442ea9f1bSShay Drory */ 91542ea9f1bSShay Drory mlx5_drain_health_wq(dev); 916a31208b1SMajd Dibbiny iounmap(dev->iseg); 917a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 918a31208b1SMajd Dibbiny release_bar(dev->pdev); 91989d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 920a31208b1SMajd Dibbiny } 921a31208b1SMajd Dibbiny 922868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 92359211bd3SMohamad Haj Yahia { 92459211bd3SMohamad Haj Yahia int err; 92559211bd3SMohamad Haj Yahia 926868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 927868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 92898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 929868bc06bSSaeed Mahameed dev->priv.devcom); 930fadd59fcSAviv Heller 93159211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 93259211bd3SMohamad Haj Yahia if (err) { 93398a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 934fadd59fcSAviv Heller goto err_devcom; 93559211bd3SMohamad Haj Yahia } 93659211bd3SMohamad Haj Yahia 937561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 938561aa15aSYuval Avnery if (err) { 939561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 940561aa15aSYuval Avnery goto err_devcom; 941561aa15aSYuval Avnery } 942561aa15aSYuval Avnery 943f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 94459211bd3SMohamad Haj Yahia if (err) { 94598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 946561aa15aSYuval Avnery goto err_irq_cleanup; 94759211bd3SMohamad Haj Yahia } 94859211bd3SMohamad Haj Yahia 94969c1280bSSaeed Mahameed err = mlx5_events_init(dev); 95069c1280bSSaeed Mahameed if (err) { 95198a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 95269c1280bSSaeed Mahameed goto err_eq_cleanup; 95369c1280bSSaeed Mahameed } 95469c1280bSSaeed Mahameed 95538b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 95638b9f903SMoshe Shemesh if (err) { 95738b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 95838b9f903SMoshe Shemesh goto err_events_cleanup; 95938b9f903SMoshe Shemesh } 96038b9f903SMoshe Shemesh 9619f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 96259211bd3SMohamad Haj Yahia 96352ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 96452ec462eSIlan Tayari 9657c39afb3SFeras Daoud mlx5_init_clock(dev); 9667c39afb3SFeras Daoud 967358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 9680ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 969358aa5ceSSaeed Mahameed 97059211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 97159211bd3SMohamad Haj Yahia if (err) { 97298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 97359211bd3SMohamad Haj Yahia goto err_tables_cleanup; 97459211bd3SMohamad Haj Yahia } 97559211bd3SMohamad Haj Yahia 976eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 977eeb66cdbSSaeed Mahameed if (err) { 97898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 979eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 980eeb66cdbSSaeed Mahameed } 981eeb66cdbSSaeed Mahameed 982c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 983c2d6e31aSMohamad Haj Yahia if (err) { 98498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 98586eec50bSBodong Wang goto err_mpfs_cleanup; 98686eec50bSBodong Wang } 98786eec50bSBodong Wang 98886eec50bSBodong Wang err = mlx5_eswitch_init(dev); 98986eec50bSBodong Wang if (err) { 99086eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 99186eec50bSBodong Wang goto err_sriov_cleanup; 992c2d6e31aSMohamad Haj Yahia } 993c2d6e31aSMohamad Haj Yahia 9949410733cSIlan Tayari err = mlx5_fpga_init(dev); 9959410733cSIlan Tayari if (err) { 99698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 99786eec50bSBodong Wang goto err_eswitch_cleanup; 9989410733cSIlan Tayari } 9999410733cSIlan Tayari 1000f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 1001f3196bb0SParav Pandit if (err) { 1002f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1003f3196bb0SParav Pandit goto err_fpga_cleanup; 1004f3196bb0SParav Pandit } 1005f3196bb0SParav Pandit 10068f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 10078f010541SParav Pandit if (err) { 10088f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 10098f010541SParav Pandit goto err_sf_hw_table_cleanup; 10108f010541SParav Pandit } 10118f010541SParav Pandit 10128f010541SParav Pandit err = mlx5_sf_table_init(dev); 10138f010541SParav Pandit if (err) { 10148f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 10158f010541SParav Pandit goto err_sf_table_cleanup; 10168f010541SParav Pandit } 10178f010541SParav Pandit 1018b3388697SShay Drory err = mlx5_fs_core_alloc(dev); 1019b3388697SShay Drory if (err) { 1020b3388697SShay Drory mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1021b3388697SShay Drory goto err_fs; 1022b3388697SShay Drory } 1023b3388697SShay Drory 1024c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 1025c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 1026c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 1027c9b9dcb4SAriel Levkovich 102824406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 102987175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 103012206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 103124406953SFeras Daoud 103259211bd3SMohamad Haj Yahia return 0; 103359211bd3SMohamad Haj Yahia 1034b3388697SShay Drory err_fs: 1035b3388697SShay Drory mlx5_sf_table_cleanup(dev); 10368f010541SParav Pandit err_sf_table_cleanup: 10378f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 10388f010541SParav Pandit err_sf_hw_table_cleanup: 10398f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 1040f3196bb0SParav Pandit err_fpga_cleanup: 1041f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 1042c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 1043c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 104486eec50bSBodong Wang err_sriov_cleanup: 104586eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1046eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 1047eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 1048c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 1049c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 105059211bd3SMohamad Haj Yahia err_tables_cleanup: 10510ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1052358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 10532a35b2c2SJiri Pirko mlx5_cleanup_clock(dev); 10542a35b2c2SJiri Pirko mlx5_cleanup_reserved_gids(dev); 105502d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 105638b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 105738b9f903SMoshe Shemesh err_events_cleanup: 105869c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 105959211bd3SMohamad Haj Yahia err_eq_cleanup: 1060f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1061561aa15aSYuval Avnery err_irq_cleanup: 1062561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1063fadd59fcSAviv Heller err_devcom: 1064fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 106559211bd3SMohamad Haj Yahia 106659211bd3SMohamad Haj Yahia return err; 106759211bd3SMohamad Haj Yahia } 106859211bd3SMohamad Haj Yahia 106959211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 107059211bd3SMohamad Haj Yahia { 107112206b17SAya Levin mlx5_rsc_dump_destroy(dev); 107287175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 107324406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 1074c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 1075b3388697SShay Drory mlx5_fs_core_free(dev); 10768f010541SParav Pandit mlx5_sf_table_cleanup(dev); 10778f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 1078f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 10799410733cSIlan Tayari mlx5_fpga_cleanup(dev); 1080c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 108186eec50bSBodong Wang mlx5_sriov_cleanup(dev); 1082eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 108359211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 10840ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 1085358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 10867c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 108752ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 108802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 108938b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 109069c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 1091f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1092561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1093fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 109459211bd3SMohamad Haj Yahia } 109559211bd3SMohamad Haj Yahia 10969b98d395SMoshe Shemesh static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1097a31208b1SMajd Dibbiny { 1098a31208b1SMajd Dibbiny int err; 1099a31208b1SMajd Dibbiny 110098a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1101e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 1102e126ba97SEli Cohen 110300c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 110400c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 110500c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 110600c6bcb0STal Gilboa 11076c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 11086c780a02SEli Cohen */ 110937ca95e6SGavin Li err = wait_fw_init(dev, timeout, 11105945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 11116c780a02SEli Cohen if (err) { 11125945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 111337ca95e6SGavin Li timeout); 111476091b0fSAmir Tzin return err; 11156c780a02SEli Cohen } 11166c780a02SEli Cohen 1117e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1118e126ba97SEli Cohen if (err) { 111998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 112076091b0fSAmir Tzin return err; 1121e126ba97SEli Cohen } 1122e126ba97SEli Cohen 11235945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 11245945e1adSAmir Tzin 11255945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1126e3297246SEli Cohen if (err) { 11275945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 11285945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 112955378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1130e3297246SEli Cohen } 1131e3297246SEli Cohen 1132f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1133f7936dddSEran Ben Elisha 11349b98d395SMoshe Shemesh mlx5_start_health_poll(dev); 11359b98d395SMoshe Shemesh 11360b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1137cd23b14bSEli Cohen if (err) { 113898a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 11399b98d395SMoshe Shemesh goto stop_health_poll; 1140cd23b14bSEli Cohen } 1141cd23b14bSEli Cohen 1142f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1143f62b8bb8SAmir Vadai if (err) { 114498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1145f62b8bb8SAmir Vadai goto err_disable_hca; 1146f62b8bb8SAmir Vadai } 1147f62b8bb8SAmir Vadai 1148cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1149cd23b14bSEli Cohen if (err) { 115098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1151cd23b14bSEli Cohen goto err_disable_hca; 1152cd23b14bSEli Cohen } 1153cd23b14bSEli Cohen 115432def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 115532def412SAmir Tzin if (err) { 115632def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 115732def412SAmir Tzin goto reclaim_boot_pages; 115832def412SAmir Tzin } 115932def412SAmir Tzin 1160e126ba97SEli Cohen err = set_hca_ctrl(dev); 1161e126ba97SEli Cohen if (err) { 116298a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1163cd23b14bSEli Cohen goto reclaim_boot_pages; 1164e126ba97SEli Cohen } 1165e126ba97SEli Cohen 116637b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1167e126ba97SEli Cohen if (err) { 116898a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 116946861e3eSMoni Shoua goto reclaim_boot_pages; 117046861e3eSMoni Shoua } 117146861e3eSMoni Shoua 1172cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1173e126ba97SEli Cohen if (err) { 117498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1175cd23b14bSEli Cohen goto reclaim_boot_pages; 1176e126ba97SEli Cohen } 1177e126ba97SEli Cohen 11788737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1179e126ba97SEli Cohen if (err) { 118098a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 11810cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1182e126ba97SEli Cohen } 1183e126ba97SEli Cohen 1184012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1185012e50e1SHuy Nguyen 1186bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1187bba1574cSDaniel Jurgens if (err) { 118898a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1189502e82b9SAya Levin goto reclaim_boot_pages; 1190bba1574cSDaniel Jurgens } 11919b98d395SMoshe Shemesh mlx5_start_health_fw_log_up(dev); 1192502e82b9SAya Levin 1193e161105eSSaeed Mahameed return 0; 1194e161105eSSaeed Mahameed 1195e161105eSSaeed Mahameed reclaim_boot_pages: 1196e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1197e161105eSSaeed Mahameed err_disable_hca: 1198e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 11999b98d395SMoshe Shemesh stop_health_poll: 12009b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1201e161105eSSaeed Mahameed err_cmd_cleanup: 1202f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1203e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1204e161105eSSaeed Mahameed 1205e161105eSSaeed Mahameed return err; 1206e161105eSSaeed Mahameed } 1207e161105eSSaeed Mahameed 1208e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1209e161105eSSaeed Mahameed { 1210e161105eSSaeed Mahameed int err; 1211e161105eSSaeed Mahameed 1212e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1213259bbc57SMaor Gottlieb if (err) { 121498a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1215e161105eSSaeed Mahameed return err; 1216e126ba97SEli Cohen } 1217e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1218e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 12199b98d395SMoshe Shemesh mlx5_stop_health_poll(dev, boot); 1220f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1221e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1222e161105eSSaeed Mahameed 1223e161105eSSaeed Mahameed return 0; 1224259bbc57SMaor Gottlieb } 1225e126ba97SEli Cohen 1226a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1227e161105eSSaeed Mahameed { 1228e161105eSSaeed Mahameed int err; 1229e161105eSSaeed Mahameed 123001187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 123172f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 123298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 123372f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1234a80d1b68SSaeed Mahameed return err; 1235e126ba97SEli Cohen } 1236e126ba97SEli Cohen 123769c1280bSSaeed Mahameed mlx5_events_start(dev); 12380cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 12390cf53c12SSaeed Mahameed 1240e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1241e1706e62SYuval Avnery if (err) { 1242e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1243e1706e62SYuval Avnery goto err_irq_table; 1244e1706e62SYuval Avnery } 1245e1706e62SYuval Avnery 1246c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1247e126ba97SEli Cohen if (err) { 124898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1249c8e21b3bSSaeed Mahameed goto err_eq_table; 1250e126ba97SEli Cohen } 1251e126ba97SEli Cohen 125224406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 125324406953SFeras Daoud if (err) { 1254f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1255f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1256f62eb932SAya Levin dev->tracer = NULL; 125724406953SFeras Daoud } 125824406953SFeras Daoud 125938b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 126087175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 126187175120SEran Ben Elisha 126212206b17SAya Levin err = mlx5_rsc_dump_init(dev); 126312206b17SAya Levin if (err) { 1264f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1265f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1266f62eb932SAya Levin dev->rsc_dump = NULL; 126712206b17SAya Levin } 126812206b17SAya Levin 126904e87170SMatan Barak err = mlx5_fpga_device_start(dev); 127004e87170SMatan Barak if (err) { 127198a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 127204e87170SMatan Barak goto err_fpga_start; 127304e87170SMatan Barak } 127404e87170SMatan Barak 1275b3388697SShay Drory err = mlx5_fs_core_init(dev); 127686d722adSMaor Gottlieb if (err) { 127798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 127886d722adSMaor Gottlieb goto err_fs; 127986d722adSMaor Gottlieb } 12801466cc5bSYevgeny Petrilin 1281c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1282c85023e1SHuy Nguyen if (err) { 128398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 128494a4b841SLeon Romanovsky goto err_set_hca; 1285c85023e1SHuy Nguyen } 1286c85023e1SHuy Nguyen 1287f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1288f3196bb0SParav Pandit 12896a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 12906a327321SParav Pandit if (err) { 12916a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 12926a327321SParav Pandit goto err_vhca; 12936a327321SParav Pandit } 12946a327321SParav Pandit 129522e939a9SBodong Wang err = mlx5_ec_init(dev); 129622e939a9SBodong Wang if (err) { 129798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 129822e939a9SBodong Wang goto err_ec; 129922e939a9SBodong Wang } 130022e939a9SBodong Wang 1301cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 13025bef709dSParav Pandit err = mlx5_sriov_attach(dev); 13035bef709dSParav Pandit if (err) { 13045bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 13055bef709dSParav Pandit goto err_sriov; 13065bef709dSParav Pandit } 13075bef709dSParav Pandit 130890d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 130990d010b8SParav Pandit 131071b75f0eSMoshe Shemesh err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 131171b75f0eSMoshe Shemesh if (err) 131271b75f0eSMoshe Shemesh goto err_traps_reg; 131371b75f0eSMoshe Shemesh 1314a80d1b68SSaeed Mahameed return 0; 1315a80d1b68SSaeed Mahameed 131671b75f0eSMoshe Shemesh err_traps_reg: 131771b75f0eSMoshe Shemesh mlx5_sf_dev_table_destroy(dev); 131871b75f0eSMoshe Shemesh mlx5_sriov_detach(dev); 1319a80d1b68SSaeed Mahameed err_sriov: 1320cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13215bef709dSParav Pandit mlx5_ec_cleanup(dev); 13225bef709dSParav Pandit err_ec: 13236a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 13246a327321SParav Pandit err_vhca: 1325f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 132694a4b841SLeon Romanovsky err_set_hca: 1327b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1328a80d1b68SSaeed Mahameed err_fs: 1329a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1330a80d1b68SSaeed Mahameed err_fpga_start: 133112206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 133287175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 133338b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1334a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1335a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1336a80d1b68SSaeed Mahameed err_eq_table: 1337e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1338e1706e62SYuval Avnery err_irq_table: 1339a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1340a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1341a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1342a80d1b68SSaeed Mahameed return err; 1343a80d1b68SSaeed Mahameed } 1344a80d1b68SSaeed Mahameed 1345a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1346a80d1b68SSaeed Mahameed { 134771b75f0eSMoshe Shemesh mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 134890d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1349a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1350f019679eSChris Mi mlx5_eswitch_disable(dev->priv.eswitch); 1351cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 13525bef709dSParav Pandit mlx5_ec_cleanup(dev); 13536a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1354f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1355b3388697SShay Drory mlx5_fs_core_cleanup(dev); 1356a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 135712206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 135887175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 135938b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1360a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1361a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1362e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1363a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1364a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1365a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1366a80d1b68SSaeed Mahameed } 1367a80d1b68SSaeed Mahameed 13686dea2f7eSLeon Romanovsky int mlx5_init_one(struct mlx5_core_dev *dev) 1369a80d1b68SSaeed Mahameed { 137084a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 1371a80d1b68SSaeed Mahameed int err = 0; 1372a80d1b68SSaeed Mahameed 137384a433a4SMoshe Shemesh devl_lock(devlink); 1374a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1375a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1376a80d1b68SSaeed Mahameed 13779b98d395SMoshe Shemesh err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1378a80d1b68SSaeed Mahameed if (err) 13794f7400d5SShay Drory goto err_function; 1380a80d1b68SSaeed Mahameed 1381a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1382a80d1b68SSaeed Mahameed if (err) { 138398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1384a80d1b68SSaeed Mahameed goto function_teardown; 1385a80d1b68SSaeed Mahameed } 1386a80d1b68SSaeed Mahameed 1387a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1388a80d1b68SSaeed Mahameed if (err) 1389a80d1b68SSaeed Mahameed goto err_load; 1390a80d1b68SSaeed Mahameed 139198f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 139298f91c45SParav Pandit 1393919d13a7SLeon Romanovsky err = mlx5_devlink_register(priv_to_devlink(dev)); 1394a6f3b623SMichael Guralnik if (err) 1395a6f3b623SMichael Guralnik goto err_devlink_reg; 1396a925b5e3SLeon Romanovsky 1397a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1398a925b5e3SLeon Romanovsky if (err) 1399a925b5e3SLeon Romanovsky goto err_register; 1400a925b5e3SLeon Romanovsky 14014162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 140284a433a4SMoshe Shemesh devl_unlock(devlink); 14034162f58bSParav Pandit return 0; 1404e126ba97SEli Cohen 1405a925b5e3SLeon Romanovsky err_register: 1406a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1407a6f3b623SMichael Guralnik err_devlink_reg: 140898f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1409a80d1b68SSaeed Mahameed mlx5_unload(dev); 1410a80d1b68SSaeed Mahameed err_load: 141159211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1412e161105eSSaeed Mahameed function_teardown: 14136dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14144f7400d5SShay Drory err_function: 141589d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 141689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 141784a433a4SMoshe Shemesh devl_unlock(devlink); 1418e126ba97SEli Cohen return err; 1419e126ba97SEli Cohen } 1420e126ba97SEli Cohen 14216dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1422e126ba97SEli Cohen { 142384a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 142484a433a4SMoshe Shemesh 142584a433a4SMoshe Shemesh devl_lock(devlink); 142689d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 142798f91c45SParav Pandit 142898f91c45SParav Pandit mlx5_unregister_device(dev); 142998f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 143098f91c45SParav Pandit 1431b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 143298a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 143389d44f0aSMajd Dibbiny __func__); 143459211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 143589d44f0aSMajd Dibbiny goto out; 143689d44f0aSMajd Dibbiny } 14376b6adee3SMohamad Haj Yahia 14389ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1439a80d1b68SSaeed Mahameed mlx5_unload(dev); 144059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 14416dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 14426dea2f7eSLeon Romanovsky out: 14436dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 144484a433a4SMoshe Shemesh devl_unlock(devlink); 14456dea2f7eSLeon Romanovsky } 14460cf53c12SSaeed Mahameed 144784a433a4SMoshe Shemesh int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 14486dea2f7eSLeon Romanovsky { 14496dea2f7eSLeon Romanovsky int err = 0; 145037ca95e6SGavin Li u64 timeout; 14516dea2f7eSLeon Romanovsky 145284a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 14536dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 14546dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 14556dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 14566dea2f7eSLeon Romanovsky goto out; 14576dea2f7eSLeon Romanovsky } 14586dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 14596dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 14606dea2f7eSLeon Romanovsky 146137ca95e6SGavin Li if (recovery) 146237ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 146337ca95e6SGavin Li else 146437ca95e6SGavin Li timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 14659b98d395SMoshe Shemesh err = mlx5_function_setup(dev, false, timeout); 14666dea2f7eSLeon Romanovsky if (err) 14676dea2f7eSLeon Romanovsky goto err_function; 14686dea2f7eSLeon Romanovsky 14696dea2f7eSLeon Romanovsky err = mlx5_load(dev); 14706dea2f7eSLeon Romanovsky if (err) 14716dea2f7eSLeon Romanovsky goto err_load; 14726dea2f7eSLeon Romanovsky 14736dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 14746dea2f7eSLeon Romanovsky 14756dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 14766dea2f7eSLeon Romanovsky if (err) 14776dea2f7eSLeon Romanovsky goto err_attach; 14786dea2f7eSLeon Romanovsky 14796dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 14806dea2f7eSLeon Romanovsky return 0; 14816dea2f7eSLeon Romanovsky 14826dea2f7eSLeon Romanovsky err_attach: 14836dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 14846dea2f7eSLeon Romanovsky mlx5_unload(dev); 14856dea2f7eSLeon Romanovsky err_load: 14866dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 14876dea2f7eSLeon Romanovsky err_function: 14886dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 14896dea2f7eSLeon Romanovsky out: 14906dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 14916dea2f7eSLeon Romanovsky return err; 14926dea2f7eSLeon Romanovsky } 14936dea2f7eSLeon Romanovsky 149484a433a4SMoshe Shemesh int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 14956dea2f7eSLeon Romanovsky { 149684a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 149784a433a4SMoshe Shemesh int ret; 149884a433a4SMoshe Shemesh 149984a433a4SMoshe Shemesh devl_lock(devlink); 150084a433a4SMoshe Shemesh ret = mlx5_load_one_devl_locked(dev, recovery); 150184a433a4SMoshe Shemesh devl_unlock(devlink); 150284a433a4SMoshe Shemesh return ret; 150384a433a4SMoshe Shemesh } 150484a433a4SMoshe Shemesh 150584a433a4SMoshe Shemesh void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev) 150684a433a4SMoshe Shemesh { 150784a433a4SMoshe Shemesh devl_assert_locked(priv_to_devlink(dev)); 15086dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 15096dea2f7eSLeon Romanovsky 15106dea2f7eSLeon Romanovsky mlx5_detach_device(dev); 15116dea2f7eSLeon Romanovsky 15126dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 15136dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 15146dea2f7eSLeon Romanovsky __func__); 15156dea2f7eSLeon Romanovsky goto out; 15166dea2f7eSLeon Romanovsky } 15176dea2f7eSLeon Romanovsky 15186dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 15196dea2f7eSLeon Romanovsky mlx5_unload(dev); 15206dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1521ac6ea6e8SEli Cohen out: 152289d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 15239603b61dSJack Morgenstein } 152464613d94SSaeed Mahameed 152584a433a4SMoshe Shemesh void mlx5_unload_one(struct mlx5_core_dev *dev) 152684a433a4SMoshe Shemesh { 152784a433a4SMoshe Shemesh struct devlink *devlink = priv_to_devlink(dev); 152884a433a4SMoshe Shemesh 152984a433a4SMoshe Shemesh devl_lock(devlink); 153084a433a4SMoshe Shemesh mlx5_unload_one_devl_locked(dev); 153184a433a4SMoshe Shemesh devl_unlock(devlink); 153284a433a4SMoshe Shemesh } 153384a433a4SMoshe Shemesh 153448f02eefSParav Pandit static const int types[] = { 153548f02eefSParav Pandit MLX5_CAP_GENERAL, 153648f02eefSParav Pandit MLX5_CAP_GENERAL_2, 153748f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 153848f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 153948f02eefSParav Pandit MLX5_CAP_ODP, 154048f02eefSParav Pandit MLX5_CAP_ATOMIC, 154148f02eefSParav Pandit MLX5_CAP_ROCE, 154248f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 154348f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 154448f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 154548f02eefSParav Pandit MLX5_CAP_ESWITCH, 154648f02eefSParav Pandit MLX5_CAP_VECTOR_CALC, 154748f02eefSParav Pandit MLX5_CAP_QOS, 154848f02eefSParav Pandit MLX5_CAP_DEBUG, 154948f02eefSParav Pandit MLX5_CAP_DEV_MEM, 155048f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 155148f02eefSParav Pandit MLX5_CAP_TLS, 155248f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 155348f02eefSParav Pandit MLX5_CAP_IPSEC, 1554425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 15557025329dSBen Ben-Ishay MLX5_CAP_DEV_SHAMPO, 15568ff0ac5bSLior Nahmanson MLX5_CAP_MACSEC, 155793983863SYishai Hadas MLX5_CAP_ADV_VIRTUALIZATION, 155848f02eefSParav Pandit }; 155948f02eefSParav Pandit 156048f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 156148f02eefSParav Pandit { 156248f02eefSParav Pandit int type; 156348f02eefSParav Pandit int i; 156448f02eefSParav Pandit 156548f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 156648f02eefSParav Pandit type = types[i]; 156748f02eefSParav Pandit kfree(dev->caps.hca[type]); 156848f02eefSParav Pandit } 156948f02eefSParav Pandit } 157048f02eefSParav Pandit 157148f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 157248f02eefSParav Pandit { 157348f02eefSParav Pandit struct mlx5_hca_cap *cap; 157448f02eefSParav Pandit int type; 157548f02eefSParav Pandit int i; 157648f02eefSParav Pandit 157748f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 157848f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 157948f02eefSParav Pandit if (!cap) 158048f02eefSParav Pandit goto err; 158148f02eefSParav Pandit type = types[i]; 158248f02eefSParav Pandit dev->caps.hca[type] = cap; 158348f02eefSParav Pandit } 158448f02eefSParav Pandit 158548f02eefSParav Pandit return 0; 158648f02eefSParav Pandit 158748f02eefSParav Pandit err: 158848f02eefSParav Pandit mlx5_hca_caps_free(dev); 158948f02eefSParav Pandit return -ENOMEM; 159048f02eefSParav Pandit } 159148f02eefSParav Pandit 1592dd3dd726SEli Cohen static int vhca_id_show(struct seq_file *file, void *priv) 1593dd3dd726SEli Cohen { 1594dd3dd726SEli Cohen struct mlx5_core_dev *dev = file->private; 1595dd3dd726SEli Cohen 1596dd3dd726SEli Cohen seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1597dd3dd726SEli Cohen return 0; 1598dd3dd726SEli Cohen } 1599dd3dd726SEli Cohen 1600dd3dd726SEli Cohen DEFINE_SHOW_ATTRIBUTE(vhca_id); 1601dd3dd726SEli Cohen 16021958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 16039603b61dSJack Morgenstein { 160411f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 16059603b61dSJack Morgenstein int err; 16069603b61dSJack Morgenstein 16073410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1608d59b73a6SMoshe Shemesh lockdep_register_key(&dev->lock_key); 160989d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1610d59b73a6SMoshe Shemesh lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1611d9aaed83SArtemy Kovalyov 161201187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 161301187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 161401187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 161501187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 161601187175SEli Cohen 161711f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 161811f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 161911f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 162011f3b84dSSaeed Mahameed 162144f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 162266771a1cSMoshe Shemesh priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 162327b942fbSParav Pandit mlx5_debugfs_root); 1624dd3dd726SEli Cohen debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 16253d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 16263d347b1bSAya Levin 162776091b0fSAmir Tzin err = mlx5_tout_init(dev); 162876091b0fSAmir Tzin if (err) { 162976091b0fSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 163076091b0fSAmir Tzin goto err_timeout_init; 163176091b0fSAmir Tzin } 163276091b0fSAmir Tzin 1633ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 163452c368dcSSaeed Mahameed if (err) 163552c368dcSSaeed Mahameed goto err_health_init; 1636ac6ea6e8SEli Cohen 16370cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 16380cf53c12SSaeed Mahameed if (err) 16390cf53c12SSaeed Mahameed goto err_pagealloc_init; 164059211bd3SMohamad Haj Yahia 1641a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1642a925b5e3SLeon Romanovsky if (err) 1643a925b5e3SLeon Romanovsky goto err_adev_init; 1644a925b5e3SLeon Romanovsky 164548f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 164648f02eefSParav Pandit if (err) 164748f02eefSParav Pandit goto err_hca_caps; 164848f02eefSParav Pandit 1649dc402cccSYishai Hadas /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1650dc402cccSYishai Hadas * unique id per function which uses mlx5_core. 1651dc402cccSYishai Hadas * Those values are supplied to FW as part of the init HCA command to 1652dc402cccSYishai Hadas * be used by both driver and FW when it's applicable. 1653dc402cccSYishai Hadas */ 1654dc402cccSYishai Hadas dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1655dc402cccSYishai Hadas MAX_SW_VHCA_ID, 1656dc402cccSYishai Hadas GFP_KERNEL); 1657dc402cccSYishai Hadas if (dev->priv.sw_vhca_id < 0) 1658dc402cccSYishai Hadas mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1659dc402cccSYishai Hadas dev->priv.sw_vhca_id); 1660dc402cccSYishai Hadas 166111f3b84dSSaeed Mahameed return 0; 166252c368dcSSaeed Mahameed 166348f02eefSParav Pandit err_hca_caps: 166448f02eefSParav Pandit mlx5_adev_cleanup(dev); 1665a925b5e3SLeon Romanovsky err_adev_init: 1666a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 166752c368dcSSaeed Mahameed err_pagealloc_init: 166852c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 166952c368dcSSaeed Mahameed err_health_init: 167076091b0fSAmir Tzin mlx5_tout_cleanup(dev); 167176091b0fSAmir Tzin err_timeout_init: 167266771a1cSMoshe Shemesh debugfs_remove(dev->priv.dbg.dbg_root); 1673810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1674810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1675810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1676810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1677810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1678d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 167952c368dcSSaeed Mahameed return err; 168011f3b84dSSaeed Mahameed } 168111f3b84dSSaeed Mahameed 16821958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 168311f3b84dSSaeed Mahameed { 1684810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1685810cbb25SParav Pandit 1686dc402cccSYishai Hadas if (priv->sw_vhca_id > 0) 1687dc402cccSYishai Hadas ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1688dc402cccSYishai Hadas 168948f02eefSParav Pandit mlx5_hca_caps_free(dev); 1690a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 169152c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 169252c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 169376091b0fSAmir Tzin mlx5_tout_cleanup(dev); 169466771a1cSMoshe Shemesh debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1695810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1696810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1697810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1698810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1699810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 1700d59b73a6SMoshe Shemesh lockdep_unregister_key(&dev->lock_key); 170111f3b84dSSaeed Mahameed } 170211f3b84dSSaeed Mahameed 17036dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 170411f3b84dSSaeed Mahameed { 170511f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 170611f3b84dSSaeed Mahameed struct devlink *devlink; 170711f3b84dSSaeed Mahameed int err; 170811f3b84dSSaeed Mahameed 1709919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 171011f3b84dSSaeed Mahameed if (!devlink) { 17111f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 171211f3b84dSSaeed Mahameed return -ENOMEM; 171311f3b84dSSaeed Mahameed } 171411f3b84dSSaeed Mahameed 171511f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 171627b942fbSParav Pandit dev->device = &pdev->dev; 171727b942fbSParav Pandit dev->pdev = pdev; 171811f3b84dSSaeed Mahameed 1719386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1720386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1721386e75afSHuy Nguyen 1722a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 17234d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 17244d8be211SLeon Romanovsky err = dev->priv.adev_idx; 17254d8be211SLeon Romanovsky goto adev_init_err; 17264d8be211SLeon Romanovsky } 1727a925b5e3SLeon Romanovsky 172827b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 172911f3b84dSSaeed Mahameed if (err) 173011f3b84dSSaeed Mahameed goto mdev_init_err; 173111f3b84dSSaeed Mahameed 173211f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 17339603b61dSJack Morgenstein if (err) { 173498a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 173598a8e6fcSHuy Nguyen err); 173611f3b84dSSaeed Mahameed goto pci_init_err; 17379603b61dSJack Morgenstein } 17389603b61dSJack Morgenstein 17396dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 17409603b61dSJack Morgenstein if (err) { 17416dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 174298a8e6fcSHuy Nguyen err); 17436dea2f7eSLeon Romanovsky goto err_init_one; 17449603b61dSJack Morgenstein } 174559211bd3SMohamad Haj Yahia 17468b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 17478b9d8baaSAlex Vesker if (err) 17488b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 17498b9d8baaSAlex Vesker 17505d47f6c8SDaniel Jurgens pci_save_state(pdev); 175164ea2d0eSLeon Romanovsky devlink_register(devlink); 17529603b61dSJack Morgenstein return 0; 17539603b61dSJack Morgenstein 17546dea2f7eSLeon Romanovsky err_init_one: 1755868bc06bSSaeed Mahameed mlx5_pci_close(dev); 175611f3b84dSSaeed Mahameed pci_init_err: 175711f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 175811f3b84dSSaeed Mahameed mdev_init_err: 1759a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 17604d8be211SLeon Romanovsky adev_init_err: 17611f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1762a31208b1SMajd Dibbiny 17639603b61dSJack Morgenstein return err; 17649603b61dSJack Morgenstein } 1765a31208b1SMajd Dibbiny 17669603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 17679603b61dSJack Morgenstein { 17689603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1769feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 17709603b61dSJack Morgenstein 177116d42d31SShay Drory /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain 177216d42d31SShay Drory * fw_reset before unregistering the devlink. 177316d42d31SShay Drory */ 177416d42d31SShay Drory mlx5_drain_fw_reset(dev); 17758324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 177664ea2d0eSLeon Romanovsky devlink_unregister(devlink); 1777143a41d7SYishai Hadas mlx5_sriov_disable(pdev); 17788b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 177941798df9SParav Pandit mlx5_drain_health_wq(dev); 17806dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1781868bc06bSSaeed Mahameed mlx5_pci_close(dev); 178211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1783a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 17841f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 17859603b61dSJack Morgenstein } 17869603b61dSJack Morgenstein 1787fad1783aSSaeed Mahameed #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1788fad1783aSSaeed Mahameed struct mlx5_core_dev *__dev = (dev); \ 1789fad1783aSSaeed Mahameed mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1790fad1783aSSaeed Mahameed __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1791fad1783aSSaeed Mahameed __dev->pci_status, ##__VA_ARGS__); \ 1792fad1783aSSaeed Mahameed }) 1793fad1783aSSaeed Mahameed 1794fad1783aSSaeed Mahameed static const char *result2str(enum pci_ers_result result) 1795fad1783aSSaeed Mahameed { 1796fad1783aSSaeed Mahameed return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1797fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1798fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1799fad1783aSSaeed Mahameed "unknown"; 1800fad1783aSSaeed Mahameed } 1801fad1783aSSaeed Mahameed 180289d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 180389d44f0aSMajd Dibbiny pci_channel_state_t state) 180489d44f0aSMajd Dibbiny { 180589d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1806fad1783aSSaeed Mahameed enum pci_ers_result res; 180789d44f0aSMajd Dibbiny 1808fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 180904c0c1abSMohamad Haj Yahia 18108812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 18113e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 18126dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 18135e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 181489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 181505ac2c0bSMohamad Haj Yahia 1816fad1783aSSaeed Mahameed res = state == pci_channel_io_perm_failure ? 181789d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1818fad1783aSSaeed Mahameed 1819394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 1820394164f9SRoy Novich __func__, dev->state, dev->pci_status, res, result2str(res)); 1821fad1783aSSaeed Mahameed return res; 182289d44f0aSMajd Dibbiny } 182389d44f0aSMajd Dibbiny 1824d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1825d57847dcSDaniel Jurgens * for the health counter to start counting. 182689d44f0aSMajd Dibbiny */ 1827d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 182889d44f0aSMajd Dibbiny { 182989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 183089d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 183189d44f0aSMajd Dibbiny const int niter = 100; 1832d57847dcSDaniel Jurgens u32 last_count = 0; 183389d44f0aSMajd Dibbiny u32 count; 183489d44f0aSMajd Dibbiny int i; 183589d44f0aSMajd Dibbiny 183689d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 183789d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 183889d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1839d57847dcSDaniel Jurgens if (last_count && last_count != count) { 184098a8e6fcSHuy Nguyen mlx5_core_info(dev, 184198a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 184298a8e6fcSHuy Nguyen count, i); 1843d57847dcSDaniel Jurgens return 0; 1844d57847dcSDaniel Jurgens } 1845d57847dcSDaniel Jurgens last_count = count; 184689d44f0aSMajd Dibbiny } 184789d44f0aSMajd Dibbiny msleep(50); 184889d44f0aSMajd Dibbiny } 184989d44f0aSMajd Dibbiny 1850d57847dcSDaniel Jurgens return -ETIMEDOUT; 185189d44f0aSMajd Dibbiny } 185289d44f0aSMajd Dibbiny 18531061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 18541061c90fSMohamad Haj Yahia { 1855fad1783aSSaeed Mahameed enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 18561061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18571061c90fSMohamad Haj Yahia int err; 18581061c90fSMohamad Haj Yahia 1859394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 1860394164f9SRoy Novich __func__, dev->state, dev->pci_status); 18611061c90fSMohamad Haj Yahia 18621061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 18631061c90fSMohamad Haj Yahia if (err) { 186498a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 186598a8e6fcSHuy Nguyen __func__, err); 1866fad1783aSSaeed Mahameed goto out; 18671061c90fSMohamad Haj Yahia } 18681061c90fSMohamad Haj Yahia 18691061c90fSMohamad Haj Yahia pci_set_master(pdev); 18701061c90fSMohamad Haj Yahia pci_restore_state(pdev); 18715d47f6c8SDaniel Jurgens pci_save_state(pdev); 18721061c90fSMohamad Haj Yahia 1873fad1783aSSaeed Mahameed err = wait_vital(pdev); 1874fad1783aSSaeed Mahameed if (err) { 1875fad1783aSSaeed Mahameed mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1876fad1783aSSaeed Mahameed __func__, err); 1877fad1783aSSaeed Mahameed goto out; 18781061c90fSMohamad Haj Yahia } 18791061c90fSMohamad Haj Yahia 1880fad1783aSSaeed Mahameed res = PCI_ERS_RESULT_RECOVERED; 1881fad1783aSSaeed Mahameed out: 1882394164f9SRoy Novich mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 1883394164f9SRoy Novich __func__, dev->state, dev->pci_status, err, res, result2str(res)); 1884fad1783aSSaeed Mahameed return res; 18851061c90fSMohamad Haj Yahia } 18861061c90fSMohamad Haj Yahia 188789d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 188889d44f0aSMajd Dibbiny { 188989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 189089d44f0aSMajd Dibbiny int err; 189189d44f0aSMajd Dibbiny 1892fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, loading driver..\n"); 189389d44f0aSMajd Dibbiny 189437ca95e6SGavin Li err = mlx5_load_one(dev, false); 1895fad1783aSSaeed Mahameed 1896416ef713SRoy Novich if (!err) 1897416ef713SRoy Novich devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 1898416ef713SRoy Novich DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 1899416ef713SRoy Novich 1900fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1901fad1783aSSaeed Mahameed !err ? "recovered" : "Failed"); 190289d44f0aSMajd Dibbiny } 190389d44f0aSMajd Dibbiny 190489d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 190589d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 190689d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 190789d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 190889d44f0aSMajd Dibbiny }; 190989d44f0aSMajd Dibbiny 19108812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 19118812c24dSMajd Dibbiny { 1912fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1913fcd29ad1SFeras Daoud int ret = 1; 19148812c24dSMajd Dibbiny 1915fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1916fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1917fcd29ad1SFeras Daoud 1918fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1919fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1920fcd29ad1SFeras Daoud 1921fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 19228812c24dSMajd Dibbiny return -EOPNOTSUPP; 19238812c24dSMajd Dibbiny 19248812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 19258812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 19268812c24dSMajd Dibbiny return -EAGAIN; 19278812c24dSMajd Dibbiny } 19288812c24dSMajd Dibbiny 1929d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1930b0ea505bSJulia Lawall * with the HCA, so the health poll is no longer needed. 1931d2aa060dSHuy Nguyen */ 1932d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 193376d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1934d2aa060dSHuy Nguyen 1935fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1936fcd29ad1SFeras Daoud if (!ret) 1937fcd29ad1SFeras Daoud goto succeed; 1938fcd29ad1SFeras Daoud 19398812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1940fcd29ad1SFeras Daoud if (!ret) 1941fcd29ad1SFeras Daoud goto succeed; 1942fcd29ad1SFeras Daoud 19438812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1944d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 19458812c24dSMajd Dibbiny return ret; 19468812c24dSMajd Dibbiny 1947fcd29ad1SFeras Daoud succeed: 19488812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 19498812c24dSMajd Dibbiny 19501ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 19511ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 19521ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 19531ef903bfSDaniel Jurgens * contexts. 19541ef903bfSDaniel Jurgens */ 19551ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 19561ef903bfSDaniel Jurgens 19578812c24dSMajd Dibbiny return 0; 19588812c24dSMajd Dibbiny } 19598812c24dSMajd Dibbiny 19605fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 19615fc7197dSMajd Dibbiny { 19625fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19638812c24dSMajd Dibbiny int err; 19645fc7197dSMajd Dibbiny 196598a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 19668324a02cSGavin Li set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 19678812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 19688812c24dSMajd Dibbiny if (err) 19696dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 19705fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 19715fc7197dSMajd Dibbiny } 19725fc7197dSMajd Dibbiny 19738fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 19748fc3e29bSMark Bloch { 19758fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19768fc3e29bSMark Bloch 19776dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 19788fc3e29bSMark Bloch 19798fc3e29bSMark Bloch return 0; 19808fc3e29bSMark Bloch } 19818fc3e29bSMark Bloch 19828fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 19838fc3e29bSMark Bloch { 19848fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 19858fc3e29bSMark Bloch 198637ca95e6SGavin Li return mlx5_load_one(dev, false); 19878fc3e29bSMark Bloch } 19888fc3e29bSMark Bloch 19899603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1990bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1991fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1992bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1993fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1994bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1995fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 19967092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 199764dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1998d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1999d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2000d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2001d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 200285327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 200385327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2004b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2005505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2006f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 20072e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 20082e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2009d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2010dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2011f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 20129603b61dSJack Morgenstein { 0, } 20139603b61dSJack Morgenstein }; 20149603b61dSJack Morgenstein 20159603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 20169603b61dSJack Morgenstein 201704c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 201804c0c1abSMohamad Haj Yahia { 2019b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 2020d3dbdc9fSMoshe Shemesh mlx5_unload_one_devl_locked(dev); 202104c0c1abSMohamad Haj Yahia } 202204c0c1abSMohamad Haj Yahia 2023fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 202404c0c1abSMohamad Haj Yahia { 202533de865fSMoshe Shemesh if (!mlx5_core_is_sf(dev)) { 202604c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 202733de865fSMoshe Shemesh if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 202833de865fSMoshe Shemesh return -EIO; 202933de865fSMoshe Shemesh } 203033de865fSMoshe Shemesh 2031d3dbdc9fSMoshe Shemesh return mlx5_load_one_devl_locked(dev, true); 203204c0c1abSMohamad Haj Yahia } 203304c0c1abSMohamad Haj Yahia 20349603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 203517a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 20369603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 20376dea2f7eSLeon Romanovsky .probe = probe_one, 203889d44f0aSMajd Dibbiny .remove = remove_one, 20398fc3e29bSMark Bloch .suspend = mlx5_suspend, 20408fc3e29bSMark Bloch .resume = mlx5_resume, 20415fc7197dSMajd Dibbiny .shutdown = shutdown, 2042fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 2043fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 2044e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2045e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 20469603b61dSJack Morgenstein }; 2047e126ba97SEli Cohen 20481695b97bSYishai Hadas /** 20491695b97bSYishai Hadas * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 20501695b97bSYishai Hadas * mlx5_core is its driver. 20511695b97bSYishai Hadas * @pdev: The associated PCI device. 20521695b97bSYishai Hadas * 20531695b97bSYishai Hadas * Upon return the interface state lock stay held to let caller uses it safely. 20541695b97bSYishai Hadas * Caller must ensure to use the returned mlx5 device for a narrow window 20551695b97bSYishai Hadas * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 20561695b97bSYishai Hadas * 20571695b97bSYishai Hadas * Return: Pointer to the associated mlx5_core_dev or NULL. 20581695b97bSYishai Hadas */ 20591695b97bSYishai Hadas struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 20601695b97bSYishai Hadas { 20611695b97bSYishai Hadas struct mlx5_core_dev *mdev; 20621695b97bSYishai Hadas 20631695b97bSYishai Hadas mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 20641695b97bSYishai Hadas if (IS_ERR(mdev)) 20651695b97bSYishai Hadas return NULL; 20661695b97bSYishai Hadas 20671695b97bSYishai Hadas mutex_lock(&mdev->intf_state_mutex); 20681695b97bSYishai Hadas if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 20691695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 20701695b97bSYishai Hadas return NULL; 20711695b97bSYishai Hadas } 20721695b97bSYishai Hadas 20731695b97bSYishai Hadas return mdev; 20741695b97bSYishai Hadas } 20751695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_get_core_dev); 20761695b97bSYishai Hadas 20771695b97bSYishai Hadas /** 20781695b97bSYishai Hadas * mlx5_vf_put_core_dev - Put the mlx5 core device back. 20791695b97bSYishai Hadas * @mdev: The mlx5 core device. 20801695b97bSYishai Hadas * 20811695b97bSYishai Hadas * Upon return the interface state lock is unlocked and caller should not 20821695b97bSYishai Hadas * access the mdev any more. 20831695b97bSYishai Hadas */ 20841695b97bSYishai Hadas void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 20851695b97bSYishai Hadas { 20861695b97bSYishai Hadas mutex_unlock(&mdev->intf_state_mutex); 20871695b97bSYishai Hadas } 20881695b97bSYishai Hadas EXPORT_SYMBOL(mlx5_vf_put_core_dev); 20891695b97bSYishai Hadas 2090f663ad98SKamal Heib static void mlx5_core_verify_params(void) 2091f663ad98SKamal Heib { 2092f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 2093f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2094f663ad98SKamal Heib prof_sel, 2095f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 2096f663ad98SKamal Heib MLX5_DEFAULT_PROF); 2097f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 2098f663ad98SKamal Heib } 2099f663ad98SKamal Heib } 2100f663ad98SKamal Heib 21012c1e1b94SRandy Dunlap static int __init mlx5_init(void) 2102e126ba97SEli Cohen { 2103e126ba97SEli Cohen int err; 2104e126ba97SEli Cohen 210517a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 210617a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 210717a7612bSLeon Romanovsky 21088737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 21098737f818SDaniel Jurgens 2110f663ad98SKamal Heib mlx5_core_verify_params(); 2111e126ba97SEli Cohen mlx5_register_debugfs(); 2112e126ba97SEli Cohen 2113*8f0d1451SShay Drory err = mlx5e_init(); 21149603b61dSJack Morgenstein if (err) 2115ac6ea6e8SEli Cohen goto err_debug; 21169603b61dSJack Morgenstein 21171958fc2fSParav Pandit err = mlx5_sf_driver_register(); 21181958fc2fSParav Pandit if (err) 21191958fc2fSParav Pandit goto err_sf; 21201958fc2fSParav Pandit 2121*8f0d1451SShay Drory err = pci_register_driver(&mlx5_core_driver); 2122c633e799SLeon Romanovsky if (err) 2123*8f0d1451SShay Drory goto err_pci; 2124f62b8bb8SAmir Vadai 2125e126ba97SEli Cohen return 0; 2126e126ba97SEli Cohen 2127*8f0d1451SShay Drory err_pci: 2128c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 21291958fc2fSParav Pandit err_sf: 2130*8f0d1451SShay Drory mlx5e_cleanup(); 2131e126ba97SEli Cohen err_debug: 2132e126ba97SEli Cohen mlx5_unregister_debugfs(); 2133e126ba97SEli Cohen return err; 2134e126ba97SEli Cohen } 2135e126ba97SEli Cohen 21362c1e1b94SRandy Dunlap static void __exit mlx5_cleanup(void) 2137e126ba97SEli Cohen { 21389603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 2139*8f0d1451SShay Drory mlx5_sf_driver_unregister(); 2140*8f0d1451SShay Drory mlx5e_cleanup(); 2141e126ba97SEli Cohen mlx5_unregister_debugfs(); 2142e126ba97SEli Cohen } 2143e126ba97SEli Cohen 21442c1e1b94SRandy Dunlap module_init(mlx5_init); 21452c1e1b94SRandy Dunlap module_exit(mlx5_cleanup); 2146