1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6052ec462eSIlan Tayari #include "lib/mlx5.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 6205564d0aSAviad Yehezkel #include "fpga/ipsec.h" 63bebb23e6SIlan Tayari #include "accel/ipsec.h" 641ae17322SIlya Lesokhin #include "accel/tls.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 7287175120SEran Ben Elisha #include "lib/hv_vhca.h" 7312206b17SAya Levin #include "diag/rsc_dump.h" 74e126ba97SEli Cohen 75e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 77e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 78e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 79e126ba97SEli Cohen 80f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 81f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 82e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 83e126ba97SEli Cohen 849603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 85f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 86f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 879603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 889603b61dSJack Morgenstein 898737f818SDaniel Jurgens static u32 sw_owner_id[4]; 908737f818SDaniel Jurgens 91f91e6d89SEran Ben Elisha enum { 92f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 93f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 94f91e6d89SEran Ben Elisha }; 95f91e6d89SEran Ben Elisha 969603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 979603b61dSJack Morgenstein [0] = { 989603b61dSJack Morgenstein .mask = 0, 999603b61dSJack Morgenstein }, 1009603b61dSJack Morgenstein [1] = { 1019603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1029603b61dSJack Morgenstein .log_max_qp = 12, 1039603b61dSJack Morgenstein }, 1049603b61dSJack Morgenstein [2] = { 1059603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1069603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1075f40b4edSMaor Gottlieb .log_max_qp = 18, 1089603b61dSJack Morgenstein .mr_cache[0] = { 1099603b61dSJack Morgenstein .size = 500, 1109603b61dSJack Morgenstein .limit = 250 1119603b61dSJack Morgenstein }, 1129603b61dSJack Morgenstein .mr_cache[1] = { 1139603b61dSJack Morgenstein .size = 500, 1149603b61dSJack Morgenstein .limit = 250 1159603b61dSJack Morgenstein }, 1169603b61dSJack Morgenstein .mr_cache[2] = { 1179603b61dSJack Morgenstein .size = 500, 1189603b61dSJack Morgenstein .limit = 250 1199603b61dSJack Morgenstein }, 1209603b61dSJack Morgenstein .mr_cache[3] = { 1219603b61dSJack Morgenstein .size = 500, 1229603b61dSJack Morgenstein .limit = 250 1239603b61dSJack Morgenstein }, 1249603b61dSJack Morgenstein .mr_cache[4] = { 1259603b61dSJack Morgenstein .size = 500, 1269603b61dSJack Morgenstein .limit = 250 1279603b61dSJack Morgenstein }, 1289603b61dSJack Morgenstein .mr_cache[5] = { 1299603b61dSJack Morgenstein .size = 500, 1309603b61dSJack Morgenstein .limit = 250 1319603b61dSJack Morgenstein }, 1329603b61dSJack Morgenstein .mr_cache[6] = { 1339603b61dSJack Morgenstein .size = 500, 1349603b61dSJack Morgenstein .limit = 250 1359603b61dSJack Morgenstein }, 1369603b61dSJack Morgenstein .mr_cache[7] = { 1379603b61dSJack Morgenstein .size = 500, 1389603b61dSJack Morgenstein .limit = 250 1399603b61dSJack Morgenstein }, 1409603b61dSJack Morgenstein .mr_cache[8] = { 1419603b61dSJack Morgenstein .size = 500, 1429603b61dSJack Morgenstein .limit = 250 1439603b61dSJack Morgenstein }, 1449603b61dSJack Morgenstein .mr_cache[9] = { 1459603b61dSJack Morgenstein .size = 500, 1469603b61dSJack Morgenstein .limit = 250 1479603b61dSJack Morgenstein }, 1489603b61dSJack Morgenstein .mr_cache[10] = { 1499603b61dSJack Morgenstein .size = 500, 1509603b61dSJack Morgenstein .limit = 250 1519603b61dSJack Morgenstein }, 1529603b61dSJack Morgenstein .mr_cache[11] = { 1539603b61dSJack Morgenstein .size = 500, 1549603b61dSJack Morgenstein .limit = 250 1559603b61dSJack Morgenstein }, 1569603b61dSJack Morgenstein .mr_cache[12] = { 1579603b61dSJack Morgenstein .size = 64, 1589603b61dSJack Morgenstein .limit = 32 1599603b61dSJack Morgenstein }, 1609603b61dSJack Morgenstein .mr_cache[13] = { 1619603b61dSJack Morgenstein .size = 32, 1629603b61dSJack Morgenstein .limit = 16 1639603b61dSJack Morgenstein }, 1649603b61dSJack Morgenstein .mr_cache[14] = { 1659603b61dSJack Morgenstein .size = 16, 1669603b61dSJack Morgenstein .limit = 8 1679603b61dSJack Morgenstein }, 1689603b61dSJack Morgenstein .mr_cache[15] = { 1699603b61dSJack Morgenstein .size = 8, 1709603b61dSJack Morgenstein .limit = 4 1719603b61dSJack Morgenstein }, 1729603b61dSJack Morgenstein }, 1739603b61dSJack Morgenstein }; 174e126ba97SEli Cohen 175e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 176e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 177b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 178b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 179e3297246SEli Cohen 180b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 181b8a92577SDaniel Jurgens u32 warn_time_mili) 182e3297246SEli Cohen { 183b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 184e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 185e3297246SEli Cohen int err = 0; 186e3297246SEli Cohen 187b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 188b8a92577SDaniel Jurgens 189e3297246SEli Cohen while (fw_initializing(dev)) { 190e3297246SEli Cohen if (time_after(jiffies, end)) { 191e3297246SEli Cohen err = -EBUSY; 192e3297246SEli Cohen break; 193e3297246SEli Cohen } 194b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 195b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 196b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 197b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 198b8a92577SDaniel Jurgens } 199e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 200e3297246SEli Cohen } 201e3297246SEli Cohen 202e3297246SEli Cohen return err; 203e3297246SEli Cohen } 204e3297246SEli Cohen 205012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 206012e50e1SHuy Nguyen { 207012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 208012e50e1SHuy Nguyen driver_version); 2093ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 210012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 211012e50e1SHuy Nguyen char *string; 212012e50e1SHuy Nguyen 213012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 214012e50e1SHuy Nguyen return; 215012e50e1SHuy Nguyen 216012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 217012e50e1SHuy Nguyen 218012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 219012e50e1SHuy Nguyen 220012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 221012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 222012e50e1SHuy Nguyen 223012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 224012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 225012e50e1SHuy Nguyen 226012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 227012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 228012e50e1SHuy Nguyen 229012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 230012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 231012e50e1SHuy Nguyen 232012e50e1SHuy Nguyen /*Send the command*/ 233012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 234012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 235012e50e1SHuy Nguyen 2363ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 237012e50e1SHuy Nguyen } 238012e50e1SHuy Nguyen 239e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 240e126ba97SEli Cohen { 241e126ba97SEli Cohen int err; 242e126ba97SEli Cohen 243e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 244e126ba97SEli Cohen if (err) { 2451a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 246e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 247e126ba97SEli Cohen if (err) { 2481a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 249e126ba97SEli Cohen return err; 250e126ba97SEli Cohen } 251e126ba97SEli Cohen } 252e126ba97SEli Cohen 253e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 254e126ba97SEli Cohen if (err) { 255e126ba97SEli Cohen dev_warn(&pdev->dev, 2561a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 257e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 258e126ba97SEli Cohen if (err) { 259e126ba97SEli Cohen dev_err(&pdev->dev, 2601a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 261e126ba97SEli Cohen return err; 262e126ba97SEli Cohen } 263e126ba97SEli Cohen } 264e126ba97SEli Cohen 265e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 266e126ba97SEli Cohen return err; 267e126ba97SEli Cohen } 268e126ba97SEli Cohen 26989d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 27089d44f0aSMajd Dibbiny { 27189d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27289d44f0aSMajd Dibbiny int err = 0; 27389d44f0aSMajd Dibbiny 27489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27689d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27789d44f0aSMajd Dibbiny if (!err) 27889d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27989d44f0aSMajd Dibbiny } 28089d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28189d44f0aSMajd Dibbiny 28289d44f0aSMajd Dibbiny return err; 28389d44f0aSMajd Dibbiny } 28489d44f0aSMajd Dibbiny 28589d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28689d44f0aSMajd Dibbiny { 28789d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28889d44f0aSMajd Dibbiny 28989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 29089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29189d44f0aSMajd Dibbiny pci_disable_device(pdev); 29289d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29389d44f0aSMajd Dibbiny } 29489d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29589d44f0aSMajd Dibbiny } 29689d44f0aSMajd Dibbiny 297e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 298e126ba97SEli Cohen { 299e126ba97SEli Cohen int err = 0; 300e126ba97SEli Cohen 301e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3021a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 303e126ba97SEli Cohen return -ENODEV; 304e126ba97SEli Cohen } 305e126ba97SEli Cohen 306e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 307e126ba97SEli Cohen if (err) 308e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 309e126ba97SEli Cohen 310e126ba97SEli Cohen return err; 311e126ba97SEli Cohen } 312e126ba97SEli Cohen 313e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 314e126ba97SEli Cohen { 315e126ba97SEli Cohen pci_release_regions(pdev); 316e126ba97SEli Cohen } 317e126ba97SEli Cohen 318bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 319e126ba97SEli Cohen u8 he; 320e126ba97SEli Cohen u8 rsvd[15]; 321e126ba97SEli Cohen }; 322e126ba97SEli Cohen 32387b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32487b8de49SEli Cohen 32587b8de49SEli Cohen enum { 32687b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 327c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 32887b8de49SEli Cohen }; 32987b8de49SEli Cohen 3302974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 331c7a08ac7SEli Cohen { 332c7a08ac7SEli Cohen switch (size) { 333c7a08ac7SEli Cohen case 128: 334c7a08ac7SEli Cohen return 0; 335c7a08ac7SEli Cohen case 256: 336c7a08ac7SEli Cohen return 1; 337c7a08ac7SEli Cohen case 512: 338c7a08ac7SEli Cohen return 2; 339c7a08ac7SEli Cohen case 1024: 340c7a08ac7SEli Cohen return 3; 341c7a08ac7SEli Cohen case 2048: 342c7a08ac7SEli Cohen return 4; 343c7a08ac7SEli Cohen case 4096: 344c7a08ac7SEli Cohen return 5; 345c7a08ac7SEli Cohen default: 3462974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 347c7a08ac7SEli Cohen return 0; 348c7a08ac7SEli Cohen } 349c7a08ac7SEli Cohen } 350c7a08ac7SEli Cohen 351b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 352b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 353938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 354c7a08ac7SEli Cohen { 355b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 356b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 357938fe83cSSaeed Mahameed void *out, *hca_caps; 358938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 359c7a08ac7SEli Cohen int err; 360c7a08ac7SEli Cohen 361b775516bSEli Cohen memset(in, 0, sizeof(in)); 362b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 363c7a08ac7SEli Cohen if (!out) 364c7a08ac7SEli Cohen return -ENOMEM; 365938fe83cSSaeed Mahameed 366b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 367b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3683ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 369c7a08ac7SEli Cohen if (err) { 370938fe83cSSaeed Mahameed mlx5_core_warn(dev, 371938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 372938fe83cSSaeed Mahameed cap_type, cap_mode, err); 373c7a08ac7SEli Cohen goto query_ex; 374c7a08ac7SEli Cohen } 375c7a08ac7SEli Cohen 376938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 377938fe83cSSaeed Mahameed 378938fe83cSSaeed Mahameed switch (cap_mode) { 379938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 380701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 381938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 382938fe83cSSaeed Mahameed break; 383938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 384701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 385938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 386938fe83cSSaeed Mahameed break; 387938fe83cSSaeed Mahameed default: 388938fe83cSSaeed Mahameed mlx5_core_warn(dev, 389938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 390938fe83cSSaeed Mahameed cap_type, cap_mode); 391938fe83cSSaeed Mahameed err = -EINVAL; 392938fe83cSSaeed Mahameed break; 393938fe83cSSaeed Mahameed } 394c7a08ac7SEli Cohen query_ex: 395c7a08ac7SEli Cohen kfree(out); 396c7a08ac7SEli Cohen return err; 397c7a08ac7SEli Cohen } 398c7a08ac7SEli Cohen 399b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 400b06e7de8SLeon Romanovsky { 401b06e7de8SLeon Romanovsky int ret; 402b06e7de8SLeon Romanovsky 403b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 404b06e7de8SLeon Romanovsky if (ret) 405b06e7de8SLeon Romanovsky return ret; 406b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 407b06e7de8SLeon Romanovsky } 408b06e7de8SLeon Romanovsky 409a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 410c7a08ac7SEli Cohen { 411b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 412f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4133ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 414c7a08ac7SEli Cohen } 41587b8de49SEli Cohen 416a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 417f91e6d89SEran Ben Elisha { 418f91e6d89SEran Ben Elisha void *set_hca_cap; 419f91e6d89SEran Ben Elisha int req_endianness; 420f91e6d89SEran Ben Elisha int err; 421f91e6d89SEran Ben Elisha 422a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 423a2a322f4SLeon Romanovsky return 0; 424a2a322f4SLeon Romanovsky 425b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 426f91e6d89SEran Ben Elisha if (err) 427f91e6d89SEran Ben Elisha return err; 428f91e6d89SEran Ben Elisha 429f91e6d89SEran Ben Elisha req_endianness = 430f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 431bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 432f91e6d89SEran Ben Elisha 433f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 434f91e6d89SEran Ben Elisha return 0; 435f91e6d89SEran Ben Elisha 436f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 437f91e6d89SEran Ben Elisha 438f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 439bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 440f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 441f91e6d89SEran Ben Elisha 442a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 443f91e6d89SEran Ben Elisha } 444f91e6d89SEran Ben Elisha 445a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 44646861e3eSMoni Shoua { 44746861e3eSMoni Shoua void *set_hca_cap; 448fca22e7eSMoni Shoua bool do_set = false; 44946861e3eSMoni Shoua int err; 45046861e3eSMoni Shoua 45137b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 45237b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 45346861e3eSMoni Shoua return 0; 45446861e3eSMoni Shoua 45546861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 45646861e3eSMoni Shoua if (err) 45746861e3eSMoni Shoua return err; 45846861e3eSMoni Shoua 45946861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 46046861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 46146861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 46246861e3eSMoni Shoua 463fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 464fca22e7eSMoni Shoua do { \ 465fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 466fca22e7eSMoni Shoua if (_res) { \ 467fca22e7eSMoni Shoua do_set = true; \ 468fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 469fca22e7eSMoni Shoua } \ 470fca22e7eSMoni Shoua } while (0) 47146861e3eSMoni Shoua 472fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 473fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 474fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 475fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 476fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 477fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 478fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 479fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 48000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 48100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 48200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 48300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 48400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 48500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 48646861e3eSMoni Shoua 487a2a322f4SLeon Romanovsky if (!do_set) 488a2a322f4SLeon Romanovsky return 0; 48946861e3eSMoni Shoua 490a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 49146861e3eSMoni Shoua } 49246861e3eSMoni Shoua 493a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 494e126ba97SEli Cohen { 495c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 496938fe83cSSaeed Mahameed void *set_hca_cap; 497a2a322f4SLeon Romanovsky int err; 498e126ba97SEli Cohen 499b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 500c7a08ac7SEli Cohen if (err) 501a2a322f4SLeon Romanovsky return err; 502e126ba97SEli Cohen 503938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 504938fe83cSSaeed Mahameed capability); 505701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 506938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 507938fe83cSSaeed Mahameed 508938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 509707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 510938fe83cSSaeed Mahameed 128); 511c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 512938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5132974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 514e126ba97SEli Cohen 515883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 516883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 517883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 518883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 519883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 520883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 521883371c4SNoa Osherovich } 522c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 523938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 524938fe83cSSaeed Mahameed prof->log_max_qp); 525e126ba97SEli Cohen 526938fe83cSSaeed Mahameed /* disable cmdif checksum */ 527938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 528c1868b82SEli Cohen 52991828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 53091828bd8SMajd Dibbiny * than 4K. 53191828bd8SMajd Dibbiny */ 53291828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 533f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 534f502d834SEli Cohen 535fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 536fe1e1876SCarol L Soto 537f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 538f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 539f32f5bd2SDaniel Jurgens set_hca_cap, 540f32f5bd2SDaniel Jurgens cache_line_128byte, 541c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 542f32f5bd2SDaniel Jurgens 543dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 544dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 545dd44572aSMoni Shoua 546c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 547c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 548c4b76d8dSDaniel Jurgens set_hca_cap, 549c4b76d8dSDaniel Jurgens num_vhca_ports, 550c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 551c4b76d8dSDaniel Jurgens 552c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 553c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 554c6168161SEran Ben Elisha 555a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 556e126ba97SEli Cohen } 557cd23b14bSEli Cohen 55859e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 55959e9e8e4SMark Zhang { 56059e9e8e4SMark Zhang void *set_hca_cap; 56159e9e8e4SMark Zhang int err; 56259e9e8e4SMark Zhang 56359e9e8e4SMark Zhang if (!MLX5_CAP_GEN(dev, roce)) 56459e9e8e4SMark Zhang return 0; 56559e9e8e4SMark Zhang 56659e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 56759e9e8e4SMark Zhang if (err) 56859e9e8e4SMark Zhang return err; 56959e9e8e4SMark Zhang 57059e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 57159e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 57259e9e8e4SMark Zhang return 0; 57359e9e8e4SMark Zhang 57459e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 57559e9e8e4SMark Zhang memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 57659e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 57759e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 57859e9e8e4SMark Zhang 57959e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 580e126ba97SEli Cohen return err; 581e126ba97SEli Cohen } 582e126ba97SEli Cohen 58337b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 58437b6bb77SLeon Romanovsky { 585a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 586a2a322f4SLeon Romanovsky void *set_ctx; 58737b6bb77SLeon Romanovsky int err; 58837b6bb77SLeon Romanovsky 589a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 590a2a322f4SLeon Romanovsky if (!set_ctx) 591a2a322f4SLeon Romanovsky return -ENOMEM; 592a2a322f4SLeon Romanovsky 593a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 59437b6bb77SLeon Romanovsky if (err) { 59598a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 59637b6bb77SLeon Romanovsky goto out; 59737b6bb77SLeon Romanovsky } 59837b6bb77SLeon Romanovsky 599a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 600a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 60137b6bb77SLeon Romanovsky if (err) { 60298a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 60337b6bb77SLeon Romanovsky goto out; 60437b6bb77SLeon Romanovsky } 60537b6bb77SLeon Romanovsky 606a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 607a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 60837b6bb77SLeon Romanovsky if (err) { 60998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 61037b6bb77SLeon Romanovsky goto out; 61137b6bb77SLeon Romanovsky } 61237b6bb77SLeon Romanovsky 61359e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 61459e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 61559e9e8e4SMark Zhang if (err) { 61659e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 61759e9e8e4SMark Zhang goto out; 61859e9e8e4SMark Zhang } 61959e9e8e4SMark Zhang 62037b6bb77SLeon Romanovsky out: 621a2a322f4SLeon Romanovsky kfree(set_ctx); 62237b6bb77SLeon Romanovsky return err; 62337b6bb77SLeon Romanovsky } 62437b6bb77SLeon Romanovsky 625e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 626e126ba97SEli Cohen { 627bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 628bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 629e126ba97SEli Cohen int err; 630e126ba97SEli Cohen 631fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 632fc50db98SEli Cohen return 0; 633fc50db98SEli Cohen 634e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 635e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 636e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 637e126ba97SEli Cohen &he_out, sizeof(he_out), 638e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 639e126ba97SEli Cohen return err; 640e126ba97SEli Cohen } 641e126ba97SEli Cohen 642c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 643c85023e1SHuy Nguyen { 644c85023e1SHuy Nguyen int ret = 0; 645c85023e1SHuy Nguyen 646c85023e1SHuy Nguyen /* Disable local_lb by default */ 6478978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 648c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 649c85023e1SHuy Nguyen 650c85023e1SHuy Nguyen return ret; 651c85023e1SHuy Nguyen } 652c85023e1SHuy Nguyen 6530b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 654e126ba97SEli Cohen { 6553ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 656e126ba97SEli Cohen 6570b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6580b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 65922e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 66022e939a9SBodong Wang dev->caps.embedded_cpu); 6613ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 662e126ba97SEli Cohen } 663e126ba97SEli Cohen 6640b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 665e126ba97SEli Cohen { 6663ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 667e126ba97SEli Cohen 6680b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6690b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 67022e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 67122e939a9SBodong Wang dev->caps.embedded_cpu); 6723ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 673e126ba97SEli Cohen } 674e126ba97SEli Cohen 675f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 676f62b8bb8SAmir Vadai { 6773ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 6783ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 679f62b8bb8SAmir Vadai u32 sup_issi; 680c4f287c4SSaeed Mahameed int err; 681f62b8bb8SAmir Vadai 682f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 6833ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 684f62b8bb8SAmir Vadai if (err) { 685c4f287c4SSaeed Mahameed u32 syndrome; 686c4f287c4SSaeed Mahameed u8 status; 687c4f287c4SSaeed Mahameed 688c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 689f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 690f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 691f9c14e46SKamal Heib err, status, syndrome); 692f9c14e46SKamal Heib return err; 693f62b8bb8SAmir Vadai } 694f62b8bb8SAmir Vadai 695f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 696f9c14e46SKamal Heib dev->issi = 0; 697f9c14e46SKamal Heib return 0; 698f62b8bb8SAmir Vadai } 699f62b8bb8SAmir Vadai 700f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 701f62b8bb8SAmir Vadai 702f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7033ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 704f62b8bb8SAmir Vadai 705f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 706f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7073ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 708f62b8bb8SAmir Vadai if (err) { 709f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 710f9c14e46SKamal Heib err); 711f62b8bb8SAmir Vadai return err; 712f62b8bb8SAmir Vadai } 713f62b8bb8SAmir Vadai 714f62b8bb8SAmir Vadai dev->issi = 1; 715f62b8bb8SAmir Vadai 716f62b8bb8SAmir Vadai return 0; 717e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 718f62b8bb8SAmir Vadai return 0; 719f62b8bb8SAmir Vadai } 720f62b8bb8SAmir Vadai 7219eb78923SOr Gerlitz return -EOPNOTSUPP; 722f62b8bb8SAmir Vadai } 723f62b8bb8SAmir Vadai 72411f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 72511f3b84dSSaeed Mahameed const struct pci_device_id *id) 726a31208b1SMajd Dibbiny { 727868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 728a31208b1SMajd Dibbiny int err = 0; 729a31208b1SMajd Dibbiny 730d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 731e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 732e126ba97SEli Cohen 733aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 734311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 735311c7c71SSaeed Mahameed 73689d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 737e126ba97SEli Cohen if (err) { 73898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 73911f3b84dSSaeed Mahameed return err; 740e126ba97SEli Cohen } 741e126ba97SEli Cohen 742e126ba97SEli Cohen err = request_bar(pdev); 743e126ba97SEli Cohen if (err) { 74498a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 745e126ba97SEli Cohen goto err_disable; 746e126ba97SEli Cohen } 747e126ba97SEli Cohen 748e126ba97SEli Cohen pci_set_master(pdev); 749e126ba97SEli Cohen 750e126ba97SEli Cohen err = set_dma_caps(pdev); 751e126ba97SEli Cohen if (err) { 75298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 753e126ba97SEli Cohen goto err_clr_master; 754e126ba97SEli Cohen } 755e126ba97SEli Cohen 756ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 757ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 758ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 759ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 760ce4eee53SMichael Guralnik 761aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 762e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 763e126ba97SEli Cohen if (!dev->iseg) { 764e126ba97SEli Cohen err = -ENOMEM; 76598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 766e126ba97SEli Cohen goto err_clr_master; 767e126ba97SEli Cohen } 768a31208b1SMajd Dibbiny 769b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 770c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 771a31208b1SMajd Dibbiny return 0; 772a31208b1SMajd Dibbiny 773a31208b1SMajd Dibbiny err_clr_master: 774a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 775a31208b1SMajd Dibbiny release_bar(dev->pdev); 776a31208b1SMajd Dibbiny err_disable: 77789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 778a31208b1SMajd Dibbiny return err; 779a31208b1SMajd Dibbiny } 780a31208b1SMajd Dibbiny 781868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 782a31208b1SMajd Dibbiny { 783a31208b1SMajd Dibbiny iounmap(dev->iseg); 784a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 785a31208b1SMajd Dibbiny release_bar(dev->pdev); 78689d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 787a31208b1SMajd Dibbiny } 788a31208b1SMajd Dibbiny 789868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 79059211bd3SMohamad Haj Yahia { 79159211bd3SMohamad Haj Yahia int err; 79259211bd3SMohamad Haj Yahia 793868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 794868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 79598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 796868bc06bSSaeed Mahameed dev->priv.devcom); 797fadd59fcSAviv Heller 79859211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 79959211bd3SMohamad Haj Yahia if (err) { 80098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 801fadd59fcSAviv Heller goto err_devcom; 80259211bd3SMohamad Haj Yahia } 80359211bd3SMohamad Haj Yahia 804561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 805561aa15aSYuval Avnery if (err) { 806561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 807561aa15aSYuval Avnery goto err_devcom; 808561aa15aSYuval Avnery } 809561aa15aSYuval Avnery 810f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 81159211bd3SMohamad Haj Yahia if (err) { 81298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 813561aa15aSYuval Avnery goto err_irq_cleanup; 81459211bd3SMohamad Haj Yahia } 81559211bd3SMohamad Haj Yahia 81669c1280bSSaeed Mahameed err = mlx5_events_init(dev); 81769c1280bSSaeed Mahameed if (err) { 81898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 81969c1280bSSaeed Mahameed goto err_eq_cleanup; 82069c1280bSSaeed Mahameed } 82169c1280bSSaeed Mahameed 8229f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 82359211bd3SMohamad Haj Yahia 82452ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 82552ec462eSIlan Tayari 8267c39afb3SFeras Daoud mlx5_init_clock(dev); 8277c39afb3SFeras Daoud 828358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8290ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 830358aa5ceSSaeed Mahameed 83159211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 83259211bd3SMohamad Haj Yahia if (err) { 83398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 83459211bd3SMohamad Haj Yahia goto err_tables_cleanup; 83559211bd3SMohamad Haj Yahia } 83659211bd3SMohamad Haj Yahia 837eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 838eeb66cdbSSaeed Mahameed if (err) { 83998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 840eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 841eeb66cdbSSaeed Mahameed } 842eeb66cdbSSaeed Mahameed 843c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 844c2d6e31aSMohamad Haj Yahia if (err) { 84598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 84686eec50bSBodong Wang goto err_mpfs_cleanup; 84786eec50bSBodong Wang } 84886eec50bSBodong Wang 84986eec50bSBodong Wang err = mlx5_eswitch_init(dev); 85086eec50bSBodong Wang if (err) { 85186eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 85286eec50bSBodong Wang goto err_sriov_cleanup; 853c2d6e31aSMohamad Haj Yahia } 854c2d6e31aSMohamad Haj Yahia 8559410733cSIlan Tayari err = mlx5_fpga_init(dev); 8569410733cSIlan Tayari if (err) { 85798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 85886eec50bSBodong Wang goto err_eswitch_cleanup; 8599410733cSIlan Tayari } 8609410733cSIlan Tayari 861c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 862c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 863c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 864c9b9dcb4SAriel Levkovich 86524406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 86687175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 86712206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 86824406953SFeras Daoud 86959211bd3SMohamad Haj Yahia return 0; 87059211bd3SMohamad Haj Yahia 871c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 872c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 87386eec50bSBodong Wang err_sriov_cleanup: 87486eec50bSBodong Wang mlx5_sriov_cleanup(dev); 875eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 876eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 877c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 878c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 87959211bd3SMohamad Haj Yahia err_tables_cleanup: 8800ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 881358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 88202d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 88369c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 88459211bd3SMohamad Haj Yahia err_eq_cleanup: 885f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 886561aa15aSYuval Avnery err_irq_cleanup: 887561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 888fadd59fcSAviv Heller err_devcom: 889fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 89059211bd3SMohamad Haj Yahia 89159211bd3SMohamad Haj Yahia return err; 89259211bd3SMohamad Haj Yahia } 89359211bd3SMohamad Haj Yahia 89459211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 89559211bd3SMohamad Haj Yahia { 89612206b17SAya Levin mlx5_rsc_dump_destroy(dev); 89787175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 89824406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 899c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9009410733cSIlan Tayari mlx5_fpga_cleanup(dev); 901c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 90286eec50bSBodong Wang mlx5_sriov_cleanup(dev); 903eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 90459211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9050ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 906358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9077c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 90852ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 90902d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 91069c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 911f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 912561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 913fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 91459211bd3SMohamad Haj Yahia } 91559211bd3SMohamad Haj Yahia 916e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 917a31208b1SMajd Dibbiny { 918a31208b1SMajd Dibbiny int err; 919a31208b1SMajd Dibbiny 92098a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 921e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 922e126ba97SEli Cohen 92300c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 92400c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 92500c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 92600c6bcb0STal Gilboa 9276c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9286c780a02SEli Cohen */ 929b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9306c780a02SEli Cohen if (err) { 93198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9326c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 933e161105eSSaeed Mahameed return err; 9346c780a02SEli Cohen } 9356c780a02SEli Cohen 936e126ba97SEli Cohen err = mlx5_cmd_init(dev); 937e126ba97SEli Cohen if (err) { 93898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 939e161105eSSaeed Mahameed return err; 940e126ba97SEli Cohen } 941e126ba97SEli Cohen 942b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 943e3297246SEli Cohen if (err) { 94498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 945e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 94655378a23SMohamad Haj Yahia goto err_cmd_cleanup; 947e3297246SEli Cohen } 948e3297246SEli Cohen 949f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 950f7936dddSEran Ben Elisha 9510b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 952cd23b14bSEli Cohen if (err) { 95398a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 95459211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 955cd23b14bSEli Cohen } 956cd23b14bSEli Cohen 957f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 958f62b8bb8SAmir Vadai if (err) { 95998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 960f62b8bb8SAmir Vadai goto err_disable_hca; 961f62b8bb8SAmir Vadai } 962f62b8bb8SAmir Vadai 963cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 964cd23b14bSEli Cohen if (err) { 96598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 966cd23b14bSEli Cohen goto err_disable_hca; 967cd23b14bSEli Cohen } 968cd23b14bSEli Cohen 969e126ba97SEli Cohen err = set_hca_ctrl(dev); 970e126ba97SEli Cohen if (err) { 97198a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 972cd23b14bSEli Cohen goto reclaim_boot_pages; 973e126ba97SEli Cohen } 974e126ba97SEli Cohen 97537b6bb77SLeon Romanovsky err = set_hca_cap(dev); 976e126ba97SEli Cohen if (err) { 97798a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 97846861e3eSMoni Shoua goto reclaim_boot_pages; 97946861e3eSMoni Shoua } 98046861e3eSMoni Shoua 981cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 982e126ba97SEli Cohen if (err) { 98398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 984cd23b14bSEli Cohen goto reclaim_boot_pages; 985e126ba97SEli Cohen } 986e126ba97SEli Cohen 9878737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 988e126ba97SEli Cohen if (err) { 98998a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 9900cf53c12SSaeed Mahameed goto reclaim_boot_pages; 991e126ba97SEli Cohen } 992e126ba97SEli Cohen 993012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 994012e50e1SHuy Nguyen 995e126ba97SEli Cohen mlx5_start_health_poll(dev); 996e126ba97SEli Cohen 997bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 998bba1574cSDaniel Jurgens if (err) { 99998a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1000e161105eSSaeed Mahameed goto stop_health; 1001bba1574cSDaniel Jurgens } 1002bba1574cSDaniel Jurgens 1003e161105eSSaeed Mahameed return 0; 1004e161105eSSaeed Mahameed 1005e161105eSSaeed Mahameed stop_health: 1006e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1007e161105eSSaeed Mahameed reclaim_boot_pages: 1008e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1009e161105eSSaeed Mahameed err_disable_hca: 1010e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1011e161105eSSaeed Mahameed err_cmd_cleanup: 1012f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1013e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1014e161105eSSaeed Mahameed 1015e161105eSSaeed Mahameed return err; 1016e161105eSSaeed Mahameed } 1017e161105eSSaeed Mahameed 1018e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1019e161105eSSaeed Mahameed { 1020e161105eSSaeed Mahameed int err; 1021e161105eSSaeed Mahameed 1022e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1023e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1024259bbc57SMaor Gottlieb if (err) { 102598a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1026e161105eSSaeed Mahameed return err; 1027e126ba97SEli Cohen } 1028e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1029e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1030f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1031e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1032e161105eSSaeed Mahameed 1033e161105eSSaeed Mahameed return 0; 1034259bbc57SMaor Gottlieb } 1035e126ba97SEli Cohen 1036a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1037e161105eSSaeed Mahameed { 1038e161105eSSaeed Mahameed int err; 1039e161105eSSaeed Mahameed 104001187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 104172f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 104298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 104372f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1044a80d1b68SSaeed Mahameed return err; 1045e126ba97SEli Cohen } 1046e126ba97SEli Cohen 104769c1280bSSaeed Mahameed mlx5_events_start(dev); 10480cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10490cf53c12SSaeed Mahameed 1050e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1051e1706e62SYuval Avnery if (err) { 1052e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1053e1706e62SYuval Avnery goto err_irq_table; 1054e1706e62SYuval Avnery } 1055e1706e62SYuval Avnery 1056c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1057e126ba97SEli Cohen if (err) { 105898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1059c8e21b3bSSaeed Mahameed goto err_eq_table; 1060e126ba97SEli Cohen } 1061e126ba97SEli Cohen 106224406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 106324406953SFeras Daoud if (err) { 106498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 106524406953SFeras Daoud goto err_fw_tracer; 106624406953SFeras Daoud } 106724406953SFeras Daoud 106887175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 106987175120SEran Ben Elisha 107012206b17SAya Levin err = mlx5_rsc_dump_init(dev); 107112206b17SAya Levin if (err) { 107212206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 107312206b17SAya Levin goto err_rsc_dump; 107412206b17SAya Levin } 107512206b17SAya Levin 107604e87170SMatan Barak err = mlx5_fpga_device_start(dev); 107704e87170SMatan Barak if (err) { 107898a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 107904e87170SMatan Barak goto err_fpga_start; 108004e87170SMatan Barak } 108104e87170SMatan Barak 108204e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 108304e87170SMatan Barak if (err) { 108498a8e6fcSHuy Nguyen mlx5_core_err(dev, "IPSec device start failed %d\n", err); 108504e87170SMatan Barak goto err_ipsec_start; 108604e87170SMatan Barak } 108704e87170SMatan Barak 10881ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 10891ae17322SIlya Lesokhin if (err) { 109098a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 10911ae17322SIlya Lesokhin goto err_tls_start; 10921ae17322SIlya Lesokhin } 10931ae17322SIlya Lesokhin 109486d722adSMaor Gottlieb err = mlx5_init_fs(dev); 109586d722adSMaor Gottlieb if (err) { 109698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 109786d722adSMaor Gottlieb goto err_fs; 109886d722adSMaor Gottlieb } 10991466cc5bSYevgeny Petrilin 1100c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1101c85023e1SHuy Nguyen if (err) { 110298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 110387883929SSaeed Mahameed goto err_sriov; 1104c85023e1SHuy Nguyen } 1105c85023e1SHuy Nguyen 1106c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1107fc50db98SEli Cohen if (err) { 110898a8e6fcSHuy Nguyen mlx5_core_err(dev, "sriov init failed %d\n", err); 1109fc50db98SEli Cohen goto err_sriov; 1110fc50db98SEli Cohen } 1111fc50db98SEli Cohen 111222e939a9SBodong Wang err = mlx5_ec_init(dev); 111322e939a9SBodong Wang if (err) { 111498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 111522e939a9SBodong Wang goto err_ec; 111622e939a9SBodong Wang } 111722e939a9SBodong Wang 1118a80d1b68SSaeed Mahameed return 0; 1119a80d1b68SSaeed Mahameed 1120a80d1b68SSaeed Mahameed err_ec: 1121a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1122a80d1b68SSaeed Mahameed err_sriov: 1123a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1124a80d1b68SSaeed Mahameed err_fs: 1125a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1126a80d1b68SSaeed Mahameed err_tls_start: 1127a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1128a80d1b68SSaeed Mahameed err_ipsec_start: 1129a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1130a80d1b68SSaeed Mahameed err_fpga_start: 113112206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 113212206b17SAya Levin err_rsc_dump: 113387175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1134a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1135a80d1b68SSaeed Mahameed err_fw_tracer: 1136a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1137a80d1b68SSaeed Mahameed err_eq_table: 1138e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1139e1706e62SYuval Avnery err_irq_table: 1140a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1141a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1142a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1143a80d1b68SSaeed Mahameed return err; 1144a80d1b68SSaeed Mahameed } 1145a80d1b68SSaeed Mahameed 1146a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1147a80d1b68SSaeed Mahameed { 1148a80d1b68SSaeed Mahameed mlx5_ec_cleanup(dev); 1149a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1150a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1151a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1152a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1153a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 115412206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 115587175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 1156a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1157a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1158e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1159a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1160a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1161a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1162a80d1b68SSaeed Mahameed } 1163a80d1b68SSaeed Mahameed 11644383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1165a80d1b68SSaeed Mahameed { 1166a80d1b68SSaeed Mahameed int err = 0; 1167a80d1b68SSaeed Mahameed 1168a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1169a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1170a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1171a80d1b68SSaeed Mahameed goto out; 1172a80d1b68SSaeed Mahameed } 1173a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1174a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1175a80d1b68SSaeed Mahameed 1176a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1177a80d1b68SSaeed Mahameed if (err) 11784f7400d5SShay Drory goto err_function; 1179a80d1b68SSaeed Mahameed 1180a80d1b68SSaeed Mahameed if (boot) { 1181a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1182a80d1b68SSaeed Mahameed if (err) { 118398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1184a80d1b68SSaeed Mahameed goto function_teardown; 1185a80d1b68SSaeed Mahameed } 1186a80d1b68SSaeed Mahameed } 1187a80d1b68SSaeed Mahameed 1188a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1189a80d1b68SSaeed Mahameed if (err) 1190a80d1b68SSaeed Mahameed goto err_load; 1191a80d1b68SSaeed Mahameed 1192a6f3b623SMichael Guralnik if (boot) { 1193a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1194a6f3b623SMichael Guralnik if (err) 1195a6f3b623SMichael Guralnik goto err_devlink_reg; 1196a6f3b623SMichael Guralnik } 1197a6f3b623SMichael Guralnik 1198ecd01db8SParav Pandit if (mlx5_device_registered(dev)) 1199737a234bSMohamad Haj Yahia mlx5_attach_device(dev); 1200ecd01db8SParav Pandit else 1201ecd01db8SParav Pandit mlx5_register_device(dev); 1202a31208b1SMajd Dibbiny 12035fc7197dSMajd Dibbiny set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 120489d44f0aSMajd Dibbiny 12054162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 12064162f58bSParav Pandit return 0; 1207e126ba97SEli Cohen 1208a6f3b623SMichael Guralnik err_devlink_reg: 1209a80d1b68SSaeed Mahameed mlx5_unload(dev); 1210a80d1b68SSaeed Mahameed err_load: 121159211bd3SMohamad Haj Yahia if (boot) 121259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1213e161105eSSaeed Mahameed function_teardown: 1214e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 12154f7400d5SShay Drory err_function: 121689d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 12174162f58bSParav Pandit out: 121889d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1219e126ba97SEli Cohen return err; 1220e126ba97SEli Cohen } 1221e126ba97SEli Cohen 1222f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1223e126ba97SEli Cohen { 122441798df9SParav Pandit if (cleanup) 12250000a5f2SParav Pandit mlx5_unregister_device(dev); 1226689a248dSDaniel Jurgens 122789d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 1228b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 122998a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 123089d44f0aSMajd Dibbiny __func__); 123159211bd3SMohamad Haj Yahia if (cleanup) 123259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 123389d44f0aSMajd Dibbiny goto out; 123489d44f0aSMajd Dibbiny } 12356b6adee3SMohamad Haj Yahia 12369ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12379ade8c7cSIlan Tayari 1238737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) 1239737a234bSMohamad Haj Yahia mlx5_detach_device(dev); 1240737a234bSMohamad Haj Yahia 1241a80d1b68SSaeed Mahameed mlx5_unload(dev); 1242a80d1b68SSaeed Mahameed 124359211bd3SMohamad Haj Yahia if (cleanup) 124459211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12450cf53c12SSaeed Mahameed 1246e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1247ac6ea6e8SEli Cohen out: 124889d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 12499603b61dSJack Morgenstein } 125064613d94SSaeed Mahameed 125127b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12529603b61dSJack Morgenstein { 125311f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12549603b61dSJack Morgenstein int err; 12559603b61dSJack Morgenstein 125611f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12579603b61dSJack Morgenstein 1258364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1259364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 126089d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1261d9aaed83SArtemy Kovalyov 126201187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 126301187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 126401187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 126501187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 126601187175SEli Cohen 126711f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 126811f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 126911f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 127011f3b84dSSaeed Mahameed 127127b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 127227b942fbSParav Pandit mlx5_debugfs_root); 127311f3b84dSSaeed Mahameed if (!priv->dbg_root) { 127427b942fbSParav Pandit dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 1275810cbb25SParav Pandit goto err_dbg_root; 12769603b61dSJack Morgenstein } 12779603b61dSJack Morgenstein 1278ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 127952c368dcSSaeed Mahameed if (err) 128052c368dcSSaeed Mahameed goto err_health_init; 1281ac6ea6e8SEli Cohen 12820cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 12830cf53c12SSaeed Mahameed if (err) 12840cf53c12SSaeed Mahameed goto err_pagealloc_init; 128559211bd3SMohamad Haj Yahia 128611f3b84dSSaeed Mahameed return 0; 128752c368dcSSaeed Mahameed 128852c368dcSSaeed Mahameed err_pagealloc_init: 128952c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 129052c368dcSSaeed Mahameed err_health_init: 129152c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1292810cbb25SParav Pandit err_dbg_root: 1293810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1294810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1295810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1296810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1297810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 129852c368dcSSaeed Mahameed return err; 129911f3b84dSSaeed Mahameed } 130011f3b84dSSaeed Mahameed 130111f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 130211f3b84dSSaeed Mahameed { 1303810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1304810cbb25SParav Pandit 130552c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 130652c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 130711f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1308810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1309810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1310810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1311810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1312810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 131311f3b84dSSaeed Mahameed } 131411f3b84dSSaeed Mahameed 131511f3b84dSSaeed Mahameed #define MLX5_IB_MOD "mlx5_ib" 131611f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 131711f3b84dSSaeed Mahameed { 131811f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 131911f3b84dSSaeed Mahameed struct devlink *devlink; 132011f3b84dSSaeed Mahameed int err; 132111f3b84dSSaeed Mahameed 13221f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 132311f3b84dSSaeed Mahameed if (!devlink) { 13241f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 132511f3b84dSSaeed Mahameed return -ENOMEM; 132611f3b84dSSaeed Mahameed } 132711f3b84dSSaeed Mahameed 132811f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 132927b942fbSParav Pandit dev->device = &pdev->dev; 133027b942fbSParav Pandit dev->pdev = pdev; 133111f3b84dSSaeed Mahameed 1332386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1333386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1334386e75afSHuy Nguyen 133527b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 133611f3b84dSSaeed Mahameed if (err) 133711f3b84dSSaeed Mahameed goto mdev_init_err; 133811f3b84dSSaeed Mahameed 133911f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 13409603b61dSJack Morgenstein if (err) { 134198a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 134298a8e6fcSHuy Nguyen err); 134311f3b84dSSaeed Mahameed goto pci_init_err; 13449603b61dSJack Morgenstein } 13459603b61dSJack Morgenstein 1346868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13479603b61dSJack Morgenstein if (err) { 134898a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 134998a8e6fcSHuy Nguyen err); 13500cf53c12SSaeed Mahameed goto err_load_one; 13519603b61dSJack Morgenstein } 135259211bd3SMohamad Haj Yahia 1353f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 13549603b61dSJack Morgenstein 13558b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13568b9d8baaSAlex Vesker if (err) 13578b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13588b9d8baaSAlex Vesker 13595d47f6c8SDaniel Jurgens pci_save_state(pdev); 13609603b61dSJack Morgenstein return 0; 13619603b61dSJack Morgenstein 13620cf53c12SSaeed Mahameed err_load_one: 1363868bc06bSSaeed Mahameed mlx5_pci_close(dev); 136411f3b84dSSaeed Mahameed pci_init_err: 136511f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 136611f3b84dSSaeed Mahameed mdev_init_err: 13671f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1368a31208b1SMajd Dibbiny 13699603b61dSJack Morgenstein return err; 13709603b61dSJack Morgenstein } 1371a31208b1SMajd Dibbiny 13729603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13739603b61dSJack Morgenstein { 13749603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1375feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 13769603b61dSJack Morgenstein 13778b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 13781f28d776SEran Ben Elisha mlx5_devlink_unregister(devlink); 1379737a234bSMohamad Haj Yahia 138041798df9SParav Pandit mlx5_drain_health_wq(dev); 1381f999b706SParav Pandit mlx5_unload_one(dev, true); 1382868bc06bSSaeed Mahameed mlx5_pci_close(dev); 138311f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 13841f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 13859603b61dSJack Morgenstein } 13869603b61dSJack Morgenstein 138789d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 138889d44f0aSMajd Dibbiny pci_channel_state_t state) 138989d44f0aSMajd Dibbiny { 139089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 139189d44f0aSMajd Dibbiny 139298a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 139304c0c1abSMohamad Haj Yahia 13948812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 13953e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1396868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 13975e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 139889d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 139905ac2c0bSMohamad Haj Yahia 140089d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 140189d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 140289d44f0aSMajd Dibbiny } 140389d44f0aSMajd Dibbiny 1404d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1405d57847dcSDaniel Jurgens * for the health counter to start counting. 140689d44f0aSMajd Dibbiny */ 1407d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 140889d44f0aSMajd Dibbiny { 140989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 141089d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 141189d44f0aSMajd Dibbiny const int niter = 100; 1412d57847dcSDaniel Jurgens u32 last_count = 0; 141389d44f0aSMajd Dibbiny u32 count; 141489d44f0aSMajd Dibbiny int i; 141589d44f0aSMajd Dibbiny 141689d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 141789d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 141889d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1419d57847dcSDaniel Jurgens if (last_count && last_count != count) { 142098a8e6fcSHuy Nguyen mlx5_core_info(dev, 142198a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 142298a8e6fcSHuy Nguyen count, i); 1423d57847dcSDaniel Jurgens return 0; 1424d57847dcSDaniel Jurgens } 1425d57847dcSDaniel Jurgens last_count = count; 142689d44f0aSMajd Dibbiny } 142789d44f0aSMajd Dibbiny msleep(50); 142889d44f0aSMajd Dibbiny } 142989d44f0aSMajd Dibbiny 1430d57847dcSDaniel Jurgens return -ETIMEDOUT; 143189d44f0aSMajd Dibbiny } 143289d44f0aSMajd Dibbiny 14331061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14341061c90fSMohamad Haj Yahia { 14351061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14361061c90fSMohamad Haj Yahia int err; 14371061c90fSMohamad Haj Yahia 143898a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14391061c90fSMohamad Haj Yahia 14401061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14411061c90fSMohamad Haj Yahia if (err) { 144298a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 144398a8e6fcSHuy Nguyen __func__, err); 14441061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14451061c90fSMohamad Haj Yahia } 14461061c90fSMohamad Haj Yahia 14471061c90fSMohamad Haj Yahia pci_set_master(pdev); 14481061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14495d47f6c8SDaniel Jurgens pci_save_state(pdev); 14501061c90fSMohamad Haj Yahia 14511061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 145298a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14531061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14541061c90fSMohamad Haj Yahia } 14551061c90fSMohamad Haj Yahia 14561061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 14571061c90fSMohamad Haj Yahia } 14581061c90fSMohamad Haj Yahia 145989d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 146089d44f0aSMajd Dibbiny { 146189d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 146289d44f0aSMajd Dibbiny int err; 146389d44f0aSMajd Dibbiny 146498a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 146589d44f0aSMajd Dibbiny 1466868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 146789d44f0aSMajd Dibbiny if (err) 146898a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 146998a8e6fcSHuy Nguyen __func__, err); 147089d44f0aSMajd Dibbiny else 147198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 147289d44f0aSMajd Dibbiny } 147389d44f0aSMajd Dibbiny 147489d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 147589d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 147689d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 147789d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 147889d44f0aSMajd Dibbiny }; 147989d44f0aSMajd Dibbiny 14808812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 14818812c24dSMajd Dibbiny { 1482fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1483fcd29ad1SFeras Daoud int ret = 1; 14848812c24dSMajd Dibbiny 1485fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1486fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1487fcd29ad1SFeras Daoud 1488fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1489fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1490fcd29ad1SFeras Daoud 1491fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 14928812c24dSMajd Dibbiny return -EOPNOTSUPP; 14938812c24dSMajd Dibbiny 14948812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 14958812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 14968812c24dSMajd Dibbiny return -EAGAIN; 14978812c24dSMajd Dibbiny } 14988812c24dSMajd Dibbiny 1499d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1500d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1501d2aa060dSHuy Nguyen */ 1502d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 150376d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1504d2aa060dSHuy Nguyen 1505fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1506fcd29ad1SFeras Daoud if (!ret) 1507fcd29ad1SFeras Daoud goto succeed; 1508fcd29ad1SFeras Daoud 15098812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1510fcd29ad1SFeras Daoud if (!ret) 1511fcd29ad1SFeras Daoud goto succeed; 1512fcd29ad1SFeras Daoud 15138812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1514d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 15158812c24dSMajd Dibbiny return ret; 15168812c24dSMajd Dibbiny 1517fcd29ad1SFeras Daoud succeed: 15188812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 15198812c24dSMajd Dibbiny 15201ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 15211ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 15221ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 15231ef903bfSDaniel Jurgens * contexts. 15241ef903bfSDaniel Jurgens */ 15251ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 15261ef903bfSDaniel Jurgens 15278812c24dSMajd Dibbiny return 0; 15288812c24dSMajd Dibbiny } 15298812c24dSMajd Dibbiny 15305fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15315fc7197dSMajd Dibbiny { 15325fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15338812c24dSMajd Dibbiny int err; 15345fc7197dSMajd Dibbiny 153598a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15368812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15378812c24dSMajd Dibbiny if (err) 1538868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15395fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15405fc7197dSMajd Dibbiny } 15415fc7197dSMajd Dibbiny 15429603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1543bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1544fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1545bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1546fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1547bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1548fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 15497092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 155064dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1551d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1552d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1553d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1554d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 155585327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 155685327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1557b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1558505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 15592e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 15602e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1561d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 15629603b61dSJack Morgenstein { 0, } 15639603b61dSJack Morgenstein }; 15649603b61dSJack Morgenstein 15659603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 15669603b61dSJack Morgenstein 156704c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 156804c0c1abSMohamad Haj Yahia { 1569b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1570b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 157104c0c1abSMohamad Haj Yahia } 157204c0c1abSMohamad Haj Yahia 157304c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 157404c0c1abSMohamad Haj Yahia { 157504c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 157604c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 157704c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 157804c0c1abSMohamad Haj Yahia } 157904c0c1abSMohamad Haj Yahia 15809603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 15819603b61dSJack Morgenstein .name = DRIVER_NAME, 15829603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 15839603b61dSJack Morgenstein .probe = init_one, 158489d44f0aSMajd Dibbiny .remove = remove_one, 15855fc7197dSMajd Dibbiny .shutdown = shutdown, 1586fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1587fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 15889603b61dSJack Morgenstein }; 1589e126ba97SEli Cohen 1590f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1591f663ad98SKamal Heib { 1592f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1593f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1594f663ad98SKamal Heib prof_sel, 1595f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1596f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1597f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1598f663ad98SKamal Heib } 1599f663ad98SKamal Heib } 1600f663ad98SKamal Heib 1601e126ba97SEli Cohen static int __init init(void) 1602e126ba97SEli Cohen { 1603e126ba97SEli Cohen int err; 1604e126ba97SEli Cohen 16058737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 16068737f818SDaniel Jurgens 1607f663ad98SKamal Heib mlx5_core_verify_params(); 1608c778dd31STariq Toukan mlx5_accel_ipsec_build_fs_cmds(); 1609e126ba97SEli Cohen mlx5_register_debugfs(); 1610e126ba97SEli Cohen 16119603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 16129603b61dSJack Morgenstein if (err) 1613ac6ea6e8SEli Cohen goto err_debug; 16149603b61dSJack Morgenstein 1615f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1616f62b8bb8SAmir Vadai mlx5e_init(); 1617f62b8bb8SAmir Vadai #endif 1618f62b8bb8SAmir Vadai 1619e126ba97SEli Cohen return 0; 1620e126ba97SEli Cohen 1621e126ba97SEli Cohen err_debug: 1622e126ba97SEli Cohen mlx5_unregister_debugfs(); 1623e126ba97SEli Cohen return err; 1624e126ba97SEli Cohen } 1625e126ba97SEli Cohen 1626e126ba97SEli Cohen static void __exit cleanup(void) 1627e126ba97SEli Cohen { 1628f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1629f62b8bb8SAmir Vadai mlx5e_cleanup(); 1630f62b8bb8SAmir Vadai #endif 16319603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1632e126ba97SEli Cohen mlx5_unregister_debugfs(); 1633e126ba97SEli Cohen } 1634e126ba97SEli Cohen 1635e126ba97SEli Cohen module_init(init); 1636e126ba97SEli Cohen module_exit(cleanup); 1637