1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53907af0f0SLeon Romanovsky #include <linux/version.h> 54feae9087SOr Gerlitz #include <net/devlink.h> 55e126ba97SEli Cohen #include "mlx5_core.h" 56f2f3df55SSaeed Mahameed #include "lib/eq.h" 5716d76083SSaeed Mahameed #include "fs_core.h" 58eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 59073bb189SSaeed Mahameed #include "eswitch.h" 601f28d776SEran Ben Elisha #include "devlink.h" 6138b9f903SMoshe Shemesh #include "fw_reset.h" 6252ec462eSIlan Tayari #include "lib/mlx5.h" 63e29341fbSIlan Tayari #include "fpga/core.h" 6405564d0aSAviad Yehezkel #include "fpga/ipsec.h" 65bebb23e6SIlan Tayari #include "accel/ipsec.h" 661ae17322SIlya Lesokhin #include "accel/tls.h" 677c39afb3SFeras Daoud #include "lib/clock.h" 68358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 690ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 70fadd59fcSAviv Heller #include "lib/devcom.h" 71b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7224406953SFeras Daoud #include "diag/fw_tracer.h" 73591905baSBodong Wang #include "ecpf.h" 7487175120SEran Ben Elisha #include "lib/hv_vhca.h" 7512206b17SAya Levin #include "diag/rsc_dump.h" 76f3196bb0SParav Pandit #include "sf/vhca_event.h" 7790d010b8SParav Pandit #include "sf/dev/dev.h" 78*6a327321SParav Pandit #include "sf/sf.h" 79e126ba97SEli Cohen 80e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 81048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 82e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 83e126ba97SEli Cohen 84f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 85f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 86e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 87e126ba97SEli Cohen 88f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 89f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 909603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 919603b61dSJack Morgenstein 928737f818SDaniel Jurgens static u32 sw_owner_id[4]; 938737f818SDaniel Jurgens 94f91e6d89SEran Ben Elisha enum { 95f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97f91e6d89SEran Ben Elisha }; 98f91e6d89SEran Ben Elisha 999603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1009603b61dSJack Morgenstein [0] = { 1019603b61dSJack Morgenstein .mask = 0, 1029603b61dSJack Morgenstein }, 1039603b61dSJack Morgenstein [1] = { 1049603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1059603b61dSJack Morgenstein .log_max_qp = 12, 1069603b61dSJack Morgenstein }, 1079603b61dSJack Morgenstein [2] = { 1089603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1099603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1105f40b4edSMaor Gottlieb .log_max_qp = 18, 1119603b61dSJack Morgenstein .mr_cache[0] = { 1129603b61dSJack Morgenstein .size = 500, 1139603b61dSJack Morgenstein .limit = 250 1149603b61dSJack Morgenstein }, 1159603b61dSJack Morgenstein .mr_cache[1] = { 1169603b61dSJack Morgenstein .size = 500, 1179603b61dSJack Morgenstein .limit = 250 1189603b61dSJack Morgenstein }, 1199603b61dSJack Morgenstein .mr_cache[2] = { 1209603b61dSJack Morgenstein .size = 500, 1219603b61dSJack Morgenstein .limit = 250 1229603b61dSJack Morgenstein }, 1239603b61dSJack Morgenstein .mr_cache[3] = { 1249603b61dSJack Morgenstein .size = 500, 1259603b61dSJack Morgenstein .limit = 250 1269603b61dSJack Morgenstein }, 1279603b61dSJack Morgenstein .mr_cache[4] = { 1289603b61dSJack Morgenstein .size = 500, 1299603b61dSJack Morgenstein .limit = 250 1309603b61dSJack Morgenstein }, 1319603b61dSJack Morgenstein .mr_cache[5] = { 1329603b61dSJack Morgenstein .size = 500, 1339603b61dSJack Morgenstein .limit = 250 1349603b61dSJack Morgenstein }, 1359603b61dSJack Morgenstein .mr_cache[6] = { 1369603b61dSJack Morgenstein .size = 500, 1379603b61dSJack Morgenstein .limit = 250 1389603b61dSJack Morgenstein }, 1399603b61dSJack Morgenstein .mr_cache[7] = { 1409603b61dSJack Morgenstein .size = 500, 1419603b61dSJack Morgenstein .limit = 250 1429603b61dSJack Morgenstein }, 1439603b61dSJack Morgenstein .mr_cache[8] = { 1449603b61dSJack Morgenstein .size = 500, 1459603b61dSJack Morgenstein .limit = 250 1469603b61dSJack Morgenstein }, 1479603b61dSJack Morgenstein .mr_cache[9] = { 1489603b61dSJack Morgenstein .size = 500, 1499603b61dSJack Morgenstein .limit = 250 1509603b61dSJack Morgenstein }, 1519603b61dSJack Morgenstein .mr_cache[10] = { 1529603b61dSJack Morgenstein .size = 500, 1539603b61dSJack Morgenstein .limit = 250 1549603b61dSJack Morgenstein }, 1559603b61dSJack Morgenstein .mr_cache[11] = { 1569603b61dSJack Morgenstein .size = 500, 1579603b61dSJack Morgenstein .limit = 250 1589603b61dSJack Morgenstein }, 1599603b61dSJack Morgenstein .mr_cache[12] = { 1609603b61dSJack Morgenstein .size = 64, 1619603b61dSJack Morgenstein .limit = 32 1629603b61dSJack Morgenstein }, 1639603b61dSJack Morgenstein .mr_cache[13] = { 1649603b61dSJack Morgenstein .size = 32, 1659603b61dSJack Morgenstein .limit = 16 1669603b61dSJack Morgenstein }, 1679603b61dSJack Morgenstein .mr_cache[14] = { 1689603b61dSJack Morgenstein .size = 16, 1699603b61dSJack Morgenstein .limit = 8 1709603b61dSJack Morgenstein }, 1719603b61dSJack Morgenstein .mr_cache[15] = { 1729603b61dSJack Morgenstein .size = 8, 1739603b61dSJack Morgenstein .limit = 4 1749603b61dSJack Morgenstein }, 1759603b61dSJack Morgenstein }, 1769603b61dSJack Morgenstein }; 177e126ba97SEli Cohen 178e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 179e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 180b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 181b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 182e3297246SEli Cohen 183555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 184555af0c3SParav Pandit { 185555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 186555af0c3SParav Pandit } 187555af0c3SParav Pandit 188b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189b8a92577SDaniel Jurgens u32 warn_time_mili) 190e3297246SEli Cohen { 191b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193e3297246SEli Cohen int err = 0; 194e3297246SEli Cohen 195b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 196b8a92577SDaniel Jurgens 197e3297246SEli Cohen while (fw_initializing(dev)) { 198e3297246SEli Cohen if (time_after(jiffies, end)) { 199e3297246SEli Cohen err = -EBUSY; 200e3297246SEli Cohen break; 201e3297246SEli Cohen } 202b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 203b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 204b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 205b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 206b8a92577SDaniel Jurgens } 207e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 208e3297246SEli Cohen } 209e3297246SEli Cohen 210e3297246SEli Cohen return err; 211e3297246SEli Cohen } 212e3297246SEli Cohen 213012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 214012e50e1SHuy Nguyen { 215012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 216012e50e1SHuy Nguyen driver_version); 2173ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 218012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 219012e50e1SHuy Nguyen char *string; 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 222012e50e1SHuy Nguyen return; 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 225012e50e1SHuy Nguyen 226012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 23217a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238907af0f0SLeon Romanovsky 239907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 240907af0f0SLeon Romanovsky (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff), 241907af0f0SLeon Romanovsky (u16)(LINUX_VERSION_CODE & 0xffff)); 242012e50e1SHuy Nguyen 243012e50e1SHuy Nguyen /*Send the command*/ 244012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 245012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 246012e50e1SHuy Nguyen 2473ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 248012e50e1SHuy Nguyen } 249012e50e1SHuy Nguyen 250e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 251e126ba97SEli Cohen { 252e126ba97SEli Cohen int err; 253e126ba97SEli Cohen 254e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 255e126ba97SEli Cohen if (err) { 2561a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 257e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 258e126ba97SEli Cohen if (err) { 2591a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 260e126ba97SEli Cohen return err; 261e126ba97SEli Cohen } 262e126ba97SEli Cohen } 263e126ba97SEli Cohen 264e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 265e126ba97SEli Cohen if (err) { 266e126ba97SEli Cohen dev_warn(&pdev->dev, 2671a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 268e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 269e126ba97SEli Cohen if (err) { 270e126ba97SEli Cohen dev_err(&pdev->dev, 2711a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 272e126ba97SEli Cohen return err; 273e126ba97SEli Cohen } 274e126ba97SEli Cohen } 275e126ba97SEli Cohen 276e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 277e126ba97SEli Cohen return err; 278e126ba97SEli Cohen } 279e126ba97SEli Cohen 28089d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 28189d44f0aSMajd Dibbiny { 28289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28389d44f0aSMajd Dibbiny int err = 0; 28489d44f0aSMajd Dibbiny 28589d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28689d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 28789d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 28889d44f0aSMajd Dibbiny if (!err) 28989d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 29089d44f0aSMajd Dibbiny } 29189d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29289d44f0aSMajd Dibbiny 29389d44f0aSMajd Dibbiny return err; 29489d44f0aSMajd Dibbiny } 29589d44f0aSMajd Dibbiny 29689d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 29789d44f0aSMajd Dibbiny { 29889d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29989d44f0aSMajd Dibbiny 30089d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 30189d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 30289d44f0aSMajd Dibbiny pci_disable_device(pdev); 30389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 30489d44f0aSMajd Dibbiny } 30589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 30689d44f0aSMajd Dibbiny } 30789d44f0aSMajd Dibbiny 308e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 309e126ba97SEli Cohen { 310e126ba97SEli Cohen int err = 0; 311e126ba97SEli Cohen 312e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3131a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 314e126ba97SEli Cohen return -ENODEV; 315e126ba97SEli Cohen } 316e126ba97SEli Cohen 31717a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 318e126ba97SEli Cohen if (err) 319e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 320e126ba97SEli Cohen 321e126ba97SEli Cohen return err; 322e126ba97SEli Cohen } 323e126ba97SEli Cohen 324e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 325e126ba97SEli Cohen { 326e126ba97SEli Cohen pci_release_regions(pdev); 327e126ba97SEli Cohen } 328e126ba97SEli Cohen 329bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 330e126ba97SEli Cohen u8 he; 331e126ba97SEli Cohen u8 rsvd[15]; 332e126ba97SEli Cohen }; 333e126ba97SEli Cohen 33487b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 33587b8de49SEli Cohen 33687b8de49SEli Cohen enum { 33787b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 338c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 33987b8de49SEli Cohen }; 34087b8de49SEli Cohen 3412974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 342c7a08ac7SEli Cohen { 343c7a08ac7SEli Cohen switch (size) { 344c7a08ac7SEli Cohen case 128: 345c7a08ac7SEli Cohen return 0; 346c7a08ac7SEli Cohen case 256: 347c7a08ac7SEli Cohen return 1; 348c7a08ac7SEli Cohen case 512: 349c7a08ac7SEli Cohen return 2; 350c7a08ac7SEli Cohen case 1024: 351c7a08ac7SEli Cohen return 3; 352c7a08ac7SEli Cohen case 2048: 353c7a08ac7SEli Cohen return 4; 354c7a08ac7SEli Cohen case 4096: 355c7a08ac7SEli Cohen return 5; 356c7a08ac7SEli Cohen default: 3572974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 358c7a08ac7SEli Cohen return 0; 359c7a08ac7SEli Cohen } 360c7a08ac7SEli Cohen } 361c7a08ac7SEli Cohen 362b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 363b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 364938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 365c7a08ac7SEli Cohen { 366b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 367b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 368938fe83cSSaeed Mahameed void *out, *hca_caps; 369938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 370c7a08ac7SEli Cohen int err; 371c7a08ac7SEli Cohen 372b775516bSEli Cohen memset(in, 0, sizeof(in)); 373b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 374c7a08ac7SEli Cohen if (!out) 375c7a08ac7SEli Cohen return -ENOMEM; 376938fe83cSSaeed Mahameed 377b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 378b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3793ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 380c7a08ac7SEli Cohen if (err) { 381938fe83cSSaeed Mahameed mlx5_core_warn(dev, 382938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 383938fe83cSSaeed Mahameed cap_type, cap_mode, err); 384c7a08ac7SEli Cohen goto query_ex; 385c7a08ac7SEli Cohen } 386c7a08ac7SEli Cohen 387938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 388938fe83cSSaeed Mahameed 389938fe83cSSaeed Mahameed switch (cap_mode) { 390938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 391701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 392938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 393938fe83cSSaeed Mahameed break; 394938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 395701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 396938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 397938fe83cSSaeed Mahameed break; 398938fe83cSSaeed Mahameed default: 399938fe83cSSaeed Mahameed mlx5_core_warn(dev, 400938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 401938fe83cSSaeed Mahameed cap_type, cap_mode); 402938fe83cSSaeed Mahameed err = -EINVAL; 403938fe83cSSaeed Mahameed break; 404938fe83cSSaeed Mahameed } 405c7a08ac7SEli Cohen query_ex: 406c7a08ac7SEli Cohen kfree(out); 407c7a08ac7SEli Cohen return err; 408c7a08ac7SEli Cohen } 409c7a08ac7SEli Cohen 410b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 411b06e7de8SLeon Romanovsky { 412b06e7de8SLeon Romanovsky int ret; 413b06e7de8SLeon Romanovsky 414b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 415b06e7de8SLeon Romanovsky if (ret) 416b06e7de8SLeon Romanovsky return ret; 417b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 418b06e7de8SLeon Romanovsky } 419b06e7de8SLeon Romanovsky 420a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 421c7a08ac7SEli Cohen { 422b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 423f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4243ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 425c7a08ac7SEli Cohen } 42687b8de49SEli Cohen 427a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 428f91e6d89SEran Ben Elisha { 429f91e6d89SEran Ben Elisha void *set_hca_cap; 430f91e6d89SEran Ben Elisha int req_endianness; 431f91e6d89SEran Ben Elisha int err; 432f91e6d89SEran Ben Elisha 433a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 434a2a322f4SLeon Romanovsky return 0; 435a2a322f4SLeon Romanovsky 436b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 437f91e6d89SEran Ben Elisha if (err) 438f91e6d89SEran Ben Elisha return err; 439f91e6d89SEran Ben Elisha 440f91e6d89SEran Ben Elisha req_endianness = 441f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 442bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 443f91e6d89SEran Ben Elisha 444f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 445f91e6d89SEran Ben Elisha return 0; 446f91e6d89SEran Ben Elisha 447f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 448f91e6d89SEran Ben Elisha 449f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 450bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 451f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 452f91e6d89SEran Ben Elisha 453a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 454f91e6d89SEran Ben Elisha } 455f91e6d89SEran Ben Elisha 456a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45746861e3eSMoni Shoua { 45846861e3eSMoni Shoua void *set_hca_cap; 459fca22e7eSMoni Shoua bool do_set = false; 46046861e3eSMoni Shoua int err; 46146861e3eSMoni Shoua 46237b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46337b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46446861e3eSMoni Shoua return 0; 46546861e3eSMoni Shoua 46646861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46746861e3eSMoni Shoua if (err) 46846861e3eSMoni Shoua return err; 46946861e3eSMoni Shoua 47046861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 47146861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 47246861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47346861e3eSMoni Shoua 474fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 475fca22e7eSMoni Shoua do { \ 476fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 477fca22e7eSMoni Shoua if (_res) { \ 478fca22e7eSMoni Shoua do_set = true; \ 479fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 480fca22e7eSMoni Shoua } \ 481fca22e7eSMoni Shoua } while (0) 48246861e3eSMoni Shoua 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 488fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 489fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 490fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 49100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 49200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 49300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 49400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49746861e3eSMoni Shoua 498a2a322f4SLeon Romanovsky if (!do_set) 499a2a322f4SLeon Romanovsky return 0; 50046861e3eSMoni Shoua 501a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 50246861e3eSMoni Shoua } 50346861e3eSMoni Shoua 504a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 505e126ba97SEli Cohen { 506c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 507938fe83cSSaeed Mahameed void *set_hca_cap; 508a2a322f4SLeon Romanovsky int err; 509e126ba97SEli Cohen 510b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 511c7a08ac7SEli Cohen if (err) 512a2a322f4SLeon Romanovsky return err; 513e126ba97SEli Cohen 514938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 515938fe83cSSaeed Mahameed capability); 516701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 517938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 518938fe83cSSaeed Mahameed 519938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 520707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 521938fe83cSSaeed Mahameed 128); 522c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 523938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5242974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 525e126ba97SEli Cohen 526883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 527883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 528883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 529883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 530883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 531883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 532883371c4SNoa Osherovich } 533c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 534938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 535938fe83cSSaeed Mahameed prof->log_max_qp); 536e126ba97SEli Cohen 537938fe83cSSaeed Mahameed /* disable cmdif checksum */ 538938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 539c1868b82SEli Cohen 54091828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 54191828bd8SMajd Dibbiny * than 4K. 54291828bd8SMajd Dibbiny */ 54391828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 544f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 545f502d834SEli Cohen 546fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 547fe1e1876SCarol L Soto 548f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 549f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 550f32f5bd2SDaniel Jurgens set_hca_cap, 551f32f5bd2SDaniel Jurgens cache_line_128byte, 552c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 553f32f5bd2SDaniel Jurgens 554dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 555dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 556dd44572aSMoni Shoua 557e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 558e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 559e7f4d0bcSMoshe Shemesh 560c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 561c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 562c4b76d8dSDaniel Jurgens set_hca_cap, 563c4b76d8dSDaniel Jurgens num_vhca_ports, 564c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 565c4b76d8dSDaniel Jurgens 566c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 567c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 568c6168161SEran Ben Elisha 5694dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 5704dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 5714dca6509SMichael Guralnik 572f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 573f3196bb0SParav Pandit 574a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 575e126ba97SEli Cohen } 576cd23b14bSEli Cohen 57759e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 57859e9e8e4SMark Zhang { 57959e9e8e4SMark Zhang void *set_hca_cap; 58059e9e8e4SMark Zhang int err; 58159e9e8e4SMark Zhang 58259e9e8e4SMark Zhang if (!MLX5_CAP_GEN(dev, roce)) 58359e9e8e4SMark Zhang return 0; 58459e9e8e4SMark Zhang 58559e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 58659e9e8e4SMark Zhang if (err) 58759e9e8e4SMark Zhang return err; 58859e9e8e4SMark Zhang 58959e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 59059e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 59159e9e8e4SMark Zhang return 0; 59259e9e8e4SMark Zhang 59359e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 59459e9e8e4SMark Zhang memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 59559e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 59659e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 59759e9e8e4SMark Zhang 59859e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 599e126ba97SEli Cohen return err; 600e126ba97SEli Cohen } 601e126ba97SEli Cohen 60237b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 60337b6bb77SLeon Romanovsky { 604a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 605a2a322f4SLeon Romanovsky void *set_ctx; 60637b6bb77SLeon Romanovsky int err; 60737b6bb77SLeon Romanovsky 608a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 609a2a322f4SLeon Romanovsky if (!set_ctx) 610a2a322f4SLeon Romanovsky return -ENOMEM; 611a2a322f4SLeon Romanovsky 612a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 61337b6bb77SLeon Romanovsky if (err) { 61498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 61537b6bb77SLeon Romanovsky goto out; 61637b6bb77SLeon Romanovsky } 61737b6bb77SLeon Romanovsky 618a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 619a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 62037b6bb77SLeon Romanovsky if (err) { 62198a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 62237b6bb77SLeon Romanovsky goto out; 62337b6bb77SLeon Romanovsky } 62437b6bb77SLeon Romanovsky 625a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 626a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 62737b6bb77SLeon Romanovsky if (err) { 62898a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 62937b6bb77SLeon Romanovsky goto out; 63037b6bb77SLeon Romanovsky } 63137b6bb77SLeon Romanovsky 63259e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 63359e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 63459e9e8e4SMark Zhang if (err) { 63559e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 63659e9e8e4SMark Zhang goto out; 63759e9e8e4SMark Zhang } 63859e9e8e4SMark Zhang 63937b6bb77SLeon Romanovsky out: 640a2a322f4SLeon Romanovsky kfree(set_ctx); 64137b6bb77SLeon Romanovsky return err; 64237b6bb77SLeon Romanovsky } 64337b6bb77SLeon Romanovsky 644e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 645e126ba97SEli Cohen { 646bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 647bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 648e126ba97SEli Cohen int err; 649e126ba97SEli Cohen 650fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 651fc50db98SEli Cohen return 0; 652fc50db98SEli Cohen 653e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 654e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 655e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 656e126ba97SEli Cohen &he_out, sizeof(he_out), 657e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 658e126ba97SEli Cohen return err; 659e126ba97SEli Cohen } 660e126ba97SEli Cohen 661c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 662c85023e1SHuy Nguyen { 663c85023e1SHuy Nguyen int ret = 0; 664c85023e1SHuy Nguyen 665c85023e1SHuy Nguyen /* Disable local_lb by default */ 6668978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 667c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 668c85023e1SHuy Nguyen 669c85023e1SHuy Nguyen return ret; 670c85023e1SHuy Nguyen } 671c85023e1SHuy Nguyen 6720b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 673e126ba97SEli Cohen { 6743ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 675e126ba97SEli Cohen 6760b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6770b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 67822e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 67922e939a9SBodong Wang dev->caps.embedded_cpu); 6803ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 681e126ba97SEli Cohen } 682e126ba97SEli Cohen 6830b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 684e126ba97SEli Cohen { 6853ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 686e126ba97SEli Cohen 6870b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6880b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 68922e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 69022e939a9SBodong Wang dev->caps.embedded_cpu); 6913ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 692e126ba97SEli Cohen } 693e126ba97SEli Cohen 694f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 695f62b8bb8SAmir Vadai { 6963ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 6973ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 698f62b8bb8SAmir Vadai u32 sup_issi; 699c4f287c4SSaeed Mahameed int err; 700f62b8bb8SAmir Vadai 701f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 7023ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 703f62b8bb8SAmir Vadai if (err) { 704c4f287c4SSaeed Mahameed u32 syndrome; 705c4f287c4SSaeed Mahameed u8 status; 706c4f287c4SSaeed Mahameed 707c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 708f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 709f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 710f9c14e46SKamal Heib err, status, syndrome); 711f9c14e46SKamal Heib return err; 712f62b8bb8SAmir Vadai } 713f62b8bb8SAmir Vadai 714f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 715f9c14e46SKamal Heib dev->issi = 0; 716f9c14e46SKamal Heib return 0; 717f62b8bb8SAmir Vadai } 718f62b8bb8SAmir Vadai 719f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 720f62b8bb8SAmir Vadai 721f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7223ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 723f62b8bb8SAmir Vadai 724f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 725f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7263ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 727f62b8bb8SAmir Vadai if (err) { 728f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 729f9c14e46SKamal Heib err); 730f62b8bb8SAmir Vadai return err; 731f62b8bb8SAmir Vadai } 732f62b8bb8SAmir Vadai 733f62b8bb8SAmir Vadai dev->issi = 1; 734f62b8bb8SAmir Vadai 735f62b8bb8SAmir Vadai return 0; 736e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 737f62b8bb8SAmir Vadai return 0; 738f62b8bb8SAmir Vadai } 739f62b8bb8SAmir Vadai 7409eb78923SOr Gerlitz return -EOPNOTSUPP; 741f62b8bb8SAmir Vadai } 742f62b8bb8SAmir Vadai 74311f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 74411f3b84dSSaeed Mahameed const struct pci_device_id *id) 745a31208b1SMajd Dibbiny { 746868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 747a31208b1SMajd Dibbiny int err = 0; 748a31208b1SMajd Dibbiny 749d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 750e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 751e126ba97SEli Cohen 752aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 7537be3412aSParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 754311c7c71SSaeed Mahameed 75589d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 756e126ba97SEli Cohen if (err) { 75798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 75811f3b84dSSaeed Mahameed return err; 759e126ba97SEli Cohen } 760e126ba97SEli Cohen 761e126ba97SEli Cohen err = request_bar(pdev); 762e126ba97SEli Cohen if (err) { 76398a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 764e126ba97SEli Cohen goto err_disable; 765e126ba97SEli Cohen } 766e126ba97SEli Cohen 767e126ba97SEli Cohen pci_set_master(pdev); 768e126ba97SEli Cohen 769e126ba97SEli Cohen err = set_dma_caps(pdev); 770e126ba97SEli Cohen if (err) { 77198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 772e126ba97SEli Cohen goto err_clr_master; 773e126ba97SEli Cohen } 774e126ba97SEli Cohen 775ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 776ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 777ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 778ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 779ce4eee53SMichael Guralnik 780aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 781e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 782e126ba97SEli Cohen if (!dev->iseg) { 783e126ba97SEli Cohen err = -ENOMEM; 78498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 785e126ba97SEli Cohen goto err_clr_master; 786e126ba97SEli Cohen } 787a31208b1SMajd Dibbiny 788b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 789c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 790a31208b1SMajd Dibbiny return 0; 791a31208b1SMajd Dibbiny 792a31208b1SMajd Dibbiny err_clr_master: 793a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 794a31208b1SMajd Dibbiny release_bar(dev->pdev); 795a31208b1SMajd Dibbiny err_disable: 79689d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 797a31208b1SMajd Dibbiny return err; 798a31208b1SMajd Dibbiny } 799a31208b1SMajd Dibbiny 800868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 801a31208b1SMajd Dibbiny { 80242ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 80342ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 80442ea9f1bSShay Drory * before removing the pci bars 80542ea9f1bSShay Drory */ 80642ea9f1bSShay Drory mlx5_drain_health_wq(dev); 807a31208b1SMajd Dibbiny iounmap(dev->iseg); 808a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 809a31208b1SMajd Dibbiny release_bar(dev->pdev); 81089d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 811a31208b1SMajd Dibbiny } 812a31208b1SMajd Dibbiny 813868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 81459211bd3SMohamad Haj Yahia { 81559211bd3SMohamad Haj Yahia int err; 81659211bd3SMohamad Haj Yahia 817868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 818868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 81998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 820868bc06bSSaeed Mahameed dev->priv.devcom); 821fadd59fcSAviv Heller 82259211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 82359211bd3SMohamad Haj Yahia if (err) { 82498a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 825fadd59fcSAviv Heller goto err_devcom; 82659211bd3SMohamad Haj Yahia } 82759211bd3SMohamad Haj Yahia 828561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 829561aa15aSYuval Avnery if (err) { 830561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 831561aa15aSYuval Avnery goto err_devcom; 832561aa15aSYuval Avnery } 833561aa15aSYuval Avnery 834f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 83559211bd3SMohamad Haj Yahia if (err) { 83698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 837561aa15aSYuval Avnery goto err_irq_cleanup; 83859211bd3SMohamad Haj Yahia } 83959211bd3SMohamad Haj Yahia 84069c1280bSSaeed Mahameed err = mlx5_events_init(dev); 84169c1280bSSaeed Mahameed if (err) { 84298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 84369c1280bSSaeed Mahameed goto err_eq_cleanup; 84469c1280bSSaeed Mahameed } 84569c1280bSSaeed Mahameed 84638b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 84738b9f903SMoshe Shemesh if (err) { 84838b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 84938b9f903SMoshe Shemesh goto err_events_cleanup; 85038b9f903SMoshe Shemesh } 85138b9f903SMoshe Shemesh 8529f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 85359211bd3SMohamad Haj Yahia 85452ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 85552ec462eSIlan Tayari 8567c39afb3SFeras Daoud mlx5_init_clock(dev); 8577c39afb3SFeras Daoud 858358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8590ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 860358aa5ceSSaeed Mahameed 86159211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 86259211bd3SMohamad Haj Yahia if (err) { 86398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 86459211bd3SMohamad Haj Yahia goto err_tables_cleanup; 86559211bd3SMohamad Haj Yahia } 86659211bd3SMohamad Haj Yahia 867eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 868eeb66cdbSSaeed Mahameed if (err) { 86998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 870eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 871eeb66cdbSSaeed Mahameed } 872eeb66cdbSSaeed Mahameed 873c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 874c2d6e31aSMohamad Haj Yahia if (err) { 87598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 87686eec50bSBodong Wang goto err_mpfs_cleanup; 87786eec50bSBodong Wang } 87886eec50bSBodong Wang 87986eec50bSBodong Wang err = mlx5_eswitch_init(dev); 88086eec50bSBodong Wang if (err) { 88186eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 88286eec50bSBodong Wang goto err_sriov_cleanup; 883c2d6e31aSMohamad Haj Yahia } 884c2d6e31aSMohamad Haj Yahia 8859410733cSIlan Tayari err = mlx5_fpga_init(dev); 8869410733cSIlan Tayari if (err) { 88798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 88886eec50bSBodong Wang goto err_eswitch_cleanup; 8899410733cSIlan Tayari } 8909410733cSIlan Tayari 891f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 892f3196bb0SParav Pandit if (err) { 893f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 894f3196bb0SParav Pandit goto err_fpga_cleanup; 895f3196bb0SParav Pandit } 896f3196bb0SParav Pandit 8978f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 8988f010541SParav Pandit if (err) { 8998f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 9008f010541SParav Pandit goto err_sf_hw_table_cleanup; 9018f010541SParav Pandit } 9028f010541SParav Pandit 9038f010541SParav Pandit err = mlx5_sf_table_init(dev); 9048f010541SParav Pandit if (err) { 9058f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 9068f010541SParav Pandit goto err_sf_table_cleanup; 9078f010541SParav Pandit } 9088f010541SParav Pandit 909c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 910c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 911c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 912c9b9dcb4SAriel Levkovich 91324406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 91487175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 91512206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 91624406953SFeras Daoud 91759211bd3SMohamad Haj Yahia return 0; 91859211bd3SMohamad Haj Yahia 9198f010541SParav Pandit err_sf_table_cleanup: 9208f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 9218f010541SParav Pandit err_sf_hw_table_cleanup: 9228f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 923f3196bb0SParav Pandit err_fpga_cleanup: 924f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 925c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 926c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 92786eec50bSBodong Wang err_sriov_cleanup: 92886eec50bSBodong Wang mlx5_sriov_cleanup(dev); 929eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 930eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 931c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 932c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 93359211bd3SMohamad Haj Yahia err_tables_cleanup: 9340ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 935358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 93602d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 93738b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 93838b9f903SMoshe Shemesh err_events_cleanup: 93969c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 94059211bd3SMohamad Haj Yahia err_eq_cleanup: 941f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 942561aa15aSYuval Avnery err_irq_cleanup: 943561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 944fadd59fcSAviv Heller err_devcom: 945fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 94659211bd3SMohamad Haj Yahia 94759211bd3SMohamad Haj Yahia return err; 94859211bd3SMohamad Haj Yahia } 94959211bd3SMohamad Haj Yahia 95059211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 95159211bd3SMohamad Haj Yahia { 95212206b17SAya Levin mlx5_rsc_dump_destroy(dev); 95387175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 95424406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 955c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9568f010541SParav Pandit mlx5_sf_table_cleanup(dev); 9578f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 958f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 9599410733cSIlan Tayari mlx5_fpga_cleanup(dev); 960c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 96186eec50bSBodong Wang mlx5_sriov_cleanup(dev); 962eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 96359211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9640ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 965358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9667c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 96752ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 96802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 96938b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 97069c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 971f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 972561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 973fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 97459211bd3SMohamad Haj Yahia } 97559211bd3SMohamad Haj Yahia 976e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 977a31208b1SMajd Dibbiny { 978a31208b1SMajd Dibbiny int err; 979a31208b1SMajd Dibbiny 98098a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 981e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 982e126ba97SEli Cohen 98300c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 98400c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 98500c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 98600c6bcb0STal Gilboa 9876c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9886c780a02SEli Cohen */ 989b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9906c780a02SEli Cohen if (err) { 99198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9926c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 993e161105eSSaeed Mahameed return err; 9946c780a02SEli Cohen } 9956c780a02SEli Cohen 996e126ba97SEli Cohen err = mlx5_cmd_init(dev); 997e126ba97SEli Cohen if (err) { 99898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 999e161105eSSaeed Mahameed return err; 1000e126ba97SEli Cohen } 1001e126ba97SEli Cohen 1002b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1003e3297246SEli Cohen if (err) { 100498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 1005e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 100655378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1007e3297246SEli Cohen } 1008e3297246SEli Cohen 1009f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1010f7936dddSEran Ben Elisha 10110b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1012cd23b14bSEli Cohen if (err) { 101398a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 101459211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 1015cd23b14bSEli Cohen } 1016cd23b14bSEli Cohen 1017f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1018f62b8bb8SAmir Vadai if (err) { 101998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1020f62b8bb8SAmir Vadai goto err_disable_hca; 1021f62b8bb8SAmir Vadai } 1022f62b8bb8SAmir Vadai 1023cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1024cd23b14bSEli Cohen if (err) { 102598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1026cd23b14bSEli Cohen goto err_disable_hca; 1027cd23b14bSEli Cohen } 1028cd23b14bSEli Cohen 1029e126ba97SEli Cohen err = set_hca_ctrl(dev); 1030e126ba97SEli Cohen if (err) { 103198a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1032cd23b14bSEli Cohen goto reclaim_boot_pages; 1033e126ba97SEli Cohen } 1034e126ba97SEli Cohen 103537b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1036e126ba97SEli Cohen if (err) { 103798a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 103846861e3eSMoni Shoua goto reclaim_boot_pages; 103946861e3eSMoni Shoua } 104046861e3eSMoni Shoua 1041cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1042e126ba97SEli Cohen if (err) { 104398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1044cd23b14bSEli Cohen goto reclaim_boot_pages; 1045e126ba97SEli Cohen } 1046e126ba97SEli Cohen 10478737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1048e126ba97SEli Cohen if (err) { 104998a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10500cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1051e126ba97SEli Cohen } 1052e126ba97SEli Cohen 1053012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1054012e50e1SHuy Nguyen 1055e126ba97SEli Cohen mlx5_start_health_poll(dev); 1056e126ba97SEli Cohen 1057bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1058bba1574cSDaniel Jurgens if (err) { 105998a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1060e161105eSSaeed Mahameed goto stop_health; 1061bba1574cSDaniel Jurgens } 1062bba1574cSDaniel Jurgens 1063e161105eSSaeed Mahameed return 0; 1064e161105eSSaeed Mahameed 1065e161105eSSaeed Mahameed stop_health: 1066e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1067e161105eSSaeed Mahameed reclaim_boot_pages: 1068e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1069e161105eSSaeed Mahameed err_disable_hca: 1070e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1071e161105eSSaeed Mahameed err_cmd_cleanup: 1072f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1073e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1074e161105eSSaeed Mahameed 1075e161105eSSaeed Mahameed return err; 1076e161105eSSaeed Mahameed } 1077e161105eSSaeed Mahameed 1078e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1079e161105eSSaeed Mahameed { 1080e161105eSSaeed Mahameed int err; 1081e161105eSSaeed Mahameed 1082e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1083e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1084259bbc57SMaor Gottlieb if (err) { 108598a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1086e161105eSSaeed Mahameed return err; 1087e126ba97SEli Cohen } 1088e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1089e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1090f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1091e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1092e161105eSSaeed Mahameed 1093e161105eSSaeed Mahameed return 0; 1094259bbc57SMaor Gottlieb } 1095e126ba97SEli Cohen 1096a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1097e161105eSSaeed Mahameed { 1098e161105eSSaeed Mahameed int err; 1099e161105eSSaeed Mahameed 110001187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 110172f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 110298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 110372f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1104a80d1b68SSaeed Mahameed return err; 1105e126ba97SEli Cohen } 1106e126ba97SEli Cohen 110769c1280bSSaeed Mahameed mlx5_events_start(dev); 11080cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 11090cf53c12SSaeed Mahameed 1110e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1111e1706e62SYuval Avnery if (err) { 1112e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1113e1706e62SYuval Avnery goto err_irq_table; 1114e1706e62SYuval Avnery } 1115e1706e62SYuval Avnery 1116c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1117e126ba97SEli Cohen if (err) { 111898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1119c8e21b3bSSaeed Mahameed goto err_eq_table; 1120e126ba97SEli Cohen } 1121e126ba97SEli Cohen 112224406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 112324406953SFeras Daoud if (err) { 112498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 112524406953SFeras Daoud goto err_fw_tracer; 112624406953SFeras Daoud } 112724406953SFeras Daoud 112838b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 112987175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 113087175120SEran Ben Elisha 113112206b17SAya Levin err = mlx5_rsc_dump_init(dev); 113212206b17SAya Levin if (err) { 113312206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 113412206b17SAya Levin goto err_rsc_dump; 113512206b17SAya Levin } 113612206b17SAya Levin 113704e87170SMatan Barak err = mlx5_fpga_device_start(dev); 113804e87170SMatan Barak if (err) { 113998a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 114004e87170SMatan Barak goto err_fpga_start; 114104e87170SMatan Barak } 114204e87170SMatan Barak 11439a6ad1adSRaed Salem mlx5_accel_ipsec_init(dev); 114404e87170SMatan Barak 11451ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11461ae17322SIlya Lesokhin if (err) { 114798a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11481ae17322SIlya Lesokhin goto err_tls_start; 11491ae17322SIlya Lesokhin } 11501ae17322SIlya Lesokhin 115186d722adSMaor Gottlieb err = mlx5_init_fs(dev); 115286d722adSMaor Gottlieb if (err) { 115398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 115486d722adSMaor Gottlieb goto err_fs; 115586d722adSMaor Gottlieb } 11561466cc5bSYevgeny Petrilin 1157c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1158c85023e1SHuy Nguyen if (err) { 115998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 116087883929SSaeed Mahameed goto err_sriov; 1161c85023e1SHuy Nguyen } 1162c85023e1SHuy Nguyen 1163f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1164f3196bb0SParav Pandit 1165*6a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 1166*6a327321SParav Pandit if (err) { 1167*6a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 1168*6a327321SParav Pandit goto err_vhca; 1169*6a327321SParav Pandit } 1170*6a327321SParav Pandit 117122e939a9SBodong Wang err = mlx5_ec_init(dev); 117222e939a9SBodong Wang if (err) { 117398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 117422e939a9SBodong Wang goto err_ec; 117522e939a9SBodong Wang } 117622e939a9SBodong Wang 11775bef709dSParav Pandit err = mlx5_sriov_attach(dev); 11785bef709dSParav Pandit if (err) { 11795bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 11805bef709dSParav Pandit goto err_sriov; 11815bef709dSParav Pandit } 11825bef709dSParav Pandit 118390d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 118490d010b8SParav Pandit 1185a80d1b68SSaeed Mahameed return 0; 1186a80d1b68SSaeed Mahameed 1187a80d1b68SSaeed Mahameed err_sriov: 11885bef709dSParav Pandit mlx5_ec_cleanup(dev); 11895bef709dSParav Pandit err_ec: 1190*6a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1191*6a327321SParav Pandit err_vhca: 1192f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1193a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1194a80d1b68SSaeed Mahameed err_fs: 1195a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1196a80d1b68SSaeed Mahameed err_tls_start: 1197a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1198a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1199a80d1b68SSaeed Mahameed err_fpga_start: 120012206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 120112206b17SAya Levin err_rsc_dump: 120287175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 120338b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1204a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1205a80d1b68SSaeed Mahameed err_fw_tracer: 1206a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1207a80d1b68SSaeed Mahameed err_eq_table: 1208e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1209e1706e62SYuval Avnery err_irq_table: 1210a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1211a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1212a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1213a80d1b68SSaeed Mahameed return err; 1214a80d1b68SSaeed Mahameed } 1215a80d1b68SSaeed Mahameed 1216a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1217a80d1b68SSaeed Mahameed { 121890d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1219a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 12205bef709dSParav Pandit mlx5_ec_cleanup(dev); 1221*6a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1222f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1223a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1224a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1225a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1226a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 122712206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 122887175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 122938b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1230a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1231a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1232e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1233a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1234a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1235a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1236a80d1b68SSaeed Mahameed } 1237a80d1b68SSaeed Mahameed 12384383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1239a80d1b68SSaeed Mahameed { 1240a80d1b68SSaeed Mahameed int err = 0; 1241a80d1b68SSaeed Mahameed 1242a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1243a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1244a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1245a80d1b68SSaeed Mahameed goto out; 1246a80d1b68SSaeed Mahameed } 1247a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1248a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1249a80d1b68SSaeed Mahameed 1250a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1251a80d1b68SSaeed Mahameed if (err) 12524f7400d5SShay Drory goto err_function; 1253a80d1b68SSaeed Mahameed 1254a80d1b68SSaeed Mahameed if (boot) { 1255a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1256a80d1b68SSaeed Mahameed if (err) { 125798a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1258a80d1b68SSaeed Mahameed goto function_teardown; 1259a80d1b68SSaeed Mahameed } 1260a80d1b68SSaeed Mahameed } 1261a80d1b68SSaeed Mahameed 1262a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1263a80d1b68SSaeed Mahameed if (err) 1264a80d1b68SSaeed Mahameed goto err_load; 1265a80d1b68SSaeed Mahameed 126698f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 126798f91c45SParav Pandit 1268a6f3b623SMichael Guralnik if (boot) { 1269a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1270a6f3b623SMichael Guralnik if (err) 1271a6f3b623SMichael Guralnik goto err_devlink_reg; 1272a925b5e3SLeon Romanovsky 1273a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 127498f91c45SParav Pandit } else { 1275a925b5e3SLeon Romanovsky err = mlx5_attach_device(dev); 127698f91c45SParav Pandit } 127789d44f0aSMajd Dibbiny 1278a925b5e3SLeon Romanovsky if (err) 1279a925b5e3SLeon Romanovsky goto err_register; 1280a925b5e3SLeon Romanovsky 12814162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 12824162f58bSParav Pandit return 0; 1283e126ba97SEli Cohen 1284a925b5e3SLeon Romanovsky err_register: 1285a925b5e3SLeon Romanovsky if (boot) 1286a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1287a6f3b623SMichael Guralnik err_devlink_reg: 128898f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1289a80d1b68SSaeed Mahameed mlx5_unload(dev); 1290a80d1b68SSaeed Mahameed err_load: 129159211bd3SMohamad Haj Yahia if (boot) 129259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1293e161105eSSaeed Mahameed function_teardown: 1294e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 12954f7400d5SShay Drory err_function: 129689d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 12974162f58bSParav Pandit out: 129889d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1299e126ba97SEli Cohen return err; 1300e126ba97SEli Cohen } 1301e126ba97SEli Cohen 1302f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1303e126ba97SEli Cohen { 130489d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 130598f91c45SParav Pandit 130698f91c45SParav Pandit if (cleanup) { 130798f91c45SParav Pandit mlx5_unregister_device(dev); 130898f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 130998f91c45SParav Pandit } else { 131098f91c45SParav Pandit mlx5_detach_device(dev); 131198f91c45SParav Pandit } 131298f91c45SParav Pandit 1313b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 131498a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 131589d44f0aSMajd Dibbiny __func__); 131659211bd3SMohamad Haj Yahia if (cleanup) 131759211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 131889d44f0aSMajd Dibbiny goto out; 131989d44f0aSMajd Dibbiny } 13206b6adee3SMohamad Haj Yahia 13219ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13229ade8c7cSIlan Tayari 1323a80d1b68SSaeed Mahameed mlx5_unload(dev); 1324a80d1b68SSaeed Mahameed 132559211bd3SMohamad Haj Yahia if (cleanup) 132659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 13270cf53c12SSaeed Mahameed 1328e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1329ac6ea6e8SEli Cohen out: 133089d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 13319603b61dSJack Morgenstein } 133264613d94SSaeed Mahameed 13331958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 13349603b61dSJack Morgenstein { 133511f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 13369603b61dSJack Morgenstein int err; 13379603b61dSJack Morgenstein 133811f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 13399603b61dSJack Morgenstein 1340364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1341364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 134289d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1343d9aaed83SArtemy Kovalyov 134401187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 134501187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 134601187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 134701187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 134801187175SEli Cohen 134911f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 135011f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 135111f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 135211f3b84dSSaeed Mahameed 135327b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 135427b942fbSParav Pandit mlx5_debugfs_root); 1355ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 135652c368dcSSaeed Mahameed if (err) 135752c368dcSSaeed Mahameed goto err_health_init; 1358ac6ea6e8SEli Cohen 13590cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 13600cf53c12SSaeed Mahameed if (err) 13610cf53c12SSaeed Mahameed goto err_pagealloc_init; 136259211bd3SMohamad Haj Yahia 1363a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1364a925b5e3SLeon Romanovsky if (err) 1365a925b5e3SLeon Romanovsky goto err_adev_init; 1366a925b5e3SLeon Romanovsky 136711f3b84dSSaeed Mahameed return 0; 136852c368dcSSaeed Mahameed 1369a925b5e3SLeon Romanovsky err_adev_init: 1370a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 137152c368dcSSaeed Mahameed err_pagealloc_init: 137252c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 137352c368dcSSaeed Mahameed err_health_init: 137452c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1375810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1376810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1377810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1378810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1379810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 138052c368dcSSaeed Mahameed return err; 138111f3b84dSSaeed Mahameed } 138211f3b84dSSaeed Mahameed 13831958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 138411f3b84dSSaeed Mahameed { 1385810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1386810cbb25SParav Pandit 1387a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 138852c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 138952c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 139011f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1391810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1392810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1393810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1394810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1395810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 139611f3b84dSSaeed Mahameed } 139711f3b84dSSaeed Mahameed 139811f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 139911f3b84dSSaeed Mahameed { 140011f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 140111f3b84dSSaeed Mahameed struct devlink *devlink; 140211f3b84dSSaeed Mahameed int err; 140311f3b84dSSaeed Mahameed 14041f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 140511f3b84dSSaeed Mahameed if (!devlink) { 14061f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 140711f3b84dSSaeed Mahameed return -ENOMEM; 140811f3b84dSSaeed Mahameed } 140911f3b84dSSaeed Mahameed 141011f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 141127b942fbSParav Pandit dev->device = &pdev->dev; 141227b942fbSParav Pandit dev->pdev = pdev; 141311f3b84dSSaeed Mahameed 1414386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1415386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1416386e75afSHuy Nguyen 1417a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 14184d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 14194d8be211SLeon Romanovsky err = dev->priv.adev_idx; 14204d8be211SLeon Romanovsky goto adev_init_err; 14214d8be211SLeon Romanovsky } 1422a925b5e3SLeon Romanovsky 142327b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 142411f3b84dSSaeed Mahameed if (err) 142511f3b84dSSaeed Mahameed goto mdev_init_err; 142611f3b84dSSaeed Mahameed 142711f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 14289603b61dSJack Morgenstein if (err) { 142998a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 143098a8e6fcSHuy Nguyen err); 143111f3b84dSSaeed Mahameed goto pci_init_err; 14329603b61dSJack Morgenstein } 14339603b61dSJack Morgenstein 1434868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 14359603b61dSJack Morgenstein if (err) { 143698a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 143798a8e6fcSHuy Nguyen err); 14380cf53c12SSaeed Mahameed goto err_load_one; 14399603b61dSJack Morgenstein } 144059211bd3SMohamad Haj Yahia 14418b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 14428b9d8baaSAlex Vesker if (err) 14438b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 14448b9d8baaSAlex Vesker 14455d47f6c8SDaniel Jurgens pci_save_state(pdev); 144660904cd3SParav Pandit devlink_reload_enable(devlink); 14479603b61dSJack Morgenstein return 0; 14489603b61dSJack Morgenstein 14490cf53c12SSaeed Mahameed err_load_one: 1450868bc06bSSaeed Mahameed mlx5_pci_close(dev); 145111f3b84dSSaeed Mahameed pci_init_err: 145211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 145311f3b84dSSaeed Mahameed mdev_init_err: 1454a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14554d8be211SLeon Romanovsky adev_init_err: 14561f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1457a31208b1SMajd Dibbiny 14589603b61dSJack Morgenstein return err; 14599603b61dSJack Morgenstein } 1460a31208b1SMajd Dibbiny 14619603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 14629603b61dSJack Morgenstein { 14639603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1464feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 14659603b61dSJack Morgenstein 146660904cd3SParav Pandit devlink_reload_disable(devlink); 14678b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 146841798df9SParav Pandit mlx5_drain_health_wq(dev); 1469f999b706SParav Pandit mlx5_unload_one(dev, true); 1470868bc06bSSaeed Mahameed mlx5_pci_close(dev); 147111f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1472a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14731f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 14749603b61dSJack Morgenstein } 14759603b61dSJack Morgenstein 147689d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 147789d44f0aSMajd Dibbiny pci_channel_state_t state) 147889d44f0aSMajd Dibbiny { 147989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 148089d44f0aSMajd Dibbiny 148198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 148204c0c1abSMohamad Haj Yahia 14838812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 14843e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1485868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 14865e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 148789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 148805ac2c0bSMohamad Haj Yahia 148989d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 149089d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 149189d44f0aSMajd Dibbiny } 149289d44f0aSMajd Dibbiny 1493d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1494d57847dcSDaniel Jurgens * for the health counter to start counting. 149589d44f0aSMajd Dibbiny */ 1496d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 149789d44f0aSMajd Dibbiny { 149889d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 149989d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 150089d44f0aSMajd Dibbiny const int niter = 100; 1501d57847dcSDaniel Jurgens u32 last_count = 0; 150289d44f0aSMajd Dibbiny u32 count; 150389d44f0aSMajd Dibbiny int i; 150489d44f0aSMajd Dibbiny 150589d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 150689d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 150789d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1508d57847dcSDaniel Jurgens if (last_count && last_count != count) { 150998a8e6fcSHuy Nguyen mlx5_core_info(dev, 151098a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 151198a8e6fcSHuy Nguyen count, i); 1512d57847dcSDaniel Jurgens return 0; 1513d57847dcSDaniel Jurgens } 1514d57847dcSDaniel Jurgens last_count = count; 151589d44f0aSMajd Dibbiny } 151689d44f0aSMajd Dibbiny msleep(50); 151789d44f0aSMajd Dibbiny } 151889d44f0aSMajd Dibbiny 1519d57847dcSDaniel Jurgens return -ETIMEDOUT; 152089d44f0aSMajd Dibbiny } 152189d44f0aSMajd Dibbiny 15221061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 15231061c90fSMohamad Haj Yahia { 15241061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15251061c90fSMohamad Haj Yahia int err; 15261061c90fSMohamad Haj Yahia 152798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 15281061c90fSMohamad Haj Yahia 15291061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 15301061c90fSMohamad Haj Yahia if (err) { 153198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 153298a8e6fcSHuy Nguyen __func__, err); 15331061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 15341061c90fSMohamad Haj Yahia } 15351061c90fSMohamad Haj Yahia 15361061c90fSMohamad Haj Yahia pci_set_master(pdev); 15371061c90fSMohamad Haj Yahia pci_restore_state(pdev); 15385d47f6c8SDaniel Jurgens pci_save_state(pdev); 15391061c90fSMohamad Haj Yahia 15401061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 154198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 15421061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 15431061c90fSMohamad Haj Yahia } 15441061c90fSMohamad Haj Yahia 15451061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 15461061c90fSMohamad Haj Yahia } 15471061c90fSMohamad Haj Yahia 154889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 154989d44f0aSMajd Dibbiny { 155089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 155189d44f0aSMajd Dibbiny int err; 155289d44f0aSMajd Dibbiny 155398a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 155489d44f0aSMajd Dibbiny 1555868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 155689d44f0aSMajd Dibbiny if (err) 155798a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 155898a8e6fcSHuy Nguyen __func__, err); 155989d44f0aSMajd Dibbiny else 156098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 156189d44f0aSMajd Dibbiny } 156289d44f0aSMajd Dibbiny 156389d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 156489d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 156589d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 156689d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 156789d44f0aSMajd Dibbiny }; 156889d44f0aSMajd Dibbiny 15698812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 15708812c24dSMajd Dibbiny { 1571fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1572fcd29ad1SFeras Daoud int ret = 1; 15738812c24dSMajd Dibbiny 1574fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1575fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1576fcd29ad1SFeras Daoud 1577fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1578fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1579fcd29ad1SFeras Daoud 1580fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 15818812c24dSMajd Dibbiny return -EOPNOTSUPP; 15828812c24dSMajd Dibbiny 15838812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 15848812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 15858812c24dSMajd Dibbiny return -EAGAIN; 15868812c24dSMajd Dibbiny } 15878812c24dSMajd Dibbiny 1588d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1589d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1590d2aa060dSHuy Nguyen */ 1591d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 159276d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1593d2aa060dSHuy Nguyen 1594fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1595fcd29ad1SFeras Daoud if (!ret) 1596fcd29ad1SFeras Daoud goto succeed; 1597fcd29ad1SFeras Daoud 15988812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1599fcd29ad1SFeras Daoud if (!ret) 1600fcd29ad1SFeras Daoud goto succeed; 1601fcd29ad1SFeras Daoud 16028812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1603d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 16048812c24dSMajd Dibbiny return ret; 16058812c24dSMajd Dibbiny 1606fcd29ad1SFeras Daoud succeed: 16078812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 16088812c24dSMajd Dibbiny 16091ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 16101ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 16111ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 16121ef903bfSDaniel Jurgens * contexts. 16131ef903bfSDaniel Jurgens */ 16141ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 16151ef903bfSDaniel Jurgens 16168812c24dSMajd Dibbiny return 0; 16178812c24dSMajd Dibbiny } 16188812c24dSMajd Dibbiny 16195fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 16205fc7197dSMajd Dibbiny { 16215fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16228812c24dSMajd Dibbiny int err; 16235fc7197dSMajd Dibbiny 162498a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 16258812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 16268812c24dSMajd Dibbiny if (err) 1627868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 16285fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 16295fc7197dSMajd Dibbiny } 16305fc7197dSMajd Dibbiny 16318fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 16328fc3e29bSMark Bloch { 16338fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16348fc3e29bSMark Bloch 16358fc3e29bSMark Bloch mlx5_unload_one(dev, false); 16368fc3e29bSMark Bloch 16378fc3e29bSMark Bloch return 0; 16388fc3e29bSMark Bloch } 16398fc3e29bSMark Bloch 16408fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 16418fc3e29bSMark Bloch { 16428fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16438fc3e29bSMark Bloch 16448fc3e29bSMark Bloch return mlx5_load_one(dev, false); 16458fc3e29bSMark Bloch } 16468fc3e29bSMark Bloch 16479603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1648bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1649fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1650bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1651fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1652bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1653fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 16547092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 165564dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1656d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1657d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1658d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1659d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 166085327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 166185327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1662b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1663505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 16642e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 16652e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1666d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1667dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 16689603b61dSJack Morgenstein { 0, } 16699603b61dSJack Morgenstein }; 16709603b61dSJack Morgenstein 16719603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 16729603b61dSJack Morgenstein 167304c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 167404c0c1abSMohamad Haj Yahia { 1675b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1676b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 167704c0c1abSMohamad Haj Yahia } 167804c0c1abSMohamad Haj Yahia 167904c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 168004c0c1abSMohamad Haj Yahia { 168104c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 168204c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 168304c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 168404c0c1abSMohamad Haj Yahia } 168504c0c1abSMohamad Haj Yahia 16869603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 168717a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 16889603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 16899603b61dSJack Morgenstein .probe = init_one, 169089d44f0aSMajd Dibbiny .remove = remove_one, 16918fc3e29bSMark Bloch .suspend = mlx5_suspend, 16928fc3e29bSMark Bloch .resume = mlx5_resume, 16935fc7197dSMajd Dibbiny .shutdown = shutdown, 1694fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1695fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 16969603b61dSJack Morgenstein }; 1697e126ba97SEli Cohen 1698f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1699f663ad98SKamal Heib { 1700f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1701f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1702f663ad98SKamal Heib prof_sel, 1703f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1704f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1705f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1706f663ad98SKamal Heib } 1707f663ad98SKamal Heib } 1708f663ad98SKamal Heib 1709e126ba97SEli Cohen static int __init init(void) 1710e126ba97SEli Cohen { 1711e126ba97SEli Cohen int err; 1712e126ba97SEli Cohen 171317a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 171417a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 171517a7612bSLeon Romanovsky 17168737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 17178737f818SDaniel Jurgens 1718f663ad98SKamal Heib mlx5_core_verify_params(); 17199a6ad1adSRaed Salem mlx5_fpga_ipsec_build_fs_cmds(); 1720e126ba97SEli Cohen mlx5_register_debugfs(); 1721e126ba97SEli Cohen 17229603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 17239603b61dSJack Morgenstein if (err) 1724ac6ea6e8SEli Cohen goto err_debug; 17259603b61dSJack Morgenstein 17261958fc2fSParav Pandit err = mlx5_sf_driver_register(); 17271958fc2fSParav Pandit if (err) 17281958fc2fSParav Pandit goto err_sf; 17291958fc2fSParav Pandit 1730f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1731912cebf4SLeon Romanovsky err = mlx5e_init(); 1732912cebf4SLeon Romanovsky if (err) { 1733912cebf4SLeon Romanovsky pci_unregister_driver(&mlx5_core_driver); 1734912cebf4SLeon Romanovsky goto err_debug; 1735912cebf4SLeon Romanovsky } 1736f62b8bb8SAmir Vadai #endif 1737f62b8bb8SAmir Vadai 1738e126ba97SEli Cohen return 0; 1739e126ba97SEli Cohen 17401958fc2fSParav Pandit err_sf: 17411958fc2fSParav Pandit pci_unregister_driver(&mlx5_core_driver); 1742e126ba97SEli Cohen err_debug: 1743e126ba97SEli Cohen mlx5_unregister_debugfs(); 1744e126ba97SEli Cohen return err; 1745e126ba97SEli Cohen } 1746e126ba97SEli Cohen 1747e126ba97SEli Cohen static void __exit cleanup(void) 1748e126ba97SEli Cohen { 1749f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1750f62b8bb8SAmir Vadai mlx5e_cleanup(); 1751f62b8bb8SAmir Vadai #endif 17521958fc2fSParav Pandit mlx5_sf_driver_unregister(); 17539603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1754e126ba97SEli Cohen mlx5_unregister_debugfs(); 1755e126ba97SEli Cohen } 1756e126ba97SEli Cohen 1757e126ba97SEli Cohen module_init(init); 1758e126ba97SEli Cohen module_exit(cleanup); 1759