1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53907af0f0SLeon Romanovsky #include <linux/version.h> 54feae9087SOr Gerlitz #include <net/devlink.h> 55e126ba97SEli Cohen #include "mlx5_core.h" 56f2f3df55SSaeed Mahameed #include "lib/eq.h" 5716d76083SSaeed Mahameed #include "fs_core.h" 58eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 59073bb189SSaeed Mahameed #include "eswitch.h" 601f28d776SEran Ben Elisha #include "devlink.h" 6138b9f903SMoshe Shemesh #include "fw_reset.h" 6252ec462eSIlan Tayari #include "lib/mlx5.h" 635945e1adSAmir Tzin #include "lib/tout.h" 64e29341fbSIlan Tayari #include "fpga/core.h" 6505564d0aSAviad Yehezkel #include "fpga/ipsec.h" 66bebb23e6SIlan Tayari #include "accel/ipsec.h" 671ae17322SIlya Lesokhin #include "accel/tls.h" 687c39afb3SFeras Daoud #include "lib/clock.h" 69358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 700ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 71fadd59fcSAviv Heller #include "lib/devcom.h" 72b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7324406953SFeras Daoud #include "diag/fw_tracer.h" 74591905baSBodong Wang #include "ecpf.h" 7587175120SEran Ben Elisha #include "lib/hv_vhca.h" 7612206b17SAya Levin #include "diag/rsc_dump.h" 77f3196bb0SParav Pandit #include "sf/vhca_event.h" 7890d010b8SParav Pandit #include "sf/dev/dev.h" 796a327321SParav Pandit #include "sf/sf.h" 803b43190bSShay Drory #include "mlx5_irq.h" 81e126ba97SEli Cohen 82e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 83048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 84e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 85e126ba97SEli Cohen 86f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 87f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 88e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 89e126ba97SEli Cohen 90f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 91f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 929603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 939603b61dSJack Morgenstein 948737f818SDaniel Jurgens static u32 sw_owner_id[4]; 958737f818SDaniel Jurgens 96f91e6d89SEran Ben Elisha enum { 97f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 98f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 99f91e6d89SEran Ben Elisha }; 100f91e6d89SEran Ben Elisha 101f79a609eSMaher Sanalla #define LOG_MAX_SUPPORTED_QPS 0xff 102f79a609eSMaher Sanalla 1039603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1049603b61dSJack Morgenstein [0] = { 1059603b61dSJack Morgenstein .mask = 0, 1069603b61dSJack Morgenstein }, 1079603b61dSJack Morgenstein [1] = { 1089603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1099603b61dSJack Morgenstein .log_max_qp = 12, 1109603b61dSJack Morgenstein }, 1119603b61dSJack Morgenstein [2] = { 1129603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1139603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 114f79a609eSMaher Sanalla .log_max_qp = LOG_MAX_SUPPORTED_QPS, 1159603b61dSJack Morgenstein .mr_cache[0] = { 1169603b61dSJack Morgenstein .size = 500, 1179603b61dSJack Morgenstein .limit = 250 1189603b61dSJack Morgenstein }, 1199603b61dSJack Morgenstein .mr_cache[1] = { 1209603b61dSJack Morgenstein .size = 500, 1219603b61dSJack Morgenstein .limit = 250 1229603b61dSJack Morgenstein }, 1239603b61dSJack Morgenstein .mr_cache[2] = { 1249603b61dSJack Morgenstein .size = 500, 1259603b61dSJack Morgenstein .limit = 250 1269603b61dSJack Morgenstein }, 1279603b61dSJack Morgenstein .mr_cache[3] = { 1289603b61dSJack Morgenstein .size = 500, 1299603b61dSJack Morgenstein .limit = 250 1309603b61dSJack Morgenstein }, 1319603b61dSJack Morgenstein .mr_cache[4] = { 1329603b61dSJack Morgenstein .size = 500, 1339603b61dSJack Morgenstein .limit = 250 1349603b61dSJack Morgenstein }, 1359603b61dSJack Morgenstein .mr_cache[5] = { 1369603b61dSJack Morgenstein .size = 500, 1379603b61dSJack Morgenstein .limit = 250 1389603b61dSJack Morgenstein }, 1399603b61dSJack Morgenstein .mr_cache[6] = { 1409603b61dSJack Morgenstein .size = 500, 1419603b61dSJack Morgenstein .limit = 250 1429603b61dSJack Morgenstein }, 1439603b61dSJack Morgenstein .mr_cache[7] = { 1449603b61dSJack Morgenstein .size = 500, 1459603b61dSJack Morgenstein .limit = 250 1469603b61dSJack Morgenstein }, 1479603b61dSJack Morgenstein .mr_cache[8] = { 1489603b61dSJack Morgenstein .size = 500, 1499603b61dSJack Morgenstein .limit = 250 1509603b61dSJack Morgenstein }, 1519603b61dSJack Morgenstein .mr_cache[9] = { 1529603b61dSJack Morgenstein .size = 500, 1539603b61dSJack Morgenstein .limit = 250 1549603b61dSJack Morgenstein }, 1559603b61dSJack Morgenstein .mr_cache[10] = { 1569603b61dSJack Morgenstein .size = 500, 1579603b61dSJack Morgenstein .limit = 250 1589603b61dSJack Morgenstein }, 1599603b61dSJack Morgenstein .mr_cache[11] = { 1609603b61dSJack Morgenstein .size = 500, 1619603b61dSJack Morgenstein .limit = 250 1629603b61dSJack Morgenstein }, 1639603b61dSJack Morgenstein .mr_cache[12] = { 1649603b61dSJack Morgenstein .size = 64, 1659603b61dSJack Morgenstein .limit = 32 1669603b61dSJack Morgenstein }, 1679603b61dSJack Morgenstein .mr_cache[13] = { 1689603b61dSJack Morgenstein .size = 32, 1699603b61dSJack Morgenstein .limit = 16 1709603b61dSJack Morgenstein }, 1719603b61dSJack Morgenstein .mr_cache[14] = { 1729603b61dSJack Morgenstein .size = 16, 1739603b61dSJack Morgenstein .limit = 8 1749603b61dSJack Morgenstein }, 1759603b61dSJack Morgenstein .mr_cache[15] = { 1769603b61dSJack Morgenstein .size = 8, 1779603b61dSJack Morgenstein .limit = 4 1789603b61dSJack Morgenstein }, 1799603b61dSJack Morgenstein }, 1809603b61dSJack Morgenstein }; 181e126ba97SEli Cohen 182555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 183555af0c3SParav Pandit { 184555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 185555af0c3SParav Pandit } 186555af0c3SParav Pandit 187b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 188b8a92577SDaniel Jurgens u32 warn_time_mili) 189e3297246SEli Cohen { 190b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 191e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 192e3297246SEli Cohen int err = 0; 193e3297246SEli Cohen 194e3297246SEli Cohen while (fw_initializing(dev)) { 195e3297246SEli Cohen if (time_after(jiffies, end)) { 196e3297246SEli Cohen err = -EBUSY; 197e3297246SEli Cohen break; 198e3297246SEli Cohen } 199b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 200b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 201b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 202b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 203b8a92577SDaniel Jurgens } 2045945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 205e3297246SEli Cohen } 206e3297246SEli Cohen 207e3297246SEli Cohen return err; 208e3297246SEli Cohen } 209e3297246SEli Cohen 210012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 211012e50e1SHuy Nguyen { 212012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 213012e50e1SHuy Nguyen driver_version); 2143ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 215012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 216012e50e1SHuy Nguyen char *string; 217012e50e1SHuy Nguyen 218012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 219012e50e1SHuy Nguyen return; 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 222012e50e1SHuy Nguyen 223012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 224012e50e1SHuy Nguyen 225012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 226012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 22917a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235907af0f0SLeon Romanovsky 236907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 23788a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 23888a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 239012e50e1SHuy Nguyen 240012e50e1SHuy Nguyen /*Send the command*/ 241012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 242012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 243012e50e1SHuy Nguyen 2443ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 245012e50e1SHuy Nguyen } 246012e50e1SHuy Nguyen 247e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 248e126ba97SEli Cohen { 249e126ba97SEli Cohen int err; 250e126ba97SEli Cohen 251eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 252e126ba97SEli Cohen if (err) { 2531a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 254eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 255e126ba97SEli Cohen if (err) { 2561a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 257e126ba97SEli Cohen return err; 258e126ba97SEli Cohen } 259e126ba97SEli Cohen } 260e126ba97SEli Cohen 261e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 262e126ba97SEli Cohen return err; 263e126ba97SEli Cohen } 264e126ba97SEli Cohen 26589d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 26689d44f0aSMajd Dibbiny { 26789d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 26889d44f0aSMajd Dibbiny int err = 0; 26989d44f0aSMajd Dibbiny 27089d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27189d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27289d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27389d44f0aSMajd Dibbiny if (!err) 27489d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27589d44f0aSMajd Dibbiny } 27689d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 27789d44f0aSMajd Dibbiny 27889d44f0aSMajd Dibbiny return err; 27989d44f0aSMajd Dibbiny } 28089d44f0aSMajd Dibbiny 28189d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28289d44f0aSMajd Dibbiny { 28389d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28489d44f0aSMajd Dibbiny 28589d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28689d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 28789d44f0aSMajd Dibbiny pci_disable_device(pdev); 28889d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 28989d44f0aSMajd Dibbiny } 29089d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29189d44f0aSMajd Dibbiny } 29289d44f0aSMajd Dibbiny 293e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 294e126ba97SEli Cohen { 295e126ba97SEli Cohen int err = 0; 296e126ba97SEli Cohen 297e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2981a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 299e126ba97SEli Cohen return -ENODEV; 300e126ba97SEli Cohen } 301e126ba97SEli Cohen 30217a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 303e126ba97SEli Cohen if (err) 304e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 305e126ba97SEli Cohen 306e126ba97SEli Cohen return err; 307e126ba97SEli Cohen } 308e126ba97SEli Cohen 309e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 310e126ba97SEli Cohen { 311e126ba97SEli Cohen pci_release_regions(pdev); 312e126ba97SEli Cohen } 313e126ba97SEli Cohen 314bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 315e126ba97SEli Cohen u8 he; 316e126ba97SEli Cohen u8 rsvd[15]; 317e126ba97SEli Cohen }; 318e126ba97SEli Cohen 31987b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32087b8de49SEli Cohen 32187b8de49SEli Cohen enum { 32287b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 323c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 32487b8de49SEli Cohen }; 32587b8de49SEli Cohen 3262974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 327c7a08ac7SEli Cohen { 328c7a08ac7SEli Cohen switch (size) { 329c7a08ac7SEli Cohen case 128: 330c7a08ac7SEli Cohen return 0; 331c7a08ac7SEli Cohen case 256: 332c7a08ac7SEli Cohen return 1; 333c7a08ac7SEli Cohen case 512: 334c7a08ac7SEli Cohen return 2; 335c7a08ac7SEli Cohen case 1024: 336c7a08ac7SEli Cohen return 3; 337c7a08ac7SEli Cohen case 2048: 338c7a08ac7SEli Cohen return 4; 339c7a08ac7SEli Cohen case 4096: 340c7a08ac7SEli Cohen return 5; 341c7a08ac7SEli Cohen default: 3422974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 343c7a08ac7SEli Cohen return 0; 344c7a08ac7SEli Cohen } 345c7a08ac7SEli Cohen } 346c7a08ac7SEli Cohen 347b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 348b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 349938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 350c7a08ac7SEli Cohen { 351b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 352b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 353938fe83cSSaeed Mahameed void *out, *hca_caps; 354938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 355c7a08ac7SEli Cohen int err; 356c7a08ac7SEli Cohen 357b775516bSEli Cohen memset(in, 0, sizeof(in)); 358b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 359c7a08ac7SEli Cohen if (!out) 360c7a08ac7SEli Cohen return -ENOMEM; 361938fe83cSSaeed Mahameed 362b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 363b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3643ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 365c7a08ac7SEli Cohen if (err) { 366938fe83cSSaeed Mahameed mlx5_core_warn(dev, 367938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 368938fe83cSSaeed Mahameed cap_type, cap_mode, err); 369c7a08ac7SEli Cohen goto query_ex; 370c7a08ac7SEli Cohen } 371c7a08ac7SEli Cohen 372938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 373938fe83cSSaeed Mahameed 374938fe83cSSaeed Mahameed switch (cap_mode) { 375938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 37648f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 377938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 378938fe83cSSaeed Mahameed break; 379938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 38048f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 381938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 382938fe83cSSaeed Mahameed break; 383938fe83cSSaeed Mahameed default: 384938fe83cSSaeed Mahameed mlx5_core_warn(dev, 385938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 386938fe83cSSaeed Mahameed cap_type, cap_mode); 387938fe83cSSaeed Mahameed err = -EINVAL; 388938fe83cSSaeed Mahameed break; 389938fe83cSSaeed Mahameed } 390c7a08ac7SEli Cohen query_ex: 391c7a08ac7SEli Cohen kfree(out); 392c7a08ac7SEli Cohen return err; 393c7a08ac7SEli Cohen } 394c7a08ac7SEli Cohen 395b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 396b06e7de8SLeon Romanovsky { 397b06e7de8SLeon Romanovsky int ret; 398b06e7de8SLeon Romanovsky 399b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 400b06e7de8SLeon Romanovsky if (ret) 401b06e7de8SLeon Romanovsky return ret; 402b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 403b06e7de8SLeon Romanovsky } 404b06e7de8SLeon Romanovsky 405a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 406c7a08ac7SEli Cohen { 407b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 408f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4093ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 410c7a08ac7SEli Cohen } 41187b8de49SEli Cohen 412a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 413f91e6d89SEran Ben Elisha { 414f91e6d89SEran Ben Elisha void *set_hca_cap; 415f91e6d89SEran Ben Elisha int req_endianness; 416f91e6d89SEran Ben Elisha int err; 417f91e6d89SEran Ben Elisha 418a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 419a2a322f4SLeon Romanovsky return 0; 420a2a322f4SLeon Romanovsky 421b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 422f91e6d89SEran Ben Elisha if (err) 423f91e6d89SEran Ben Elisha return err; 424f91e6d89SEran Ben Elisha 425f91e6d89SEran Ben Elisha req_endianness = 426f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 427bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 428f91e6d89SEran Ben Elisha 429f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 430f91e6d89SEran Ben Elisha return 0; 431f91e6d89SEran Ben Elisha 432f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 433f91e6d89SEran Ben Elisha 434f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 435bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 436f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 437f91e6d89SEran Ben Elisha 438a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 439f91e6d89SEran Ben Elisha } 440f91e6d89SEran Ben Elisha 441a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 44246861e3eSMoni Shoua { 44346861e3eSMoni Shoua void *set_hca_cap; 444fca22e7eSMoni Shoua bool do_set = false; 44546861e3eSMoni Shoua int err; 44646861e3eSMoni Shoua 44737b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 44837b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 44946861e3eSMoni Shoua return 0; 45046861e3eSMoni Shoua 45146861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 45246861e3eSMoni Shoua if (err) 45346861e3eSMoni Shoua return err; 45446861e3eSMoni Shoua 45546861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 45648f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 45746861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 45846861e3eSMoni Shoua 459fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 460fca22e7eSMoni Shoua do { \ 461fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 462fca22e7eSMoni Shoua if (_res) { \ 463fca22e7eSMoni Shoua do_set = true; \ 464fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 465fca22e7eSMoni Shoua } \ 466fca22e7eSMoni Shoua } while (0) 46746861e3eSMoni Shoua 468fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 469fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 470fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 471fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 472fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 473fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 474fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 475fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 47600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 47700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 47800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 47900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 48000679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 48100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 48246861e3eSMoni Shoua 483a2a322f4SLeon Romanovsky if (!do_set) 484a2a322f4SLeon Romanovsky return 0; 48546861e3eSMoni Shoua 486a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 48746861e3eSMoni Shoua } 48846861e3eSMoni Shoua 4898680a60fSShay Drory static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 4908680a60fSShay Drory { 4918680a60fSShay Drory struct devlink *devlink = priv_to_devlink(dev); 4928680a60fSShay Drory union devlink_param_value val; 4938680a60fSShay Drory int err; 4948680a60fSShay Drory 4958680a60fSShay Drory err = devlink_param_driverinit_value_get(devlink, 4968680a60fSShay Drory DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 4978680a60fSShay Drory &val); 4988680a60fSShay Drory if (!err) 4998680a60fSShay Drory return val.vu32; 5008680a60fSShay Drory mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 5018680a60fSShay Drory return err; 5028680a60fSShay Drory } 5038680a60fSShay Drory 504a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 505e126ba97SEli Cohen { 5063410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 507938fe83cSSaeed Mahameed void *set_hca_cap; 5088680a60fSShay Drory int max_uc_list; 509a2a322f4SLeon Romanovsky int err; 510e126ba97SEli Cohen 511b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 512c7a08ac7SEli Cohen if (err) 513a2a322f4SLeon Romanovsky return err; 514e126ba97SEli Cohen 515938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 516938fe83cSSaeed Mahameed capability); 51748f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 518938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 519938fe83cSSaeed Mahameed 520938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 521707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 522938fe83cSSaeed Mahameed 128); 523c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 524938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5252974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 526e126ba97SEli Cohen 527883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 528f79a609eSMaher Sanalla if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 5297f839965SMaher Sanalla prof->log_max_qp = min_t(u8, 17, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 530f79a609eSMaher Sanalla } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 531883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5323410fbcdSMaor Gottlieb prof->log_max_qp, 533883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5343410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 535883371c4SNoa Osherovich } 536c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 537938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 538938fe83cSSaeed Mahameed prof->log_max_qp); 539e126ba97SEli Cohen 540938fe83cSSaeed Mahameed /* disable cmdif checksum */ 541938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 542c1868b82SEli Cohen 54391828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 54491828bd8SMajd Dibbiny * than 4K. 54591828bd8SMajd Dibbiny */ 54691828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 547f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 548f502d834SEli Cohen 549fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 550fe1e1876SCarol L Soto 551f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 552f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 553f32f5bd2SDaniel Jurgens set_hca_cap, 554f32f5bd2SDaniel Jurgens cache_line_128byte, 555c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 556f32f5bd2SDaniel Jurgens 557dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 558dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 559dd44572aSMoni Shoua 560e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 561e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 562e7f4d0bcSMoshe Shemesh 563c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 564c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 565c4b76d8dSDaniel Jurgens set_hca_cap, 566c4b76d8dSDaniel Jurgens num_vhca_ports, 567c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 568c4b76d8dSDaniel Jurgens 569c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 570c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 571c6168161SEran Ben Elisha 5724dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 5734dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 5744dca6509SMichael Guralnik 575f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 576f3196bb0SParav Pandit 577604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 578604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 579604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 580604774adSLeon Romanovsky 581fbfa97b4SShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported)) 582fbfa97b4SShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev)); 583fbfa97b4SShay Drory 5848680a60fSShay Drory max_uc_list = max_uc_list_get_devlink_param(dev); 5858680a60fSShay Drory if (max_uc_list > 0) 5868680a60fSShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 5878680a60fSShay Drory ilog2(max_uc_list)); 5888680a60fSShay Drory 589a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 590e126ba97SEli Cohen } 591cd23b14bSEli Cohen 592fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 593fbfa97b4SShay Drory * boot process. 594fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 595fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 596fbfa97b4SShay Drory * Hence, the need for this function. 597fbfa97b4SShay Drory * 598fbfa97b4SShay Drory * Returns 599fbfa97b4SShay Drory * True: 600fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 601fbfa97b4SShay Drory * OR: 602fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 603fbfa97b4SShay Drory * 604fbfa97b4SShay Drory * In any other case, return False. 605fbfa97b4SShay Drory */ 606fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 607fbfa97b4SShay Drory { 608fbfa97b4SShay Drory return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) || 609fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 610fbfa97b4SShay Drory } 611fbfa97b4SShay Drory 61259e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 61359e9e8e4SMark Zhang { 61459e9e8e4SMark Zhang void *set_hca_cap; 61559e9e8e4SMark Zhang int err; 61659e9e8e4SMark Zhang 617fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 61859e9e8e4SMark Zhang return 0; 61959e9e8e4SMark Zhang 62059e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 62159e9e8e4SMark Zhang if (err) 62259e9e8e4SMark Zhang return err; 62359e9e8e4SMark Zhang 62459e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 62559e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 62659e9e8e4SMark Zhang return 0; 62759e9e8e4SMark Zhang 62859e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 62948f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 63059e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 63159e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 63259e9e8e4SMark Zhang 63359e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 634e126ba97SEli Cohen return err; 635e126ba97SEli Cohen } 636e126ba97SEli Cohen 63737b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 63837b6bb77SLeon Romanovsky { 639a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 640a2a322f4SLeon Romanovsky void *set_ctx; 64137b6bb77SLeon Romanovsky int err; 64237b6bb77SLeon Romanovsky 643a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 644a2a322f4SLeon Romanovsky if (!set_ctx) 645a2a322f4SLeon Romanovsky return -ENOMEM; 646a2a322f4SLeon Romanovsky 647a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 64837b6bb77SLeon Romanovsky if (err) { 64998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 65037b6bb77SLeon Romanovsky goto out; 65137b6bb77SLeon Romanovsky } 65237b6bb77SLeon Romanovsky 653a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 654a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 65537b6bb77SLeon Romanovsky if (err) { 65698a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 65737b6bb77SLeon Romanovsky goto out; 65837b6bb77SLeon Romanovsky } 65937b6bb77SLeon Romanovsky 660a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 661a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 66237b6bb77SLeon Romanovsky if (err) { 66398a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 66437b6bb77SLeon Romanovsky goto out; 66537b6bb77SLeon Romanovsky } 66637b6bb77SLeon Romanovsky 66759e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 66859e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 66959e9e8e4SMark Zhang if (err) { 67059e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 67159e9e8e4SMark Zhang goto out; 67259e9e8e4SMark Zhang } 67359e9e8e4SMark Zhang 67437b6bb77SLeon Romanovsky out: 675a2a322f4SLeon Romanovsky kfree(set_ctx); 67637b6bb77SLeon Romanovsky return err; 67737b6bb77SLeon Romanovsky } 67837b6bb77SLeon Romanovsky 679e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 680e126ba97SEli Cohen { 681bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 682bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 683e126ba97SEli Cohen int err; 684e126ba97SEli Cohen 685fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 686fc50db98SEli Cohen return 0; 687fc50db98SEli Cohen 688e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 689e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 690e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 691e126ba97SEli Cohen &he_out, sizeof(he_out), 692e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 693e126ba97SEli Cohen return err; 694e126ba97SEli Cohen } 695e126ba97SEli Cohen 696c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 697c85023e1SHuy Nguyen { 698c85023e1SHuy Nguyen int ret = 0; 699c85023e1SHuy Nguyen 700c85023e1SHuy Nguyen /* Disable local_lb by default */ 7018978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 702c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 703c85023e1SHuy Nguyen 704c85023e1SHuy Nguyen return ret; 705c85023e1SHuy Nguyen } 706c85023e1SHuy Nguyen 7070b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 708e126ba97SEli Cohen { 7093ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 710e126ba97SEli Cohen 7110b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 7120b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 71322e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 71422e939a9SBodong Wang dev->caps.embedded_cpu); 7153ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 716e126ba97SEli Cohen } 717e126ba97SEli Cohen 7180b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 719e126ba97SEli Cohen { 7203ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 721e126ba97SEli Cohen 7220b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 7230b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 72422e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 72522e939a9SBodong Wang dev->caps.embedded_cpu); 7263ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 727e126ba97SEli Cohen } 728e126ba97SEli Cohen 729f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 730f62b8bb8SAmir Vadai { 7313ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 7323ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 733f62b8bb8SAmir Vadai u32 sup_issi; 734c4f287c4SSaeed Mahameed int err; 735f62b8bb8SAmir Vadai 736f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 7373ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 738f62b8bb8SAmir Vadai if (err) { 739605bef00SSaeed Mahameed u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 740605bef00SSaeed Mahameed u8 status = MLX5_GET(query_issi_out, query_out, status); 741c4f287c4SSaeed Mahameed 742f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 743f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 744f9c14e46SKamal Heib err, status, syndrome); 745f9c14e46SKamal Heib return err; 746f62b8bb8SAmir Vadai } 747f62b8bb8SAmir Vadai 748f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 749f9c14e46SKamal Heib dev->issi = 0; 750f9c14e46SKamal Heib return 0; 751f62b8bb8SAmir Vadai } 752f62b8bb8SAmir Vadai 753f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 754f62b8bb8SAmir Vadai 755f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7563ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 757f62b8bb8SAmir Vadai 758f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 759f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7603ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 761f62b8bb8SAmir Vadai if (err) { 762f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 763f9c14e46SKamal Heib err); 764f62b8bb8SAmir Vadai return err; 765f62b8bb8SAmir Vadai } 766f62b8bb8SAmir Vadai 767f62b8bb8SAmir Vadai dev->issi = 1; 768f62b8bb8SAmir Vadai 769f62b8bb8SAmir Vadai return 0; 770e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 771f62b8bb8SAmir Vadai return 0; 772f62b8bb8SAmir Vadai } 773f62b8bb8SAmir Vadai 7749eb78923SOr Gerlitz return -EOPNOTSUPP; 775f62b8bb8SAmir Vadai } 776f62b8bb8SAmir Vadai 77711f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 77811f3b84dSSaeed Mahameed const struct pci_device_id *id) 779a31208b1SMajd Dibbiny { 780a31208b1SMajd Dibbiny int err = 0; 781a31208b1SMajd Dibbiny 782d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 783e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 784e126ba97SEli Cohen 785aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 786311c7c71SSaeed Mahameed 78789d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 788e126ba97SEli Cohen if (err) { 78998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 79011f3b84dSSaeed Mahameed return err; 791e126ba97SEli Cohen } 792e126ba97SEli Cohen 793e126ba97SEli Cohen err = request_bar(pdev); 794e126ba97SEli Cohen if (err) { 79598a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 796e126ba97SEli Cohen goto err_disable; 797e126ba97SEli Cohen } 798e126ba97SEli Cohen 799e126ba97SEli Cohen pci_set_master(pdev); 800e126ba97SEli Cohen 801e126ba97SEli Cohen err = set_dma_caps(pdev); 802e126ba97SEli Cohen if (err) { 80398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 804e126ba97SEli Cohen goto err_clr_master; 805e126ba97SEli Cohen } 806e126ba97SEli Cohen 807ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 808ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 809ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 810ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 811ce4eee53SMichael Guralnik 812aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 813e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 814e126ba97SEli Cohen if (!dev->iseg) { 815e126ba97SEli Cohen err = -ENOMEM; 81698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 817e126ba97SEli Cohen goto err_clr_master; 818e126ba97SEli Cohen } 819a31208b1SMajd Dibbiny 820b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 821c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 822a31208b1SMajd Dibbiny return 0; 823a31208b1SMajd Dibbiny 824a31208b1SMajd Dibbiny err_clr_master: 825a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 826a31208b1SMajd Dibbiny release_bar(dev->pdev); 827a31208b1SMajd Dibbiny err_disable: 82889d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 829a31208b1SMajd Dibbiny return err; 830a31208b1SMajd Dibbiny } 831a31208b1SMajd Dibbiny 832868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 833a31208b1SMajd Dibbiny { 83442ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 83542ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 83642ea9f1bSShay Drory * before removing the pci bars 83742ea9f1bSShay Drory */ 83842ea9f1bSShay Drory mlx5_drain_health_wq(dev); 839a31208b1SMajd Dibbiny iounmap(dev->iseg); 840a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 841a31208b1SMajd Dibbiny release_bar(dev->pdev); 84289d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 843a31208b1SMajd Dibbiny } 844a31208b1SMajd Dibbiny 845868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 84659211bd3SMohamad Haj Yahia { 84759211bd3SMohamad Haj Yahia int err; 84859211bd3SMohamad Haj Yahia 849868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 850868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 85198a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 852868bc06bSSaeed Mahameed dev->priv.devcom); 853fadd59fcSAviv Heller 85459211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 85559211bd3SMohamad Haj Yahia if (err) { 85698a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 857fadd59fcSAviv Heller goto err_devcom; 85859211bd3SMohamad Haj Yahia } 85959211bd3SMohamad Haj Yahia 860561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 861561aa15aSYuval Avnery if (err) { 862561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 863561aa15aSYuval Avnery goto err_devcom; 864561aa15aSYuval Avnery } 865561aa15aSYuval Avnery 866f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 86759211bd3SMohamad Haj Yahia if (err) { 86898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 869561aa15aSYuval Avnery goto err_irq_cleanup; 87059211bd3SMohamad Haj Yahia } 87159211bd3SMohamad Haj Yahia 87269c1280bSSaeed Mahameed err = mlx5_events_init(dev); 87369c1280bSSaeed Mahameed if (err) { 87498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 87569c1280bSSaeed Mahameed goto err_eq_cleanup; 87669c1280bSSaeed Mahameed } 87769c1280bSSaeed Mahameed 87838b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 87938b9f903SMoshe Shemesh if (err) { 88038b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 88138b9f903SMoshe Shemesh goto err_events_cleanup; 88238b9f903SMoshe Shemesh } 88338b9f903SMoshe Shemesh 8849f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 88559211bd3SMohamad Haj Yahia 88652ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 88752ec462eSIlan Tayari 8887c39afb3SFeras Daoud mlx5_init_clock(dev); 8897c39afb3SFeras Daoud 890358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8910ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 892358aa5ceSSaeed Mahameed 89359211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 89459211bd3SMohamad Haj Yahia if (err) { 89598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 89659211bd3SMohamad Haj Yahia goto err_tables_cleanup; 89759211bd3SMohamad Haj Yahia } 89859211bd3SMohamad Haj Yahia 899eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 900eeb66cdbSSaeed Mahameed if (err) { 90198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 902eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 903eeb66cdbSSaeed Mahameed } 904eeb66cdbSSaeed Mahameed 905c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 906c2d6e31aSMohamad Haj Yahia if (err) { 90798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 90886eec50bSBodong Wang goto err_mpfs_cleanup; 90986eec50bSBodong Wang } 91086eec50bSBodong Wang 91186eec50bSBodong Wang err = mlx5_eswitch_init(dev); 91286eec50bSBodong Wang if (err) { 91386eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 91486eec50bSBodong Wang goto err_sriov_cleanup; 915c2d6e31aSMohamad Haj Yahia } 916c2d6e31aSMohamad Haj Yahia 9179410733cSIlan Tayari err = mlx5_fpga_init(dev); 9189410733cSIlan Tayari if (err) { 91998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 92086eec50bSBodong Wang goto err_eswitch_cleanup; 9219410733cSIlan Tayari } 9229410733cSIlan Tayari 923f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 924f3196bb0SParav Pandit if (err) { 925f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 926f3196bb0SParav Pandit goto err_fpga_cleanup; 927f3196bb0SParav Pandit } 928f3196bb0SParav Pandit 9298f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 9308f010541SParav Pandit if (err) { 9318f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 9328f010541SParav Pandit goto err_sf_hw_table_cleanup; 9338f010541SParav Pandit } 9348f010541SParav Pandit 9358f010541SParav Pandit err = mlx5_sf_table_init(dev); 9368f010541SParav Pandit if (err) { 9378f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 9388f010541SParav Pandit goto err_sf_table_cleanup; 9398f010541SParav Pandit } 9408f010541SParav Pandit 941c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 942c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 943c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 944c9b9dcb4SAriel Levkovich 94524406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 94687175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 94712206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 94824406953SFeras Daoud 94959211bd3SMohamad Haj Yahia return 0; 95059211bd3SMohamad Haj Yahia 9518f010541SParav Pandit err_sf_table_cleanup: 9528f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 9538f010541SParav Pandit err_sf_hw_table_cleanup: 9548f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 955f3196bb0SParav Pandit err_fpga_cleanup: 956f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 957c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 958c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 95986eec50bSBodong Wang err_sriov_cleanup: 96086eec50bSBodong Wang mlx5_sriov_cleanup(dev); 961eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 962eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 963c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 964c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 96559211bd3SMohamad Haj Yahia err_tables_cleanup: 9660ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 967358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 96802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 96938b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 97038b9f903SMoshe Shemesh err_events_cleanup: 97169c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 97259211bd3SMohamad Haj Yahia err_eq_cleanup: 973f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 974561aa15aSYuval Avnery err_irq_cleanup: 975561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 976fadd59fcSAviv Heller err_devcom: 977fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 97859211bd3SMohamad Haj Yahia 97959211bd3SMohamad Haj Yahia return err; 98059211bd3SMohamad Haj Yahia } 98159211bd3SMohamad Haj Yahia 98259211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 98359211bd3SMohamad Haj Yahia { 98412206b17SAya Levin mlx5_rsc_dump_destroy(dev); 98587175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 98624406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 987c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9888f010541SParav Pandit mlx5_sf_table_cleanup(dev); 9898f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 990f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 9919410733cSIlan Tayari mlx5_fpga_cleanup(dev); 992c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 99386eec50bSBodong Wang mlx5_sriov_cleanup(dev); 994eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 99559211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9960ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 997358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9987c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 99952ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 100002d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 100138b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 100269c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 1003f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 1004561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 1005fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 100659211bd3SMohamad Haj Yahia } 100759211bd3SMohamad Haj Yahia 1008e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 1009a31208b1SMajd Dibbiny { 1010a31208b1SMajd Dibbiny int err; 1011a31208b1SMajd Dibbiny 101298a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1013e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 1014e126ba97SEli Cohen 101500c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 101600c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 101700c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 101800c6bcb0STal Gilboa 101976091b0fSAmir Tzin mlx5_tout_set_def_val(dev); 10205945e1adSAmir Tzin 10216c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 10226c780a02SEli Cohen */ 10235945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT), 10245945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 10256c780a02SEli Cohen if (err) { 10265945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 10275945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 102876091b0fSAmir Tzin return err; 10296c780a02SEli Cohen } 10306c780a02SEli Cohen 1031e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1032e126ba97SEli Cohen if (err) { 103398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 103476091b0fSAmir Tzin return err; 1035e126ba97SEli Cohen } 1036e126ba97SEli Cohen 10375945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 10385945e1adSAmir Tzin 10395945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1040e3297246SEli Cohen if (err) { 10415945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 10425945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 104355378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1044e3297246SEli Cohen } 1045e3297246SEli Cohen 1046f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1047f7936dddSEran Ben Elisha 10480b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1049cd23b14bSEli Cohen if (err) { 105098a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 105159211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 1052cd23b14bSEli Cohen } 1053cd23b14bSEli Cohen 1054f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1055f62b8bb8SAmir Vadai if (err) { 105698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1057f62b8bb8SAmir Vadai goto err_disable_hca; 1058f62b8bb8SAmir Vadai } 1059f62b8bb8SAmir Vadai 1060cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1061cd23b14bSEli Cohen if (err) { 106298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1063cd23b14bSEli Cohen goto err_disable_hca; 1064cd23b14bSEli Cohen } 1065cd23b14bSEli Cohen 106632def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 106732def412SAmir Tzin if (err) { 106832def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 106932def412SAmir Tzin goto reclaim_boot_pages; 107032def412SAmir Tzin } 107132def412SAmir Tzin 1072e126ba97SEli Cohen err = set_hca_ctrl(dev); 1073e126ba97SEli Cohen if (err) { 107498a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1075cd23b14bSEli Cohen goto reclaim_boot_pages; 1076e126ba97SEli Cohen } 1077e126ba97SEli Cohen 107837b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1079e126ba97SEli Cohen if (err) { 108098a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 108146861e3eSMoni Shoua goto reclaim_boot_pages; 108246861e3eSMoni Shoua } 108346861e3eSMoni Shoua 1084cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1085e126ba97SEli Cohen if (err) { 108698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1087cd23b14bSEli Cohen goto reclaim_boot_pages; 1088e126ba97SEli Cohen } 1089e126ba97SEli Cohen 10908737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1091e126ba97SEli Cohen if (err) { 109298a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10930cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1094e126ba97SEli Cohen } 1095e126ba97SEli Cohen 1096012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1097012e50e1SHuy Nguyen 1098bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1099bba1574cSDaniel Jurgens if (err) { 110098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1101502e82b9SAya Levin goto reclaim_boot_pages; 1102bba1574cSDaniel Jurgens } 1103bba1574cSDaniel Jurgens 1104502e82b9SAya Levin mlx5_start_health_poll(dev); 1105502e82b9SAya Levin 1106e161105eSSaeed Mahameed return 0; 1107e161105eSSaeed Mahameed 1108e161105eSSaeed Mahameed reclaim_boot_pages: 1109e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1110e161105eSSaeed Mahameed err_disable_hca: 1111e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1112e161105eSSaeed Mahameed err_cmd_cleanup: 1113f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1114e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1115e161105eSSaeed Mahameed 1116e161105eSSaeed Mahameed return err; 1117e161105eSSaeed Mahameed } 1118e161105eSSaeed Mahameed 1119e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1120e161105eSSaeed Mahameed { 1121e161105eSSaeed Mahameed int err; 1122e161105eSSaeed Mahameed 1123e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1124e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1125259bbc57SMaor Gottlieb if (err) { 112698a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1127e161105eSSaeed Mahameed return err; 1128e126ba97SEli Cohen } 1129e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1130e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1131f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1132e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1133e161105eSSaeed Mahameed 1134e161105eSSaeed Mahameed return 0; 1135259bbc57SMaor Gottlieb } 1136e126ba97SEli Cohen 1137a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1138e161105eSSaeed Mahameed { 1139e161105eSSaeed Mahameed int err; 1140e161105eSSaeed Mahameed 114101187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 114272f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 114398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 114472f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1145a80d1b68SSaeed Mahameed return err; 1146e126ba97SEli Cohen } 1147e126ba97SEli Cohen 114869c1280bSSaeed Mahameed mlx5_events_start(dev); 11490cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 11500cf53c12SSaeed Mahameed 1151e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1152e1706e62SYuval Avnery if (err) { 1153e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1154e1706e62SYuval Avnery goto err_irq_table; 1155e1706e62SYuval Avnery } 1156e1706e62SYuval Avnery 1157c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1158e126ba97SEli Cohen if (err) { 115998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1160c8e21b3bSSaeed Mahameed goto err_eq_table; 1161e126ba97SEli Cohen } 1162e126ba97SEli Cohen 116324406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 116424406953SFeras Daoud if (err) { 1165f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1166f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1167f62eb932SAya Levin dev->tracer = NULL; 116824406953SFeras Daoud } 116924406953SFeras Daoud 117038b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 117187175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 117287175120SEran Ben Elisha 117312206b17SAya Levin err = mlx5_rsc_dump_init(dev); 117412206b17SAya Levin if (err) { 1175f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1176f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1177f62eb932SAya Levin dev->rsc_dump = NULL; 117812206b17SAya Levin } 117912206b17SAya Levin 118004e87170SMatan Barak err = mlx5_fpga_device_start(dev); 118104e87170SMatan Barak if (err) { 118298a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 118304e87170SMatan Barak goto err_fpga_start; 118404e87170SMatan Barak } 118504e87170SMatan Barak 11869a6ad1adSRaed Salem mlx5_accel_ipsec_init(dev); 118704e87170SMatan Barak 11881ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11891ae17322SIlya Lesokhin if (err) { 119098a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11911ae17322SIlya Lesokhin goto err_tls_start; 11921ae17322SIlya Lesokhin } 11931ae17322SIlya Lesokhin 119486d722adSMaor Gottlieb err = mlx5_init_fs(dev); 119586d722adSMaor Gottlieb if (err) { 119698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 119786d722adSMaor Gottlieb goto err_fs; 119886d722adSMaor Gottlieb } 11991466cc5bSYevgeny Petrilin 1200c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1201c85023e1SHuy Nguyen if (err) { 120298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 120394a4b841SLeon Romanovsky goto err_set_hca; 1204c85023e1SHuy Nguyen } 1205c85023e1SHuy Nguyen 1206f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1207f3196bb0SParav Pandit 12086a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 12096a327321SParav Pandit if (err) { 12106a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 12116a327321SParav Pandit goto err_vhca; 12126a327321SParav Pandit } 12136a327321SParav Pandit 121422e939a9SBodong Wang err = mlx5_ec_init(dev); 121522e939a9SBodong Wang if (err) { 121698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 121722e939a9SBodong Wang goto err_ec; 121822e939a9SBodong Wang } 121922e939a9SBodong Wang 1220cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 12215bef709dSParav Pandit err = mlx5_sriov_attach(dev); 12225bef709dSParav Pandit if (err) { 12235bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 12245bef709dSParav Pandit goto err_sriov; 12255bef709dSParav Pandit } 12265bef709dSParav Pandit 122790d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 122890d010b8SParav Pandit 1229a80d1b68SSaeed Mahameed return 0; 1230a80d1b68SSaeed Mahameed 1231a80d1b68SSaeed Mahameed err_sriov: 1232cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 12335bef709dSParav Pandit mlx5_ec_cleanup(dev); 12345bef709dSParav Pandit err_ec: 12356a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 12366a327321SParav Pandit err_vhca: 1237f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 123894a4b841SLeon Romanovsky err_set_hca: 1239a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1240a80d1b68SSaeed Mahameed err_fs: 1241a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1242a80d1b68SSaeed Mahameed err_tls_start: 1243a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1244a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1245a80d1b68SSaeed Mahameed err_fpga_start: 124612206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 124787175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 124838b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1249a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1250a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1251a80d1b68SSaeed Mahameed err_eq_table: 1252e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1253e1706e62SYuval Avnery err_irq_table: 1254a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1255a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1256a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1257a80d1b68SSaeed Mahameed return err; 1258a80d1b68SSaeed Mahameed } 1259a80d1b68SSaeed Mahameed 1260a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1261a80d1b68SSaeed Mahameed { 126290d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1263a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1264cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 12655bef709dSParav Pandit mlx5_ec_cleanup(dev); 12666a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1267f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1268a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1269a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1270a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1271a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 127212206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 127387175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 127438b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1275a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1276a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1277e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1278a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1279a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1280a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1281a80d1b68SSaeed Mahameed } 1282a80d1b68SSaeed Mahameed 12836dea2f7eSLeon Romanovsky int mlx5_init_one(struct mlx5_core_dev *dev) 1284a80d1b68SSaeed Mahameed { 1285a80d1b68SSaeed Mahameed int err = 0; 1286a80d1b68SSaeed Mahameed 1287a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1288a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1289a80d1b68SSaeed Mahameed 12906dea2f7eSLeon Romanovsky err = mlx5_function_setup(dev, true); 1291a80d1b68SSaeed Mahameed if (err) 12924f7400d5SShay Drory goto err_function; 1293a80d1b68SSaeed Mahameed 1294a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1295a80d1b68SSaeed Mahameed if (err) { 129698a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1297a80d1b68SSaeed Mahameed goto function_teardown; 1298a80d1b68SSaeed Mahameed } 1299a80d1b68SSaeed Mahameed 1300a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1301a80d1b68SSaeed Mahameed if (err) 1302a80d1b68SSaeed Mahameed goto err_load; 1303a80d1b68SSaeed Mahameed 130498f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 130598f91c45SParav Pandit 1306919d13a7SLeon Romanovsky err = mlx5_devlink_register(priv_to_devlink(dev)); 1307a6f3b623SMichael Guralnik if (err) 1308a6f3b623SMichael Guralnik goto err_devlink_reg; 1309a925b5e3SLeon Romanovsky 1310a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1311a925b5e3SLeon Romanovsky if (err) 1312a925b5e3SLeon Romanovsky goto err_register; 1313a925b5e3SLeon Romanovsky 13144162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 13154162f58bSParav Pandit return 0; 1316e126ba97SEli Cohen 1317a925b5e3SLeon Romanovsky err_register: 1318a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1319a6f3b623SMichael Guralnik err_devlink_reg: 132098f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1321a80d1b68SSaeed Mahameed mlx5_unload(dev); 1322a80d1b68SSaeed Mahameed err_load: 132359211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1324e161105eSSaeed Mahameed function_teardown: 13256dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 13264f7400d5SShay Drory err_function: 132789d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 132889d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1329e126ba97SEli Cohen return err; 1330e126ba97SEli Cohen } 1331e126ba97SEli Cohen 13326dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1333e126ba97SEli Cohen { 133489d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 133598f91c45SParav Pandit 133698f91c45SParav Pandit mlx5_unregister_device(dev); 133798f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 133898f91c45SParav Pandit 1339b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 134098a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 134189d44f0aSMajd Dibbiny __func__); 134259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 134389d44f0aSMajd Dibbiny goto out; 134489d44f0aSMajd Dibbiny } 13456b6adee3SMohamad Haj Yahia 13469ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1347a80d1b68SSaeed Mahameed mlx5_unload(dev); 134859211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 13496dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 13506dea2f7eSLeon Romanovsky out: 13516dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13526dea2f7eSLeon Romanovsky } 13530cf53c12SSaeed Mahameed 13546dea2f7eSLeon Romanovsky int mlx5_load_one(struct mlx5_core_dev *dev) 13556dea2f7eSLeon Romanovsky { 13566dea2f7eSLeon Romanovsky int err = 0; 13576dea2f7eSLeon Romanovsky 13586dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 13596dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 13606dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 13616dea2f7eSLeon Romanovsky goto out; 13626dea2f7eSLeon Romanovsky } 13636dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 13646dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 13656dea2f7eSLeon Romanovsky 13666dea2f7eSLeon Romanovsky err = mlx5_function_setup(dev, false); 13676dea2f7eSLeon Romanovsky if (err) 13686dea2f7eSLeon Romanovsky goto err_function; 13696dea2f7eSLeon Romanovsky 13706dea2f7eSLeon Romanovsky err = mlx5_load(dev); 13716dea2f7eSLeon Romanovsky if (err) 13726dea2f7eSLeon Romanovsky goto err_load; 13736dea2f7eSLeon Romanovsky 13746dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13756dea2f7eSLeon Romanovsky 13766dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 13776dea2f7eSLeon Romanovsky if (err) 13786dea2f7eSLeon Romanovsky goto err_attach; 13796dea2f7eSLeon Romanovsky 13806dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13816dea2f7eSLeon Romanovsky return 0; 13826dea2f7eSLeon Romanovsky 13836dea2f7eSLeon Romanovsky err_attach: 13846dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13856dea2f7eSLeon Romanovsky mlx5_unload(dev); 13866dea2f7eSLeon Romanovsky err_load: 13876dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 13886dea2f7eSLeon Romanovsky err_function: 13896dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 13906dea2f7eSLeon Romanovsky out: 13916dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13926dea2f7eSLeon Romanovsky return err; 13936dea2f7eSLeon Romanovsky } 13946dea2f7eSLeon Romanovsky 13956dea2f7eSLeon Romanovsky void mlx5_unload_one(struct mlx5_core_dev *dev) 13966dea2f7eSLeon Romanovsky { 13976dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 13986dea2f7eSLeon Romanovsky 13996dea2f7eSLeon Romanovsky mlx5_detach_device(dev); 14006dea2f7eSLeon Romanovsky 14016dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 14026dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 14036dea2f7eSLeon Romanovsky __func__); 14046dea2f7eSLeon Romanovsky goto out; 14056dea2f7eSLeon Romanovsky } 14066dea2f7eSLeon Romanovsky 14076dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 14086dea2f7eSLeon Romanovsky mlx5_unload(dev); 14096dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1410ac6ea6e8SEli Cohen out: 141189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 14129603b61dSJack Morgenstein } 141364613d94SSaeed Mahameed 141448f02eefSParav Pandit static const int types[] = { 141548f02eefSParav Pandit MLX5_CAP_GENERAL, 141648f02eefSParav Pandit MLX5_CAP_GENERAL_2, 141748f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 141848f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 141948f02eefSParav Pandit MLX5_CAP_ODP, 142048f02eefSParav Pandit MLX5_CAP_ATOMIC, 142148f02eefSParav Pandit MLX5_CAP_ROCE, 142248f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 142348f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 142448f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 142548f02eefSParav Pandit MLX5_CAP_ESWITCH, 142648f02eefSParav Pandit MLX5_CAP_VECTOR_CALC, 142748f02eefSParav Pandit MLX5_CAP_QOS, 142848f02eefSParav Pandit MLX5_CAP_DEBUG, 142948f02eefSParav Pandit MLX5_CAP_DEV_MEM, 143048f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 143148f02eefSParav Pandit MLX5_CAP_TLS, 143248f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 143348f02eefSParav Pandit MLX5_CAP_IPSEC, 1434425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 14357025329dSBen Ben-Ishay MLX5_CAP_DEV_SHAMPO, 143648f02eefSParav Pandit }; 143748f02eefSParav Pandit 143848f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 143948f02eefSParav Pandit { 144048f02eefSParav Pandit int type; 144148f02eefSParav Pandit int i; 144248f02eefSParav Pandit 144348f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 144448f02eefSParav Pandit type = types[i]; 144548f02eefSParav Pandit kfree(dev->caps.hca[type]); 144648f02eefSParav Pandit } 144748f02eefSParav Pandit } 144848f02eefSParav Pandit 144948f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 145048f02eefSParav Pandit { 145148f02eefSParav Pandit struct mlx5_hca_cap *cap; 145248f02eefSParav Pandit int type; 145348f02eefSParav Pandit int i; 145448f02eefSParav Pandit 145548f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 145648f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 145748f02eefSParav Pandit if (!cap) 145848f02eefSParav Pandit goto err; 145948f02eefSParav Pandit type = types[i]; 146048f02eefSParav Pandit dev->caps.hca[type] = cap; 146148f02eefSParav Pandit } 146248f02eefSParav Pandit 146348f02eefSParav Pandit return 0; 146448f02eefSParav Pandit 146548f02eefSParav Pandit err: 146648f02eefSParav Pandit mlx5_hca_caps_free(dev); 146748f02eefSParav Pandit return -ENOMEM; 146848f02eefSParav Pandit } 146948f02eefSParav Pandit 14701958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 14719603b61dSJack Morgenstein { 147211f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 14739603b61dSJack Morgenstein int err; 14749603b61dSJack Morgenstein 14753410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1476364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1477364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 147889d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1479d9aaed83SArtemy Kovalyov 148001187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 148101187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 148201187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 148301187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 148401187175SEli Cohen 148511f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 148611f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 148711f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 148811f3b84dSSaeed Mahameed 148944f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1490*66771a1cSMoshe Shemesh priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 149127b942fbSParav Pandit mlx5_debugfs_root); 14923d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 14933d347b1bSAya Levin 149476091b0fSAmir Tzin err = mlx5_tout_init(dev); 149576091b0fSAmir Tzin if (err) { 149676091b0fSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 149776091b0fSAmir Tzin goto err_timeout_init; 149876091b0fSAmir Tzin } 149976091b0fSAmir Tzin 1500ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 150152c368dcSSaeed Mahameed if (err) 150252c368dcSSaeed Mahameed goto err_health_init; 1503ac6ea6e8SEli Cohen 15040cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 15050cf53c12SSaeed Mahameed if (err) 15060cf53c12SSaeed Mahameed goto err_pagealloc_init; 150759211bd3SMohamad Haj Yahia 1508a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1509a925b5e3SLeon Romanovsky if (err) 1510a925b5e3SLeon Romanovsky goto err_adev_init; 1511a925b5e3SLeon Romanovsky 151248f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 151348f02eefSParav Pandit if (err) 151448f02eefSParav Pandit goto err_hca_caps; 151548f02eefSParav Pandit 151611f3b84dSSaeed Mahameed return 0; 151752c368dcSSaeed Mahameed 151848f02eefSParav Pandit err_hca_caps: 151948f02eefSParav Pandit mlx5_adev_cleanup(dev); 1520a925b5e3SLeon Romanovsky err_adev_init: 1521a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 152252c368dcSSaeed Mahameed err_pagealloc_init: 152352c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 152452c368dcSSaeed Mahameed err_health_init: 152576091b0fSAmir Tzin mlx5_tout_cleanup(dev); 152676091b0fSAmir Tzin err_timeout_init: 1527*66771a1cSMoshe Shemesh debugfs_remove(dev->priv.dbg.dbg_root); 1528810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1529810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1530810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1531810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1532810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 153352c368dcSSaeed Mahameed return err; 153411f3b84dSSaeed Mahameed } 153511f3b84dSSaeed Mahameed 15361958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 153711f3b84dSSaeed Mahameed { 1538810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1539810cbb25SParav Pandit 154048f02eefSParav Pandit mlx5_hca_caps_free(dev); 1541a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 154252c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 154352c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 154476091b0fSAmir Tzin mlx5_tout_cleanup(dev); 1545*66771a1cSMoshe Shemesh debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1546810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1547810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1548810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1549810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1550810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 155111f3b84dSSaeed Mahameed } 155211f3b84dSSaeed Mahameed 15536dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 155411f3b84dSSaeed Mahameed { 155511f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 155611f3b84dSSaeed Mahameed struct devlink *devlink; 155711f3b84dSSaeed Mahameed int err; 155811f3b84dSSaeed Mahameed 1559919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 156011f3b84dSSaeed Mahameed if (!devlink) { 15611f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 156211f3b84dSSaeed Mahameed return -ENOMEM; 156311f3b84dSSaeed Mahameed } 156411f3b84dSSaeed Mahameed 156511f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 156627b942fbSParav Pandit dev->device = &pdev->dev; 156727b942fbSParav Pandit dev->pdev = pdev; 156811f3b84dSSaeed Mahameed 1569386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1570386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1571386e75afSHuy Nguyen 1572a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 15734d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 15744d8be211SLeon Romanovsky err = dev->priv.adev_idx; 15754d8be211SLeon Romanovsky goto adev_init_err; 15764d8be211SLeon Romanovsky } 1577a925b5e3SLeon Romanovsky 157827b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 157911f3b84dSSaeed Mahameed if (err) 158011f3b84dSSaeed Mahameed goto mdev_init_err; 158111f3b84dSSaeed Mahameed 158211f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 15839603b61dSJack Morgenstein if (err) { 158498a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 158598a8e6fcSHuy Nguyen err); 158611f3b84dSSaeed Mahameed goto pci_init_err; 15879603b61dSJack Morgenstein } 15889603b61dSJack Morgenstein 15896dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 15909603b61dSJack Morgenstein if (err) { 15916dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 159298a8e6fcSHuy Nguyen err); 15936dea2f7eSLeon Romanovsky goto err_init_one; 15949603b61dSJack Morgenstein } 159559211bd3SMohamad Haj Yahia 15968b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 15978b9d8baaSAlex Vesker if (err) 15988b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 15998b9d8baaSAlex Vesker 16005d47f6c8SDaniel Jurgens pci_save_state(pdev); 160164ea2d0eSLeon Romanovsky devlink_register(devlink); 16029603b61dSJack Morgenstein return 0; 16039603b61dSJack Morgenstein 16046dea2f7eSLeon Romanovsky err_init_one: 1605868bc06bSSaeed Mahameed mlx5_pci_close(dev); 160611f3b84dSSaeed Mahameed pci_init_err: 160711f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 160811f3b84dSSaeed Mahameed mdev_init_err: 1609a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 16104d8be211SLeon Romanovsky adev_init_err: 16111f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1612a31208b1SMajd Dibbiny 16139603b61dSJack Morgenstein return err; 16149603b61dSJack Morgenstein } 1615a31208b1SMajd Dibbiny 16169603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 16179603b61dSJack Morgenstein { 16189603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1619feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 16209603b61dSJack Morgenstein 162164ea2d0eSLeon Romanovsky devlink_unregister(devlink); 16228b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 162341798df9SParav Pandit mlx5_drain_health_wq(dev); 16246dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1625868bc06bSSaeed Mahameed mlx5_pci_close(dev); 162611f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1627a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 16281f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 16299603b61dSJack Morgenstein } 16309603b61dSJack Morgenstein 1631fad1783aSSaeed Mahameed #define mlx5_pci_trace(dev, fmt, ...) ({ \ 1632fad1783aSSaeed Mahameed struct mlx5_core_dev *__dev = (dev); \ 1633fad1783aSSaeed Mahameed mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 1634fad1783aSSaeed Mahameed __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 1635fad1783aSSaeed Mahameed __dev->pci_status, ##__VA_ARGS__); \ 1636fad1783aSSaeed Mahameed }) 1637fad1783aSSaeed Mahameed 1638fad1783aSSaeed Mahameed static const char *result2str(enum pci_ers_result result) 1639fad1783aSSaeed Mahameed { 1640fad1783aSSaeed Mahameed return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 1641fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 1642fad1783aSSaeed Mahameed result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 1643fad1783aSSaeed Mahameed "unknown"; 1644fad1783aSSaeed Mahameed } 1645fad1783aSSaeed Mahameed 164689d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 164789d44f0aSMajd Dibbiny pci_channel_state_t state) 164889d44f0aSMajd Dibbiny { 164989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1650fad1783aSSaeed Mahameed enum pci_ers_result res; 165189d44f0aSMajd Dibbiny 1652fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 165304c0c1abSMohamad Haj Yahia 16548812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 16553e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 16566dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 16575e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 165889d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 165905ac2c0bSMohamad Haj Yahia 1660fad1783aSSaeed Mahameed res = state == pci_channel_io_perm_failure ? 166189d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1662fad1783aSSaeed Mahameed 1663fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res)); 1664fad1783aSSaeed Mahameed return res; 166589d44f0aSMajd Dibbiny } 166689d44f0aSMajd Dibbiny 1667d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1668d57847dcSDaniel Jurgens * for the health counter to start counting. 166989d44f0aSMajd Dibbiny */ 1670d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 167189d44f0aSMajd Dibbiny { 167289d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 167389d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 167489d44f0aSMajd Dibbiny const int niter = 100; 1675d57847dcSDaniel Jurgens u32 last_count = 0; 167689d44f0aSMajd Dibbiny u32 count; 167789d44f0aSMajd Dibbiny int i; 167889d44f0aSMajd Dibbiny 167989d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 168089d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 168189d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1682d57847dcSDaniel Jurgens if (last_count && last_count != count) { 168398a8e6fcSHuy Nguyen mlx5_core_info(dev, 168498a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 168598a8e6fcSHuy Nguyen count, i); 1686d57847dcSDaniel Jurgens return 0; 1687d57847dcSDaniel Jurgens } 1688d57847dcSDaniel Jurgens last_count = count; 168989d44f0aSMajd Dibbiny } 169089d44f0aSMajd Dibbiny msleep(50); 169189d44f0aSMajd Dibbiny } 169289d44f0aSMajd Dibbiny 1693d57847dcSDaniel Jurgens return -ETIMEDOUT; 169489d44f0aSMajd Dibbiny } 169589d44f0aSMajd Dibbiny 16961061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 16971061c90fSMohamad Haj Yahia { 1698fad1783aSSaeed Mahameed enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 16991061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 17001061c90fSMohamad Haj Yahia int err; 17011061c90fSMohamad Haj Yahia 1702fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter\n"); 17031061c90fSMohamad Haj Yahia 17041061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 17051061c90fSMohamad Haj Yahia if (err) { 170698a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 170798a8e6fcSHuy Nguyen __func__, err); 1708fad1783aSSaeed Mahameed goto out; 17091061c90fSMohamad Haj Yahia } 17101061c90fSMohamad Haj Yahia 17111061c90fSMohamad Haj Yahia pci_set_master(pdev); 17121061c90fSMohamad Haj Yahia pci_restore_state(pdev); 17135d47f6c8SDaniel Jurgens pci_save_state(pdev); 17141061c90fSMohamad Haj Yahia 1715fad1783aSSaeed Mahameed err = wait_vital(pdev); 1716fad1783aSSaeed Mahameed if (err) { 1717fad1783aSSaeed Mahameed mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 1718fad1783aSSaeed Mahameed __func__, err); 1719fad1783aSSaeed Mahameed goto out; 17201061c90fSMohamad Haj Yahia } 17211061c90fSMohamad Haj Yahia 1722fad1783aSSaeed Mahameed res = PCI_ERS_RESULT_RECOVERED; 1723fad1783aSSaeed Mahameed out: 1724fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res)); 1725fad1783aSSaeed Mahameed return res; 17261061c90fSMohamad Haj Yahia } 17271061c90fSMohamad Haj Yahia 172889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 172989d44f0aSMajd Dibbiny { 173089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 173189d44f0aSMajd Dibbiny int err; 173289d44f0aSMajd Dibbiny 1733fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Enter, loading driver..\n"); 173489d44f0aSMajd Dibbiny 17356dea2f7eSLeon Romanovsky err = mlx5_load_one(dev); 1736fad1783aSSaeed Mahameed 1737fad1783aSSaeed Mahameed mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 1738fad1783aSSaeed Mahameed !err ? "recovered" : "Failed"); 173989d44f0aSMajd Dibbiny } 174089d44f0aSMajd Dibbiny 174189d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 174289d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 174389d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 174489d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 174589d44f0aSMajd Dibbiny }; 174689d44f0aSMajd Dibbiny 17478812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 17488812c24dSMajd Dibbiny { 1749fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1750fcd29ad1SFeras Daoud int ret = 1; 17518812c24dSMajd Dibbiny 1752fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1753fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1754fcd29ad1SFeras Daoud 1755fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1756fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1757fcd29ad1SFeras Daoud 1758fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 17598812c24dSMajd Dibbiny return -EOPNOTSUPP; 17608812c24dSMajd Dibbiny 17618812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 17628812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 17638812c24dSMajd Dibbiny return -EAGAIN; 17648812c24dSMajd Dibbiny } 17658812c24dSMajd Dibbiny 1766d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1767d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1768d2aa060dSHuy Nguyen */ 1769d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 177076d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1771d2aa060dSHuy Nguyen 1772fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1773fcd29ad1SFeras Daoud if (!ret) 1774fcd29ad1SFeras Daoud goto succeed; 1775fcd29ad1SFeras Daoud 17768812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1777fcd29ad1SFeras Daoud if (!ret) 1778fcd29ad1SFeras Daoud goto succeed; 1779fcd29ad1SFeras Daoud 17808812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1781d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 17828812c24dSMajd Dibbiny return ret; 17838812c24dSMajd Dibbiny 1784fcd29ad1SFeras Daoud succeed: 17858812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 17868812c24dSMajd Dibbiny 17871ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 17881ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 17891ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 17901ef903bfSDaniel Jurgens * contexts. 17911ef903bfSDaniel Jurgens */ 17921ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 17931ef903bfSDaniel Jurgens 17948812c24dSMajd Dibbiny return 0; 17958812c24dSMajd Dibbiny } 17968812c24dSMajd Dibbiny 17975fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 17985fc7197dSMajd Dibbiny { 17995fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18008812c24dSMajd Dibbiny int err; 18015fc7197dSMajd Dibbiny 180298a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 18038812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 18048812c24dSMajd Dibbiny if (err) 18056dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 18065fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 18075fc7197dSMajd Dibbiny } 18085fc7197dSMajd Dibbiny 18098fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 18108fc3e29bSMark Bloch { 18118fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18128fc3e29bSMark Bloch 18136dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 18148fc3e29bSMark Bloch 18158fc3e29bSMark Bloch return 0; 18168fc3e29bSMark Bloch } 18178fc3e29bSMark Bloch 18188fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 18198fc3e29bSMark Bloch { 18208fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 18218fc3e29bSMark Bloch 18226dea2f7eSLeon Romanovsky return mlx5_load_one(dev); 18238fc3e29bSMark Bloch } 18248fc3e29bSMark Bloch 18259603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1826bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1827fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1828bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1829fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1830bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1831fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 18327092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 183364dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1834d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1835d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1836d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1837d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 183885327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 183985327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1840b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1841505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1842f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 18432e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 18442e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1845d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1846dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1847f908a35bSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 18489603b61dSJack Morgenstein { 0, } 18499603b61dSJack Morgenstein }; 18509603b61dSJack Morgenstein 18519603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 18529603b61dSJack Morgenstein 185304c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 185404c0c1abSMohamad Haj Yahia { 1855b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 18566dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 185704c0c1abSMohamad Haj Yahia } 185804c0c1abSMohamad Haj Yahia 1859fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 186004c0c1abSMohamad Haj Yahia { 186133de865fSMoshe Shemesh if (!mlx5_core_is_sf(dev)) { 186204c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 186333de865fSMoshe Shemesh if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 186433de865fSMoshe Shemesh return -EIO; 186533de865fSMoshe Shemesh } 186633de865fSMoshe Shemesh 186733de865fSMoshe Shemesh return mlx5_load_one(dev); 186804c0c1abSMohamad Haj Yahia } 186904c0c1abSMohamad Haj Yahia 18709603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 187117a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 18729603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 18736dea2f7eSLeon Romanovsky .probe = probe_one, 187489d44f0aSMajd Dibbiny .remove = remove_one, 18758fc3e29bSMark Bloch .suspend = mlx5_suspend, 18768fc3e29bSMark Bloch .resume = mlx5_resume, 18775fc7197dSMajd Dibbiny .shutdown = shutdown, 1878fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1879fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 1880e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1881e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 18829603b61dSJack Morgenstein }; 1883e126ba97SEli Cohen 1884f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1885f663ad98SKamal Heib { 1886f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1887f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1888f663ad98SKamal Heib prof_sel, 1889f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1890f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1891f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1892f663ad98SKamal Heib } 1893f663ad98SKamal Heib } 1894f663ad98SKamal Heib 1895e126ba97SEli Cohen static int __init init(void) 1896e126ba97SEli Cohen { 1897e126ba97SEli Cohen int err; 1898e126ba97SEli Cohen 189917a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 190017a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 190117a7612bSLeon Romanovsky 19028737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 19038737f818SDaniel Jurgens 1904f663ad98SKamal Heib mlx5_core_verify_params(); 19059a6ad1adSRaed Salem mlx5_fpga_ipsec_build_fs_cmds(); 1906e126ba97SEli Cohen mlx5_register_debugfs(); 1907e126ba97SEli Cohen 19089603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 19099603b61dSJack Morgenstein if (err) 1910ac6ea6e8SEli Cohen goto err_debug; 19119603b61dSJack Morgenstein 19121958fc2fSParav Pandit err = mlx5_sf_driver_register(); 19131958fc2fSParav Pandit if (err) 19141958fc2fSParav Pandit goto err_sf; 19151958fc2fSParav Pandit 1916912cebf4SLeon Romanovsky err = mlx5e_init(); 1917c633e799SLeon Romanovsky if (err) 1918c633e799SLeon Romanovsky goto err_en; 1919f62b8bb8SAmir Vadai 1920e126ba97SEli Cohen return 0; 1921e126ba97SEli Cohen 1922c633e799SLeon Romanovsky err_en: 1923c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 19241958fc2fSParav Pandit err_sf: 19251958fc2fSParav Pandit pci_unregister_driver(&mlx5_core_driver); 1926e126ba97SEli Cohen err_debug: 1927e126ba97SEli Cohen mlx5_unregister_debugfs(); 1928e126ba97SEli Cohen return err; 1929e126ba97SEli Cohen } 1930e126ba97SEli Cohen 1931e126ba97SEli Cohen static void __exit cleanup(void) 1932e126ba97SEli Cohen { 1933f62b8bb8SAmir Vadai mlx5e_cleanup(); 19341958fc2fSParav Pandit mlx5_sf_driver_unregister(); 19359603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1936e126ba97SEli Cohen mlx5_unregister_debugfs(); 1937e126ba97SEli Cohen } 1938e126ba97SEli Cohen 1939e126ba97SEli Cohen module_init(init); 1940e126ba97SEli Cohen module_exit(cleanup); 1941