1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53907af0f0SLeon Romanovsky #include <linux/version.h> 54feae9087SOr Gerlitz #include <net/devlink.h> 55e126ba97SEli Cohen #include "mlx5_core.h" 56f2f3df55SSaeed Mahameed #include "lib/eq.h" 5716d76083SSaeed Mahameed #include "fs_core.h" 58eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 59073bb189SSaeed Mahameed #include "eswitch.h" 601f28d776SEran Ben Elisha #include "devlink.h" 6138b9f903SMoshe Shemesh #include "fw_reset.h" 6252ec462eSIlan Tayari #include "lib/mlx5.h" 63e29341fbSIlan Tayari #include "fpga/core.h" 6405564d0aSAviad Yehezkel #include "fpga/ipsec.h" 65bebb23e6SIlan Tayari #include "accel/ipsec.h" 661ae17322SIlya Lesokhin #include "accel/tls.h" 677c39afb3SFeras Daoud #include "lib/clock.h" 68358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 690ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 70fadd59fcSAviv Heller #include "lib/devcom.h" 71b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7224406953SFeras Daoud #include "diag/fw_tracer.h" 73591905baSBodong Wang #include "ecpf.h" 7487175120SEran Ben Elisha #include "lib/hv_vhca.h" 7512206b17SAya Levin #include "diag/rsc_dump.h" 76f3196bb0SParav Pandit #include "sf/vhca_event.h" 7790d010b8SParav Pandit #include "sf/dev/dev.h" 786a327321SParav Pandit #include "sf/sf.h" 79e126ba97SEli Cohen 80e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 81048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 82e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 83e126ba97SEli Cohen 84f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 85f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 86e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 87e126ba97SEli Cohen 88f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 89f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 909603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 919603b61dSJack Morgenstein 928737f818SDaniel Jurgens static u32 sw_owner_id[4]; 938737f818SDaniel Jurgens 94f91e6d89SEran Ben Elisha enum { 95f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97f91e6d89SEran Ben Elisha }; 98f91e6d89SEran Ben Elisha 999603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1009603b61dSJack Morgenstein [0] = { 1019603b61dSJack Morgenstein .mask = 0, 1029603b61dSJack Morgenstein }, 1039603b61dSJack Morgenstein [1] = { 1049603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1059603b61dSJack Morgenstein .log_max_qp = 12, 1069603b61dSJack Morgenstein }, 1079603b61dSJack Morgenstein [2] = { 1089603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1099603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1105f40b4edSMaor Gottlieb .log_max_qp = 18, 1119603b61dSJack Morgenstein .mr_cache[0] = { 1129603b61dSJack Morgenstein .size = 500, 1139603b61dSJack Morgenstein .limit = 250 1149603b61dSJack Morgenstein }, 1159603b61dSJack Morgenstein .mr_cache[1] = { 1169603b61dSJack Morgenstein .size = 500, 1179603b61dSJack Morgenstein .limit = 250 1189603b61dSJack Morgenstein }, 1199603b61dSJack Morgenstein .mr_cache[2] = { 1209603b61dSJack Morgenstein .size = 500, 1219603b61dSJack Morgenstein .limit = 250 1229603b61dSJack Morgenstein }, 1239603b61dSJack Morgenstein .mr_cache[3] = { 1249603b61dSJack Morgenstein .size = 500, 1259603b61dSJack Morgenstein .limit = 250 1269603b61dSJack Morgenstein }, 1279603b61dSJack Morgenstein .mr_cache[4] = { 1289603b61dSJack Morgenstein .size = 500, 1299603b61dSJack Morgenstein .limit = 250 1309603b61dSJack Morgenstein }, 1319603b61dSJack Morgenstein .mr_cache[5] = { 1329603b61dSJack Morgenstein .size = 500, 1339603b61dSJack Morgenstein .limit = 250 1349603b61dSJack Morgenstein }, 1359603b61dSJack Morgenstein .mr_cache[6] = { 1369603b61dSJack Morgenstein .size = 500, 1379603b61dSJack Morgenstein .limit = 250 1389603b61dSJack Morgenstein }, 1399603b61dSJack Morgenstein .mr_cache[7] = { 1409603b61dSJack Morgenstein .size = 500, 1419603b61dSJack Morgenstein .limit = 250 1429603b61dSJack Morgenstein }, 1439603b61dSJack Morgenstein .mr_cache[8] = { 1449603b61dSJack Morgenstein .size = 500, 1459603b61dSJack Morgenstein .limit = 250 1469603b61dSJack Morgenstein }, 1479603b61dSJack Morgenstein .mr_cache[9] = { 1489603b61dSJack Morgenstein .size = 500, 1499603b61dSJack Morgenstein .limit = 250 1509603b61dSJack Morgenstein }, 1519603b61dSJack Morgenstein .mr_cache[10] = { 1529603b61dSJack Morgenstein .size = 500, 1539603b61dSJack Morgenstein .limit = 250 1549603b61dSJack Morgenstein }, 1559603b61dSJack Morgenstein .mr_cache[11] = { 1569603b61dSJack Morgenstein .size = 500, 1579603b61dSJack Morgenstein .limit = 250 1589603b61dSJack Morgenstein }, 1599603b61dSJack Morgenstein .mr_cache[12] = { 1609603b61dSJack Morgenstein .size = 64, 1619603b61dSJack Morgenstein .limit = 32 1629603b61dSJack Morgenstein }, 1639603b61dSJack Morgenstein .mr_cache[13] = { 1649603b61dSJack Morgenstein .size = 32, 1659603b61dSJack Morgenstein .limit = 16 1669603b61dSJack Morgenstein }, 1679603b61dSJack Morgenstein .mr_cache[14] = { 1689603b61dSJack Morgenstein .size = 16, 1699603b61dSJack Morgenstein .limit = 8 1709603b61dSJack Morgenstein }, 1719603b61dSJack Morgenstein .mr_cache[15] = { 1729603b61dSJack Morgenstein .size = 8, 1739603b61dSJack Morgenstein .limit = 4 1749603b61dSJack Morgenstein }, 1759603b61dSJack Morgenstein }, 1769603b61dSJack Morgenstein }; 177e126ba97SEli Cohen 178e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 179e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 180b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 181b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 182e3297246SEli Cohen 183555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 184555af0c3SParav Pandit { 185555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 186555af0c3SParav Pandit } 187555af0c3SParav Pandit 188b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189b8a92577SDaniel Jurgens u32 warn_time_mili) 190e3297246SEli Cohen { 191b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193e3297246SEli Cohen int err = 0; 194e3297246SEli Cohen 195b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 196b8a92577SDaniel Jurgens 197e3297246SEli Cohen while (fw_initializing(dev)) { 198e3297246SEli Cohen if (time_after(jiffies, end)) { 199e3297246SEli Cohen err = -EBUSY; 200e3297246SEli Cohen break; 201e3297246SEli Cohen } 202b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 203b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 204b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 205b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 206b8a92577SDaniel Jurgens } 207e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 208e3297246SEli Cohen } 209e3297246SEli Cohen 210e3297246SEli Cohen return err; 211e3297246SEli Cohen } 212e3297246SEli Cohen 213012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 214012e50e1SHuy Nguyen { 215012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 216012e50e1SHuy Nguyen driver_version); 2173ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 218012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 219012e50e1SHuy Nguyen char *string; 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 222012e50e1SHuy Nguyen return; 223012e50e1SHuy Nguyen 224012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 225012e50e1SHuy Nguyen 226012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 23217a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 233012e50e1SHuy Nguyen 234012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 236012e50e1SHuy Nguyen 237012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238907af0f0SLeon Romanovsky 239907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 24088a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 24188a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 242012e50e1SHuy Nguyen 243012e50e1SHuy Nguyen /*Send the command*/ 244012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 245012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 246012e50e1SHuy Nguyen 2473ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 248012e50e1SHuy Nguyen } 249012e50e1SHuy Nguyen 250e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 251e126ba97SEli Cohen { 252e126ba97SEli Cohen int err; 253e126ba97SEli Cohen 254e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 255e126ba97SEli Cohen if (err) { 2561a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 257e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 258e126ba97SEli Cohen if (err) { 2591a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 260e126ba97SEli Cohen return err; 261e126ba97SEli Cohen } 262e126ba97SEli Cohen } 263e126ba97SEli Cohen 264e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 265e126ba97SEli Cohen if (err) { 266e126ba97SEli Cohen dev_warn(&pdev->dev, 2671a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 268e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 269e126ba97SEli Cohen if (err) { 270e126ba97SEli Cohen dev_err(&pdev->dev, 2711a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 272e126ba97SEli Cohen return err; 273e126ba97SEli Cohen } 274e126ba97SEli Cohen } 275e126ba97SEli Cohen 276e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 277e126ba97SEli Cohen return err; 278e126ba97SEli Cohen } 279e126ba97SEli Cohen 28089d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 28189d44f0aSMajd Dibbiny { 28289d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28389d44f0aSMajd Dibbiny int err = 0; 28489d44f0aSMajd Dibbiny 28589d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28689d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 28789d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 28889d44f0aSMajd Dibbiny if (!err) 28989d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 29089d44f0aSMajd Dibbiny } 29189d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29289d44f0aSMajd Dibbiny 29389d44f0aSMajd Dibbiny return err; 29489d44f0aSMajd Dibbiny } 29589d44f0aSMajd Dibbiny 29689d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 29789d44f0aSMajd Dibbiny { 29889d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 29989d44f0aSMajd Dibbiny 30089d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 30189d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 30289d44f0aSMajd Dibbiny pci_disable_device(pdev); 30389d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 30489d44f0aSMajd Dibbiny } 30589d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 30689d44f0aSMajd Dibbiny } 30789d44f0aSMajd Dibbiny 308e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 309e126ba97SEli Cohen { 310e126ba97SEli Cohen int err = 0; 311e126ba97SEli Cohen 312e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3131a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 314e126ba97SEli Cohen return -ENODEV; 315e126ba97SEli Cohen } 316e126ba97SEli Cohen 31717a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 318e126ba97SEli Cohen if (err) 319e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 320e126ba97SEli Cohen 321e126ba97SEli Cohen return err; 322e126ba97SEli Cohen } 323e126ba97SEli Cohen 324e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 325e126ba97SEli Cohen { 326e126ba97SEli Cohen pci_release_regions(pdev); 327e126ba97SEli Cohen } 328e126ba97SEli Cohen 329bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 330e126ba97SEli Cohen u8 he; 331e126ba97SEli Cohen u8 rsvd[15]; 332e126ba97SEli Cohen }; 333e126ba97SEli Cohen 33487b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 33587b8de49SEli Cohen 33687b8de49SEli Cohen enum { 33787b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 338c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 33987b8de49SEli Cohen }; 34087b8de49SEli Cohen 3412974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 342c7a08ac7SEli Cohen { 343c7a08ac7SEli Cohen switch (size) { 344c7a08ac7SEli Cohen case 128: 345c7a08ac7SEli Cohen return 0; 346c7a08ac7SEli Cohen case 256: 347c7a08ac7SEli Cohen return 1; 348c7a08ac7SEli Cohen case 512: 349c7a08ac7SEli Cohen return 2; 350c7a08ac7SEli Cohen case 1024: 351c7a08ac7SEli Cohen return 3; 352c7a08ac7SEli Cohen case 2048: 353c7a08ac7SEli Cohen return 4; 354c7a08ac7SEli Cohen case 4096: 355c7a08ac7SEli Cohen return 5; 356c7a08ac7SEli Cohen default: 3572974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 358c7a08ac7SEli Cohen return 0; 359c7a08ac7SEli Cohen } 360c7a08ac7SEli Cohen } 361c7a08ac7SEli Cohen 362b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 363b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 364938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 365c7a08ac7SEli Cohen { 366b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 367b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 368938fe83cSSaeed Mahameed void *out, *hca_caps; 369938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 370c7a08ac7SEli Cohen int err; 371c7a08ac7SEli Cohen 372b775516bSEli Cohen memset(in, 0, sizeof(in)); 373b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 374c7a08ac7SEli Cohen if (!out) 375c7a08ac7SEli Cohen return -ENOMEM; 376938fe83cSSaeed Mahameed 377b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 378b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3793ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 380c7a08ac7SEli Cohen if (err) { 381938fe83cSSaeed Mahameed mlx5_core_warn(dev, 382938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 383938fe83cSSaeed Mahameed cap_type, cap_mode, err); 384c7a08ac7SEli Cohen goto query_ex; 385c7a08ac7SEli Cohen } 386c7a08ac7SEli Cohen 387938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 388938fe83cSSaeed Mahameed 389938fe83cSSaeed Mahameed switch (cap_mode) { 390938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 391701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 392938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 393938fe83cSSaeed Mahameed break; 394938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 395701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 396938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 397938fe83cSSaeed Mahameed break; 398938fe83cSSaeed Mahameed default: 399938fe83cSSaeed Mahameed mlx5_core_warn(dev, 400938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 401938fe83cSSaeed Mahameed cap_type, cap_mode); 402938fe83cSSaeed Mahameed err = -EINVAL; 403938fe83cSSaeed Mahameed break; 404938fe83cSSaeed Mahameed } 405c7a08ac7SEli Cohen query_ex: 406c7a08ac7SEli Cohen kfree(out); 407c7a08ac7SEli Cohen return err; 408c7a08ac7SEli Cohen } 409c7a08ac7SEli Cohen 410b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 411b06e7de8SLeon Romanovsky { 412b06e7de8SLeon Romanovsky int ret; 413b06e7de8SLeon Romanovsky 414b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 415b06e7de8SLeon Romanovsky if (ret) 416b06e7de8SLeon Romanovsky return ret; 417b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 418b06e7de8SLeon Romanovsky } 419b06e7de8SLeon Romanovsky 420a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 421c7a08ac7SEli Cohen { 422b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 423f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4243ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 425c7a08ac7SEli Cohen } 42687b8de49SEli Cohen 427a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 428f91e6d89SEran Ben Elisha { 429f91e6d89SEran Ben Elisha void *set_hca_cap; 430f91e6d89SEran Ben Elisha int req_endianness; 431f91e6d89SEran Ben Elisha int err; 432f91e6d89SEran Ben Elisha 433a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 434a2a322f4SLeon Romanovsky return 0; 435a2a322f4SLeon Romanovsky 436b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 437f91e6d89SEran Ben Elisha if (err) 438f91e6d89SEran Ben Elisha return err; 439f91e6d89SEran Ben Elisha 440f91e6d89SEran Ben Elisha req_endianness = 441f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 442bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 443f91e6d89SEran Ben Elisha 444f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 445f91e6d89SEran Ben Elisha return 0; 446f91e6d89SEran Ben Elisha 447f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 448f91e6d89SEran Ben Elisha 449f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 450bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 451f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 452f91e6d89SEran Ben Elisha 453a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 454f91e6d89SEran Ben Elisha } 455f91e6d89SEran Ben Elisha 456a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 45746861e3eSMoni Shoua { 45846861e3eSMoni Shoua void *set_hca_cap; 459fca22e7eSMoni Shoua bool do_set = false; 46046861e3eSMoni Shoua int err; 46146861e3eSMoni Shoua 46237b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46337b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46446861e3eSMoni Shoua return 0; 46546861e3eSMoni Shoua 46646861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46746861e3eSMoni Shoua if (err) 46846861e3eSMoni Shoua return err; 46946861e3eSMoni Shoua 47046861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 47146861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 47246861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47346861e3eSMoni Shoua 474fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 475fca22e7eSMoni Shoua do { \ 476fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 477fca22e7eSMoni Shoua if (_res) { \ 478fca22e7eSMoni Shoua do_set = true; \ 479fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 480fca22e7eSMoni Shoua } \ 481fca22e7eSMoni Shoua } while (0) 48246861e3eSMoni Shoua 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 488fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 489fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 490fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 49100679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 49200679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 49300679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 49400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 49500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 49600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 49746861e3eSMoni Shoua 498a2a322f4SLeon Romanovsky if (!do_set) 499a2a322f4SLeon Romanovsky return 0; 50046861e3eSMoni Shoua 501a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 50246861e3eSMoni Shoua } 50346861e3eSMoni Shoua 504a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 505e126ba97SEli Cohen { 506c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 507938fe83cSSaeed Mahameed void *set_hca_cap; 508a2a322f4SLeon Romanovsky int err; 509e126ba97SEli Cohen 510b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 511c7a08ac7SEli Cohen if (err) 512a2a322f4SLeon Romanovsky return err; 513e126ba97SEli Cohen 514938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 515938fe83cSSaeed Mahameed capability); 516701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 517938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 518938fe83cSSaeed Mahameed 519938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 520707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 521938fe83cSSaeed Mahameed 128); 522c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 523938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5242974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 525e126ba97SEli Cohen 526883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 527883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 528883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 529883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 530883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 531883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 532883371c4SNoa Osherovich } 533c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 534938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 535938fe83cSSaeed Mahameed prof->log_max_qp); 536e126ba97SEli Cohen 537938fe83cSSaeed Mahameed /* disable cmdif checksum */ 538938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 539c1868b82SEli Cohen 54091828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 54191828bd8SMajd Dibbiny * than 4K. 54291828bd8SMajd Dibbiny */ 54391828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 544f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 545f502d834SEli Cohen 546fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 547fe1e1876SCarol L Soto 548f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 549f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 550f32f5bd2SDaniel Jurgens set_hca_cap, 551f32f5bd2SDaniel Jurgens cache_line_128byte, 552c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 553f32f5bd2SDaniel Jurgens 554dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 555dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 556dd44572aSMoni Shoua 557e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 558e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 559e7f4d0bcSMoshe Shemesh 560c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 561c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 562c4b76d8dSDaniel Jurgens set_hca_cap, 563c4b76d8dSDaniel Jurgens num_vhca_ports, 564c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 565c4b76d8dSDaniel Jurgens 566c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 567c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 568c6168161SEran Ben Elisha 5694dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 5704dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 5714dca6509SMichael Guralnik 572f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 573f3196bb0SParav Pandit 574*604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 575*604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 576*604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 577*604774adSLeon Romanovsky 578a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 579e126ba97SEli Cohen } 580cd23b14bSEli Cohen 58159e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 58259e9e8e4SMark Zhang { 58359e9e8e4SMark Zhang void *set_hca_cap; 58459e9e8e4SMark Zhang int err; 58559e9e8e4SMark Zhang 58659e9e8e4SMark Zhang if (!MLX5_CAP_GEN(dev, roce)) 58759e9e8e4SMark Zhang return 0; 58859e9e8e4SMark Zhang 58959e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 59059e9e8e4SMark Zhang if (err) 59159e9e8e4SMark Zhang return err; 59259e9e8e4SMark Zhang 59359e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 59459e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 59559e9e8e4SMark Zhang return 0; 59659e9e8e4SMark Zhang 59759e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 59859e9e8e4SMark Zhang memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 59959e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 60059e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 60159e9e8e4SMark Zhang 60259e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 603e126ba97SEli Cohen return err; 604e126ba97SEli Cohen } 605e126ba97SEli Cohen 60637b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 60737b6bb77SLeon Romanovsky { 608a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 609a2a322f4SLeon Romanovsky void *set_ctx; 61037b6bb77SLeon Romanovsky int err; 61137b6bb77SLeon Romanovsky 612a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 613a2a322f4SLeon Romanovsky if (!set_ctx) 614a2a322f4SLeon Romanovsky return -ENOMEM; 615a2a322f4SLeon Romanovsky 616a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 61737b6bb77SLeon Romanovsky if (err) { 61898a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 61937b6bb77SLeon Romanovsky goto out; 62037b6bb77SLeon Romanovsky } 62137b6bb77SLeon Romanovsky 622a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 623a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 62437b6bb77SLeon Romanovsky if (err) { 62598a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 62637b6bb77SLeon Romanovsky goto out; 62737b6bb77SLeon Romanovsky } 62837b6bb77SLeon Romanovsky 629a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 630a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 63137b6bb77SLeon Romanovsky if (err) { 63298a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 63337b6bb77SLeon Romanovsky goto out; 63437b6bb77SLeon Romanovsky } 63537b6bb77SLeon Romanovsky 63659e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 63759e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 63859e9e8e4SMark Zhang if (err) { 63959e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 64059e9e8e4SMark Zhang goto out; 64159e9e8e4SMark Zhang } 64259e9e8e4SMark Zhang 64337b6bb77SLeon Romanovsky out: 644a2a322f4SLeon Romanovsky kfree(set_ctx); 64537b6bb77SLeon Romanovsky return err; 64637b6bb77SLeon Romanovsky } 64737b6bb77SLeon Romanovsky 648e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 649e126ba97SEli Cohen { 650bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 651bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 652e126ba97SEli Cohen int err; 653e126ba97SEli Cohen 654fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 655fc50db98SEli Cohen return 0; 656fc50db98SEli Cohen 657e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 658e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 659e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 660e126ba97SEli Cohen &he_out, sizeof(he_out), 661e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 662e126ba97SEli Cohen return err; 663e126ba97SEli Cohen } 664e126ba97SEli Cohen 665c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 666c85023e1SHuy Nguyen { 667c85023e1SHuy Nguyen int ret = 0; 668c85023e1SHuy Nguyen 669c85023e1SHuy Nguyen /* Disable local_lb by default */ 6708978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 671c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 672c85023e1SHuy Nguyen 673c85023e1SHuy Nguyen return ret; 674c85023e1SHuy Nguyen } 675c85023e1SHuy Nguyen 6760b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 677e126ba97SEli Cohen { 6783ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 679e126ba97SEli Cohen 6800b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6810b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 68222e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 68322e939a9SBodong Wang dev->caps.embedded_cpu); 6843ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 685e126ba97SEli Cohen } 686e126ba97SEli Cohen 6870b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 688e126ba97SEli Cohen { 6893ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 690e126ba97SEli Cohen 6910b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6920b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 69322e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 69422e939a9SBodong Wang dev->caps.embedded_cpu); 6953ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 696e126ba97SEli Cohen } 697e126ba97SEli Cohen 698f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 699f62b8bb8SAmir Vadai { 7003ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 7013ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 702f62b8bb8SAmir Vadai u32 sup_issi; 703c4f287c4SSaeed Mahameed int err; 704f62b8bb8SAmir Vadai 705f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 7063ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 707f62b8bb8SAmir Vadai if (err) { 708c4f287c4SSaeed Mahameed u32 syndrome; 709c4f287c4SSaeed Mahameed u8 status; 710c4f287c4SSaeed Mahameed 711c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 712f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 713f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 714f9c14e46SKamal Heib err, status, syndrome); 715f9c14e46SKamal Heib return err; 716f62b8bb8SAmir Vadai } 717f62b8bb8SAmir Vadai 718f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 719f9c14e46SKamal Heib dev->issi = 0; 720f9c14e46SKamal Heib return 0; 721f62b8bb8SAmir Vadai } 722f62b8bb8SAmir Vadai 723f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 724f62b8bb8SAmir Vadai 725f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7263ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 727f62b8bb8SAmir Vadai 728f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 729f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7303ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 731f62b8bb8SAmir Vadai if (err) { 732f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 733f9c14e46SKamal Heib err); 734f62b8bb8SAmir Vadai return err; 735f62b8bb8SAmir Vadai } 736f62b8bb8SAmir Vadai 737f62b8bb8SAmir Vadai dev->issi = 1; 738f62b8bb8SAmir Vadai 739f62b8bb8SAmir Vadai return 0; 740e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 741f62b8bb8SAmir Vadai return 0; 742f62b8bb8SAmir Vadai } 743f62b8bb8SAmir Vadai 7449eb78923SOr Gerlitz return -EOPNOTSUPP; 745f62b8bb8SAmir Vadai } 746f62b8bb8SAmir Vadai 74711f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 74811f3b84dSSaeed Mahameed const struct pci_device_id *id) 749a31208b1SMajd Dibbiny { 750868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 751a31208b1SMajd Dibbiny int err = 0; 752a31208b1SMajd Dibbiny 753d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 754e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 755e126ba97SEli Cohen 756aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 7577be3412aSParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 758311c7c71SSaeed Mahameed 75989d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 760e126ba97SEli Cohen if (err) { 76198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 76211f3b84dSSaeed Mahameed return err; 763e126ba97SEli Cohen } 764e126ba97SEli Cohen 765e126ba97SEli Cohen err = request_bar(pdev); 766e126ba97SEli Cohen if (err) { 76798a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 768e126ba97SEli Cohen goto err_disable; 769e126ba97SEli Cohen } 770e126ba97SEli Cohen 771e126ba97SEli Cohen pci_set_master(pdev); 772e126ba97SEli Cohen 773e126ba97SEli Cohen err = set_dma_caps(pdev); 774e126ba97SEli Cohen if (err) { 77598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 776e126ba97SEli Cohen goto err_clr_master; 777e126ba97SEli Cohen } 778e126ba97SEli Cohen 779ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 780ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 781ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 782ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 783ce4eee53SMichael Guralnik 784aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 785e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 786e126ba97SEli Cohen if (!dev->iseg) { 787e126ba97SEli Cohen err = -ENOMEM; 78898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 789e126ba97SEli Cohen goto err_clr_master; 790e126ba97SEli Cohen } 791a31208b1SMajd Dibbiny 792b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 793c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 794a31208b1SMajd Dibbiny return 0; 795a31208b1SMajd Dibbiny 796a31208b1SMajd Dibbiny err_clr_master: 797a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 798a31208b1SMajd Dibbiny release_bar(dev->pdev); 799a31208b1SMajd Dibbiny err_disable: 80089d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 801a31208b1SMajd Dibbiny return err; 802a31208b1SMajd Dibbiny } 803a31208b1SMajd Dibbiny 804868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 805a31208b1SMajd Dibbiny { 80642ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 80742ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 80842ea9f1bSShay Drory * before removing the pci bars 80942ea9f1bSShay Drory */ 81042ea9f1bSShay Drory mlx5_drain_health_wq(dev); 811a31208b1SMajd Dibbiny iounmap(dev->iseg); 812a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 813a31208b1SMajd Dibbiny release_bar(dev->pdev); 81489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 815a31208b1SMajd Dibbiny } 816a31208b1SMajd Dibbiny 817868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 81859211bd3SMohamad Haj Yahia { 81959211bd3SMohamad Haj Yahia int err; 82059211bd3SMohamad Haj Yahia 821868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 822868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 82398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 824868bc06bSSaeed Mahameed dev->priv.devcom); 825fadd59fcSAviv Heller 82659211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 82759211bd3SMohamad Haj Yahia if (err) { 82898a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 829fadd59fcSAviv Heller goto err_devcom; 83059211bd3SMohamad Haj Yahia } 83159211bd3SMohamad Haj Yahia 832561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 833561aa15aSYuval Avnery if (err) { 834561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 835561aa15aSYuval Avnery goto err_devcom; 836561aa15aSYuval Avnery } 837561aa15aSYuval Avnery 838f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 83959211bd3SMohamad Haj Yahia if (err) { 84098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 841561aa15aSYuval Avnery goto err_irq_cleanup; 84259211bd3SMohamad Haj Yahia } 84359211bd3SMohamad Haj Yahia 84469c1280bSSaeed Mahameed err = mlx5_events_init(dev); 84569c1280bSSaeed Mahameed if (err) { 84698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 84769c1280bSSaeed Mahameed goto err_eq_cleanup; 84869c1280bSSaeed Mahameed } 84969c1280bSSaeed Mahameed 85038b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 85138b9f903SMoshe Shemesh if (err) { 85238b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 85338b9f903SMoshe Shemesh goto err_events_cleanup; 85438b9f903SMoshe Shemesh } 85538b9f903SMoshe Shemesh 8569f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 85759211bd3SMohamad Haj Yahia 85852ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 85952ec462eSIlan Tayari 8607c39afb3SFeras Daoud mlx5_init_clock(dev); 8617c39afb3SFeras Daoud 862358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8630ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 864358aa5ceSSaeed Mahameed 86559211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 86659211bd3SMohamad Haj Yahia if (err) { 86798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 86859211bd3SMohamad Haj Yahia goto err_tables_cleanup; 86959211bd3SMohamad Haj Yahia } 87059211bd3SMohamad Haj Yahia 871eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 872eeb66cdbSSaeed Mahameed if (err) { 87398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 874eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 875eeb66cdbSSaeed Mahameed } 876eeb66cdbSSaeed Mahameed 877c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 878c2d6e31aSMohamad Haj Yahia if (err) { 87998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 88086eec50bSBodong Wang goto err_mpfs_cleanup; 88186eec50bSBodong Wang } 88286eec50bSBodong Wang 88386eec50bSBodong Wang err = mlx5_eswitch_init(dev); 88486eec50bSBodong Wang if (err) { 88586eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 88686eec50bSBodong Wang goto err_sriov_cleanup; 887c2d6e31aSMohamad Haj Yahia } 888c2d6e31aSMohamad Haj Yahia 8899410733cSIlan Tayari err = mlx5_fpga_init(dev); 8909410733cSIlan Tayari if (err) { 89198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 89286eec50bSBodong Wang goto err_eswitch_cleanup; 8939410733cSIlan Tayari } 8949410733cSIlan Tayari 895f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 896f3196bb0SParav Pandit if (err) { 897f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 898f3196bb0SParav Pandit goto err_fpga_cleanup; 899f3196bb0SParav Pandit } 900f3196bb0SParav Pandit 9018f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 9028f010541SParav Pandit if (err) { 9038f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 9048f010541SParav Pandit goto err_sf_hw_table_cleanup; 9058f010541SParav Pandit } 9068f010541SParav Pandit 9078f010541SParav Pandit err = mlx5_sf_table_init(dev); 9088f010541SParav Pandit if (err) { 9098f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 9108f010541SParav Pandit goto err_sf_table_cleanup; 9118f010541SParav Pandit } 9128f010541SParav Pandit 913c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 914c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 915c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 916c9b9dcb4SAriel Levkovich 91724406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 91887175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 91912206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 92024406953SFeras Daoud 92159211bd3SMohamad Haj Yahia return 0; 92259211bd3SMohamad Haj Yahia 9238f010541SParav Pandit err_sf_table_cleanup: 9248f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 9258f010541SParav Pandit err_sf_hw_table_cleanup: 9268f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 927f3196bb0SParav Pandit err_fpga_cleanup: 928f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 929c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 930c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 93186eec50bSBodong Wang err_sriov_cleanup: 93286eec50bSBodong Wang mlx5_sriov_cleanup(dev); 933eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 934eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 935c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 936c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 93759211bd3SMohamad Haj Yahia err_tables_cleanup: 9380ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 939358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 94002d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 94138b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 94238b9f903SMoshe Shemesh err_events_cleanup: 94369c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 94459211bd3SMohamad Haj Yahia err_eq_cleanup: 945f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 946561aa15aSYuval Avnery err_irq_cleanup: 947561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 948fadd59fcSAviv Heller err_devcom: 949fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 95059211bd3SMohamad Haj Yahia 95159211bd3SMohamad Haj Yahia return err; 95259211bd3SMohamad Haj Yahia } 95359211bd3SMohamad Haj Yahia 95459211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 95559211bd3SMohamad Haj Yahia { 95612206b17SAya Levin mlx5_rsc_dump_destroy(dev); 95787175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 95824406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 959c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9608f010541SParav Pandit mlx5_sf_table_cleanup(dev); 9618f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 962f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 9639410733cSIlan Tayari mlx5_fpga_cleanup(dev); 964c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 96586eec50bSBodong Wang mlx5_sriov_cleanup(dev); 966eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 96759211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9680ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 969358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9707c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 97152ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 97202d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 97338b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 97469c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 975f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 976561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 977fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 97859211bd3SMohamad Haj Yahia } 97959211bd3SMohamad Haj Yahia 980e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 981a31208b1SMajd Dibbiny { 982a31208b1SMajd Dibbiny int err; 983a31208b1SMajd Dibbiny 98498a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 985e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 986e126ba97SEli Cohen 98700c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 98800c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 98900c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 99000c6bcb0STal Gilboa 9916c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9926c780a02SEli Cohen */ 993b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9946c780a02SEli Cohen if (err) { 99598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9966c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 997e161105eSSaeed Mahameed return err; 9986c780a02SEli Cohen } 9996c780a02SEli Cohen 1000e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1001e126ba97SEli Cohen if (err) { 100298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1003e161105eSSaeed Mahameed return err; 1004e126ba97SEli Cohen } 1005e126ba97SEli Cohen 1006b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1007e3297246SEli Cohen if (err) { 100898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 1009e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 101055378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1011e3297246SEli Cohen } 1012e3297246SEli Cohen 1013f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1014f7936dddSEran Ben Elisha 10150b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1016cd23b14bSEli Cohen if (err) { 101798a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 101859211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 1019cd23b14bSEli Cohen } 1020cd23b14bSEli Cohen 1021f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1022f62b8bb8SAmir Vadai if (err) { 102398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1024f62b8bb8SAmir Vadai goto err_disable_hca; 1025f62b8bb8SAmir Vadai } 1026f62b8bb8SAmir Vadai 1027cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1028cd23b14bSEli Cohen if (err) { 102998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1030cd23b14bSEli Cohen goto err_disable_hca; 1031cd23b14bSEli Cohen } 1032cd23b14bSEli Cohen 1033e126ba97SEli Cohen err = set_hca_ctrl(dev); 1034e126ba97SEli Cohen if (err) { 103598a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1036cd23b14bSEli Cohen goto reclaim_boot_pages; 1037e126ba97SEli Cohen } 1038e126ba97SEli Cohen 103937b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1040e126ba97SEli Cohen if (err) { 104198a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 104246861e3eSMoni Shoua goto reclaim_boot_pages; 104346861e3eSMoni Shoua } 104446861e3eSMoni Shoua 1045cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1046e126ba97SEli Cohen if (err) { 104798a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1048cd23b14bSEli Cohen goto reclaim_boot_pages; 1049e126ba97SEli Cohen } 1050e126ba97SEli Cohen 10518737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1052e126ba97SEli Cohen if (err) { 105398a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10540cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1055e126ba97SEli Cohen } 1056e126ba97SEli Cohen 1057012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1058012e50e1SHuy Nguyen 1059e126ba97SEli Cohen mlx5_start_health_poll(dev); 1060e126ba97SEli Cohen 1061bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1062bba1574cSDaniel Jurgens if (err) { 106398a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1064e161105eSSaeed Mahameed goto stop_health; 1065bba1574cSDaniel Jurgens } 1066bba1574cSDaniel Jurgens 1067e161105eSSaeed Mahameed return 0; 1068e161105eSSaeed Mahameed 1069e161105eSSaeed Mahameed stop_health: 1070e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1071e161105eSSaeed Mahameed reclaim_boot_pages: 1072e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1073e161105eSSaeed Mahameed err_disable_hca: 1074e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1075e161105eSSaeed Mahameed err_cmd_cleanup: 1076f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1077e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1078e161105eSSaeed Mahameed 1079e161105eSSaeed Mahameed return err; 1080e161105eSSaeed Mahameed } 1081e161105eSSaeed Mahameed 1082e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1083e161105eSSaeed Mahameed { 1084e161105eSSaeed Mahameed int err; 1085e161105eSSaeed Mahameed 1086e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1087e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1088259bbc57SMaor Gottlieb if (err) { 108998a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1090e161105eSSaeed Mahameed return err; 1091e126ba97SEli Cohen } 1092e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1093e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1094f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1095e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1096e161105eSSaeed Mahameed 1097e161105eSSaeed Mahameed return 0; 1098259bbc57SMaor Gottlieb } 1099e126ba97SEli Cohen 1100a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1101e161105eSSaeed Mahameed { 1102e161105eSSaeed Mahameed int err; 1103e161105eSSaeed Mahameed 110401187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 110572f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 110698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 110772f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1108a80d1b68SSaeed Mahameed return err; 1109e126ba97SEli Cohen } 1110e126ba97SEli Cohen 111169c1280bSSaeed Mahameed mlx5_events_start(dev); 11120cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 11130cf53c12SSaeed Mahameed 1114e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1115e1706e62SYuval Avnery if (err) { 1116e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1117e1706e62SYuval Avnery goto err_irq_table; 1118e1706e62SYuval Avnery } 1119e1706e62SYuval Avnery 1120c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1121e126ba97SEli Cohen if (err) { 112298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1123c8e21b3bSSaeed Mahameed goto err_eq_table; 1124e126ba97SEli Cohen } 1125e126ba97SEli Cohen 112624406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 112724406953SFeras Daoud if (err) { 112898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 112924406953SFeras Daoud goto err_fw_tracer; 113024406953SFeras Daoud } 113124406953SFeras Daoud 113238b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 113387175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 113487175120SEran Ben Elisha 113512206b17SAya Levin err = mlx5_rsc_dump_init(dev); 113612206b17SAya Levin if (err) { 113712206b17SAya Levin mlx5_core_err(dev, "Failed to init Resource dump\n"); 113812206b17SAya Levin goto err_rsc_dump; 113912206b17SAya Levin } 114012206b17SAya Levin 114104e87170SMatan Barak err = mlx5_fpga_device_start(dev); 114204e87170SMatan Barak if (err) { 114398a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 114404e87170SMatan Barak goto err_fpga_start; 114504e87170SMatan Barak } 114604e87170SMatan Barak 11479a6ad1adSRaed Salem mlx5_accel_ipsec_init(dev); 114804e87170SMatan Barak 11491ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11501ae17322SIlya Lesokhin if (err) { 115198a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11521ae17322SIlya Lesokhin goto err_tls_start; 11531ae17322SIlya Lesokhin } 11541ae17322SIlya Lesokhin 115586d722adSMaor Gottlieb err = mlx5_init_fs(dev); 115686d722adSMaor Gottlieb if (err) { 115798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 115886d722adSMaor Gottlieb goto err_fs; 115986d722adSMaor Gottlieb } 11601466cc5bSYevgeny Petrilin 1161c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1162c85023e1SHuy Nguyen if (err) { 116398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 116487883929SSaeed Mahameed goto err_sriov; 1165c85023e1SHuy Nguyen } 1166c85023e1SHuy Nguyen 1167f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1168f3196bb0SParav Pandit 11696a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 11706a327321SParav Pandit if (err) { 11716a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 11726a327321SParav Pandit goto err_vhca; 11736a327321SParav Pandit } 11746a327321SParav Pandit 117522e939a9SBodong Wang err = mlx5_ec_init(dev); 117622e939a9SBodong Wang if (err) { 117798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 117822e939a9SBodong Wang goto err_ec; 117922e939a9SBodong Wang } 118022e939a9SBodong Wang 11815bef709dSParav Pandit err = mlx5_sriov_attach(dev); 11825bef709dSParav Pandit if (err) { 11835bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 11845bef709dSParav Pandit goto err_sriov; 11855bef709dSParav Pandit } 11865bef709dSParav Pandit 118790d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 118890d010b8SParav Pandit 1189a80d1b68SSaeed Mahameed return 0; 1190a80d1b68SSaeed Mahameed 1191a80d1b68SSaeed Mahameed err_sriov: 11925bef709dSParav Pandit mlx5_ec_cleanup(dev); 11935bef709dSParav Pandit err_ec: 11946a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 11956a327321SParav Pandit err_vhca: 1196f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1197a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1198a80d1b68SSaeed Mahameed err_fs: 1199a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1200a80d1b68SSaeed Mahameed err_tls_start: 1201a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1202a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1203a80d1b68SSaeed Mahameed err_fpga_start: 120412206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 120512206b17SAya Levin err_rsc_dump: 120687175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 120738b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1208a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1209a80d1b68SSaeed Mahameed err_fw_tracer: 1210a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1211a80d1b68SSaeed Mahameed err_eq_table: 1212e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1213e1706e62SYuval Avnery err_irq_table: 1214a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1215a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1216a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1217a80d1b68SSaeed Mahameed return err; 1218a80d1b68SSaeed Mahameed } 1219a80d1b68SSaeed Mahameed 1220a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1221a80d1b68SSaeed Mahameed { 122290d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1223a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 12245bef709dSParav Pandit mlx5_ec_cleanup(dev); 12256a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1226f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1227a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1228a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1229a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1230a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 123112206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 123287175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 123338b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1234a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1235a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1236e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1237a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1238a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1239a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1240a80d1b68SSaeed Mahameed } 1241a80d1b68SSaeed Mahameed 12424383cfccSMichael Guralnik int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1243a80d1b68SSaeed Mahameed { 1244a80d1b68SSaeed Mahameed int err = 0; 1245a80d1b68SSaeed Mahameed 1246a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1247a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1248a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1249a80d1b68SSaeed Mahameed goto out; 1250a80d1b68SSaeed Mahameed } 1251a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1252a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1253a80d1b68SSaeed Mahameed 1254a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1255a80d1b68SSaeed Mahameed if (err) 12564f7400d5SShay Drory goto err_function; 1257a80d1b68SSaeed Mahameed 1258a80d1b68SSaeed Mahameed if (boot) { 1259a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1260a80d1b68SSaeed Mahameed if (err) { 126198a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1262a80d1b68SSaeed Mahameed goto function_teardown; 1263a80d1b68SSaeed Mahameed } 1264a80d1b68SSaeed Mahameed } 1265a80d1b68SSaeed Mahameed 1266a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1267a80d1b68SSaeed Mahameed if (err) 1268a80d1b68SSaeed Mahameed goto err_load; 1269a80d1b68SSaeed Mahameed 127098f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 127198f91c45SParav Pandit 1272a6f3b623SMichael Guralnik if (boot) { 1273a6f3b623SMichael Guralnik err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1274a6f3b623SMichael Guralnik if (err) 1275a6f3b623SMichael Guralnik goto err_devlink_reg; 1276a925b5e3SLeon Romanovsky 1277a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 127898f91c45SParav Pandit } else { 1279a925b5e3SLeon Romanovsky err = mlx5_attach_device(dev); 128098f91c45SParav Pandit } 128189d44f0aSMajd Dibbiny 1282a925b5e3SLeon Romanovsky if (err) 1283a925b5e3SLeon Romanovsky goto err_register; 1284a925b5e3SLeon Romanovsky 12854162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 12864162f58bSParav Pandit return 0; 1287e126ba97SEli Cohen 1288a925b5e3SLeon Romanovsky err_register: 1289a925b5e3SLeon Romanovsky if (boot) 1290a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1291a6f3b623SMichael Guralnik err_devlink_reg: 129298f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1293a80d1b68SSaeed Mahameed mlx5_unload(dev); 1294a80d1b68SSaeed Mahameed err_load: 129559211bd3SMohamad Haj Yahia if (boot) 129659211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1297e161105eSSaeed Mahameed function_teardown: 1298e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 12994f7400d5SShay Drory err_function: 130089d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 13014162f58bSParav Pandit out: 130289d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1303e126ba97SEli Cohen return err; 1304e126ba97SEli Cohen } 1305e126ba97SEli Cohen 1306f999b706SParav Pandit void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1307e126ba97SEli Cohen { 130889d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 130998f91c45SParav Pandit 131098f91c45SParav Pandit if (cleanup) { 131198f91c45SParav Pandit mlx5_unregister_device(dev); 131298f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 131398f91c45SParav Pandit } else { 131498f91c45SParav Pandit mlx5_detach_device(dev); 131598f91c45SParav Pandit } 131698f91c45SParav Pandit 1317b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 131898a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 131989d44f0aSMajd Dibbiny __func__); 132059211bd3SMohamad Haj Yahia if (cleanup) 132159211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 132289d44f0aSMajd Dibbiny goto out; 132389d44f0aSMajd Dibbiny } 13246b6adee3SMohamad Haj Yahia 13259ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13269ade8c7cSIlan Tayari 1327a80d1b68SSaeed Mahameed mlx5_unload(dev); 1328a80d1b68SSaeed Mahameed 132959211bd3SMohamad Haj Yahia if (cleanup) 133059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 13310cf53c12SSaeed Mahameed 1332e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1333ac6ea6e8SEli Cohen out: 133489d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 13359603b61dSJack Morgenstein } 133664613d94SSaeed Mahameed 13371958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 13389603b61dSJack Morgenstein { 133911f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 13409603b61dSJack Morgenstein int err; 13419603b61dSJack Morgenstein 134211f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 13439603b61dSJack Morgenstein 1344364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1345364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 134689d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1347d9aaed83SArtemy Kovalyov 134801187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 134901187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 135001187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 135101187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 135201187175SEli Cohen 135311f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 135411f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 135511f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 135611f3b84dSSaeed Mahameed 135727b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 135827b942fbSParav Pandit mlx5_debugfs_root); 13593d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 13603d347b1bSAya Levin 1361ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 136252c368dcSSaeed Mahameed if (err) 136352c368dcSSaeed Mahameed goto err_health_init; 1364ac6ea6e8SEli Cohen 13650cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 13660cf53c12SSaeed Mahameed if (err) 13670cf53c12SSaeed Mahameed goto err_pagealloc_init; 136859211bd3SMohamad Haj Yahia 1369a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1370a925b5e3SLeon Romanovsky if (err) 1371a925b5e3SLeon Romanovsky goto err_adev_init; 1372a925b5e3SLeon Romanovsky 137311f3b84dSSaeed Mahameed return 0; 137452c368dcSSaeed Mahameed 1375a925b5e3SLeon Romanovsky err_adev_init: 1376a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 137752c368dcSSaeed Mahameed err_pagealloc_init: 137852c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 137952c368dcSSaeed Mahameed err_health_init: 138052c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1381810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1382810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1383810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1384810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1385810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 138652c368dcSSaeed Mahameed return err; 138711f3b84dSSaeed Mahameed } 138811f3b84dSSaeed Mahameed 13891958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 139011f3b84dSSaeed Mahameed { 1391810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1392810cbb25SParav Pandit 1393a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 139452c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 139552c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 139611f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1397810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1398810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1399810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1400810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1401810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 140211f3b84dSSaeed Mahameed } 140311f3b84dSSaeed Mahameed 140411f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 140511f3b84dSSaeed Mahameed { 140611f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 140711f3b84dSSaeed Mahameed struct devlink *devlink; 140811f3b84dSSaeed Mahameed int err; 140911f3b84dSSaeed Mahameed 14101f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 141111f3b84dSSaeed Mahameed if (!devlink) { 14121f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 141311f3b84dSSaeed Mahameed return -ENOMEM; 141411f3b84dSSaeed Mahameed } 141511f3b84dSSaeed Mahameed 141611f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 141727b942fbSParav Pandit dev->device = &pdev->dev; 141827b942fbSParav Pandit dev->pdev = pdev; 141911f3b84dSSaeed Mahameed 1420386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1421386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1422386e75afSHuy Nguyen 1423a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 14244d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 14254d8be211SLeon Romanovsky err = dev->priv.adev_idx; 14264d8be211SLeon Romanovsky goto adev_init_err; 14274d8be211SLeon Romanovsky } 1428a925b5e3SLeon Romanovsky 142927b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 143011f3b84dSSaeed Mahameed if (err) 143111f3b84dSSaeed Mahameed goto mdev_init_err; 143211f3b84dSSaeed Mahameed 143311f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 14349603b61dSJack Morgenstein if (err) { 143598a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 143698a8e6fcSHuy Nguyen err); 143711f3b84dSSaeed Mahameed goto pci_init_err; 14389603b61dSJack Morgenstein } 14399603b61dSJack Morgenstein 1440868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 14419603b61dSJack Morgenstein if (err) { 144298a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 144398a8e6fcSHuy Nguyen err); 14440cf53c12SSaeed Mahameed goto err_load_one; 14459603b61dSJack Morgenstein } 144659211bd3SMohamad Haj Yahia 14478b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 14488b9d8baaSAlex Vesker if (err) 14498b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 14508b9d8baaSAlex Vesker 14515d47f6c8SDaniel Jurgens pci_save_state(pdev); 1452d89ddaaeSShay Drory if (!mlx5_core_is_mp_slave(dev)) 145360904cd3SParav Pandit devlink_reload_enable(devlink); 14549603b61dSJack Morgenstein return 0; 14559603b61dSJack Morgenstein 14560cf53c12SSaeed Mahameed err_load_one: 1457868bc06bSSaeed Mahameed mlx5_pci_close(dev); 145811f3b84dSSaeed Mahameed pci_init_err: 145911f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 146011f3b84dSSaeed Mahameed mdev_init_err: 1461a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14624d8be211SLeon Romanovsky adev_init_err: 14631f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1464a31208b1SMajd Dibbiny 14659603b61dSJack Morgenstein return err; 14669603b61dSJack Morgenstein } 1467a31208b1SMajd Dibbiny 14689603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 14699603b61dSJack Morgenstein { 14709603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1471feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 14729603b61dSJack Morgenstein 147360904cd3SParav Pandit devlink_reload_disable(devlink); 14748b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 147541798df9SParav Pandit mlx5_drain_health_wq(dev); 1476f999b706SParav Pandit mlx5_unload_one(dev, true); 1477868bc06bSSaeed Mahameed mlx5_pci_close(dev); 147811f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1479a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 14801f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 14819603b61dSJack Morgenstein } 14829603b61dSJack Morgenstein 148389d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 148489d44f0aSMajd Dibbiny pci_channel_state_t state) 148589d44f0aSMajd Dibbiny { 148689d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 148789d44f0aSMajd Dibbiny 148898a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 148904c0c1abSMohamad Haj Yahia 14908812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 14913e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1492868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 14935e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 149489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 149505ac2c0bSMohamad Haj Yahia 149689d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 149789d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 149889d44f0aSMajd Dibbiny } 149989d44f0aSMajd Dibbiny 1500d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1501d57847dcSDaniel Jurgens * for the health counter to start counting. 150289d44f0aSMajd Dibbiny */ 1503d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 150489d44f0aSMajd Dibbiny { 150589d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 150689d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 150789d44f0aSMajd Dibbiny const int niter = 100; 1508d57847dcSDaniel Jurgens u32 last_count = 0; 150989d44f0aSMajd Dibbiny u32 count; 151089d44f0aSMajd Dibbiny int i; 151189d44f0aSMajd Dibbiny 151289d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 151389d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 151489d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1515d57847dcSDaniel Jurgens if (last_count && last_count != count) { 151698a8e6fcSHuy Nguyen mlx5_core_info(dev, 151798a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 151898a8e6fcSHuy Nguyen count, i); 1519d57847dcSDaniel Jurgens return 0; 1520d57847dcSDaniel Jurgens } 1521d57847dcSDaniel Jurgens last_count = count; 152289d44f0aSMajd Dibbiny } 152389d44f0aSMajd Dibbiny msleep(50); 152489d44f0aSMajd Dibbiny } 152589d44f0aSMajd Dibbiny 1526d57847dcSDaniel Jurgens return -ETIMEDOUT; 152789d44f0aSMajd Dibbiny } 152889d44f0aSMajd Dibbiny 15291061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 15301061c90fSMohamad Haj Yahia { 15311061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15321061c90fSMohamad Haj Yahia int err; 15331061c90fSMohamad Haj Yahia 153498a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 15351061c90fSMohamad Haj Yahia 15361061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 15371061c90fSMohamad Haj Yahia if (err) { 153898a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 153998a8e6fcSHuy Nguyen __func__, err); 15401061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 15411061c90fSMohamad Haj Yahia } 15421061c90fSMohamad Haj Yahia 15431061c90fSMohamad Haj Yahia pci_set_master(pdev); 15441061c90fSMohamad Haj Yahia pci_restore_state(pdev); 15455d47f6c8SDaniel Jurgens pci_save_state(pdev); 15461061c90fSMohamad Haj Yahia 15471061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 154898a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 15491061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 15501061c90fSMohamad Haj Yahia } 15511061c90fSMohamad Haj Yahia 15521061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 15531061c90fSMohamad Haj Yahia } 15541061c90fSMohamad Haj Yahia 155589d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 155689d44f0aSMajd Dibbiny { 155789d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 155889d44f0aSMajd Dibbiny int err; 155989d44f0aSMajd Dibbiny 156098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 156189d44f0aSMajd Dibbiny 1562868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 156389d44f0aSMajd Dibbiny if (err) 156498a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 156598a8e6fcSHuy Nguyen __func__, err); 156689d44f0aSMajd Dibbiny else 156798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 156889d44f0aSMajd Dibbiny } 156989d44f0aSMajd Dibbiny 157089d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 157189d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 157289d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 157389d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 157489d44f0aSMajd Dibbiny }; 157589d44f0aSMajd Dibbiny 15768812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 15778812c24dSMajd Dibbiny { 1578fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1579fcd29ad1SFeras Daoud int ret = 1; 15808812c24dSMajd Dibbiny 1581fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1582fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1583fcd29ad1SFeras Daoud 1584fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1585fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1586fcd29ad1SFeras Daoud 1587fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 15888812c24dSMajd Dibbiny return -EOPNOTSUPP; 15898812c24dSMajd Dibbiny 15908812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 15918812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 15928812c24dSMajd Dibbiny return -EAGAIN; 15938812c24dSMajd Dibbiny } 15948812c24dSMajd Dibbiny 1595d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1596d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1597d2aa060dSHuy Nguyen */ 1598d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 159976d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1600d2aa060dSHuy Nguyen 1601fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1602fcd29ad1SFeras Daoud if (!ret) 1603fcd29ad1SFeras Daoud goto succeed; 1604fcd29ad1SFeras Daoud 16058812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1606fcd29ad1SFeras Daoud if (!ret) 1607fcd29ad1SFeras Daoud goto succeed; 1608fcd29ad1SFeras Daoud 16098812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1610d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 16118812c24dSMajd Dibbiny return ret; 16128812c24dSMajd Dibbiny 1613fcd29ad1SFeras Daoud succeed: 16148812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 16158812c24dSMajd Dibbiny 16161ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 16171ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 16181ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 16191ef903bfSDaniel Jurgens * contexts. 16201ef903bfSDaniel Jurgens */ 16211ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 16221ef903bfSDaniel Jurgens 16238812c24dSMajd Dibbiny return 0; 16248812c24dSMajd Dibbiny } 16258812c24dSMajd Dibbiny 16265fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 16275fc7197dSMajd Dibbiny { 16285fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16298812c24dSMajd Dibbiny int err; 16305fc7197dSMajd Dibbiny 163198a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 16328812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 16338812c24dSMajd Dibbiny if (err) 1634868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 16355fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 16365fc7197dSMajd Dibbiny } 16375fc7197dSMajd Dibbiny 16388fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 16398fc3e29bSMark Bloch { 16408fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16418fc3e29bSMark Bloch 16428fc3e29bSMark Bloch mlx5_unload_one(dev, false); 16438fc3e29bSMark Bloch 16448fc3e29bSMark Bloch return 0; 16458fc3e29bSMark Bloch } 16468fc3e29bSMark Bloch 16478fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 16488fc3e29bSMark Bloch { 16498fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16508fc3e29bSMark Bloch 16518fc3e29bSMark Bloch return mlx5_load_one(dev, false); 16528fc3e29bSMark Bloch } 16538fc3e29bSMark Bloch 16549603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1655bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1656fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1657bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1658fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1659bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1660fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 16617092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 166264dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1663d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1664d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1665d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1666d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 166785327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 166885327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1669b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1670505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 16712e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 16722e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1673d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1674dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 16759603b61dSJack Morgenstein { 0, } 16769603b61dSJack Morgenstein }; 16779603b61dSJack Morgenstein 16789603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 16799603b61dSJack Morgenstein 168004c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 168104c0c1abSMohamad Haj Yahia { 1682b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1683b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 168404c0c1abSMohamad Haj Yahia } 168504c0c1abSMohamad Haj Yahia 168604c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 168704c0c1abSMohamad Haj Yahia { 168804c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 168904c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 169004c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 169104c0c1abSMohamad Haj Yahia } 169204c0c1abSMohamad Haj Yahia 16939603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 169417a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 16959603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 16969603b61dSJack Morgenstein .probe = init_one, 169789d44f0aSMajd Dibbiny .remove = remove_one, 16988fc3e29bSMark Bloch .suspend = mlx5_suspend, 16998fc3e29bSMark Bloch .resume = mlx5_resume, 17005fc7197dSMajd Dibbiny .shutdown = shutdown, 1701fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1702fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 17039603b61dSJack Morgenstein }; 1704e126ba97SEli Cohen 1705f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1706f663ad98SKamal Heib { 1707f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1708f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1709f663ad98SKamal Heib prof_sel, 1710f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1711f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1712f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1713f663ad98SKamal Heib } 1714f663ad98SKamal Heib } 1715f663ad98SKamal Heib 1716e126ba97SEli Cohen static int __init init(void) 1717e126ba97SEli Cohen { 1718e126ba97SEli Cohen int err; 1719e126ba97SEli Cohen 172017a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 172117a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 172217a7612bSLeon Romanovsky 17238737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 17248737f818SDaniel Jurgens 1725f663ad98SKamal Heib mlx5_core_verify_params(); 17269a6ad1adSRaed Salem mlx5_fpga_ipsec_build_fs_cmds(); 1727e126ba97SEli Cohen mlx5_register_debugfs(); 1728e126ba97SEli Cohen 17299603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 17309603b61dSJack Morgenstein if (err) 1731ac6ea6e8SEli Cohen goto err_debug; 17329603b61dSJack Morgenstein 17331958fc2fSParav Pandit err = mlx5_sf_driver_register(); 17341958fc2fSParav Pandit if (err) 17351958fc2fSParav Pandit goto err_sf; 17361958fc2fSParav Pandit 1737f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1738912cebf4SLeon Romanovsky err = mlx5e_init(); 1739912cebf4SLeon Romanovsky if (err) { 1740912cebf4SLeon Romanovsky pci_unregister_driver(&mlx5_core_driver); 1741912cebf4SLeon Romanovsky goto err_debug; 1742912cebf4SLeon Romanovsky } 1743f62b8bb8SAmir Vadai #endif 1744f62b8bb8SAmir Vadai 1745e126ba97SEli Cohen return 0; 1746e126ba97SEli Cohen 17471958fc2fSParav Pandit err_sf: 17481958fc2fSParav Pandit pci_unregister_driver(&mlx5_core_driver); 1749e126ba97SEli Cohen err_debug: 1750e126ba97SEli Cohen mlx5_unregister_debugfs(); 1751e126ba97SEli Cohen return err; 1752e126ba97SEli Cohen } 1753e126ba97SEli Cohen 1754e126ba97SEli Cohen static void __exit cleanup(void) 1755e126ba97SEli Cohen { 1756f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1757f62b8bb8SAmir Vadai mlx5e_cleanup(); 1758f62b8bb8SAmir Vadai #endif 17591958fc2fSParav Pandit mlx5_sf_driver_unregister(); 17609603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1761e126ba97SEli Cohen mlx5_unregister_debugfs(); 1762e126ba97SEli Cohen } 1763e126ba97SEli Cohen 1764e126ba97SEli Cohen module_init(init); 1765e126ba97SEli Cohen module_exit(cleanup); 1766