1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53907af0f0SLeon Romanovsky #include <linux/version.h> 54feae9087SOr Gerlitz #include <net/devlink.h> 55e126ba97SEli Cohen #include "mlx5_core.h" 56f2f3df55SSaeed Mahameed #include "lib/eq.h" 5716d76083SSaeed Mahameed #include "fs_core.h" 58eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 59073bb189SSaeed Mahameed #include "eswitch.h" 601f28d776SEran Ben Elisha #include "devlink.h" 6138b9f903SMoshe Shemesh #include "fw_reset.h" 6252ec462eSIlan Tayari #include "lib/mlx5.h" 635945e1adSAmir Tzin #include "lib/tout.h" 64e29341fbSIlan Tayari #include "fpga/core.h" 6505564d0aSAviad Yehezkel #include "fpga/ipsec.h" 66bebb23e6SIlan Tayari #include "accel/ipsec.h" 671ae17322SIlya Lesokhin #include "accel/tls.h" 687c39afb3SFeras Daoud #include "lib/clock.h" 69358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 700ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 71fadd59fcSAviv Heller #include "lib/devcom.h" 72b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7324406953SFeras Daoud #include "diag/fw_tracer.h" 74591905baSBodong Wang #include "ecpf.h" 7587175120SEran Ben Elisha #include "lib/hv_vhca.h" 7612206b17SAya Levin #include "diag/rsc_dump.h" 77f3196bb0SParav Pandit #include "sf/vhca_event.h" 7890d010b8SParav Pandit #include "sf/dev/dev.h" 796a327321SParav Pandit #include "sf/sf.h" 803b43190bSShay Drory #include "mlx5_irq.h" 81e126ba97SEli Cohen 82e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 83048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 84e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 85e126ba97SEli Cohen 86f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 87f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 88e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 89e126ba97SEli Cohen 90f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 91f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 929603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 939603b61dSJack Morgenstein 948737f818SDaniel Jurgens static u32 sw_owner_id[4]; 958737f818SDaniel Jurgens 96f91e6d89SEran Ben Elisha enum { 97f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 98f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 99f91e6d89SEran Ben Elisha }; 100f91e6d89SEran Ben Elisha 1019603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 1029603b61dSJack Morgenstein [0] = { 1039603b61dSJack Morgenstein .mask = 0, 1049603b61dSJack Morgenstein }, 1059603b61dSJack Morgenstein [1] = { 1069603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1079603b61dSJack Morgenstein .log_max_qp = 12, 1089603b61dSJack Morgenstein }, 1099603b61dSJack Morgenstein [2] = { 1109603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1119603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1125f40b4edSMaor Gottlieb .log_max_qp = 18, 1139603b61dSJack Morgenstein .mr_cache[0] = { 1149603b61dSJack Morgenstein .size = 500, 1159603b61dSJack Morgenstein .limit = 250 1169603b61dSJack Morgenstein }, 1179603b61dSJack Morgenstein .mr_cache[1] = { 1189603b61dSJack Morgenstein .size = 500, 1199603b61dSJack Morgenstein .limit = 250 1209603b61dSJack Morgenstein }, 1219603b61dSJack Morgenstein .mr_cache[2] = { 1229603b61dSJack Morgenstein .size = 500, 1239603b61dSJack Morgenstein .limit = 250 1249603b61dSJack Morgenstein }, 1259603b61dSJack Morgenstein .mr_cache[3] = { 1269603b61dSJack Morgenstein .size = 500, 1279603b61dSJack Morgenstein .limit = 250 1289603b61dSJack Morgenstein }, 1299603b61dSJack Morgenstein .mr_cache[4] = { 1309603b61dSJack Morgenstein .size = 500, 1319603b61dSJack Morgenstein .limit = 250 1329603b61dSJack Morgenstein }, 1339603b61dSJack Morgenstein .mr_cache[5] = { 1349603b61dSJack Morgenstein .size = 500, 1359603b61dSJack Morgenstein .limit = 250 1369603b61dSJack Morgenstein }, 1379603b61dSJack Morgenstein .mr_cache[6] = { 1389603b61dSJack Morgenstein .size = 500, 1399603b61dSJack Morgenstein .limit = 250 1409603b61dSJack Morgenstein }, 1419603b61dSJack Morgenstein .mr_cache[7] = { 1429603b61dSJack Morgenstein .size = 500, 1439603b61dSJack Morgenstein .limit = 250 1449603b61dSJack Morgenstein }, 1459603b61dSJack Morgenstein .mr_cache[8] = { 1469603b61dSJack Morgenstein .size = 500, 1479603b61dSJack Morgenstein .limit = 250 1489603b61dSJack Morgenstein }, 1499603b61dSJack Morgenstein .mr_cache[9] = { 1509603b61dSJack Morgenstein .size = 500, 1519603b61dSJack Morgenstein .limit = 250 1529603b61dSJack Morgenstein }, 1539603b61dSJack Morgenstein .mr_cache[10] = { 1549603b61dSJack Morgenstein .size = 500, 1559603b61dSJack Morgenstein .limit = 250 1569603b61dSJack Morgenstein }, 1579603b61dSJack Morgenstein .mr_cache[11] = { 1589603b61dSJack Morgenstein .size = 500, 1599603b61dSJack Morgenstein .limit = 250 1609603b61dSJack Morgenstein }, 1619603b61dSJack Morgenstein .mr_cache[12] = { 1629603b61dSJack Morgenstein .size = 64, 1639603b61dSJack Morgenstein .limit = 32 1649603b61dSJack Morgenstein }, 1659603b61dSJack Morgenstein .mr_cache[13] = { 1669603b61dSJack Morgenstein .size = 32, 1679603b61dSJack Morgenstein .limit = 16 1689603b61dSJack Morgenstein }, 1699603b61dSJack Morgenstein .mr_cache[14] = { 1709603b61dSJack Morgenstein .size = 16, 1719603b61dSJack Morgenstein .limit = 8 1729603b61dSJack Morgenstein }, 1739603b61dSJack Morgenstein .mr_cache[15] = { 1749603b61dSJack Morgenstein .size = 8, 1759603b61dSJack Morgenstein .limit = 4 1769603b61dSJack Morgenstein }, 1779603b61dSJack Morgenstein }, 1789603b61dSJack Morgenstein }; 179e126ba97SEli Cohen 180555af0c3SParav Pandit static int fw_initializing(struct mlx5_core_dev *dev) 181555af0c3SParav Pandit { 182555af0c3SParav Pandit return ioread32be(&dev->iseg->initializing) >> 31; 183555af0c3SParav Pandit } 184555af0c3SParav Pandit 185b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 186b8a92577SDaniel Jurgens u32 warn_time_mili) 187e3297246SEli Cohen { 188b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 189e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 190e3297246SEli Cohen int err = 0; 191e3297246SEli Cohen 192e3297246SEli Cohen while (fw_initializing(dev)) { 193e3297246SEli Cohen if (time_after(jiffies, end)) { 194e3297246SEli Cohen err = -EBUSY; 195e3297246SEli Cohen break; 196e3297246SEli Cohen } 197b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 198b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 199b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 200b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 201b8a92577SDaniel Jurgens } 2025945e1adSAmir Tzin msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 203e3297246SEli Cohen } 204e3297246SEli Cohen 205e3297246SEli Cohen return err; 206e3297246SEli Cohen } 207e3297246SEli Cohen 208012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 209012e50e1SHuy Nguyen { 210012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 211012e50e1SHuy Nguyen driver_version); 2123ac0e69eSLeon Romanovsky u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 213012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 214012e50e1SHuy Nguyen char *string; 215012e50e1SHuy Nguyen 216012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 217012e50e1SHuy Nguyen return; 218012e50e1SHuy Nguyen 219012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 222012e50e1SHuy Nguyen 223012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 224012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 225012e50e1SHuy Nguyen 226012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 22717a7612bSLeon Romanovsky strncat(string, KBUILD_MODNAME, remaining_size); 228012e50e1SHuy Nguyen 229012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 230012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 231012e50e1SHuy Nguyen 232012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 233907af0f0SLeon Romanovsky 234907af0f0SLeon Romanovsky snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 23588a68672SSasha Levin LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 23688a68672SSasha Levin LINUX_VERSION_SUBLEVEL); 237012e50e1SHuy Nguyen 238012e50e1SHuy Nguyen /*Send the command*/ 239012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 240012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 241012e50e1SHuy Nguyen 2423ac0e69eSLeon Romanovsky mlx5_cmd_exec_in(dev, set_driver_version, in); 243012e50e1SHuy Nguyen } 244012e50e1SHuy Nguyen 245e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 246e126ba97SEli Cohen { 247e126ba97SEli Cohen int err; 248e126ba97SEli Cohen 249eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 250e126ba97SEli Cohen if (err) { 2511a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 252eb9c5c0dSChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 253e126ba97SEli Cohen if (err) { 2541a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 255e126ba97SEli Cohen return err; 256e126ba97SEli Cohen } 257e126ba97SEli Cohen } 258e126ba97SEli Cohen 259e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 260e126ba97SEli Cohen return err; 261e126ba97SEli Cohen } 262e126ba97SEli Cohen 26389d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 26489d44f0aSMajd Dibbiny { 26589d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 26689d44f0aSMajd Dibbiny int err = 0; 26789d44f0aSMajd Dibbiny 26889d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 26989d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27089d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27189d44f0aSMajd Dibbiny if (!err) 27289d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27389d44f0aSMajd Dibbiny } 27489d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 27589d44f0aSMajd Dibbiny 27689d44f0aSMajd Dibbiny return err; 27789d44f0aSMajd Dibbiny } 27889d44f0aSMajd Dibbiny 27989d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28089d44f0aSMajd Dibbiny { 28189d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28289d44f0aSMajd Dibbiny 28389d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28489d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 28589d44f0aSMajd Dibbiny pci_disable_device(pdev); 28689d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 28789d44f0aSMajd Dibbiny } 28889d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28989d44f0aSMajd Dibbiny } 29089d44f0aSMajd Dibbiny 291e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 292e126ba97SEli Cohen { 293e126ba97SEli Cohen int err = 0; 294e126ba97SEli Cohen 295e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2961a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 297e126ba97SEli Cohen return -ENODEV; 298e126ba97SEli Cohen } 299e126ba97SEli Cohen 30017a7612bSLeon Romanovsky err = pci_request_regions(pdev, KBUILD_MODNAME); 301e126ba97SEli Cohen if (err) 302e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 303e126ba97SEli Cohen 304e126ba97SEli Cohen return err; 305e126ba97SEli Cohen } 306e126ba97SEli Cohen 307e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 308e126ba97SEli Cohen { 309e126ba97SEli Cohen pci_release_regions(pdev); 310e126ba97SEli Cohen } 311e126ba97SEli Cohen 312bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 313e126ba97SEli Cohen u8 he; 314e126ba97SEli Cohen u8 rsvd[15]; 315e126ba97SEli Cohen }; 316e126ba97SEli Cohen 31787b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 31887b8de49SEli Cohen 31987b8de49SEli Cohen enum { 32087b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 321c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 32287b8de49SEli Cohen }; 32387b8de49SEli Cohen 3242974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 325c7a08ac7SEli Cohen { 326c7a08ac7SEli Cohen switch (size) { 327c7a08ac7SEli Cohen case 128: 328c7a08ac7SEli Cohen return 0; 329c7a08ac7SEli Cohen case 256: 330c7a08ac7SEli Cohen return 1; 331c7a08ac7SEli Cohen case 512: 332c7a08ac7SEli Cohen return 2; 333c7a08ac7SEli Cohen case 1024: 334c7a08ac7SEli Cohen return 3; 335c7a08ac7SEli Cohen case 2048: 336c7a08ac7SEli Cohen return 4; 337c7a08ac7SEli Cohen case 4096: 338c7a08ac7SEli Cohen return 5; 339c7a08ac7SEli Cohen default: 3402974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 341c7a08ac7SEli Cohen return 0; 342c7a08ac7SEli Cohen } 343c7a08ac7SEli Cohen } 344c7a08ac7SEli Cohen 345b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 346b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 347938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 348c7a08ac7SEli Cohen { 349b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 350b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 351938fe83cSSaeed Mahameed void *out, *hca_caps; 352938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 353c7a08ac7SEli Cohen int err; 354c7a08ac7SEli Cohen 355b775516bSEli Cohen memset(in, 0, sizeof(in)); 356b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 357c7a08ac7SEli Cohen if (!out) 358c7a08ac7SEli Cohen return -ENOMEM; 359938fe83cSSaeed Mahameed 360b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 361b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 3623ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 363c7a08ac7SEli Cohen if (err) { 364938fe83cSSaeed Mahameed mlx5_core_warn(dev, 365938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 366938fe83cSSaeed Mahameed cap_type, cap_mode, err); 367c7a08ac7SEli Cohen goto query_ex; 368c7a08ac7SEli Cohen } 369c7a08ac7SEli Cohen 370938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 371938fe83cSSaeed Mahameed 372938fe83cSSaeed Mahameed switch (cap_mode) { 373938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 37448f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->max, hca_caps, 375938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 376938fe83cSSaeed Mahameed break; 377938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 37848f02eefSParav Pandit memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 379938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 380938fe83cSSaeed Mahameed break; 381938fe83cSSaeed Mahameed default: 382938fe83cSSaeed Mahameed mlx5_core_warn(dev, 383938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 384938fe83cSSaeed Mahameed cap_type, cap_mode); 385938fe83cSSaeed Mahameed err = -EINVAL; 386938fe83cSSaeed Mahameed break; 387938fe83cSSaeed Mahameed } 388c7a08ac7SEli Cohen query_ex: 389c7a08ac7SEli Cohen kfree(out); 390c7a08ac7SEli Cohen return err; 391c7a08ac7SEli Cohen } 392c7a08ac7SEli Cohen 393b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 394b06e7de8SLeon Romanovsky { 395b06e7de8SLeon Romanovsky int ret; 396b06e7de8SLeon Romanovsky 397b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 398b06e7de8SLeon Romanovsky if (ret) 399b06e7de8SLeon Romanovsky return ret; 400b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 401b06e7de8SLeon Romanovsky } 402b06e7de8SLeon Romanovsky 403a2a322f4SLeon Romanovsky static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 404c7a08ac7SEli Cohen { 405b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 406f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 4073ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, set_hca_cap, in); 408c7a08ac7SEli Cohen } 40987b8de49SEli Cohen 410a2a322f4SLeon Romanovsky static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 411f91e6d89SEran Ben Elisha { 412f91e6d89SEran Ben Elisha void *set_hca_cap; 413f91e6d89SEran Ben Elisha int req_endianness; 414f91e6d89SEran Ben Elisha int err; 415f91e6d89SEran Ben Elisha 416a2a322f4SLeon Romanovsky if (!MLX5_CAP_GEN(dev, atomic)) 417a2a322f4SLeon Romanovsky return 0; 418a2a322f4SLeon Romanovsky 419b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 420f91e6d89SEran Ben Elisha if (err) 421f91e6d89SEran Ben Elisha return err; 422f91e6d89SEran Ben Elisha 423f91e6d89SEran Ben Elisha req_endianness = 424f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 425bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 426f91e6d89SEran Ben Elisha 427f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 428f91e6d89SEran Ben Elisha return 0; 429f91e6d89SEran Ben Elisha 430f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 431f91e6d89SEran Ben Elisha 432f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 433bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 434f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 435f91e6d89SEran Ben Elisha 436a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 437f91e6d89SEran Ben Elisha } 438f91e6d89SEran Ben Elisha 439a2a322f4SLeon Romanovsky static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 44046861e3eSMoni Shoua { 44146861e3eSMoni Shoua void *set_hca_cap; 442fca22e7eSMoni Shoua bool do_set = false; 44346861e3eSMoni Shoua int err; 44446861e3eSMoni Shoua 44537b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 44637b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 44746861e3eSMoni Shoua return 0; 44846861e3eSMoni Shoua 44946861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 45046861e3eSMoni Shoua if (err) 45146861e3eSMoni Shoua return err; 45246861e3eSMoni Shoua 45346861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 45448f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 45546861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 45646861e3eSMoni Shoua 457fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 458fca22e7eSMoni Shoua do { \ 459fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 460fca22e7eSMoni Shoua if (_res) { \ 461fca22e7eSMoni Shoua do_set = true; \ 462fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 463fca22e7eSMoni Shoua } \ 464fca22e7eSMoni Shoua } while (0) 46546861e3eSMoni Shoua 466fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 467fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 468fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 469fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 470fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 471fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 472fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 473fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 47400679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 47500679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 47600679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 47700679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 47800679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 47900679b63SMichael Guralnik ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 48046861e3eSMoni Shoua 481a2a322f4SLeon Romanovsky if (!do_set) 482a2a322f4SLeon Romanovsky return 0; 48346861e3eSMoni Shoua 484a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 48546861e3eSMoni Shoua } 48646861e3eSMoni Shoua 487a2a322f4SLeon Romanovsky static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 488e126ba97SEli Cohen { 4893410fbcdSMaor Gottlieb struct mlx5_profile *prof = &dev->profile; 490938fe83cSSaeed Mahameed void *set_hca_cap; 491a2a322f4SLeon Romanovsky int err; 492e126ba97SEli Cohen 493b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 494c7a08ac7SEli Cohen if (err) 495a2a322f4SLeon Romanovsky return err; 496e126ba97SEli Cohen 497938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 498938fe83cSSaeed Mahameed capability); 49948f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 500938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 501938fe83cSSaeed Mahameed 502938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 503707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 504938fe83cSSaeed Mahameed 128); 505c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 506938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5072974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 508e126ba97SEli Cohen 509883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 5103410fbcdSMaor Gottlieb if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 511883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 5123410fbcdSMaor Gottlieb prof->log_max_qp, 513883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 5143410fbcdSMaor Gottlieb prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 515883371c4SNoa Osherovich } 516c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 517938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 518938fe83cSSaeed Mahameed prof->log_max_qp); 519e126ba97SEli Cohen 520938fe83cSSaeed Mahameed /* disable cmdif checksum */ 521938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 522c1868b82SEli Cohen 52391828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 52491828bd8SMajd Dibbiny * than 4K. 52591828bd8SMajd Dibbiny */ 52691828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 527f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 528f502d834SEli Cohen 529fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 530fe1e1876SCarol L Soto 531f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 532f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 533f32f5bd2SDaniel Jurgens set_hca_cap, 534f32f5bd2SDaniel Jurgens cache_line_128byte, 535c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 536f32f5bd2SDaniel Jurgens 537dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 538dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 539dd44572aSMoni Shoua 540e7f4d0bcSMoshe Shemesh if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 541e7f4d0bcSMoshe Shemesh MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 542e7f4d0bcSMoshe Shemesh 543c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 544c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 545c4b76d8dSDaniel Jurgens set_hca_cap, 546c4b76d8dSDaniel Jurgens num_vhca_ports, 547c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 548c4b76d8dSDaniel Jurgens 549c6168161SEran Ben Elisha if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 550c6168161SEran Ben Elisha MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 551c6168161SEran Ben Elisha 5524dca6509SMichael Guralnik if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 5534dca6509SMichael Guralnik MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 5544dca6509SMichael Guralnik 555f3196bb0SParav Pandit mlx5_vhca_state_cap_handle(dev, set_hca_cap); 556f3196bb0SParav Pandit 557604774adSLeon Romanovsky if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 558604774adSLeon Romanovsky MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 559604774adSLeon Romanovsky MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 560604774adSLeon Romanovsky 561fbfa97b4SShay Drory if (MLX5_CAP_GEN(dev, roce_rw_supported)) 562fbfa97b4SShay Drory MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev)); 563fbfa97b4SShay Drory 564a2a322f4SLeon Romanovsky return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 565e126ba97SEli Cohen } 566cd23b14bSEli Cohen 567fbfa97b4SShay Drory /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 568fbfa97b4SShay Drory * boot process. 569fbfa97b4SShay Drory * In case RoCE cap is writable in FW and user/devlink requested to change the 570fbfa97b4SShay Drory * cap, we are yet to query the final state of the above cap. 571fbfa97b4SShay Drory * Hence, the need for this function. 572fbfa97b4SShay Drory * 573fbfa97b4SShay Drory * Returns 574fbfa97b4SShay Drory * True: 575fbfa97b4SShay Drory * 1) RoCE cap is read only in FW and already disabled 576fbfa97b4SShay Drory * OR: 577fbfa97b4SShay Drory * 2) RoCE cap is writable in FW and user/devlink requested it off. 578fbfa97b4SShay Drory * 579fbfa97b4SShay Drory * In any other case, return False. 580fbfa97b4SShay Drory */ 581fbfa97b4SShay Drory static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 582fbfa97b4SShay Drory { 583fbfa97b4SShay Drory return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) || 584fbfa97b4SShay Drory (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 585fbfa97b4SShay Drory } 586fbfa97b4SShay Drory 58759e9e8e4SMark Zhang static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 58859e9e8e4SMark Zhang { 58959e9e8e4SMark Zhang void *set_hca_cap; 59059e9e8e4SMark Zhang int err; 59159e9e8e4SMark Zhang 592fbfa97b4SShay Drory if (is_roce_fw_disabled(dev)) 59359e9e8e4SMark Zhang return 0; 59459e9e8e4SMark Zhang 59559e9e8e4SMark Zhang err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 59659e9e8e4SMark Zhang if (err) 59759e9e8e4SMark Zhang return err; 59859e9e8e4SMark Zhang 59959e9e8e4SMark Zhang if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 60059e9e8e4SMark Zhang !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 60159e9e8e4SMark Zhang return 0; 60259e9e8e4SMark Zhang 60359e9e8e4SMark Zhang set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 60448f02eefSParav Pandit memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 60559e9e8e4SMark Zhang MLX5_ST_SZ_BYTES(roce_cap)); 60659e9e8e4SMark Zhang MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 60759e9e8e4SMark Zhang 60859e9e8e4SMark Zhang err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 609e126ba97SEli Cohen return err; 610e126ba97SEli Cohen } 611e126ba97SEli Cohen 61237b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 61337b6bb77SLeon Romanovsky { 614a2a322f4SLeon Romanovsky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 615a2a322f4SLeon Romanovsky void *set_ctx; 61637b6bb77SLeon Romanovsky int err; 61737b6bb77SLeon Romanovsky 618a2a322f4SLeon Romanovsky set_ctx = kzalloc(set_sz, GFP_KERNEL); 619a2a322f4SLeon Romanovsky if (!set_ctx) 620a2a322f4SLeon Romanovsky return -ENOMEM; 621a2a322f4SLeon Romanovsky 622a2a322f4SLeon Romanovsky err = handle_hca_cap(dev, set_ctx); 62337b6bb77SLeon Romanovsky if (err) { 62498a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 62537b6bb77SLeon Romanovsky goto out; 62637b6bb77SLeon Romanovsky } 62737b6bb77SLeon Romanovsky 628a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 629a2a322f4SLeon Romanovsky err = handle_hca_cap_atomic(dev, set_ctx); 63037b6bb77SLeon Romanovsky if (err) { 63198a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 63237b6bb77SLeon Romanovsky goto out; 63337b6bb77SLeon Romanovsky } 63437b6bb77SLeon Romanovsky 635a2a322f4SLeon Romanovsky memset(set_ctx, 0, set_sz); 636a2a322f4SLeon Romanovsky err = handle_hca_cap_odp(dev, set_ctx); 63737b6bb77SLeon Romanovsky if (err) { 63898a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 63937b6bb77SLeon Romanovsky goto out; 64037b6bb77SLeon Romanovsky } 64137b6bb77SLeon Romanovsky 64259e9e8e4SMark Zhang memset(set_ctx, 0, set_sz); 64359e9e8e4SMark Zhang err = handle_hca_cap_roce(dev, set_ctx); 64459e9e8e4SMark Zhang if (err) { 64559e9e8e4SMark Zhang mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 64659e9e8e4SMark Zhang goto out; 64759e9e8e4SMark Zhang } 64859e9e8e4SMark Zhang 64937b6bb77SLeon Romanovsky out: 650a2a322f4SLeon Romanovsky kfree(set_ctx); 65137b6bb77SLeon Romanovsky return err; 65237b6bb77SLeon Romanovsky } 65337b6bb77SLeon Romanovsky 654e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 655e126ba97SEli Cohen { 656bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 657bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 658e126ba97SEli Cohen int err; 659e126ba97SEli Cohen 660fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 661fc50db98SEli Cohen return 0; 662fc50db98SEli Cohen 663e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 664e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 665e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 666e126ba97SEli Cohen &he_out, sizeof(he_out), 667e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 668e126ba97SEli Cohen return err; 669e126ba97SEli Cohen } 670e126ba97SEli Cohen 671c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 672c85023e1SHuy Nguyen { 673c85023e1SHuy Nguyen int ret = 0; 674c85023e1SHuy Nguyen 675c85023e1SHuy Nguyen /* Disable local_lb by default */ 6768978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 677c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 678c85023e1SHuy Nguyen 679c85023e1SHuy Nguyen return ret; 680c85023e1SHuy Nguyen } 681c85023e1SHuy Nguyen 6820b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 683e126ba97SEli Cohen { 6843ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 685e126ba97SEli Cohen 6860b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6870b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 68822e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 68922e939a9SBodong Wang dev->caps.embedded_cpu); 6903ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, enable_hca, in); 691e126ba97SEli Cohen } 692e126ba97SEli Cohen 6930b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 694e126ba97SEli Cohen { 6953ac0e69eSLeon Romanovsky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 696e126ba97SEli Cohen 6970b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6980b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 69922e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 70022e939a9SBodong Wang dev->caps.embedded_cpu); 7013ac0e69eSLeon Romanovsky return mlx5_cmd_exec_in(dev, disable_hca, in); 702e126ba97SEli Cohen } 703e126ba97SEli Cohen 704f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 705f62b8bb8SAmir Vadai { 7063ac0e69eSLeon Romanovsky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 7073ac0e69eSLeon Romanovsky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 708f62b8bb8SAmir Vadai u32 sup_issi; 709c4f287c4SSaeed Mahameed int err; 710f62b8bb8SAmir Vadai 711f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 7123ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 713f62b8bb8SAmir Vadai if (err) { 714c4f287c4SSaeed Mahameed u32 syndrome; 715c4f287c4SSaeed Mahameed u8 status; 716c4f287c4SSaeed Mahameed 717c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 718f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 719f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 720f9c14e46SKamal Heib err, status, syndrome); 721f9c14e46SKamal Heib return err; 722f62b8bb8SAmir Vadai } 723f62b8bb8SAmir Vadai 724f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 725f9c14e46SKamal Heib dev->issi = 0; 726f9c14e46SKamal Heib return 0; 727f62b8bb8SAmir Vadai } 728f62b8bb8SAmir Vadai 729f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 730f62b8bb8SAmir Vadai 731f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 7323ac0e69eSLeon Romanovsky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 733f62b8bb8SAmir Vadai 734f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 735f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 7363ac0e69eSLeon Romanovsky err = mlx5_cmd_exec_in(dev, set_issi, set_in); 737f62b8bb8SAmir Vadai if (err) { 738f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 739f9c14e46SKamal Heib err); 740f62b8bb8SAmir Vadai return err; 741f62b8bb8SAmir Vadai } 742f62b8bb8SAmir Vadai 743f62b8bb8SAmir Vadai dev->issi = 1; 744f62b8bb8SAmir Vadai 745f62b8bb8SAmir Vadai return 0; 746e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 747f62b8bb8SAmir Vadai return 0; 748f62b8bb8SAmir Vadai } 749f62b8bb8SAmir Vadai 7509eb78923SOr Gerlitz return -EOPNOTSUPP; 751f62b8bb8SAmir Vadai } 752f62b8bb8SAmir Vadai 75311f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 75411f3b84dSSaeed Mahameed const struct pci_device_id *id) 755a31208b1SMajd Dibbiny { 756a31208b1SMajd Dibbiny int err = 0; 757a31208b1SMajd Dibbiny 758d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 759e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 760e126ba97SEli Cohen 761aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 762311c7c71SSaeed Mahameed 76389d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 764e126ba97SEli Cohen if (err) { 76598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 76611f3b84dSSaeed Mahameed return err; 767e126ba97SEli Cohen } 768e126ba97SEli Cohen 769e126ba97SEli Cohen err = request_bar(pdev); 770e126ba97SEli Cohen if (err) { 77198a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 772e126ba97SEli Cohen goto err_disable; 773e126ba97SEli Cohen } 774e126ba97SEli Cohen 775e126ba97SEli Cohen pci_set_master(pdev); 776e126ba97SEli Cohen 777e126ba97SEli Cohen err = set_dma_caps(pdev); 778e126ba97SEli Cohen if (err) { 77998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 780e126ba97SEli Cohen goto err_clr_master; 781e126ba97SEli Cohen } 782e126ba97SEli Cohen 783ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 784ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 785ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 786ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 787ce4eee53SMichael Guralnik 788aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 789e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 790e126ba97SEli Cohen if (!dev->iseg) { 791e126ba97SEli Cohen err = -ENOMEM; 79298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 793e126ba97SEli Cohen goto err_clr_master; 794e126ba97SEli Cohen } 795a31208b1SMajd Dibbiny 796b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 797c89da067SParav Pandit dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 798a31208b1SMajd Dibbiny return 0; 799a31208b1SMajd Dibbiny 800a31208b1SMajd Dibbiny err_clr_master: 801a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 802a31208b1SMajd Dibbiny release_bar(dev->pdev); 803a31208b1SMajd Dibbiny err_disable: 80489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 805a31208b1SMajd Dibbiny return err; 806a31208b1SMajd Dibbiny } 807a31208b1SMajd Dibbiny 808868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 809a31208b1SMajd Dibbiny { 81042ea9f1bSShay Drory /* health work might still be active, and it needs pci bar in 81142ea9f1bSShay Drory * order to know the NIC state. Therefore, drain the health WQ 81242ea9f1bSShay Drory * before removing the pci bars 81342ea9f1bSShay Drory */ 81442ea9f1bSShay Drory mlx5_drain_health_wq(dev); 815a31208b1SMajd Dibbiny iounmap(dev->iseg); 816a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 817a31208b1SMajd Dibbiny release_bar(dev->pdev); 81889d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 819a31208b1SMajd Dibbiny } 820a31208b1SMajd Dibbiny 821868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 82259211bd3SMohamad Haj Yahia { 82359211bd3SMohamad Haj Yahia int err; 82459211bd3SMohamad Haj Yahia 825868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 826868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 82798a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 828868bc06bSSaeed Mahameed dev->priv.devcom); 829fadd59fcSAviv Heller 83059211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 83159211bd3SMohamad Haj Yahia if (err) { 83298a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 833fadd59fcSAviv Heller goto err_devcom; 83459211bd3SMohamad Haj Yahia } 83559211bd3SMohamad Haj Yahia 836561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 837561aa15aSYuval Avnery if (err) { 838561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 839561aa15aSYuval Avnery goto err_devcom; 840561aa15aSYuval Avnery } 841561aa15aSYuval Avnery 842f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 84359211bd3SMohamad Haj Yahia if (err) { 84498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 845561aa15aSYuval Avnery goto err_irq_cleanup; 84659211bd3SMohamad Haj Yahia } 84759211bd3SMohamad Haj Yahia 84869c1280bSSaeed Mahameed err = mlx5_events_init(dev); 84969c1280bSSaeed Mahameed if (err) { 85098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 85169c1280bSSaeed Mahameed goto err_eq_cleanup; 85269c1280bSSaeed Mahameed } 85369c1280bSSaeed Mahameed 85438b9f903SMoshe Shemesh err = mlx5_fw_reset_init(dev); 85538b9f903SMoshe Shemesh if (err) { 85638b9f903SMoshe Shemesh mlx5_core_err(dev, "failed to initialize fw reset events\n"); 85738b9f903SMoshe Shemesh goto err_events_cleanup; 85838b9f903SMoshe Shemesh } 85938b9f903SMoshe Shemesh 8609f818c8aSGreg Kroah-Hartman mlx5_cq_debugfs_init(dev); 86159211bd3SMohamad Haj Yahia 86252ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 86352ec462eSIlan Tayari 8647c39afb3SFeras Daoud mlx5_init_clock(dev); 8657c39afb3SFeras Daoud 866358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8670ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 868358aa5ceSSaeed Mahameed 86959211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 87059211bd3SMohamad Haj Yahia if (err) { 87198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 87259211bd3SMohamad Haj Yahia goto err_tables_cleanup; 87359211bd3SMohamad Haj Yahia } 87459211bd3SMohamad Haj Yahia 875eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 876eeb66cdbSSaeed Mahameed if (err) { 87798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 878eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 879eeb66cdbSSaeed Mahameed } 880eeb66cdbSSaeed Mahameed 881c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 882c2d6e31aSMohamad Haj Yahia if (err) { 88398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 88486eec50bSBodong Wang goto err_mpfs_cleanup; 88586eec50bSBodong Wang } 88686eec50bSBodong Wang 88786eec50bSBodong Wang err = mlx5_eswitch_init(dev); 88886eec50bSBodong Wang if (err) { 88986eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 89086eec50bSBodong Wang goto err_sriov_cleanup; 891c2d6e31aSMohamad Haj Yahia } 892c2d6e31aSMohamad Haj Yahia 8939410733cSIlan Tayari err = mlx5_fpga_init(dev); 8949410733cSIlan Tayari if (err) { 89598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 89686eec50bSBodong Wang goto err_eswitch_cleanup; 8979410733cSIlan Tayari } 8989410733cSIlan Tayari 899f3196bb0SParav Pandit err = mlx5_vhca_event_init(dev); 900f3196bb0SParav Pandit if (err) { 901f3196bb0SParav Pandit mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 902f3196bb0SParav Pandit goto err_fpga_cleanup; 903f3196bb0SParav Pandit } 904f3196bb0SParav Pandit 9058f010541SParav Pandit err = mlx5_sf_hw_table_init(dev); 9068f010541SParav Pandit if (err) { 9078f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 9088f010541SParav Pandit goto err_sf_hw_table_cleanup; 9098f010541SParav Pandit } 9108f010541SParav Pandit 9118f010541SParav Pandit err = mlx5_sf_table_init(dev); 9128f010541SParav Pandit if (err) { 9138f010541SParav Pandit mlx5_core_err(dev, "Failed to init SF table %d\n", err); 9148f010541SParav Pandit goto err_sf_table_cleanup; 9158f010541SParav Pandit } 9168f010541SParav Pandit 917c9b9dcb4SAriel Levkovich dev->dm = mlx5_dm_create(dev); 918c9b9dcb4SAriel Levkovich if (IS_ERR(dev->dm)) 919c9b9dcb4SAriel Levkovich mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 920c9b9dcb4SAriel Levkovich 92124406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 92287175120SEran Ben Elisha dev->hv_vhca = mlx5_hv_vhca_create(dev); 92312206b17SAya Levin dev->rsc_dump = mlx5_rsc_dump_create(dev); 92424406953SFeras Daoud 92559211bd3SMohamad Haj Yahia return 0; 92659211bd3SMohamad Haj Yahia 9278f010541SParav Pandit err_sf_table_cleanup: 9288f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 9298f010541SParav Pandit err_sf_hw_table_cleanup: 9308f010541SParav Pandit mlx5_vhca_event_cleanup(dev); 931f3196bb0SParav Pandit err_fpga_cleanup: 932f3196bb0SParav Pandit mlx5_fpga_cleanup(dev); 933c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 934c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 93586eec50bSBodong Wang err_sriov_cleanup: 93686eec50bSBodong Wang mlx5_sriov_cleanup(dev); 937eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 938eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 939c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 940c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 94159211bd3SMohamad Haj Yahia err_tables_cleanup: 9420ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 943358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 94402d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 94538b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 94638b9f903SMoshe Shemesh err_events_cleanup: 94769c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 94859211bd3SMohamad Haj Yahia err_eq_cleanup: 949f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 950561aa15aSYuval Avnery err_irq_cleanup: 951561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 952fadd59fcSAviv Heller err_devcom: 953fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 95459211bd3SMohamad Haj Yahia 95559211bd3SMohamad Haj Yahia return err; 95659211bd3SMohamad Haj Yahia } 95759211bd3SMohamad Haj Yahia 95859211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 95959211bd3SMohamad Haj Yahia { 96012206b17SAya Levin mlx5_rsc_dump_destroy(dev); 96187175120SEran Ben Elisha mlx5_hv_vhca_destroy(dev->hv_vhca); 96224406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 963c9b9dcb4SAriel Levkovich mlx5_dm_cleanup(dev); 9648f010541SParav Pandit mlx5_sf_table_cleanup(dev); 9658f010541SParav Pandit mlx5_sf_hw_table_cleanup(dev); 966f3196bb0SParav Pandit mlx5_vhca_event_cleanup(dev); 9679410733cSIlan Tayari mlx5_fpga_cleanup(dev); 968c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 96986eec50bSBodong Wang mlx5_sriov_cleanup(dev); 970eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 97159211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9720ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 973358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9747c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 97552ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 97602d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 97738b9f903SMoshe Shemesh mlx5_fw_reset_cleanup(dev); 97869c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 979f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 980561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 981fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 98259211bd3SMohamad Haj Yahia } 98359211bd3SMohamad Haj Yahia 984e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 985a31208b1SMajd Dibbiny { 986a31208b1SMajd Dibbiny int err; 987a31208b1SMajd Dibbiny 98898a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 989e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 990e126ba97SEli Cohen 99100c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 99200c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 99300c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 99400c6bcb0STal Gilboa 9955945e1adSAmir Tzin err = mlx5_tout_init(dev); 9965945e1adSAmir Tzin if (err) { 9975945e1adSAmir Tzin mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 9985945e1adSAmir Tzin return err; 9995945e1adSAmir Tzin } 10005945e1adSAmir Tzin 10016c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 10026c780a02SEli Cohen */ 10035945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT), 10045945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); 10056c780a02SEli Cohen if (err) { 10065945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", 10075945e1adSAmir Tzin mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 10085945e1adSAmir Tzin goto err_tout_cleanup; 10096c780a02SEli Cohen } 10106c780a02SEli Cohen 1011e126ba97SEli Cohen err = mlx5_cmd_init(dev); 1012e126ba97SEli Cohen if (err) { 101398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 10145945e1adSAmir Tzin goto err_tout_cleanup; 1015e126ba97SEli Cohen } 1016e126ba97SEli Cohen 10175945e1adSAmir Tzin mlx5_tout_query_iseg(dev); 10185945e1adSAmir Tzin 10195945e1adSAmir Tzin err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); 1020e3297246SEli Cohen if (err) { 10215945e1adSAmir Tzin mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", 10225945e1adSAmir Tzin mlx5_tout_ms(dev, FW_INIT)); 102355378a23SMohamad Haj Yahia goto err_cmd_cleanup; 1024e3297246SEli Cohen } 1025e3297246SEli Cohen 1026f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1027f7936dddSEran Ben Elisha 10280b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 1029cd23b14bSEli Cohen if (err) { 103098a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 103159211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 1032cd23b14bSEli Cohen } 1033cd23b14bSEli Cohen 1034f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 1035f62b8bb8SAmir Vadai if (err) { 103698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 1037f62b8bb8SAmir Vadai goto err_disable_hca; 1038f62b8bb8SAmir Vadai } 1039f62b8bb8SAmir Vadai 1040cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 1041cd23b14bSEli Cohen if (err) { 104298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 1043cd23b14bSEli Cohen goto err_disable_hca; 1044cd23b14bSEli Cohen } 1045cd23b14bSEli Cohen 104632def412SAmir Tzin err = mlx5_tout_query_dtor(dev); 104732def412SAmir Tzin if (err) { 104832def412SAmir Tzin mlx5_core_err(dev, "failed to read dtor\n"); 104932def412SAmir Tzin goto reclaim_boot_pages; 105032def412SAmir Tzin } 105132def412SAmir Tzin 1052e126ba97SEli Cohen err = set_hca_ctrl(dev); 1053e126ba97SEli Cohen if (err) { 105498a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1055cd23b14bSEli Cohen goto reclaim_boot_pages; 1056e126ba97SEli Cohen } 1057e126ba97SEli Cohen 105837b6bb77SLeon Romanovsky err = set_hca_cap(dev); 1059e126ba97SEli Cohen if (err) { 106098a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 106146861e3eSMoni Shoua goto reclaim_boot_pages; 106246861e3eSMoni Shoua } 106346861e3eSMoni Shoua 1064cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 1065e126ba97SEli Cohen if (err) { 106698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 1067cd23b14bSEli Cohen goto reclaim_boot_pages; 1068e126ba97SEli Cohen } 1069e126ba97SEli Cohen 10708737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 1071e126ba97SEli Cohen if (err) { 107298a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 10730cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1074e126ba97SEli Cohen } 1075e126ba97SEli Cohen 1076012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1077012e50e1SHuy Nguyen 1078e126ba97SEli Cohen mlx5_start_health_poll(dev); 1079e126ba97SEli Cohen 1080bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1081bba1574cSDaniel Jurgens if (err) { 108298a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1083e161105eSSaeed Mahameed goto stop_health; 1084bba1574cSDaniel Jurgens } 1085bba1574cSDaniel Jurgens 1086e161105eSSaeed Mahameed return 0; 1087e161105eSSaeed Mahameed 1088e161105eSSaeed Mahameed stop_health: 1089e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1090e161105eSSaeed Mahameed reclaim_boot_pages: 1091e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1092e161105eSSaeed Mahameed err_disable_hca: 1093e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1094e161105eSSaeed Mahameed err_cmd_cleanup: 1095f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1096e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 10975945e1adSAmir Tzin err_tout_cleanup: 10985945e1adSAmir Tzin mlx5_tout_cleanup(dev); 1099e161105eSSaeed Mahameed 1100e161105eSSaeed Mahameed return err; 1101e161105eSSaeed Mahameed } 1102e161105eSSaeed Mahameed 1103e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1104e161105eSSaeed Mahameed { 1105e161105eSSaeed Mahameed int err; 1106e161105eSSaeed Mahameed 1107e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1108e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1109259bbc57SMaor Gottlieb if (err) { 111098a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1111e161105eSSaeed Mahameed return err; 1112e126ba97SEli Cohen } 1113e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1114e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1115f7936dddSEran Ben Elisha mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1116e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 11175945e1adSAmir Tzin mlx5_tout_cleanup(dev); 1118e161105eSSaeed Mahameed 1119e161105eSSaeed Mahameed return 0; 1120259bbc57SMaor Gottlieb } 1121e126ba97SEli Cohen 1122a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1123e161105eSSaeed Mahameed { 1124e161105eSSaeed Mahameed int err; 1125e161105eSSaeed Mahameed 112601187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 112772f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 112898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 112972f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1130a80d1b68SSaeed Mahameed return err; 1131e126ba97SEli Cohen } 1132e126ba97SEli Cohen 113369c1280bSSaeed Mahameed mlx5_events_start(dev); 11340cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 11350cf53c12SSaeed Mahameed 1136e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1137e1706e62SYuval Avnery if (err) { 1138e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1139e1706e62SYuval Avnery goto err_irq_table; 1140e1706e62SYuval Avnery } 1141e1706e62SYuval Avnery 1142c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1143e126ba97SEli Cohen if (err) { 114498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1145c8e21b3bSSaeed Mahameed goto err_eq_table; 1146e126ba97SEli Cohen } 1147e126ba97SEli Cohen 114824406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 114924406953SFeras Daoud if (err) { 1150f62eb932SAya Levin mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1151f62eb932SAya Levin mlx5_fw_tracer_destroy(dev->tracer); 1152f62eb932SAya Levin dev->tracer = NULL; 115324406953SFeras Daoud } 115424406953SFeras Daoud 115538b9f903SMoshe Shemesh mlx5_fw_reset_events_start(dev); 115687175120SEran Ben Elisha mlx5_hv_vhca_init(dev->hv_vhca); 115787175120SEran Ben Elisha 115812206b17SAya Levin err = mlx5_rsc_dump_init(dev); 115912206b17SAya Levin if (err) { 1160f62eb932SAya Levin mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1161f62eb932SAya Levin mlx5_rsc_dump_destroy(dev); 1162f62eb932SAya Levin dev->rsc_dump = NULL; 116312206b17SAya Levin } 116412206b17SAya Levin 116504e87170SMatan Barak err = mlx5_fpga_device_start(dev); 116604e87170SMatan Barak if (err) { 116798a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 116804e87170SMatan Barak goto err_fpga_start; 116904e87170SMatan Barak } 117004e87170SMatan Barak 11719a6ad1adSRaed Salem mlx5_accel_ipsec_init(dev); 117204e87170SMatan Barak 11731ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 11741ae17322SIlya Lesokhin if (err) { 117598a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 11761ae17322SIlya Lesokhin goto err_tls_start; 11771ae17322SIlya Lesokhin } 11781ae17322SIlya Lesokhin 117986d722adSMaor Gottlieb err = mlx5_init_fs(dev); 118086d722adSMaor Gottlieb if (err) { 118198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 118286d722adSMaor Gottlieb goto err_fs; 118386d722adSMaor Gottlieb } 11841466cc5bSYevgeny Petrilin 1185c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1186c85023e1SHuy Nguyen if (err) { 118798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 118894a4b841SLeon Romanovsky goto err_set_hca; 1189c85023e1SHuy Nguyen } 1190c85023e1SHuy Nguyen 1191f3196bb0SParav Pandit mlx5_vhca_event_start(dev); 1192f3196bb0SParav Pandit 11936a327321SParav Pandit err = mlx5_sf_hw_table_create(dev); 11946a327321SParav Pandit if (err) { 11956a327321SParav Pandit mlx5_core_err(dev, "sf table create failed %d\n", err); 11966a327321SParav Pandit goto err_vhca; 11976a327321SParav Pandit } 11986a327321SParav Pandit 119922e939a9SBodong Wang err = mlx5_ec_init(dev); 120022e939a9SBodong Wang if (err) { 120198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 120222e939a9SBodong Wang goto err_ec; 120322e939a9SBodong Wang } 120422e939a9SBodong Wang 1205cac1eb2cSMark Bloch mlx5_lag_add_mdev(dev); 12065bef709dSParav Pandit err = mlx5_sriov_attach(dev); 12075bef709dSParav Pandit if (err) { 12085bef709dSParav Pandit mlx5_core_err(dev, "sriov init failed %d\n", err); 12095bef709dSParav Pandit goto err_sriov; 12105bef709dSParav Pandit } 12115bef709dSParav Pandit 121290d010b8SParav Pandit mlx5_sf_dev_table_create(dev); 121390d010b8SParav Pandit 1214a80d1b68SSaeed Mahameed return 0; 1215a80d1b68SSaeed Mahameed 1216a80d1b68SSaeed Mahameed err_sriov: 1217cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 12185bef709dSParav Pandit mlx5_ec_cleanup(dev); 12195bef709dSParav Pandit err_ec: 12206a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 12216a327321SParav Pandit err_vhca: 1222f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 122394a4b841SLeon Romanovsky err_set_hca: 1224a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1225a80d1b68SSaeed Mahameed err_fs: 1226a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1227a80d1b68SSaeed Mahameed err_tls_start: 1228a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1229a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1230a80d1b68SSaeed Mahameed err_fpga_start: 123112206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 123287175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 123338b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1234a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1235a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1236a80d1b68SSaeed Mahameed err_eq_table: 1237e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1238e1706e62SYuval Avnery err_irq_table: 1239a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1240a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1241a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1242a80d1b68SSaeed Mahameed return err; 1243a80d1b68SSaeed Mahameed } 1244a80d1b68SSaeed Mahameed 1245a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1246a80d1b68SSaeed Mahameed { 124790d010b8SParav Pandit mlx5_sf_dev_table_destroy(dev); 1248a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1249cac1eb2cSMark Bloch mlx5_lag_remove_mdev(dev); 12505bef709dSParav Pandit mlx5_ec_cleanup(dev); 12516a327321SParav Pandit mlx5_sf_hw_table_destroy(dev); 1252f3196bb0SParav Pandit mlx5_vhca_event_stop(dev); 1253a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1254a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1255a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1256a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 125712206b17SAya Levin mlx5_rsc_dump_cleanup(dev); 125887175120SEran Ben Elisha mlx5_hv_vhca_cleanup(dev->hv_vhca); 125938b9f903SMoshe Shemesh mlx5_fw_reset_events_stop(dev); 1260a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1261a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1262e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1263a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1264a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1265a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1266a80d1b68SSaeed Mahameed } 1267a80d1b68SSaeed Mahameed 12686dea2f7eSLeon Romanovsky int mlx5_init_one(struct mlx5_core_dev *dev) 1269a80d1b68SSaeed Mahameed { 1270a80d1b68SSaeed Mahameed int err = 0; 1271a80d1b68SSaeed Mahameed 1272a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1273a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1274a80d1b68SSaeed Mahameed 12756dea2f7eSLeon Romanovsky err = mlx5_function_setup(dev, true); 1276a80d1b68SSaeed Mahameed if (err) 12774f7400d5SShay Drory goto err_function; 1278a80d1b68SSaeed Mahameed 1279a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1280a80d1b68SSaeed Mahameed if (err) { 128198a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1282a80d1b68SSaeed Mahameed goto function_teardown; 1283a80d1b68SSaeed Mahameed } 1284a80d1b68SSaeed Mahameed 1285a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1286a80d1b68SSaeed Mahameed if (err) 1287a80d1b68SSaeed Mahameed goto err_load; 1288a80d1b68SSaeed Mahameed 128998f91c45SParav Pandit set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 129098f91c45SParav Pandit 1291919d13a7SLeon Romanovsky err = mlx5_devlink_register(priv_to_devlink(dev)); 1292a6f3b623SMichael Guralnik if (err) 1293a6f3b623SMichael Guralnik goto err_devlink_reg; 1294a925b5e3SLeon Romanovsky 1295a925b5e3SLeon Romanovsky err = mlx5_register_device(dev); 1296a925b5e3SLeon Romanovsky if (err) 1297a925b5e3SLeon Romanovsky goto err_register; 1298a925b5e3SLeon Romanovsky 12994162f58bSParav Pandit mutex_unlock(&dev->intf_state_mutex); 13004162f58bSParav Pandit return 0; 1301e126ba97SEli Cohen 1302a925b5e3SLeon Romanovsky err_register: 1303a925b5e3SLeon Romanovsky mlx5_devlink_unregister(priv_to_devlink(dev)); 1304a6f3b623SMichael Guralnik err_devlink_reg: 130598f91c45SParav Pandit clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1306a80d1b68SSaeed Mahameed mlx5_unload(dev); 1307a80d1b68SSaeed Mahameed err_load: 130859211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1309e161105eSSaeed Mahameed function_teardown: 13106dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 13114f7400d5SShay Drory err_function: 131289d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 131389d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1314e126ba97SEli Cohen return err; 1315e126ba97SEli Cohen } 1316e126ba97SEli Cohen 13176dea2f7eSLeon Romanovsky void mlx5_uninit_one(struct mlx5_core_dev *dev) 1318e126ba97SEli Cohen { 131989d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 132098f91c45SParav Pandit 132198f91c45SParav Pandit mlx5_unregister_device(dev); 132298f91c45SParav Pandit mlx5_devlink_unregister(priv_to_devlink(dev)); 132398f91c45SParav Pandit 1324b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 132598a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 132689d44f0aSMajd Dibbiny __func__); 132759211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 132889d44f0aSMajd Dibbiny goto out; 132989d44f0aSMajd Dibbiny } 13306b6adee3SMohamad Haj Yahia 13319ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1332a80d1b68SSaeed Mahameed mlx5_unload(dev); 133359211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 13346dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, true); 13356dea2f7eSLeon Romanovsky out: 13366dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13376dea2f7eSLeon Romanovsky } 13380cf53c12SSaeed Mahameed 13396dea2f7eSLeon Romanovsky int mlx5_load_one(struct mlx5_core_dev *dev) 13406dea2f7eSLeon Romanovsky { 13416dea2f7eSLeon Romanovsky int err = 0; 13426dea2f7eSLeon Romanovsky 13436dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 13446dea2f7eSLeon Romanovsky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 13456dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "interface is up, NOP\n"); 13466dea2f7eSLeon Romanovsky goto out; 13476dea2f7eSLeon Romanovsky } 13486dea2f7eSLeon Romanovsky /* remove any previous indication of internal error */ 13496dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_UP; 13506dea2f7eSLeon Romanovsky 13516dea2f7eSLeon Romanovsky err = mlx5_function_setup(dev, false); 13526dea2f7eSLeon Romanovsky if (err) 13536dea2f7eSLeon Romanovsky goto err_function; 13546dea2f7eSLeon Romanovsky 13556dea2f7eSLeon Romanovsky err = mlx5_load(dev); 13566dea2f7eSLeon Romanovsky if (err) 13576dea2f7eSLeon Romanovsky goto err_load; 13586dea2f7eSLeon Romanovsky 13596dea2f7eSLeon Romanovsky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13606dea2f7eSLeon Romanovsky 13616dea2f7eSLeon Romanovsky err = mlx5_attach_device(dev); 13626dea2f7eSLeon Romanovsky if (err) 13636dea2f7eSLeon Romanovsky goto err_attach; 13646dea2f7eSLeon Romanovsky 13656dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13666dea2f7eSLeon Romanovsky return 0; 13676dea2f7eSLeon Romanovsky 13686dea2f7eSLeon Romanovsky err_attach: 13696dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13706dea2f7eSLeon Romanovsky mlx5_unload(dev); 13716dea2f7eSLeon Romanovsky err_load: 13726dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 13736dea2f7eSLeon Romanovsky err_function: 13746dea2f7eSLeon Romanovsky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 13756dea2f7eSLeon Romanovsky out: 13766dea2f7eSLeon Romanovsky mutex_unlock(&dev->intf_state_mutex); 13776dea2f7eSLeon Romanovsky return err; 13786dea2f7eSLeon Romanovsky } 13796dea2f7eSLeon Romanovsky 13806dea2f7eSLeon Romanovsky void mlx5_unload_one(struct mlx5_core_dev *dev) 13816dea2f7eSLeon Romanovsky { 13826dea2f7eSLeon Romanovsky mutex_lock(&dev->intf_state_mutex); 13836dea2f7eSLeon Romanovsky 13846dea2f7eSLeon Romanovsky mlx5_detach_device(dev); 13856dea2f7eSLeon Romanovsky 13866dea2f7eSLeon Romanovsky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 13876dea2f7eSLeon Romanovsky mlx5_core_warn(dev, "%s: interface is down, NOP\n", 13886dea2f7eSLeon Romanovsky __func__); 13896dea2f7eSLeon Romanovsky goto out; 13906dea2f7eSLeon Romanovsky } 13916dea2f7eSLeon Romanovsky 13926dea2f7eSLeon Romanovsky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 13936dea2f7eSLeon Romanovsky mlx5_unload(dev); 13946dea2f7eSLeon Romanovsky mlx5_function_teardown(dev, false); 1395ac6ea6e8SEli Cohen out: 139689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 13979603b61dSJack Morgenstein } 139864613d94SSaeed Mahameed 139948f02eefSParav Pandit static const int types[] = { 140048f02eefSParav Pandit MLX5_CAP_GENERAL, 140148f02eefSParav Pandit MLX5_CAP_GENERAL_2, 140248f02eefSParav Pandit MLX5_CAP_ETHERNET_OFFLOADS, 140348f02eefSParav Pandit MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 140448f02eefSParav Pandit MLX5_CAP_ODP, 140548f02eefSParav Pandit MLX5_CAP_ATOMIC, 140648f02eefSParav Pandit MLX5_CAP_ROCE, 140748f02eefSParav Pandit MLX5_CAP_IPOIB_OFFLOADS, 140848f02eefSParav Pandit MLX5_CAP_FLOW_TABLE, 140948f02eefSParav Pandit MLX5_CAP_ESWITCH_FLOW_TABLE, 141048f02eefSParav Pandit MLX5_CAP_ESWITCH, 141148f02eefSParav Pandit MLX5_CAP_VECTOR_CALC, 141248f02eefSParav Pandit MLX5_CAP_QOS, 141348f02eefSParav Pandit MLX5_CAP_DEBUG, 141448f02eefSParav Pandit MLX5_CAP_DEV_MEM, 141548f02eefSParav Pandit MLX5_CAP_DEV_EVENT, 141648f02eefSParav Pandit MLX5_CAP_TLS, 141748f02eefSParav Pandit MLX5_CAP_VDPA_EMULATION, 141848f02eefSParav Pandit MLX5_CAP_IPSEC, 1419*425a563aSMaor Gottlieb MLX5_CAP_PORT_SELECTION, 142048f02eefSParav Pandit }; 142148f02eefSParav Pandit 142248f02eefSParav Pandit static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 142348f02eefSParav Pandit { 142448f02eefSParav Pandit int type; 142548f02eefSParav Pandit int i; 142648f02eefSParav Pandit 142748f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 142848f02eefSParav Pandit type = types[i]; 142948f02eefSParav Pandit kfree(dev->caps.hca[type]); 143048f02eefSParav Pandit } 143148f02eefSParav Pandit } 143248f02eefSParav Pandit 143348f02eefSParav Pandit static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 143448f02eefSParav Pandit { 143548f02eefSParav Pandit struct mlx5_hca_cap *cap; 143648f02eefSParav Pandit int type; 143748f02eefSParav Pandit int i; 143848f02eefSParav Pandit 143948f02eefSParav Pandit for (i = 0; i < ARRAY_SIZE(types); i++) { 144048f02eefSParav Pandit cap = kzalloc(sizeof(*cap), GFP_KERNEL); 144148f02eefSParav Pandit if (!cap) 144248f02eefSParav Pandit goto err; 144348f02eefSParav Pandit type = types[i]; 144448f02eefSParav Pandit dev->caps.hca[type] = cap; 144548f02eefSParav Pandit } 144648f02eefSParav Pandit 144748f02eefSParav Pandit return 0; 144848f02eefSParav Pandit 144948f02eefSParav Pandit err: 145048f02eefSParav Pandit mlx5_hca_caps_free(dev); 145148f02eefSParav Pandit return -ENOMEM; 145248f02eefSParav Pandit } 145348f02eefSParav Pandit 14541958fc2fSParav Pandit int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 14559603b61dSJack Morgenstein { 145611f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 14579603b61dSJack Morgenstein int err; 14589603b61dSJack Morgenstein 14593410fbcdSMaor Gottlieb memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1460364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1461364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 146289d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1463d9aaed83SArtemy Kovalyov 146401187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 146501187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 146601187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 146701187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 146801187175SEli Cohen 146911f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 147011f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 147111f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 147211f3b84dSSaeed Mahameed 147344f66ac9SParav Pandit priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 147427b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 147527b942fbSParav Pandit mlx5_debugfs_root); 14763d347b1bSAya Levin INIT_LIST_HEAD(&priv->traps); 14773d347b1bSAya Levin 1478ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 147952c368dcSSaeed Mahameed if (err) 148052c368dcSSaeed Mahameed goto err_health_init; 1481ac6ea6e8SEli Cohen 14820cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 14830cf53c12SSaeed Mahameed if (err) 14840cf53c12SSaeed Mahameed goto err_pagealloc_init; 148559211bd3SMohamad Haj Yahia 1486a925b5e3SLeon Romanovsky err = mlx5_adev_init(dev); 1487a925b5e3SLeon Romanovsky if (err) 1488a925b5e3SLeon Romanovsky goto err_adev_init; 1489a925b5e3SLeon Romanovsky 149048f02eefSParav Pandit err = mlx5_hca_caps_alloc(dev); 149148f02eefSParav Pandit if (err) 149248f02eefSParav Pandit goto err_hca_caps; 149348f02eefSParav Pandit 149411f3b84dSSaeed Mahameed return 0; 149552c368dcSSaeed Mahameed 149648f02eefSParav Pandit err_hca_caps: 149748f02eefSParav Pandit mlx5_adev_cleanup(dev); 1498a925b5e3SLeon Romanovsky err_adev_init: 1499a925b5e3SLeon Romanovsky mlx5_pagealloc_cleanup(dev); 150052c368dcSSaeed Mahameed err_pagealloc_init: 150152c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 150252c368dcSSaeed Mahameed err_health_init: 150352c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 1504810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1505810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1506810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1507810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1508810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 150952c368dcSSaeed Mahameed return err; 151011f3b84dSSaeed Mahameed } 151111f3b84dSSaeed Mahameed 15121958fc2fSParav Pandit void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 151311f3b84dSSaeed Mahameed { 1514810cbb25SParav Pandit struct mlx5_priv *priv = &dev->priv; 1515810cbb25SParav Pandit 151648f02eefSParav Pandit mlx5_hca_caps_free(dev); 1517a925b5e3SLeon Romanovsky mlx5_adev_cleanup(dev); 151852c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 151952c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 152011f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 1521810cbb25SParav Pandit mutex_destroy(&priv->pgdir_mutex); 1522810cbb25SParav Pandit mutex_destroy(&priv->alloc_mutex); 1523810cbb25SParav Pandit mutex_destroy(&priv->bfregs.wc_head.lock); 1524810cbb25SParav Pandit mutex_destroy(&priv->bfregs.reg_head.lock); 1525810cbb25SParav Pandit mutex_destroy(&dev->intf_state_mutex); 152611f3b84dSSaeed Mahameed } 152711f3b84dSSaeed Mahameed 15286dea2f7eSLeon Romanovsky static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 152911f3b84dSSaeed Mahameed { 153011f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 153111f3b84dSSaeed Mahameed struct devlink *devlink; 153211f3b84dSSaeed Mahameed int err; 153311f3b84dSSaeed Mahameed 1534919d13a7SLeon Romanovsky devlink = mlx5_devlink_alloc(&pdev->dev); 153511f3b84dSSaeed Mahameed if (!devlink) { 15361f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 153711f3b84dSSaeed Mahameed return -ENOMEM; 153811f3b84dSSaeed Mahameed } 153911f3b84dSSaeed Mahameed 154011f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 154127b942fbSParav Pandit dev->device = &pdev->dev; 154227b942fbSParav Pandit dev->pdev = pdev; 154311f3b84dSSaeed Mahameed 1544386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1545386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1546386e75afSHuy Nguyen 1547a925b5e3SLeon Romanovsky dev->priv.adev_idx = mlx5_adev_idx_alloc(); 15484d8be211SLeon Romanovsky if (dev->priv.adev_idx < 0) { 15494d8be211SLeon Romanovsky err = dev->priv.adev_idx; 15504d8be211SLeon Romanovsky goto adev_init_err; 15514d8be211SLeon Romanovsky } 1552a925b5e3SLeon Romanovsky 155327b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 155411f3b84dSSaeed Mahameed if (err) 155511f3b84dSSaeed Mahameed goto mdev_init_err; 155611f3b84dSSaeed Mahameed 155711f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 15589603b61dSJack Morgenstein if (err) { 155998a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 156098a8e6fcSHuy Nguyen err); 156111f3b84dSSaeed Mahameed goto pci_init_err; 15629603b61dSJack Morgenstein } 15639603b61dSJack Morgenstein 15646dea2f7eSLeon Romanovsky err = mlx5_init_one(dev); 15659603b61dSJack Morgenstein if (err) { 15666dea2f7eSLeon Romanovsky mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 156798a8e6fcSHuy Nguyen err); 15686dea2f7eSLeon Romanovsky goto err_init_one; 15699603b61dSJack Morgenstein } 157059211bd3SMohamad Haj Yahia 15718b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 15728b9d8baaSAlex Vesker if (err) 15738b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 15748b9d8baaSAlex Vesker 15755d47f6c8SDaniel Jurgens pci_save_state(pdev); 157664ea2d0eSLeon Romanovsky devlink_register(devlink); 15779603b61dSJack Morgenstein return 0; 15789603b61dSJack Morgenstein 15796dea2f7eSLeon Romanovsky err_init_one: 1580868bc06bSSaeed Mahameed mlx5_pci_close(dev); 158111f3b84dSSaeed Mahameed pci_init_err: 158211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 158311f3b84dSSaeed Mahameed mdev_init_err: 1584a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 15854d8be211SLeon Romanovsky adev_init_err: 15861f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1587a31208b1SMajd Dibbiny 15889603b61dSJack Morgenstein return err; 15899603b61dSJack Morgenstein } 1590a31208b1SMajd Dibbiny 15919603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 15929603b61dSJack Morgenstein { 15939603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1594feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 15959603b61dSJack Morgenstein 159664ea2d0eSLeon Romanovsky devlink_unregister(devlink); 15978b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 159841798df9SParav Pandit mlx5_drain_health_wq(dev); 15996dea2f7eSLeon Romanovsky mlx5_uninit_one(dev); 1600868bc06bSSaeed Mahameed mlx5_pci_close(dev); 160111f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 1602a925b5e3SLeon Romanovsky mlx5_adev_idx_free(dev->priv.adev_idx); 16031f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 16049603b61dSJack Morgenstein } 16059603b61dSJack Morgenstein 160689d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 160789d44f0aSMajd Dibbiny pci_channel_state_t state) 160889d44f0aSMajd Dibbiny { 160989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 161089d44f0aSMajd Dibbiny 161198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 161204c0c1abSMohamad Haj Yahia 16138812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 16143e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 16156dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 16165e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 161789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 161805ac2c0bSMohamad Haj Yahia 161989d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 162089d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 162189d44f0aSMajd Dibbiny } 162289d44f0aSMajd Dibbiny 1623d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1624d57847dcSDaniel Jurgens * for the health counter to start counting. 162589d44f0aSMajd Dibbiny */ 1626d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 162789d44f0aSMajd Dibbiny { 162889d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 162989d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 163089d44f0aSMajd Dibbiny const int niter = 100; 1631d57847dcSDaniel Jurgens u32 last_count = 0; 163289d44f0aSMajd Dibbiny u32 count; 163389d44f0aSMajd Dibbiny int i; 163489d44f0aSMajd Dibbiny 163589d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 163689d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 163789d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1638d57847dcSDaniel Jurgens if (last_count && last_count != count) { 163998a8e6fcSHuy Nguyen mlx5_core_info(dev, 164098a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 164198a8e6fcSHuy Nguyen count, i); 1642d57847dcSDaniel Jurgens return 0; 1643d57847dcSDaniel Jurgens } 1644d57847dcSDaniel Jurgens last_count = count; 164589d44f0aSMajd Dibbiny } 164689d44f0aSMajd Dibbiny msleep(50); 164789d44f0aSMajd Dibbiny } 164889d44f0aSMajd Dibbiny 1649d57847dcSDaniel Jurgens return -ETIMEDOUT; 165089d44f0aSMajd Dibbiny } 165189d44f0aSMajd Dibbiny 16521061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 16531061c90fSMohamad Haj Yahia { 16541061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 16551061c90fSMohamad Haj Yahia int err; 16561061c90fSMohamad Haj Yahia 165798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 16581061c90fSMohamad Haj Yahia 16591061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 16601061c90fSMohamad Haj Yahia if (err) { 166198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 166298a8e6fcSHuy Nguyen __func__, err); 16631061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 16641061c90fSMohamad Haj Yahia } 16651061c90fSMohamad Haj Yahia 16661061c90fSMohamad Haj Yahia pci_set_master(pdev); 16671061c90fSMohamad Haj Yahia pci_restore_state(pdev); 16685d47f6c8SDaniel Jurgens pci_save_state(pdev); 16691061c90fSMohamad Haj Yahia 16701061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 167198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 16721061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 16731061c90fSMohamad Haj Yahia } 16741061c90fSMohamad Haj Yahia 16751061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 16761061c90fSMohamad Haj Yahia } 16771061c90fSMohamad Haj Yahia 167889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 167989d44f0aSMajd Dibbiny { 168089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 168189d44f0aSMajd Dibbiny int err; 168289d44f0aSMajd Dibbiny 168398a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 168489d44f0aSMajd Dibbiny 16856dea2f7eSLeon Romanovsky err = mlx5_load_one(dev); 168689d44f0aSMajd Dibbiny if (err) 168798a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 168898a8e6fcSHuy Nguyen __func__, err); 168989d44f0aSMajd Dibbiny else 169098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 169189d44f0aSMajd Dibbiny } 169289d44f0aSMajd Dibbiny 169389d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 169489d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 169589d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 169689d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 169789d44f0aSMajd Dibbiny }; 169889d44f0aSMajd Dibbiny 16998812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 17008812c24dSMajd Dibbiny { 1701fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1702fcd29ad1SFeras Daoud int ret = 1; 17038812c24dSMajd Dibbiny 1704fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1705fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1706fcd29ad1SFeras Daoud 1707fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1708fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1709fcd29ad1SFeras Daoud 1710fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 17118812c24dSMajd Dibbiny return -EOPNOTSUPP; 17128812c24dSMajd Dibbiny 17138812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 17148812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 17158812c24dSMajd Dibbiny return -EAGAIN; 17168812c24dSMajd Dibbiny } 17178812c24dSMajd Dibbiny 1718d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1719d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1720d2aa060dSHuy Nguyen */ 1721d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 172276d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1723d2aa060dSHuy Nguyen 1724fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1725fcd29ad1SFeras Daoud if (!ret) 1726fcd29ad1SFeras Daoud goto succeed; 1727fcd29ad1SFeras Daoud 17288812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1729fcd29ad1SFeras Daoud if (!ret) 1730fcd29ad1SFeras Daoud goto succeed; 1731fcd29ad1SFeras Daoud 17328812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1733d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 17348812c24dSMajd Dibbiny return ret; 17358812c24dSMajd Dibbiny 1736fcd29ad1SFeras Daoud succeed: 17378812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 17388812c24dSMajd Dibbiny 17391ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 17401ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 17411ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 17421ef903bfSDaniel Jurgens * contexts. 17431ef903bfSDaniel Jurgens */ 17441ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 17451ef903bfSDaniel Jurgens 17468812c24dSMajd Dibbiny return 0; 17478812c24dSMajd Dibbiny } 17488812c24dSMajd Dibbiny 17495fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 17505fc7197dSMajd Dibbiny { 17515fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 17528812c24dSMajd Dibbiny int err; 17535fc7197dSMajd Dibbiny 175498a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 17558812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 17568812c24dSMajd Dibbiny if (err) 17576dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 17585fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 17595fc7197dSMajd Dibbiny } 17605fc7197dSMajd Dibbiny 17618fc3e29bSMark Bloch static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 17628fc3e29bSMark Bloch { 17638fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 17648fc3e29bSMark Bloch 17656dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 17668fc3e29bSMark Bloch 17678fc3e29bSMark Bloch return 0; 17688fc3e29bSMark Bloch } 17698fc3e29bSMark Bloch 17708fc3e29bSMark Bloch static int mlx5_resume(struct pci_dev *pdev) 17718fc3e29bSMark Bloch { 17728fc3e29bSMark Bloch struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 17738fc3e29bSMark Bloch 17746dea2f7eSLeon Romanovsky return mlx5_load_one(dev); 17758fc3e29bSMark Bloch } 17768fc3e29bSMark Bloch 17779603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1778bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1779fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1780bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1781fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1782bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1783fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 17847092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 178564dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1786d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1787d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1788d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1789d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 179085327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 179185327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1792b7eca940SShani Shapp { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1793505a7f54SMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 17942e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 17952e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1796d19a79eeSBodong Wang { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1797dd8595eaSMeir Lichtinger { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 17989603b61dSJack Morgenstein { 0, } 17999603b61dSJack Morgenstein }; 18009603b61dSJack Morgenstein 18019603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 18029603b61dSJack Morgenstein 180304c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 180404c0c1abSMohamad Haj Yahia { 1805b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 18066dea2f7eSLeon Romanovsky mlx5_unload_one(dev); 180704c0c1abSMohamad Haj Yahia } 180804c0c1abSMohamad Haj Yahia 1809fe06992bSLeon Romanovsky int mlx5_recover_device(struct mlx5_core_dev *dev) 181004c0c1abSMohamad Haj Yahia { 1811fe06992bSLeon Romanovsky int ret = -EIO; 1812fe06992bSLeon Romanovsky 181304c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 181404c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1815fe06992bSLeon Romanovsky ret = mlx5_load_one(dev); 1816fe06992bSLeon Romanovsky return ret; 181704c0c1abSMohamad Haj Yahia } 181804c0c1abSMohamad Haj Yahia 18199603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 182017a7612bSLeon Romanovsky .name = KBUILD_MODNAME, 18219603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 18226dea2f7eSLeon Romanovsky .probe = probe_one, 182389d44f0aSMajd Dibbiny .remove = remove_one, 18248fc3e29bSMark Bloch .suspend = mlx5_suspend, 18258fc3e29bSMark Bloch .resume = mlx5_resume, 18265fc7197dSMajd Dibbiny .shutdown = shutdown, 1827fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1828fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 1829e71b75f7SLeon Romanovsky .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 1830e71b75f7SLeon Romanovsky .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 18319603b61dSJack Morgenstein }; 1832e126ba97SEli Cohen 1833f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1834f663ad98SKamal Heib { 1835f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1836f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1837f663ad98SKamal Heib prof_sel, 1838f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1839f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1840f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1841f663ad98SKamal Heib } 1842f663ad98SKamal Heib } 1843f663ad98SKamal Heib 1844e126ba97SEli Cohen static int __init init(void) 1845e126ba97SEli Cohen { 1846e126ba97SEli Cohen int err; 1847e126ba97SEli Cohen 184817a7612bSLeon Romanovsky WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 184917a7612bSLeon Romanovsky "mlx5_core name not in sync with kernel module name"); 185017a7612bSLeon Romanovsky 18518737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 18528737f818SDaniel Jurgens 1853f663ad98SKamal Heib mlx5_core_verify_params(); 18549a6ad1adSRaed Salem mlx5_fpga_ipsec_build_fs_cmds(); 1855e126ba97SEli Cohen mlx5_register_debugfs(); 1856e126ba97SEli Cohen 18579603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 18589603b61dSJack Morgenstein if (err) 1859ac6ea6e8SEli Cohen goto err_debug; 18609603b61dSJack Morgenstein 18611958fc2fSParav Pandit err = mlx5_sf_driver_register(); 18621958fc2fSParav Pandit if (err) 18631958fc2fSParav Pandit goto err_sf; 18641958fc2fSParav Pandit 1865912cebf4SLeon Romanovsky err = mlx5e_init(); 1866c633e799SLeon Romanovsky if (err) 1867c633e799SLeon Romanovsky goto err_en; 1868f62b8bb8SAmir Vadai 1869e126ba97SEli Cohen return 0; 1870e126ba97SEli Cohen 1871c633e799SLeon Romanovsky err_en: 1872c633e799SLeon Romanovsky mlx5_sf_driver_unregister(); 18731958fc2fSParav Pandit err_sf: 18741958fc2fSParav Pandit pci_unregister_driver(&mlx5_core_driver); 1875e126ba97SEli Cohen err_debug: 1876e126ba97SEli Cohen mlx5_unregister_debugfs(); 1877e126ba97SEli Cohen return err; 1878e126ba97SEli Cohen } 1879e126ba97SEli Cohen 1880e126ba97SEli Cohen static void __exit cleanup(void) 1881e126ba97SEli Cohen { 1882f62b8bb8SAmir Vadai mlx5e_cleanup(); 18831958fc2fSParav Pandit mlx5_sf_driver_unregister(); 18849603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1885e126ba97SEli Cohen mlx5_unregister_debugfs(); 1886e126ba97SEli Cohen } 1887e126ba97SEli Cohen 1888e126ba97SEli Cohen module_init(init); 1889e126ba97SEli Cohen module_exit(cleanup); 1890