1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6052ec462eSIlan Tayari #include "lib/mlx5.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 6205564d0aSAviad Yehezkel #include "fpga/ipsec.h" 63bebb23e6SIlan Tayari #include "accel/ipsec.h" 641ae17322SIlya Lesokhin #include "accel/tls.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 72e126ba97SEli Cohen 73e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 74048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 75e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 76e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 77e126ba97SEli Cohen 78f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 79f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 80e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 81e126ba97SEli Cohen 829603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 83f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 84f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 859603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 869603b61dSJack Morgenstein 878737f818SDaniel Jurgens static u32 sw_owner_id[4]; 888737f818SDaniel Jurgens 89f91e6d89SEran Ben Elisha enum { 90f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 91f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 92f91e6d89SEran Ben Elisha }; 93f91e6d89SEran Ben Elisha 949603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 959603b61dSJack Morgenstein [0] = { 969603b61dSJack Morgenstein .mask = 0, 979603b61dSJack Morgenstein }, 989603b61dSJack Morgenstein [1] = { 999603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1009603b61dSJack Morgenstein .log_max_qp = 12, 1019603b61dSJack Morgenstein }, 1029603b61dSJack Morgenstein [2] = { 1039603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1049603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1055f40b4edSMaor Gottlieb .log_max_qp = 18, 1069603b61dSJack Morgenstein .mr_cache[0] = { 1079603b61dSJack Morgenstein .size = 500, 1089603b61dSJack Morgenstein .limit = 250 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein .mr_cache[1] = { 1119603b61dSJack Morgenstein .size = 500, 1129603b61dSJack Morgenstein .limit = 250 1139603b61dSJack Morgenstein }, 1149603b61dSJack Morgenstein .mr_cache[2] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[3] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[4] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[5] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[6] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[7] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[8] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[9] = { 1439603b61dSJack Morgenstein .size = 500, 1449603b61dSJack Morgenstein .limit = 250 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[10] = { 1479603b61dSJack Morgenstein .size = 500, 1489603b61dSJack Morgenstein .limit = 250 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[11] = { 1519603b61dSJack Morgenstein .size = 500, 1529603b61dSJack Morgenstein .limit = 250 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[12] = { 1559603b61dSJack Morgenstein .size = 64, 1569603b61dSJack Morgenstein .limit = 32 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein .mr_cache[13] = { 1599603b61dSJack Morgenstein .size = 32, 1609603b61dSJack Morgenstein .limit = 16 1619603b61dSJack Morgenstein }, 1629603b61dSJack Morgenstein .mr_cache[14] = { 1639603b61dSJack Morgenstein .size = 16, 1649603b61dSJack Morgenstein .limit = 8 1659603b61dSJack Morgenstein }, 1669603b61dSJack Morgenstein .mr_cache[15] = { 1679603b61dSJack Morgenstein .size = 8, 1689603b61dSJack Morgenstein .limit = 4 1699603b61dSJack Morgenstein }, 1709603b61dSJack Morgenstein }, 1719603b61dSJack Morgenstein }; 172e126ba97SEli Cohen 173e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 174e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 1756c780a02SEli Cohen #define FW_PRE_INIT_TIMEOUT_MILI 10000 176e3297246SEli Cohen 177e3297246SEli Cohen static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 178e3297246SEli Cohen { 179e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 180e3297246SEli Cohen int err = 0; 181e3297246SEli Cohen 182e3297246SEli Cohen while (fw_initializing(dev)) { 183e3297246SEli Cohen if (time_after(jiffies, end)) { 184e3297246SEli Cohen err = -EBUSY; 185e3297246SEli Cohen break; 186e3297246SEli Cohen } 187e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 188e3297246SEli Cohen } 189e3297246SEli Cohen 190e3297246SEli Cohen return err; 191e3297246SEli Cohen } 192e3297246SEli Cohen 193012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 194012e50e1SHuy Nguyen { 195012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 196012e50e1SHuy Nguyen driver_version); 197012e50e1SHuy Nguyen u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 198012e50e1SHuy Nguyen u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 199012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 200012e50e1SHuy Nguyen char *string; 201012e50e1SHuy Nguyen 202012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 203012e50e1SHuy Nguyen return; 204012e50e1SHuy Nguyen 205012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 206012e50e1SHuy Nguyen 207012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 208012e50e1SHuy Nguyen 209012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 210012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 211012e50e1SHuy Nguyen 212012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 213012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 214012e50e1SHuy Nguyen 215012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 216012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 217012e50e1SHuy Nguyen 218012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 219012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 220012e50e1SHuy Nguyen 221012e50e1SHuy Nguyen /*Send the command*/ 222012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 223012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 224012e50e1SHuy Nguyen 225012e50e1SHuy Nguyen mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 226012e50e1SHuy Nguyen } 227012e50e1SHuy Nguyen 228e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 229e126ba97SEli Cohen { 230e126ba97SEli Cohen int err; 231e126ba97SEli Cohen 232e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 233e126ba97SEli Cohen if (err) { 2341a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 235e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 236e126ba97SEli Cohen if (err) { 2371a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 238e126ba97SEli Cohen return err; 239e126ba97SEli Cohen } 240e126ba97SEli Cohen } 241e126ba97SEli Cohen 242e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 243e126ba97SEli Cohen if (err) { 244e126ba97SEli Cohen dev_warn(&pdev->dev, 2451a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 246e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 247e126ba97SEli Cohen if (err) { 248e126ba97SEli Cohen dev_err(&pdev->dev, 2491a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 250e126ba97SEli Cohen return err; 251e126ba97SEli Cohen } 252e126ba97SEli Cohen } 253e126ba97SEli Cohen 254e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 255e126ba97SEli Cohen return err; 256e126ba97SEli Cohen } 257e126ba97SEli Cohen 25889d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 25989d44f0aSMajd Dibbiny { 26089d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 26189d44f0aSMajd Dibbiny int err = 0; 26289d44f0aSMajd Dibbiny 26389d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 26489d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 26589d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 26689d44f0aSMajd Dibbiny if (!err) 26789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 26889d44f0aSMajd Dibbiny } 26989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 27089d44f0aSMajd Dibbiny 27189d44f0aSMajd Dibbiny return err; 27289d44f0aSMajd Dibbiny } 27389d44f0aSMajd Dibbiny 27489d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 27589d44f0aSMajd Dibbiny { 27689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27789d44f0aSMajd Dibbiny 27889d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27989d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 28089d44f0aSMajd Dibbiny pci_disable_device(pdev); 28189d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 28289d44f0aSMajd Dibbiny } 28389d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28489d44f0aSMajd Dibbiny } 28589d44f0aSMajd Dibbiny 286e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 287e126ba97SEli Cohen { 288e126ba97SEli Cohen int err = 0; 289e126ba97SEli Cohen 290e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2911a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 292e126ba97SEli Cohen return -ENODEV; 293e126ba97SEli Cohen } 294e126ba97SEli Cohen 295e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 296e126ba97SEli Cohen if (err) 297e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 298e126ba97SEli Cohen 299e126ba97SEli Cohen return err; 300e126ba97SEli Cohen } 301e126ba97SEli Cohen 302e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 303e126ba97SEli Cohen { 304e126ba97SEli Cohen pci_release_regions(pdev); 305e126ba97SEli Cohen } 306e126ba97SEli Cohen 307bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 308e126ba97SEli Cohen u8 he; 309e126ba97SEli Cohen u8 rsvd[15]; 310e126ba97SEli Cohen }; 311e126ba97SEli Cohen 31287b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 31387b8de49SEli Cohen 31487b8de49SEli Cohen enum { 31587b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 316c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 31787b8de49SEli Cohen }; 31887b8de49SEli Cohen 3192974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 320c7a08ac7SEli Cohen { 321c7a08ac7SEli Cohen switch (size) { 322c7a08ac7SEli Cohen case 128: 323c7a08ac7SEli Cohen return 0; 324c7a08ac7SEli Cohen case 256: 325c7a08ac7SEli Cohen return 1; 326c7a08ac7SEli Cohen case 512: 327c7a08ac7SEli Cohen return 2; 328c7a08ac7SEli Cohen case 1024: 329c7a08ac7SEli Cohen return 3; 330c7a08ac7SEli Cohen case 2048: 331c7a08ac7SEli Cohen return 4; 332c7a08ac7SEli Cohen case 4096: 333c7a08ac7SEli Cohen return 5; 334c7a08ac7SEli Cohen default: 3352974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 336c7a08ac7SEli Cohen return 0; 337c7a08ac7SEli Cohen } 338c7a08ac7SEli Cohen } 339c7a08ac7SEli Cohen 340b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 341b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 342938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 343c7a08ac7SEli Cohen { 344b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 345b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 346938fe83cSSaeed Mahameed void *out, *hca_caps; 347938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 348c7a08ac7SEli Cohen int err; 349c7a08ac7SEli Cohen 350b775516bSEli Cohen memset(in, 0, sizeof(in)); 351b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 352c7a08ac7SEli Cohen if (!out) 353c7a08ac7SEli Cohen return -ENOMEM; 354938fe83cSSaeed Mahameed 355b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 356b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 357b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 358c7a08ac7SEli Cohen if (err) { 359938fe83cSSaeed Mahameed mlx5_core_warn(dev, 360938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 361938fe83cSSaeed Mahameed cap_type, cap_mode, err); 362c7a08ac7SEli Cohen goto query_ex; 363c7a08ac7SEli Cohen } 364c7a08ac7SEli Cohen 365938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 366938fe83cSSaeed Mahameed 367938fe83cSSaeed Mahameed switch (cap_mode) { 368938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 369701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 370938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 371938fe83cSSaeed Mahameed break; 372938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 373701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 374938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 375938fe83cSSaeed Mahameed break; 376938fe83cSSaeed Mahameed default: 377938fe83cSSaeed Mahameed mlx5_core_warn(dev, 378938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 379938fe83cSSaeed Mahameed cap_type, cap_mode); 380938fe83cSSaeed Mahameed err = -EINVAL; 381938fe83cSSaeed Mahameed break; 382938fe83cSSaeed Mahameed } 383c7a08ac7SEli Cohen query_ex: 384c7a08ac7SEli Cohen kfree(out); 385c7a08ac7SEli Cohen return err; 386c7a08ac7SEli Cohen } 387c7a08ac7SEli Cohen 388b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 389b06e7de8SLeon Romanovsky { 390b06e7de8SLeon Romanovsky int ret; 391b06e7de8SLeon Romanovsky 392b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 393b06e7de8SLeon Romanovsky if (ret) 394b06e7de8SLeon Romanovsky return ret; 395b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 396b06e7de8SLeon Romanovsky } 397b06e7de8SLeon Romanovsky 398f91e6d89SEran Ben Elisha static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 399c7a08ac7SEli Cohen { 400c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 401c7a08ac7SEli Cohen 402b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 403f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 404c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 405c7a08ac7SEli Cohen } 40687b8de49SEli Cohen 407f91e6d89SEran Ben Elisha static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 408f91e6d89SEran Ben Elisha { 409f91e6d89SEran Ben Elisha void *set_ctx; 410f91e6d89SEran Ben Elisha void *set_hca_cap; 411f91e6d89SEran Ben Elisha int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 412f91e6d89SEran Ben Elisha int req_endianness; 413f91e6d89SEran Ben Elisha int err; 414f91e6d89SEran Ben Elisha 415f91e6d89SEran Ben Elisha if (MLX5_CAP_GEN(dev, atomic)) { 416b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 417f91e6d89SEran Ben Elisha if (err) 418f91e6d89SEran Ben Elisha return err; 419f91e6d89SEran Ben Elisha } else { 420f91e6d89SEran Ben Elisha return 0; 421f91e6d89SEran Ben Elisha } 422f91e6d89SEran Ben Elisha 423f91e6d89SEran Ben Elisha req_endianness = 424f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 425bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 426f91e6d89SEran Ben Elisha 427f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 428f91e6d89SEran Ben Elisha return 0; 429f91e6d89SEran Ben Elisha 430f91e6d89SEran Ben Elisha set_ctx = kzalloc(set_sz, GFP_KERNEL); 431f91e6d89SEran Ben Elisha if (!set_ctx) 432f91e6d89SEran Ben Elisha return -ENOMEM; 433f91e6d89SEran Ben Elisha 434f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 435f91e6d89SEran Ben Elisha 436f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 437bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 438f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 439f91e6d89SEran Ben Elisha 440f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 441f91e6d89SEran Ben Elisha 442f91e6d89SEran Ben Elisha kfree(set_ctx); 443f91e6d89SEran Ben Elisha return err; 444f91e6d89SEran Ben Elisha } 445f91e6d89SEran Ben Elisha 44646861e3eSMoni Shoua static int handle_hca_cap_odp(struct mlx5_core_dev *dev) 44746861e3eSMoni Shoua { 44846861e3eSMoni Shoua void *set_hca_cap; 449224d71ccSLeon Romanovsky void *set_ctx; 450224d71ccSLeon Romanovsky int set_sz; 451fca22e7eSMoni Shoua bool do_set = false; 45246861e3eSMoni Shoua int err; 45346861e3eSMoni Shoua 45437b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 45537b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 45646861e3eSMoni Shoua return 0; 45746861e3eSMoni Shoua 45846861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 45946861e3eSMoni Shoua if (err) 46046861e3eSMoni Shoua return err; 46146861e3eSMoni Shoua 462224d71ccSLeon Romanovsky set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 46346861e3eSMoni Shoua set_ctx = kzalloc(set_sz, GFP_KERNEL); 46446861e3eSMoni Shoua if (!set_ctx) 46546861e3eSMoni Shoua return -ENOMEM; 46646861e3eSMoni Shoua 46746861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 46846861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 46946861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 47046861e3eSMoni Shoua 471fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 472fca22e7eSMoni Shoua do { \ 473fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 474fca22e7eSMoni Shoua if (_res) { \ 475fca22e7eSMoni Shoua do_set = true; \ 476fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 477fca22e7eSMoni Shoua } \ 478fca22e7eSMoni Shoua } while (0) 47946861e3eSMoni Shoua 480fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 481fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 482fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 483fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 484fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 485fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 486fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 487fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 48846861e3eSMoni Shoua 489fca22e7eSMoni Shoua if (do_set) 490fca22e7eSMoni Shoua err = set_caps(dev, set_ctx, set_sz, 491fca22e7eSMoni Shoua MLX5_SET_HCA_CAP_OP_MOD_ODP); 49246861e3eSMoni Shoua 49346861e3eSMoni Shoua kfree(set_ctx); 494fca22e7eSMoni Shoua 49546861e3eSMoni Shoua return err; 49646861e3eSMoni Shoua } 49746861e3eSMoni Shoua 498e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 499e126ba97SEli Cohen { 500b775516bSEli Cohen void *set_ctx = NULL; 501c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 502c7a08ac7SEli Cohen int err = -ENOMEM; 503b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 504938fe83cSSaeed Mahameed void *set_hca_cap; 505e126ba97SEli Cohen 506b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 507c7a08ac7SEli Cohen if (!set_ctx) 508e126ba97SEli Cohen goto query_ex; 509e126ba97SEli Cohen 510b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 511c7a08ac7SEli Cohen if (err) 512e126ba97SEli Cohen goto query_ex; 513e126ba97SEli Cohen 514938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 515938fe83cSSaeed Mahameed capability); 516701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 517938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 518938fe83cSSaeed Mahameed 519938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 520707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 521938fe83cSSaeed Mahameed 128); 522c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 523938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5242974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 525e126ba97SEli Cohen 526883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 527883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 528883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 529883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 530883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 531883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 532883371c4SNoa Osherovich } 533c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 534938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 535938fe83cSSaeed Mahameed prof->log_max_qp); 536e126ba97SEli Cohen 537938fe83cSSaeed Mahameed /* disable cmdif checksum */ 538938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 539c1868b82SEli Cohen 54091828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 54191828bd8SMajd Dibbiny * than 4K. 54291828bd8SMajd Dibbiny */ 54391828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 544f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 545f502d834SEli Cohen 546fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 547fe1e1876SCarol L Soto 548f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 549f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 550f32f5bd2SDaniel Jurgens set_hca_cap, 551f32f5bd2SDaniel Jurgens cache_line_128byte, 552c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 553f32f5bd2SDaniel Jurgens 554dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 555dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 556dd44572aSMoni Shoua 557c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 558c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 559c4b76d8dSDaniel Jurgens set_hca_cap, 560c4b76d8dSDaniel Jurgens num_vhca_ports, 561c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 562c4b76d8dSDaniel Jurgens 563f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, 564f91e6d89SEran Ben Elisha MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 565e126ba97SEli Cohen 566e126ba97SEli Cohen query_ex: 567e126ba97SEli Cohen kfree(set_ctx); 568e126ba97SEli Cohen return err; 569e126ba97SEli Cohen } 570e126ba97SEli Cohen 57137b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 57237b6bb77SLeon Romanovsky { 57337b6bb77SLeon Romanovsky int err; 57437b6bb77SLeon Romanovsky 57537b6bb77SLeon Romanovsky err = handle_hca_cap(dev); 57637b6bb77SLeon Romanovsky if (err) { 57798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 57837b6bb77SLeon Romanovsky goto out; 57937b6bb77SLeon Romanovsky } 58037b6bb77SLeon Romanovsky 58137b6bb77SLeon Romanovsky err = handle_hca_cap_atomic(dev); 58237b6bb77SLeon Romanovsky if (err) { 58398a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 58437b6bb77SLeon Romanovsky goto out; 58537b6bb77SLeon Romanovsky } 58637b6bb77SLeon Romanovsky 58737b6bb77SLeon Romanovsky err = handle_hca_cap_odp(dev); 58837b6bb77SLeon Romanovsky if (err) { 58998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 59037b6bb77SLeon Romanovsky goto out; 59137b6bb77SLeon Romanovsky } 59237b6bb77SLeon Romanovsky 59337b6bb77SLeon Romanovsky out: 59437b6bb77SLeon Romanovsky return err; 59537b6bb77SLeon Romanovsky } 59637b6bb77SLeon Romanovsky 597e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 598e126ba97SEli Cohen { 599bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 600bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 601e126ba97SEli Cohen int err; 602e126ba97SEli Cohen 603fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 604fc50db98SEli Cohen return 0; 605fc50db98SEli Cohen 606e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 607e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 608e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 609e126ba97SEli Cohen &he_out, sizeof(he_out), 610e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 611e126ba97SEli Cohen return err; 612e126ba97SEli Cohen } 613e126ba97SEli Cohen 614c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 615c85023e1SHuy Nguyen { 616c85023e1SHuy Nguyen int ret = 0; 617c85023e1SHuy Nguyen 618c85023e1SHuy Nguyen /* Disable local_lb by default */ 6198978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 620c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 621c85023e1SHuy Nguyen 622c85023e1SHuy Nguyen return ret; 623c85023e1SHuy Nguyen } 624c85023e1SHuy Nguyen 6250b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 626cd23b14bSEli Cohen { 627c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 628c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 629cd23b14bSEli Cohen 6300b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6310b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 63222e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 63322e939a9SBodong Wang dev->caps.embedded_cpu); 634c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 635cd23b14bSEli Cohen } 636cd23b14bSEli Cohen 6370b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 638cd23b14bSEli Cohen { 639c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 640c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 641cd23b14bSEli Cohen 6420b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6430b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 64422e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 64522e939a9SBodong Wang dev->caps.embedded_cpu); 646c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 647cd23b14bSEli Cohen } 648cd23b14bSEli Cohen 6494a0475d5SMiroslav Lichvar u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 6504a0475d5SMiroslav Lichvar struct ptp_system_timestamp *sts) 651b0844444SEran Ben Elisha { 652b0844444SEran Ben Elisha u32 timer_h, timer_h1, timer_l; 653b0844444SEran Ben Elisha 654b0844444SEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 6554a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 656b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6574a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 658b0844444SEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 6594a0475d5SMiroslav Lichvar if (timer_h != timer_h1) { 6604a0475d5SMiroslav Lichvar /* wrap around */ 6614a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 662b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6634a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 6644a0475d5SMiroslav Lichvar } 665b0844444SEran Ben Elisha 666a5a1d1c2SThomas Gleixner return (u64)timer_l | (u64)timer_h1 << 32; 667b0844444SEran Ben Elisha } 668b0844444SEran Ben Elisha 669f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 670f62b8bb8SAmir Vadai { 671c4f287c4SSaeed Mahameed u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 672c4f287c4SSaeed Mahameed u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 673f62b8bb8SAmir Vadai u32 sup_issi; 674c4f287c4SSaeed Mahameed int err; 675f62b8bb8SAmir Vadai 676f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 677c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 678f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 679f62b8bb8SAmir Vadai if (err) { 680c4f287c4SSaeed Mahameed u32 syndrome; 681c4f287c4SSaeed Mahameed u8 status; 682c4f287c4SSaeed Mahameed 683c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 684f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 685f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 686f9c14e46SKamal Heib err, status, syndrome); 687f9c14e46SKamal Heib return err; 688f62b8bb8SAmir Vadai } 689f62b8bb8SAmir Vadai 690f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 691f9c14e46SKamal Heib dev->issi = 0; 692f9c14e46SKamal Heib return 0; 693f62b8bb8SAmir Vadai } 694f62b8bb8SAmir Vadai 695f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 696f62b8bb8SAmir Vadai 697f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 698c4f287c4SSaeed Mahameed u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 699c4f287c4SSaeed Mahameed u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 700f62b8bb8SAmir Vadai 701f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 702f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 703c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 704f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 705f62b8bb8SAmir Vadai if (err) { 706f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 707f9c14e46SKamal Heib err); 708f62b8bb8SAmir Vadai return err; 709f62b8bb8SAmir Vadai } 710f62b8bb8SAmir Vadai 711f62b8bb8SAmir Vadai dev->issi = 1; 712f62b8bb8SAmir Vadai 713f62b8bb8SAmir Vadai return 0; 714e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 715f62b8bb8SAmir Vadai return 0; 716f62b8bb8SAmir Vadai } 717f62b8bb8SAmir Vadai 7189eb78923SOr Gerlitz return -EOPNOTSUPP; 719f62b8bb8SAmir Vadai } 720f62b8bb8SAmir Vadai 72111f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 72211f3b84dSSaeed Mahameed const struct pci_device_id *id) 723a31208b1SMajd Dibbiny { 724868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 725a31208b1SMajd Dibbiny int err = 0; 726a31208b1SMajd Dibbiny 72711f3b84dSSaeed Mahameed priv->pci_dev_data = id->driver_data; 72811f3b84dSSaeed Mahameed 729e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 730e126ba97SEli Cohen 731aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 732311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 733311c7c71SSaeed Mahameed 73489d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 735e126ba97SEli Cohen if (err) { 73698a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 73711f3b84dSSaeed Mahameed return err; 738e126ba97SEli Cohen } 739e126ba97SEli Cohen 740e126ba97SEli Cohen err = request_bar(pdev); 741e126ba97SEli Cohen if (err) { 74298a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 743e126ba97SEli Cohen goto err_disable; 744e126ba97SEli Cohen } 745e126ba97SEli Cohen 746e126ba97SEli Cohen pci_set_master(pdev); 747e126ba97SEli Cohen 748e126ba97SEli Cohen err = set_dma_caps(pdev); 749e126ba97SEli Cohen if (err) { 75098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 751e126ba97SEli Cohen goto err_clr_master; 752e126ba97SEli Cohen } 753e126ba97SEli Cohen 754ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 755ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 756ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 757ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 758ce4eee53SMichael Guralnik 759aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 760e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 761e126ba97SEli Cohen if (!dev->iseg) { 762e126ba97SEli Cohen err = -ENOMEM; 76398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 764e126ba97SEli Cohen goto err_clr_master; 765e126ba97SEli Cohen } 766a31208b1SMajd Dibbiny 767b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 768b25bbc2fSAlex Vesker 769a31208b1SMajd Dibbiny return 0; 770a31208b1SMajd Dibbiny 771a31208b1SMajd Dibbiny err_clr_master: 772a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 773a31208b1SMajd Dibbiny release_bar(dev->pdev); 774a31208b1SMajd Dibbiny err_disable: 77589d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 776a31208b1SMajd Dibbiny return err; 777a31208b1SMajd Dibbiny } 778a31208b1SMajd Dibbiny 779868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 780a31208b1SMajd Dibbiny { 781a31208b1SMajd Dibbiny iounmap(dev->iseg); 782a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 783a31208b1SMajd Dibbiny release_bar(dev->pdev); 78489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 785a31208b1SMajd Dibbiny } 786a31208b1SMajd Dibbiny 787868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 78859211bd3SMohamad Haj Yahia { 78959211bd3SMohamad Haj Yahia int err; 79059211bd3SMohamad Haj Yahia 791868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 792868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 79398a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 794868bc06bSSaeed Mahameed dev->priv.devcom); 795fadd59fcSAviv Heller 79659211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 79759211bd3SMohamad Haj Yahia if (err) { 79898a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 799fadd59fcSAviv Heller goto err_devcom; 80059211bd3SMohamad Haj Yahia } 80159211bd3SMohamad Haj Yahia 802f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 80359211bd3SMohamad Haj Yahia if (err) { 80498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 805fadd59fcSAviv Heller goto err_devcom; 80659211bd3SMohamad Haj Yahia } 80759211bd3SMohamad Haj Yahia 80869c1280bSSaeed Mahameed err = mlx5_events_init(dev); 80969c1280bSSaeed Mahameed if (err) { 81098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 81169c1280bSSaeed Mahameed goto err_eq_cleanup; 81269c1280bSSaeed Mahameed } 81369c1280bSSaeed Mahameed 81402d92f79SSaeed Mahameed err = mlx5_cq_debugfs_init(dev); 81559211bd3SMohamad Haj Yahia if (err) { 81698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize cq debugfs\n"); 81769c1280bSSaeed Mahameed goto err_events_cleanup; 81859211bd3SMohamad Haj Yahia } 81959211bd3SMohamad Haj Yahia 82059211bd3SMohamad Haj Yahia mlx5_init_qp_table(dev); 82159211bd3SMohamad Haj Yahia 82259211bd3SMohamad Haj Yahia mlx5_init_mkey_table(dev); 82359211bd3SMohamad Haj Yahia 82452ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 82552ec462eSIlan Tayari 8267c39afb3SFeras Daoud mlx5_init_clock(dev); 8277c39afb3SFeras Daoud 828358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8290ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 830358aa5ceSSaeed Mahameed 83159211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 83259211bd3SMohamad Haj Yahia if (err) { 83398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 83459211bd3SMohamad Haj Yahia goto err_tables_cleanup; 83559211bd3SMohamad Haj Yahia } 83659211bd3SMohamad Haj Yahia 837eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 838eeb66cdbSSaeed Mahameed if (err) { 83998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 840eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 841eeb66cdbSSaeed Mahameed } 842eeb66cdbSSaeed Mahameed 843c2d6e31aSMohamad Haj Yahia err = mlx5_eswitch_init(dev); 844c2d6e31aSMohamad Haj Yahia if (err) { 84598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 846eeb66cdbSSaeed Mahameed goto err_mpfs_cleanup; 847c2d6e31aSMohamad Haj Yahia } 848c2d6e31aSMohamad Haj Yahia 849c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 850c2d6e31aSMohamad Haj Yahia if (err) { 85198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 852c2d6e31aSMohamad Haj Yahia goto err_eswitch_cleanup; 853c2d6e31aSMohamad Haj Yahia } 854c2d6e31aSMohamad Haj Yahia 8559410733cSIlan Tayari err = mlx5_fpga_init(dev); 8569410733cSIlan Tayari if (err) { 85798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 8589410733cSIlan Tayari goto err_sriov_cleanup; 8599410733cSIlan Tayari } 8609410733cSIlan Tayari 86124406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 86224406953SFeras Daoud 86359211bd3SMohamad Haj Yahia return 0; 86459211bd3SMohamad Haj Yahia 8659410733cSIlan Tayari err_sriov_cleanup: 8669410733cSIlan Tayari mlx5_sriov_cleanup(dev); 867c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 868c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 869eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 870eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 871c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 872c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 87359211bd3SMohamad Haj Yahia err_tables_cleanup: 8740ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 875358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 87659211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 87759211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 87802d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 87969c1280bSSaeed Mahameed err_events_cleanup: 88069c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 88159211bd3SMohamad Haj Yahia err_eq_cleanup: 882f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 883fadd59fcSAviv Heller err_devcom: 884fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 88559211bd3SMohamad Haj Yahia 88659211bd3SMohamad Haj Yahia return err; 88759211bd3SMohamad Haj Yahia } 88859211bd3SMohamad Haj Yahia 88959211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 89059211bd3SMohamad Haj Yahia { 89124406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 8929410733cSIlan Tayari mlx5_fpga_cleanup(dev); 893c2d6e31aSMohamad Haj Yahia mlx5_sriov_cleanup(dev); 894c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 895eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 89659211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 8970ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 898358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 8997c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 90052ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 90159211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 90259211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 90302d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 90469c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 905f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 906fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 90759211bd3SMohamad Haj Yahia } 90859211bd3SMohamad Haj Yahia 909e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 910a31208b1SMajd Dibbiny { 911a31208b1SMajd Dibbiny int err; 912a31208b1SMajd Dibbiny 91398a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 914e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 915e126ba97SEli Cohen 91600c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 91700c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 91800c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 91900c6bcb0STal Gilboa 9206c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9216c780a02SEli Cohen */ 9226c780a02SEli Cohen err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); 9236c780a02SEli Cohen if (err) { 92498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9256c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 926e161105eSSaeed Mahameed return err; 9276c780a02SEli Cohen } 9286c780a02SEli Cohen 929e126ba97SEli Cohen err = mlx5_cmd_init(dev); 930e126ba97SEli Cohen if (err) { 93198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 932e161105eSSaeed Mahameed return err; 933e126ba97SEli Cohen } 934e126ba97SEli Cohen 935e3297246SEli Cohen err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 936e3297246SEli Cohen if (err) { 93798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 938e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 93955378a23SMohamad Haj Yahia goto err_cmd_cleanup; 940e3297246SEli Cohen } 941e3297246SEli Cohen 9420b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 943cd23b14bSEli Cohen if (err) { 94498a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 94559211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 946cd23b14bSEli Cohen } 947cd23b14bSEli Cohen 948f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 949f62b8bb8SAmir Vadai if (err) { 95098a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 951f62b8bb8SAmir Vadai goto err_disable_hca; 952f62b8bb8SAmir Vadai } 953f62b8bb8SAmir Vadai 954cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 955cd23b14bSEli Cohen if (err) { 95698a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 957cd23b14bSEli Cohen goto err_disable_hca; 958cd23b14bSEli Cohen } 959cd23b14bSEli Cohen 960e126ba97SEli Cohen err = set_hca_ctrl(dev); 961e126ba97SEli Cohen if (err) { 96298a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 963cd23b14bSEli Cohen goto reclaim_boot_pages; 964e126ba97SEli Cohen } 965e126ba97SEli Cohen 96637b6bb77SLeon Romanovsky err = set_hca_cap(dev); 967e126ba97SEli Cohen if (err) { 96898a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 96946861e3eSMoni Shoua goto reclaim_boot_pages; 97046861e3eSMoni Shoua } 97146861e3eSMoni Shoua 972cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 973e126ba97SEli Cohen if (err) { 97498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 975cd23b14bSEli Cohen goto reclaim_boot_pages; 976e126ba97SEli Cohen } 977e126ba97SEli Cohen 9788737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 979e126ba97SEli Cohen if (err) { 98098a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 9810cf53c12SSaeed Mahameed goto reclaim_boot_pages; 982e126ba97SEli Cohen } 983e126ba97SEli Cohen 984012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 985012e50e1SHuy Nguyen 986e126ba97SEli Cohen mlx5_start_health_poll(dev); 987e126ba97SEli Cohen 988bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 989bba1574cSDaniel Jurgens if (err) { 99098a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 991e161105eSSaeed Mahameed goto stop_health; 992bba1574cSDaniel Jurgens } 993bba1574cSDaniel Jurgens 994e161105eSSaeed Mahameed return 0; 995e161105eSSaeed Mahameed 996e161105eSSaeed Mahameed stop_health: 997e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 998e161105eSSaeed Mahameed reclaim_boot_pages: 999e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1000e161105eSSaeed Mahameed err_disable_hca: 1001e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1002e161105eSSaeed Mahameed err_cmd_cleanup: 1003e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1004e161105eSSaeed Mahameed 1005e161105eSSaeed Mahameed return err; 1006e161105eSSaeed Mahameed } 1007e161105eSSaeed Mahameed 1008e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1009e161105eSSaeed Mahameed { 1010e161105eSSaeed Mahameed int err; 1011e161105eSSaeed Mahameed 1012e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1013e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1014259bbc57SMaor Gottlieb if (err) { 101598a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1016e161105eSSaeed Mahameed return err; 1017e126ba97SEli Cohen } 1018e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1019e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1020e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1021e161105eSSaeed Mahameed 1022e161105eSSaeed Mahameed return 0; 1023259bbc57SMaor Gottlieb } 1024e126ba97SEli Cohen 1025a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1026e161105eSSaeed Mahameed { 1027e161105eSSaeed Mahameed int err; 1028e161105eSSaeed Mahameed 102901187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 103072f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 103198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 103272f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1033a80d1b68SSaeed Mahameed return err; 1034e126ba97SEli Cohen } 1035e126ba97SEli Cohen 103669c1280bSSaeed Mahameed mlx5_events_start(dev); 10370cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10380cf53c12SSaeed Mahameed 1039c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1040e126ba97SEli Cohen if (err) { 104198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1042c8e21b3bSSaeed Mahameed goto err_eq_table; 1043e126ba97SEli Cohen } 1044e126ba97SEli Cohen 104524406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 104624406953SFeras Daoud if (err) { 104798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 104824406953SFeras Daoud goto err_fw_tracer; 104924406953SFeras Daoud } 105024406953SFeras Daoud 105104e87170SMatan Barak err = mlx5_fpga_device_start(dev); 105204e87170SMatan Barak if (err) { 105398a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 105404e87170SMatan Barak goto err_fpga_start; 105504e87170SMatan Barak } 105604e87170SMatan Barak 105704e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 105804e87170SMatan Barak if (err) { 105998a8e6fcSHuy Nguyen mlx5_core_err(dev, "IPSec device start failed %d\n", err); 106004e87170SMatan Barak goto err_ipsec_start; 106104e87170SMatan Barak } 106204e87170SMatan Barak 10631ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 10641ae17322SIlya Lesokhin if (err) { 106598a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 10661ae17322SIlya Lesokhin goto err_tls_start; 10671ae17322SIlya Lesokhin } 10681ae17322SIlya Lesokhin 106986d722adSMaor Gottlieb err = mlx5_init_fs(dev); 107086d722adSMaor Gottlieb if (err) { 107198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 107286d722adSMaor Gottlieb goto err_fs; 107386d722adSMaor Gottlieb } 10741466cc5bSYevgeny Petrilin 1075c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1076c85023e1SHuy Nguyen if (err) { 107798a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 107887883929SSaeed Mahameed goto err_sriov; 1079c85023e1SHuy Nguyen } 1080c85023e1SHuy Nguyen 1081c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1082fc50db98SEli Cohen if (err) { 108398a8e6fcSHuy Nguyen mlx5_core_err(dev, "sriov init failed %d\n", err); 1084fc50db98SEli Cohen goto err_sriov; 1085fc50db98SEli Cohen } 1086fc50db98SEli Cohen 108722e939a9SBodong Wang err = mlx5_ec_init(dev); 108822e939a9SBodong Wang if (err) { 108998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 109022e939a9SBodong Wang goto err_ec; 109122e939a9SBodong Wang } 109222e939a9SBodong Wang 1093a80d1b68SSaeed Mahameed return 0; 1094a80d1b68SSaeed Mahameed 1095a80d1b68SSaeed Mahameed err_ec: 1096a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1097a80d1b68SSaeed Mahameed err_sriov: 1098a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1099a80d1b68SSaeed Mahameed err_fs: 1100a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1101a80d1b68SSaeed Mahameed err_tls_start: 1102a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1103a80d1b68SSaeed Mahameed err_ipsec_start: 1104a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1105a80d1b68SSaeed Mahameed err_fpga_start: 1106a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1107a80d1b68SSaeed Mahameed err_fw_tracer: 1108a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1109a80d1b68SSaeed Mahameed err_eq_table: 1110a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1111a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1112a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1113a80d1b68SSaeed Mahameed return err; 1114a80d1b68SSaeed Mahameed } 1115a80d1b68SSaeed Mahameed 1116a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1117a80d1b68SSaeed Mahameed { 1118a80d1b68SSaeed Mahameed mlx5_ec_cleanup(dev); 1119a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1120a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1121a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1122a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1123a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1124a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1125a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1126a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1127a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1128a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1129a80d1b68SSaeed Mahameed } 1130a80d1b68SSaeed Mahameed 1131a80d1b68SSaeed Mahameed static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1132a80d1b68SSaeed Mahameed { 1133a80d1b68SSaeed Mahameed int err = 0; 1134a80d1b68SSaeed Mahameed 1135a80d1b68SSaeed Mahameed dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1136a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1137a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1138a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1139a80d1b68SSaeed Mahameed goto out; 1140a80d1b68SSaeed Mahameed } 1141a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1142a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1143a80d1b68SSaeed Mahameed 1144a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1145a80d1b68SSaeed Mahameed if (err) 1146a80d1b68SSaeed Mahameed goto out; 1147a80d1b68SSaeed Mahameed 1148a80d1b68SSaeed Mahameed if (boot) { 1149a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1150a80d1b68SSaeed Mahameed if (err) { 115198a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1152a80d1b68SSaeed Mahameed goto function_teardown; 1153a80d1b68SSaeed Mahameed } 1154a80d1b68SSaeed Mahameed } 1155a80d1b68SSaeed Mahameed 1156a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1157a80d1b68SSaeed Mahameed if (err) 1158a80d1b68SSaeed Mahameed goto err_load; 1159a80d1b68SSaeed Mahameed 1160737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) { 1161737a234bSMohamad Haj Yahia mlx5_attach_device(dev); 1162737a234bSMohamad Haj Yahia } else { 1163a31208b1SMajd Dibbiny err = mlx5_register_device(dev); 1164a31208b1SMajd Dibbiny if (err) { 116598a8e6fcSHuy Nguyen mlx5_core_err(dev, "register device failed %d\n", err); 1166a31208b1SMajd Dibbiny goto err_reg_dev; 1167a31208b1SMajd Dibbiny } 1168737a234bSMohamad Haj Yahia } 1169a31208b1SMajd Dibbiny 11705fc7197dSMajd Dibbiny set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 117189d44f0aSMajd Dibbiny out: 117289d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 117389d44f0aSMajd Dibbiny 1174a80d1b68SSaeed Mahameed return err; 1175e126ba97SEli Cohen 117659211bd3SMohamad Haj Yahia err_reg_dev: 1177a80d1b68SSaeed Mahameed mlx5_unload(dev); 1178a80d1b68SSaeed Mahameed err_load: 117959211bd3SMohamad Haj Yahia if (boot) 118059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1181e161105eSSaeed Mahameed function_teardown: 1182e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 118389d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 118489d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 118589d44f0aSMajd Dibbiny 1186e126ba97SEli Cohen return err; 1187e126ba97SEli Cohen } 1188e126ba97SEli Cohen 1189868bc06bSSaeed Mahameed static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1190e126ba97SEli Cohen { 119189d44f0aSMajd Dibbiny int err = 0; 1192e126ba97SEli Cohen 11935e44fca5SDaniel Jurgens if (cleanup) 119463cbc552SFeras Daoud mlx5_drain_health_wq(dev); 1195689a248dSDaniel Jurgens 119689d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 1197b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 119898a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 119989d44f0aSMajd Dibbiny __func__); 120059211bd3SMohamad Haj Yahia if (cleanup) 120159211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 120289d44f0aSMajd Dibbiny goto out; 120389d44f0aSMajd Dibbiny } 12046b6adee3SMohamad Haj Yahia 12059ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12069ade8c7cSIlan Tayari 1207737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) 1208737a234bSMohamad Haj Yahia mlx5_detach_device(dev); 1209737a234bSMohamad Haj Yahia 1210a80d1b68SSaeed Mahameed mlx5_unload(dev); 1211a80d1b68SSaeed Mahameed 121259211bd3SMohamad Haj Yahia if (cleanup) 121359211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12140cf53c12SSaeed Mahameed 1215e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1216ac6ea6e8SEli Cohen out: 121789d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1218ac6ea6e8SEli Cohen return err; 12199603b61dSJack Morgenstein } 122064613d94SSaeed Mahameed 122127b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12229603b61dSJack Morgenstein { 122311f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12249603b61dSJack Morgenstein int err; 12259603b61dSJack Morgenstein 122611f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12279603b61dSJack Morgenstein 1228364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1229364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 123089d44f0aSMajd Dibbiny mutex_init(&dev->pci_status_mutex); 123189d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1232d9aaed83SArtemy Kovalyov 123301187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 123401187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 123501187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 123601187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 123701187175SEli Cohen 123811f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 123911f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 124011f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 124111f3b84dSSaeed Mahameed spin_lock_init(&priv->mkey_lock); 124211f3b84dSSaeed Mahameed 124327b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 124427b942fbSParav Pandit mlx5_debugfs_root); 124511f3b84dSSaeed Mahameed if (!priv->dbg_root) { 124627b942fbSParav Pandit dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 124711f3b84dSSaeed Mahameed return -ENOMEM; 12489603b61dSJack Morgenstein } 12499603b61dSJack Morgenstein 1250ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 125152c368dcSSaeed Mahameed if (err) 125252c368dcSSaeed Mahameed goto err_health_init; 1253ac6ea6e8SEli Cohen 12540cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 12550cf53c12SSaeed Mahameed if (err) 12560cf53c12SSaeed Mahameed goto err_pagealloc_init; 125759211bd3SMohamad Haj Yahia 125811f3b84dSSaeed Mahameed return 0; 125952c368dcSSaeed Mahameed 126052c368dcSSaeed Mahameed err_pagealloc_init: 126152c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 126252c368dcSSaeed Mahameed err_health_init: 126352c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 126452c368dcSSaeed Mahameed 126552c368dcSSaeed Mahameed return err; 126611f3b84dSSaeed Mahameed } 126711f3b84dSSaeed Mahameed 126811f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 126911f3b84dSSaeed Mahameed { 127052c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 127152c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 127211f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 127311f3b84dSSaeed Mahameed } 127411f3b84dSSaeed Mahameed 127511f3b84dSSaeed Mahameed #define MLX5_IB_MOD "mlx5_ib" 127611f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 127711f3b84dSSaeed Mahameed { 127811f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 127911f3b84dSSaeed Mahameed struct devlink *devlink; 128011f3b84dSSaeed Mahameed int err; 128111f3b84dSSaeed Mahameed 12821f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 128311f3b84dSSaeed Mahameed if (!devlink) { 12841f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 128511f3b84dSSaeed Mahameed return -ENOMEM; 128611f3b84dSSaeed Mahameed } 128711f3b84dSSaeed Mahameed 128811f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 128927b942fbSParav Pandit dev->device = &pdev->dev; 129027b942fbSParav Pandit dev->pdev = pdev; 129111f3b84dSSaeed Mahameed 129227b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 129311f3b84dSSaeed Mahameed if (err) 129411f3b84dSSaeed Mahameed goto mdev_init_err; 129511f3b84dSSaeed Mahameed 129611f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 12979603b61dSJack Morgenstein if (err) { 129898a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 129998a8e6fcSHuy Nguyen err); 130011f3b84dSSaeed Mahameed goto pci_init_err; 13019603b61dSJack Morgenstein } 13029603b61dSJack Morgenstein 1303868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13049603b61dSJack Morgenstein if (err) { 130598a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 130698a8e6fcSHuy Nguyen err); 13070cf53c12SSaeed Mahameed goto err_load_one; 13089603b61dSJack Morgenstein } 130959211bd3SMohamad Haj Yahia 1310f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 13119603b61dSJack Morgenstein 13121f28d776SEran Ben Elisha err = mlx5_devlink_register(devlink, &pdev->dev); 1313feae9087SOr Gerlitz if (err) 1314feae9087SOr Gerlitz goto clean_load; 1315feae9087SOr Gerlitz 13168b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13178b9d8baaSAlex Vesker if (err) 13188b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13198b9d8baaSAlex Vesker 13205d47f6c8SDaniel Jurgens pci_save_state(pdev); 13219603b61dSJack Morgenstein return 0; 13229603b61dSJack Morgenstein 1323feae9087SOr Gerlitz clean_load: 1324868bc06bSSaeed Mahameed mlx5_unload_one(dev, true); 132552c368dcSSaeed Mahameed 13260cf53c12SSaeed Mahameed err_load_one: 1327868bc06bSSaeed Mahameed mlx5_pci_close(dev); 132811f3b84dSSaeed Mahameed pci_init_err: 132911f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 133011f3b84dSSaeed Mahameed mdev_init_err: 13311f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1332a31208b1SMajd Dibbiny 13339603b61dSJack Morgenstein return err; 13349603b61dSJack Morgenstein } 1335a31208b1SMajd Dibbiny 13369603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13379603b61dSJack Morgenstein { 13389603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1339feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 13409603b61dSJack Morgenstein 13418b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 13421f28d776SEran Ben Elisha mlx5_devlink_unregister(devlink); 1343737a234bSMohamad Haj Yahia mlx5_unregister_device(dev); 1344737a234bSMohamad Haj Yahia 1345868bc06bSSaeed Mahameed if (mlx5_unload_one(dev, true)) { 134698a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_unload_one failed\n"); 134752c368dcSSaeed Mahameed mlx5_health_flush(dev); 1348a31208b1SMajd Dibbiny return; 1349a31208b1SMajd Dibbiny } 1350737a234bSMohamad Haj Yahia 1351868bc06bSSaeed Mahameed mlx5_pci_close(dev); 135211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 13531f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 13549603b61dSJack Morgenstein } 13559603b61dSJack Morgenstein 135689d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 135789d44f0aSMajd Dibbiny pci_channel_state_t state) 135889d44f0aSMajd Dibbiny { 135989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 136089d44f0aSMajd Dibbiny 136198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 136204c0c1abSMohamad Haj Yahia 13638812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 13643e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1365868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 13665d47f6c8SDaniel Jurgens /* In case of kernel call drain the health wq */ 136705ac2c0bSMohamad Haj Yahia if (state) { 13685e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 136989d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 137005ac2c0bSMohamad Haj Yahia } 137105ac2c0bSMohamad Haj Yahia 137289d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 137389d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 137489d44f0aSMajd Dibbiny } 137589d44f0aSMajd Dibbiny 1376d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1377d57847dcSDaniel Jurgens * for the health counter to start counting. 137889d44f0aSMajd Dibbiny */ 1379d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 138089d44f0aSMajd Dibbiny { 138189d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 138289d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 138389d44f0aSMajd Dibbiny const int niter = 100; 1384d57847dcSDaniel Jurgens u32 last_count = 0; 138589d44f0aSMajd Dibbiny u32 count; 138689d44f0aSMajd Dibbiny int i; 138789d44f0aSMajd Dibbiny 138889d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 138989d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 139089d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1391d57847dcSDaniel Jurgens if (last_count && last_count != count) { 139298a8e6fcSHuy Nguyen mlx5_core_info(dev, 139398a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 139498a8e6fcSHuy Nguyen count, i); 1395d57847dcSDaniel Jurgens return 0; 1396d57847dcSDaniel Jurgens } 1397d57847dcSDaniel Jurgens last_count = count; 139889d44f0aSMajd Dibbiny } 139989d44f0aSMajd Dibbiny msleep(50); 140089d44f0aSMajd Dibbiny } 140189d44f0aSMajd Dibbiny 1402d57847dcSDaniel Jurgens return -ETIMEDOUT; 140389d44f0aSMajd Dibbiny } 140489d44f0aSMajd Dibbiny 14051061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14061061c90fSMohamad Haj Yahia { 14071061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14081061c90fSMohamad Haj Yahia int err; 14091061c90fSMohamad Haj Yahia 141098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14111061c90fSMohamad Haj Yahia 14121061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14131061c90fSMohamad Haj Yahia if (err) { 141498a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 141598a8e6fcSHuy Nguyen __func__, err); 14161061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14171061c90fSMohamad Haj Yahia } 14181061c90fSMohamad Haj Yahia 14191061c90fSMohamad Haj Yahia pci_set_master(pdev); 14201061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14215d47f6c8SDaniel Jurgens pci_save_state(pdev); 14221061c90fSMohamad Haj Yahia 14231061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 142498a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14251061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14261061c90fSMohamad Haj Yahia } 14271061c90fSMohamad Haj Yahia 14281061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 14291061c90fSMohamad Haj Yahia } 14301061c90fSMohamad Haj Yahia 143189d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 143289d44f0aSMajd Dibbiny { 143389d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 143489d44f0aSMajd Dibbiny int err; 143589d44f0aSMajd Dibbiny 143698a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 143789d44f0aSMajd Dibbiny 1438868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 143989d44f0aSMajd Dibbiny if (err) 144098a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 144198a8e6fcSHuy Nguyen __func__, err); 144289d44f0aSMajd Dibbiny else 144398a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 144489d44f0aSMajd Dibbiny } 144589d44f0aSMajd Dibbiny 144689d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 144789d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 144889d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 144989d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 145089d44f0aSMajd Dibbiny }; 145189d44f0aSMajd Dibbiny 14528812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 14538812c24dSMajd Dibbiny { 1454fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1455fcd29ad1SFeras Daoud int ret = 1; 14568812c24dSMajd Dibbiny 1457fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1458fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1459fcd29ad1SFeras Daoud 1460fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1461fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1462fcd29ad1SFeras Daoud 1463fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 14648812c24dSMajd Dibbiny return -EOPNOTSUPP; 14658812c24dSMajd Dibbiny 14668812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 14678812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 14688812c24dSMajd Dibbiny return -EAGAIN; 14698812c24dSMajd Dibbiny } 14708812c24dSMajd Dibbiny 1471d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1472d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1473d2aa060dSHuy Nguyen */ 1474d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 147576d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1476d2aa060dSHuy Nguyen 1477fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1478fcd29ad1SFeras Daoud if (!ret) 1479fcd29ad1SFeras Daoud goto succeed; 1480fcd29ad1SFeras Daoud 14818812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1482fcd29ad1SFeras Daoud if (!ret) 1483fcd29ad1SFeras Daoud goto succeed; 1484fcd29ad1SFeras Daoud 14858812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1486d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 14878812c24dSMajd Dibbiny return ret; 14888812c24dSMajd Dibbiny 1489fcd29ad1SFeras Daoud succeed: 14908812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 14918812c24dSMajd Dibbiny 14921ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 14931ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 14941ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 14951ef903bfSDaniel Jurgens * contexts. 14961ef903bfSDaniel Jurgens */ 14971ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 14981ef903bfSDaniel Jurgens 14998812c24dSMajd Dibbiny return 0; 15008812c24dSMajd Dibbiny } 15018812c24dSMajd Dibbiny 15025fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15035fc7197dSMajd Dibbiny { 15045fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15058812c24dSMajd Dibbiny int err; 15065fc7197dSMajd Dibbiny 150798a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15088812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15098812c24dSMajd Dibbiny if (err) 1510868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15115fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15125fc7197dSMajd Dibbiny } 15135fc7197dSMajd Dibbiny 15149603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1515bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1516fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1517bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1518fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1519bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1520fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 15217092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 152264dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1523d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1524d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1525d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1526d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 152785327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 152885327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 15292e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 15302e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 15319603b61dSJack Morgenstein { 0, } 15329603b61dSJack Morgenstein }; 15339603b61dSJack Morgenstein 15349603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 15359603b61dSJack Morgenstein 153604c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 153704c0c1abSMohamad Haj Yahia { 153804c0c1abSMohamad Haj Yahia mlx5_pci_err_detected(dev->pdev, 0); 153904c0c1abSMohamad Haj Yahia } 154004c0c1abSMohamad Haj Yahia 154104c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 154204c0c1abSMohamad Haj Yahia { 154304c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 154404c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 154504c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 154604c0c1abSMohamad Haj Yahia } 154704c0c1abSMohamad Haj Yahia 15489603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 15499603b61dSJack Morgenstein .name = DRIVER_NAME, 15509603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 15519603b61dSJack Morgenstein .probe = init_one, 155289d44f0aSMajd Dibbiny .remove = remove_one, 15535fc7197dSMajd Dibbiny .shutdown = shutdown, 1554fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1555fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 15569603b61dSJack Morgenstein }; 1557e126ba97SEli Cohen 1558f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1559f663ad98SKamal Heib { 1560f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1561f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1562f663ad98SKamal Heib prof_sel, 1563f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1564f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1565f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1566f663ad98SKamal Heib } 1567f663ad98SKamal Heib } 1568f663ad98SKamal Heib 1569e126ba97SEli Cohen static int __init init(void) 1570e126ba97SEli Cohen { 1571e126ba97SEli Cohen int err; 1572e126ba97SEli Cohen 15738737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 15748737f818SDaniel Jurgens 1575f663ad98SKamal Heib mlx5_core_verify_params(); 157605564d0aSAviad Yehezkel mlx5_fpga_ipsec_build_fs_cmds(); 1577e126ba97SEli Cohen mlx5_register_debugfs(); 1578e126ba97SEli Cohen 15799603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 15809603b61dSJack Morgenstein if (err) 1581ac6ea6e8SEli Cohen goto err_debug; 15829603b61dSJack Morgenstein 1583f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1584f62b8bb8SAmir Vadai mlx5e_init(); 1585f62b8bb8SAmir Vadai #endif 1586f62b8bb8SAmir Vadai 1587e126ba97SEli Cohen return 0; 1588e126ba97SEli Cohen 1589e126ba97SEli Cohen err_debug: 1590e126ba97SEli Cohen mlx5_unregister_debugfs(); 1591e126ba97SEli Cohen return err; 1592e126ba97SEli Cohen } 1593e126ba97SEli Cohen 1594e126ba97SEli Cohen static void __exit cleanup(void) 1595e126ba97SEli Cohen { 1596f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1597f62b8bb8SAmir Vadai mlx5e_cleanup(); 1598f62b8bb8SAmir Vadai #endif 15999603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1600e126ba97SEli Cohen mlx5_unregister_debugfs(); 1601e126ba97SEli Cohen } 1602e126ba97SEli Cohen 1603e126ba97SEli Cohen module_init(init); 1604e126ba97SEli Cohen module_exit(cleanup); 1605