1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/mlx5/srq.h> 47e126ba97SEli Cohen #include <linux/debugfs.h> 48f66f049fSEli Cohen #include <linux/kmod.h> 4989d44f0aSMajd Dibbiny #include <linux/delay.h> 50b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 51e126ba97SEli Cohen #include "mlx5_core.h" 5286d722adSMaor Gottlieb #include "fs_core.h" 53073bb189SSaeed Mahameed #ifdef CONFIG_MLX5_CORE_EN 54073bb189SSaeed Mahameed #include "eswitch.h" 55073bb189SSaeed Mahameed #endif 56e126ba97SEli Cohen 57e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 584ae6c18cSAchiad Shochat MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 59e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 60e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 61e126ba97SEli Cohen 62e126ba97SEli Cohen int mlx5_core_debug_mask; 63e126ba97SEli Cohen module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); 64e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 65e126ba97SEli Cohen 669603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 679603b61dSJack Morgenstein static int prof_sel = MLX5_DEFAULT_PROF; 689603b61dSJack Morgenstein module_param_named(prof_sel, prof_sel, int, 0444); 699603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 709603b61dSJack Morgenstein 719603b61dSJack Morgenstein static LIST_HEAD(intf_list); 729603b61dSJack Morgenstein static LIST_HEAD(dev_list); 739603b61dSJack Morgenstein static DEFINE_MUTEX(intf_mutex); 749603b61dSJack Morgenstein 759603b61dSJack Morgenstein struct mlx5_device_context { 769603b61dSJack Morgenstein struct list_head list; 779603b61dSJack Morgenstein struct mlx5_interface *intf; 789603b61dSJack Morgenstein void *context; 799603b61dSJack Morgenstein }; 809603b61dSJack Morgenstein 819603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 829603b61dSJack Morgenstein [0] = { 839603b61dSJack Morgenstein .mask = 0, 849603b61dSJack Morgenstein }, 859603b61dSJack Morgenstein [1] = { 869603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 879603b61dSJack Morgenstein .log_max_qp = 12, 889603b61dSJack Morgenstein }, 899603b61dSJack Morgenstein [2] = { 909603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 919603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 929603b61dSJack Morgenstein .log_max_qp = 17, 939603b61dSJack Morgenstein .mr_cache[0] = { 949603b61dSJack Morgenstein .size = 500, 959603b61dSJack Morgenstein .limit = 250 969603b61dSJack Morgenstein }, 979603b61dSJack Morgenstein .mr_cache[1] = { 989603b61dSJack Morgenstein .size = 500, 999603b61dSJack Morgenstein .limit = 250 1009603b61dSJack Morgenstein }, 1019603b61dSJack Morgenstein .mr_cache[2] = { 1029603b61dSJack Morgenstein .size = 500, 1039603b61dSJack Morgenstein .limit = 250 1049603b61dSJack Morgenstein }, 1059603b61dSJack Morgenstein .mr_cache[3] = { 1069603b61dSJack Morgenstein .size = 500, 1079603b61dSJack Morgenstein .limit = 250 1089603b61dSJack Morgenstein }, 1099603b61dSJack Morgenstein .mr_cache[4] = { 1109603b61dSJack Morgenstein .size = 500, 1119603b61dSJack Morgenstein .limit = 250 1129603b61dSJack Morgenstein }, 1139603b61dSJack Morgenstein .mr_cache[5] = { 1149603b61dSJack Morgenstein .size = 500, 1159603b61dSJack Morgenstein .limit = 250 1169603b61dSJack Morgenstein }, 1179603b61dSJack Morgenstein .mr_cache[6] = { 1189603b61dSJack Morgenstein .size = 500, 1199603b61dSJack Morgenstein .limit = 250 1209603b61dSJack Morgenstein }, 1219603b61dSJack Morgenstein .mr_cache[7] = { 1229603b61dSJack Morgenstein .size = 500, 1239603b61dSJack Morgenstein .limit = 250 1249603b61dSJack Morgenstein }, 1259603b61dSJack Morgenstein .mr_cache[8] = { 1269603b61dSJack Morgenstein .size = 500, 1279603b61dSJack Morgenstein .limit = 250 1289603b61dSJack Morgenstein }, 1299603b61dSJack Morgenstein .mr_cache[9] = { 1309603b61dSJack Morgenstein .size = 500, 1319603b61dSJack Morgenstein .limit = 250 1329603b61dSJack Morgenstein }, 1339603b61dSJack Morgenstein .mr_cache[10] = { 1349603b61dSJack Morgenstein .size = 500, 1359603b61dSJack Morgenstein .limit = 250 1369603b61dSJack Morgenstein }, 1379603b61dSJack Morgenstein .mr_cache[11] = { 1389603b61dSJack Morgenstein .size = 500, 1399603b61dSJack Morgenstein .limit = 250 1409603b61dSJack Morgenstein }, 1419603b61dSJack Morgenstein .mr_cache[12] = { 1429603b61dSJack Morgenstein .size = 64, 1439603b61dSJack Morgenstein .limit = 32 1449603b61dSJack Morgenstein }, 1459603b61dSJack Morgenstein .mr_cache[13] = { 1469603b61dSJack Morgenstein .size = 32, 1479603b61dSJack Morgenstein .limit = 16 1489603b61dSJack Morgenstein }, 1499603b61dSJack Morgenstein .mr_cache[14] = { 1509603b61dSJack Morgenstein .size = 16, 1519603b61dSJack Morgenstein .limit = 8 1529603b61dSJack Morgenstein }, 1539603b61dSJack Morgenstein .mr_cache[15] = { 1549603b61dSJack Morgenstein .size = 8, 1559603b61dSJack Morgenstein .limit = 4 1569603b61dSJack Morgenstein }, 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein }; 159e126ba97SEli Cohen 160e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 161e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 162e3297246SEli Cohen 163e3297246SEli Cohen static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 164e3297246SEli Cohen { 165e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 166e3297246SEli Cohen int err = 0; 167e3297246SEli Cohen 168e3297246SEli Cohen while (fw_initializing(dev)) { 169e3297246SEli Cohen if (time_after(jiffies, end)) { 170e3297246SEli Cohen err = -EBUSY; 171e3297246SEli Cohen break; 172e3297246SEli Cohen } 173e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 174e3297246SEli Cohen } 175e3297246SEli Cohen 176e3297246SEli Cohen return err; 177e3297246SEli Cohen } 178e3297246SEli Cohen 179e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 180e126ba97SEli Cohen { 181e126ba97SEli Cohen int err; 182e126ba97SEli Cohen 183e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 184e126ba97SEli Cohen if (err) { 1851a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 186e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 187e126ba97SEli Cohen if (err) { 1881a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 189e126ba97SEli Cohen return err; 190e126ba97SEli Cohen } 191e126ba97SEli Cohen } 192e126ba97SEli Cohen 193e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 194e126ba97SEli Cohen if (err) { 195e126ba97SEli Cohen dev_warn(&pdev->dev, 1961a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 197e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 198e126ba97SEli Cohen if (err) { 199e126ba97SEli Cohen dev_err(&pdev->dev, 2001a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 201e126ba97SEli Cohen return err; 202e126ba97SEli Cohen } 203e126ba97SEli Cohen } 204e126ba97SEli Cohen 205e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 206e126ba97SEli Cohen return err; 207e126ba97SEli Cohen } 208e126ba97SEli Cohen 20989d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 21089d44f0aSMajd Dibbiny { 21189d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 21289d44f0aSMajd Dibbiny int err = 0; 21389d44f0aSMajd Dibbiny 21489d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 21589d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 21689d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 21789d44f0aSMajd Dibbiny if (!err) 21889d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 21989d44f0aSMajd Dibbiny } 22089d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 22189d44f0aSMajd Dibbiny 22289d44f0aSMajd Dibbiny return err; 22389d44f0aSMajd Dibbiny } 22489d44f0aSMajd Dibbiny 22589d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 22689d44f0aSMajd Dibbiny { 22789d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 22889d44f0aSMajd Dibbiny 22989d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 23089d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 23189d44f0aSMajd Dibbiny pci_disable_device(pdev); 23289d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 23389d44f0aSMajd Dibbiny } 23489d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 23589d44f0aSMajd Dibbiny } 23689d44f0aSMajd Dibbiny 237e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 238e126ba97SEli Cohen { 239e126ba97SEli Cohen int err = 0; 240e126ba97SEli Cohen 241e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2421a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 243e126ba97SEli Cohen return -ENODEV; 244e126ba97SEli Cohen } 245e126ba97SEli Cohen 246e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 247e126ba97SEli Cohen if (err) 248e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 249e126ba97SEli Cohen 250e126ba97SEli Cohen return err; 251e126ba97SEli Cohen } 252e126ba97SEli Cohen 253e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 254e126ba97SEli Cohen { 255e126ba97SEli Cohen pci_release_regions(pdev); 256e126ba97SEli Cohen } 257e126ba97SEli Cohen 258e126ba97SEli Cohen static int mlx5_enable_msix(struct mlx5_core_dev *dev) 259e126ba97SEli Cohen { 260db058a18SSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 261db058a18SSaeed Mahameed struct mlx5_eq_table *table = &priv->eq_table; 262938fe83cSSaeed Mahameed int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 263e126ba97SEli Cohen int nvec; 264e126ba97SEli Cohen int i; 265e126ba97SEli Cohen 266938fe83cSSaeed Mahameed nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + 267938fe83cSSaeed Mahameed MLX5_EQ_VEC_COMP_BASE; 268e126ba97SEli Cohen nvec = min_t(int, nvec, num_eqs); 269e126ba97SEli Cohen if (nvec <= MLX5_EQ_VEC_COMP_BASE) 270e126ba97SEli Cohen return -ENOMEM; 271e126ba97SEli Cohen 272db058a18SSaeed Mahameed priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); 273db058a18SSaeed Mahameed 274db058a18SSaeed Mahameed priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); 275db058a18SSaeed Mahameed if (!priv->msix_arr || !priv->irq_info) 276db058a18SSaeed Mahameed goto err_free_msix; 277e126ba97SEli Cohen 278e126ba97SEli Cohen for (i = 0; i < nvec; i++) 279db058a18SSaeed Mahameed priv->msix_arr[i].entry = i; 280e126ba97SEli Cohen 281db058a18SSaeed Mahameed nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 2823a9e161aSEli Cohen MLX5_EQ_VEC_COMP_BASE + 1, nvec); 283f3c9407bSAlexander Gordeev if (nvec < 0) 284f3c9407bSAlexander Gordeev return nvec; 285e126ba97SEli Cohen 286f3c9407bSAlexander Gordeev table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 287e126ba97SEli Cohen 288e126ba97SEli Cohen return 0; 289db058a18SSaeed Mahameed 290db058a18SSaeed Mahameed err_free_msix: 291db058a18SSaeed Mahameed kfree(priv->irq_info); 292db058a18SSaeed Mahameed kfree(priv->msix_arr); 293db058a18SSaeed Mahameed return -ENOMEM; 294e126ba97SEli Cohen } 295e126ba97SEli Cohen 296e126ba97SEli Cohen static void mlx5_disable_msix(struct mlx5_core_dev *dev) 297e126ba97SEli Cohen { 298db058a18SSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 299e126ba97SEli Cohen 300e126ba97SEli Cohen pci_disable_msix(dev->pdev); 301db058a18SSaeed Mahameed kfree(priv->irq_info); 302db058a18SSaeed Mahameed kfree(priv->msix_arr); 303e126ba97SEli Cohen } 304e126ba97SEli Cohen 305e126ba97SEli Cohen struct mlx5_reg_host_endianess { 306e126ba97SEli Cohen u8 he; 307e126ba97SEli Cohen u8 rsvd[15]; 308e126ba97SEli Cohen }; 309e126ba97SEli Cohen 31087b8de49SEli Cohen 31187b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 31287b8de49SEli Cohen 31387b8de49SEli Cohen enum { 31487b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 315c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 31687b8de49SEli Cohen }; 31787b8de49SEli Cohen 318c7a08ac7SEli Cohen static u16 to_fw_pkey_sz(u32 size) 319c7a08ac7SEli Cohen { 320c7a08ac7SEli Cohen switch (size) { 321c7a08ac7SEli Cohen case 128: 322c7a08ac7SEli Cohen return 0; 323c7a08ac7SEli Cohen case 256: 324c7a08ac7SEli Cohen return 1; 325c7a08ac7SEli Cohen case 512: 326c7a08ac7SEli Cohen return 2; 327c7a08ac7SEli Cohen case 1024: 328c7a08ac7SEli Cohen return 3; 329c7a08ac7SEli Cohen case 2048: 330c7a08ac7SEli Cohen return 4; 331c7a08ac7SEli Cohen case 4096: 332c7a08ac7SEli Cohen return 5; 333c7a08ac7SEli Cohen default: 334c7a08ac7SEli Cohen pr_warn("invalid pkey table size %d\n", size); 335c7a08ac7SEli Cohen return 0; 336c7a08ac7SEli Cohen } 337c7a08ac7SEli Cohen } 338c7a08ac7SEli Cohen 339938fe83cSSaeed Mahameed int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 340938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 341c7a08ac7SEli Cohen { 342b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 343b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 344938fe83cSSaeed Mahameed void *out, *hca_caps; 345938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 346c7a08ac7SEli Cohen int err; 347c7a08ac7SEli Cohen 348b775516bSEli Cohen memset(in, 0, sizeof(in)); 349b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 350c7a08ac7SEli Cohen if (!out) 351c7a08ac7SEli Cohen return -ENOMEM; 352938fe83cSSaeed Mahameed 353b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 354b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 355b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 356b775516bSEli Cohen if (err) 357b775516bSEli Cohen goto query_ex; 358c7a08ac7SEli Cohen 359b775516bSEli Cohen err = mlx5_cmd_status_to_err_v2(out); 360c7a08ac7SEli Cohen if (err) { 361938fe83cSSaeed Mahameed mlx5_core_warn(dev, 362938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 363938fe83cSSaeed Mahameed cap_type, cap_mode, err); 364c7a08ac7SEli Cohen goto query_ex; 365c7a08ac7SEli Cohen } 366c7a08ac7SEli Cohen 367938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 368938fe83cSSaeed Mahameed 369938fe83cSSaeed Mahameed switch (cap_mode) { 370938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 371938fe83cSSaeed Mahameed memcpy(dev->hca_caps_max[cap_type], hca_caps, 372938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 373938fe83cSSaeed Mahameed break; 374938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 375938fe83cSSaeed Mahameed memcpy(dev->hca_caps_cur[cap_type], hca_caps, 376938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 377938fe83cSSaeed Mahameed break; 378938fe83cSSaeed Mahameed default: 379938fe83cSSaeed Mahameed mlx5_core_warn(dev, 380938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 381938fe83cSSaeed Mahameed cap_type, cap_mode); 382938fe83cSSaeed Mahameed err = -EINVAL; 383938fe83cSSaeed Mahameed break; 384938fe83cSSaeed Mahameed } 385c7a08ac7SEli Cohen query_ex: 386c7a08ac7SEli Cohen kfree(out); 387c7a08ac7SEli Cohen return err; 388c7a08ac7SEli Cohen } 389c7a08ac7SEli Cohen 390b775516bSEli Cohen static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 391c7a08ac7SEli Cohen { 392b775516bSEli Cohen u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)]; 393c7a08ac7SEli Cohen int err; 394c7a08ac7SEli Cohen 395b775516bSEli Cohen memset(out, 0, sizeof(out)); 396c7a08ac7SEli Cohen 397b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 398b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 399c7a08ac7SEli Cohen if (err) 400c7a08ac7SEli Cohen return err; 401c7a08ac7SEli Cohen 402b775516bSEli Cohen err = mlx5_cmd_status_to_err_v2(out); 403c7a08ac7SEli Cohen 404c7a08ac7SEli Cohen return err; 405c7a08ac7SEli Cohen } 40687b8de49SEli Cohen 407e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 408e126ba97SEli Cohen { 409b775516bSEli Cohen void *set_ctx = NULL; 410c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 411c7a08ac7SEli Cohen int err = -ENOMEM; 412b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 413938fe83cSSaeed Mahameed void *set_hca_cap; 414e126ba97SEli Cohen 415b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 416c7a08ac7SEli Cohen if (!set_ctx) 417e126ba97SEli Cohen goto query_ex; 418e126ba97SEli Cohen 419938fe83cSSaeed Mahameed err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX); 420e126ba97SEli Cohen if (err) 421e126ba97SEli Cohen goto query_ex; 422e126ba97SEli Cohen 423938fe83cSSaeed Mahameed err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR); 424c7a08ac7SEli Cohen if (err) 425e126ba97SEli Cohen goto query_ex; 426e126ba97SEli Cohen 427938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 428938fe83cSSaeed Mahameed capability); 429938fe83cSSaeed Mahameed memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 430938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 431938fe83cSSaeed Mahameed 432938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 433707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 434938fe83cSSaeed Mahameed 128); 435c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 436938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 437938fe83cSSaeed Mahameed to_fw_pkey_sz(128)); 438e126ba97SEli Cohen 439c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 440938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 441938fe83cSSaeed Mahameed prof->log_max_qp); 442e126ba97SEli Cohen 443938fe83cSSaeed Mahameed /* disable cmdif checksum */ 444938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 445c1868b82SEli Cohen 446fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 447fe1e1876SCarol L Soto 448b775516bSEli Cohen err = set_caps(dev, set_ctx, set_sz); 449e126ba97SEli Cohen 450e126ba97SEli Cohen query_ex: 451e126ba97SEli Cohen kfree(set_ctx); 452e126ba97SEli Cohen return err; 453e126ba97SEli Cohen } 454e126ba97SEli Cohen 455e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 456e126ba97SEli Cohen { 457e126ba97SEli Cohen struct mlx5_reg_host_endianess he_in; 458e126ba97SEli Cohen struct mlx5_reg_host_endianess he_out; 459e126ba97SEli Cohen int err; 460e126ba97SEli Cohen 461fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 462fc50db98SEli Cohen return 0; 463fc50db98SEli Cohen 464e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 465e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 466e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 467e126ba97SEli Cohen &he_out, sizeof(he_out), 468e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 469e126ba97SEli Cohen return err; 470e126ba97SEli Cohen } 471e126ba97SEli Cohen 4720b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 473cd23b14bSEli Cohen { 4740b107106SEli Cohen u32 out[MLX5_ST_SZ_DW(enable_hca_out)]; 4750b107106SEli Cohen u32 in[MLX5_ST_SZ_DW(enable_hca_in)]; 476cd23b14bSEli Cohen int err; 477cd23b14bSEli Cohen 4780b107106SEli Cohen memset(in, 0, sizeof(in)); 4790b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 4800b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 4810b107106SEli Cohen memset(out, 0, sizeof(out)); 4820b107106SEli Cohen 483cd23b14bSEli Cohen err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 484cd23b14bSEli Cohen if (err) 485cd23b14bSEli Cohen return err; 486cd23b14bSEli Cohen 4870b107106SEli Cohen return mlx5_cmd_status_to_err_v2(out); 488cd23b14bSEli Cohen } 489cd23b14bSEli Cohen 4900b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 491cd23b14bSEli Cohen { 4920b107106SEli Cohen u32 out[MLX5_ST_SZ_DW(disable_hca_out)]; 4930b107106SEli Cohen u32 in[MLX5_ST_SZ_DW(disable_hca_in)]; 494cd23b14bSEli Cohen int err; 495cd23b14bSEli Cohen 4960b107106SEli Cohen memset(in, 0, sizeof(in)); 4970b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 4980b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 4990b107106SEli Cohen memset(out, 0, sizeof(out)); 5000b107106SEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 501cd23b14bSEli Cohen if (err) 502cd23b14bSEli Cohen return err; 503cd23b14bSEli Cohen 5040b107106SEli Cohen return mlx5_cmd_status_to_err_v2(out); 505cd23b14bSEli Cohen } 506cd23b14bSEli Cohen 507b0844444SEran Ben Elisha cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev) 508b0844444SEran Ben Elisha { 509b0844444SEran Ben Elisha u32 timer_h, timer_h1, timer_l; 510b0844444SEran Ben Elisha 511b0844444SEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 512b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 513b0844444SEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 514b0844444SEran Ben Elisha if (timer_h != timer_h1) /* wrap around */ 515b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 516b0844444SEran Ben Elisha 517b0844444SEran Ben Elisha return (cycle_t)timer_l | (cycle_t)timer_h1 << 32; 518b0844444SEran Ben Elisha } 519b0844444SEran Ben Elisha 520db058a18SSaeed Mahameed static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) 521db058a18SSaeed Mahameed { 522db058a18SSaeed Mahameed struct mlx5_priv *priv = &mdev->priv; 523db058a18SSaeed Mahameed struct msix_entry *msix = priv->msix_arr; 524db058a18SSaeed Mahameed int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; 525311c7c71SSaeed Mahameed int numa_node = priv->numa_node; 526db058a18SSaeed Mahameed int err; 527db058a18SSaeed Mahameed 528db058a18SSaeed Mahameed if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { 529db058a18SSaeed Mahameed mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); 530db058a18SSaeed Mahameed return -ENOMEM; 531db058a18SSaeed Mahameed } 532db058a18SSaeed Mahameed 533dda922c8SDavid S. Miller cpumask_set_cpu(cpumask_local_spread(i, numa_node), 534dda922c8SDavid S. Miller priv->irq_info[i].mask); 535db058a18SSaeed Mahameed 536db058a18SSaeed Mahameed err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); 537db058a18SSaeed Mahameed if (err) { 538db058a18SSaeed Mahameed mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", 539db058a18SSaeed Mahameed irq); 540db058a18SSaeed Mahameed goto err_clear_mask; 541db058a18SSaeed Mahameed } 542db058a18SSaeed Mahameed 543db058a18SSaeed Mahameed return 0; 544db058a18SSaeed Mahameed 545db058a18SSaeed Mahameed err_clear_mask: 546db058a18SSaeed Mahameed free_cpumask_var(priv->irq_info[i].mask); 547db058a18SSaeed Mahameed return err; 548db058a18SSaeed Mahameed } 549db058a18SSaeed Mahameed 550db058a18SSaeed Mahameed static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) 551db058a18SSaeed Mahameed { 552db058a18SSaeed Mahameed struct mlx5_priv *priv = &mdev->priv; 553db058a18SSaeed Mahameed struct msix_entry *msix = priv->msix_arr; 554db058a18SSaeed Mahameed int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; 555db058a18SSaeed Mahameed 556db058a18SSaeed Mahameed irq_set_affinity_hint(irq, NULL); 557db058a18SSaeed Mahameed free_cpumask_var(priv->irq_info[i].mask); 558db058a18SSaeed Mahameed } 559db058a18SSaeed Mahameed 560db058a18SSaeed Mahameed static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) 561db058a18SSaeed Mahameed { 562db058a18SSaeed Mahameed int err; 563db058a18SSaeed Mahameed int i; 564db058a18SSaeed Mahameed 565db058a18SSaeed Mahameed for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { 566db058a18SSaeed Mahameed err = mlx5_irq_set_affinity_hint(mdev, i); 567db058a18SSaeed Mahameed if (err) 568db058a18SSaeed Mahameed goto err_out; 569db058a18SSaeed Mahameed } 570db058a18SSaeed Mahameed 571db058a18SSaeed Mahameed return 0; 572db058a18SSaeed Mahameed 573db058a18SSaeed Mahameed err_out: 574db058a18SSaeed Mahameed for (i--; i >= 0; i--) 575db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hint(mdev, i); 576db058a18SSaeed Mahameed 577db058a18SSaeed Mahameed return err; 578db058a18SSaeed Mahameed } 579db058a18SSaeed Mahameed 580db058a18SSaeed Mahameed static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) 581db058a18SSaeed Mahameed { 582db058a18SSaeed Mahameed int i; 583db058a18SSaeed Mahameed 584db058a18SSaeed Mahameed for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) 585db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hint(mdev, i); 586db058a18SSaeed Mahameed } 587db058a18SSaeed Mahameed 5880b6e26ceSDoron Tsur int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 5890b6e26ceSDoron Tsur unsigned int *irqn) 590233d05d2SSaeed Mahameed { 591233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 592233d05d2SSaeed Mahameed struct mlx5_eq *eq, *n; 593233d05d2SSaeed Mahameed int err = -ENOENT; 594233d05d2SSaeed Mahameed 595233d05d2SSaeed Mahameed spin_lock(&table->lock); 596233d05d2SSaeed Mahameed list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 597233d05d2SSaeed Mahameed if (eq->index == vector) { 598233d05d2SSaeed Mahameed *eqn = eq->eqn; 599233d05d2SSaeed Mahameed *irqn = eq->irqn; 600233d05d2SSaeed Mahameed err = 0; 601233d05d2SSaeed Mahameed break; 602233d05d2SSaeed Mahameed } 603233d05d2SSaeed Mahameed } 604233d05d2SSaeed Mahameed spin_unlock(&table->lock); 605233d05d2SSaeed Mahameed 606233d05d2SSaeed Mahameed return err; 607233d05d2SSaeed Mahameed } 608233d05d2SSaeed Mahameed EXPORT_SYMBOL(mlx5_vector2eqn); 609233d05d2SSaeed Mahameed 610233d05d2SSaeed Mahameed static void free_comp_eqs(struct mlx5_core_dev *dev) 611233d05d2SSaeed Mahameed { 612233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 613233d05d2SSaeed Mahameed struct mlx5_eq *eq, *n; 614233d05d2SSaeed Mahameed 615233d05d2SSaeed Mahameed spin_lock(&table->lock); 616233d05d2SSaeed Mahameed list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 617233d05d2SSaeed Mahameed list_del(&eq->list); 618233d05d2SSaeed Mahameed spin_unlock(&table->lock); 619233d05d2SSaeed Mahameed if (mlx5_destroy_unmap_eq(dev, eq)) 620233d05d2SSaeed Mahameed mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 621233d05d2SSaeed Mahameed eq->eqn); 622233d05d2SSaeed Mahameed kfree(eq); 623233d05d2SSaeed Mahameed spin_lock(&table->lock); 624233d05d2SSaeed Mahameed } 625233d05d2SSaeed Mahameed spin_unlock(&table->lock); 626233d05d2SSaeed Mahameed } 627233d05d2SSaeed Mahameed 628233d05d2SSaeed Mahameed static int alloc_comp_eqs(struct mlx5_core_dev *dev) 629233d05d2SSaeed Mahameed { 630233d05d2SSaeed Mahameed struct mlx5_eq_table *table = &dev->priv.eq_table; 631db058a18SSaeed Mahameed char name[MLX5_MAX_IRQ_NAME]; 632233d05d2SSaeed Mahameed struct mlx5_eq *eq; 633233d05d2SSaeed Mahameed int ncomp_vec; 634233d05d2SSaeed Mahameed int nent; 635233d05d2SSaeed Mahameed int err; 636233d05d2SSaeed Mahameed int i; 637233d05d2SSaeed Mahameed 638233d05d2SSaeed Mahameed INIT_LIST_HEAD(&table->comp_eqs_list); 639233d05d2SSaeed Mahameed ncomp_vec = table->num_comp_vectors; 640233d05d2SSaeed Mahameed nent = MLX5_COMP_EQ_SIZE; 641233d05d2SSaeed Mahameed for (i = 0; i < ncomp_vec; i++) { 642233d05d2SSaeed Mahameed eq = kzalloc(sizeof(*eq), GFP_KERNEL); 643233d05d2SSaeed Mahameed if (!eq) { 644233d05d2SSaeed Mahameed err = -ENOMEM; 645233d05d2SSaeed Mahameed goto clean; 646233d05d2SSaeed Mahameed } 647233d05d2SSaeed Mahameed 648db058a18SSaeed Mahameed snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 649233d05d2SSaeed Mahameed err = mlx5_create_map_eq(dev, eq, 650233d05d2SSaeed Mahameed i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 651233d05d2SSaeed Mahameed name, &dev->priv.uuari.uars[0]); 652233d05d2SSaeed Mahameed if (err) { 653233d05d2SSaeed Mahameed kfree(eq); 654233d05d2SSaeed Mahameed goto clean; 655233d05d2SSaeed Mahameed } 656233d05d2SSaeed Mahameed mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 657233d05d2SSaeed Mahameed eq->index = i; 658233d05d2SSaeed Mahameed spin_lock(&table->lock); 659233d05d2SSaeed Mahameed list_add_tail(&eq->list, &table->comp_eqs_list); 660233d05d2SSaeed Mahameed spin_unlock(&table->lock); 661233d05d2SSaeed Mahameed } 662233d05d2SSaeed Mahameed 663233d05d2SSaeed Mahameed return 0; 664233d05d2SSaeed Mahameed 665233d05d2SSaeed Mahameed clean: 666233d05d2SSaeed Mahameed free_comp_eqs(dev); 667233d05d2SSaeed Mahameed return err; 668233d05d2SSaeed Mahameed } 669233d05d2SSaeed Mahameed 670f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 671f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 672f62b8bb8SAmir Vadai { 673f62b8bb8SAmir Vadai u32 query_in[MLX5_ST_SZ_DW(query_issi_in)]; 674f62b8bb8SAmir Vadai u32 query_out[MLX5_ST_SZ_DW(query_issi_out)]; 675f62b8bb8SAmir Vadai u32 set_in[MLX5_ST_SZ_DW(set_issi_in)]; 676f62b8bb8SAmir Vadai u32 set_out[MLX5_ST_SZ_DW(set_issi_out)]; 677f62b8bb8SAmir Vadai int err; 678f62b8bb8SAmir Vadai u32 sup_issi; 679f62b8bb8SAmir Vadai 680f62b8bb8SAmir Vadai memset(query_in, 0, sizeof(query_in)); 681f62b8bb8SAmir Vadai memset(query_out, 0, sizeof(query_out)); 682f62b8bb8SAmir Vadai 683f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 684f62b8bb8SAmir Vadai 685f62b8bb8SAmir Vadai err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in), 686f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 687f62b8bb8SAmir Vadai if (err) { 688f62b8bb8SAmir Vadai if (((struct mlx5_outbox_hdr *)query_out)->status == 689f62b8bb8SAmir Vadai MLX5_CMD_STAT_BAD_OP_ERR) { 690f62b8bb8SAmir Vadai pr_debug("Only ISSI 0 is supported\n"); 691f62b8bb8SAmir Vadai return 0; 692f62b8bb8SAmir Vadai } 693f62b8bb8SAmir Vadai 694f62b8bb8SAmir Vadai pr_err("failed to query ISSI\n"); 695f62b8bb8SAmir Vadai return err; 696f62b8bb8SAmir Vadai } 697f62b8bb8SAmir Vadai 698f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 699f62b8bb8SAmir Vadai 700f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 701f62b8bb8SAmir Vadai memset(set_in, 0, sizeof(set_in)); 702f62b8bb8SAmir Vadai memset(set_out, 0, sizeof(set_out)); 703f62b8bb8SAmir Vadai 704f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 705f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 706f62b8bb8SAmir Vadai 707f62b8bb8SAmir Vadai err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in), 708f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 709f62b8bb8SAmir Vadai if (err) { 710f62b8bb8SAmir Vadai pr_err("failed to set ISSI=1\n"); 711f62b8bb8SAmir Vadai return err; 712f62b8bb8SAmir Vadai } 713f62b8bb8SAmir Vadai 714f62b8bb8SAmir Vadai dev->issi = 1; 715f62b8bb8SAmir Vadai 716f62b8bb8SAmir Vadai return 0; 717e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 718f62b8bb8SAmir Vadai return 0; 719f62b8bb8SAmir Vadai } 720f62b8bb8SAmir Vadai 721f62b8bb8SAmir Vadai return -ENOTSUPP; 722f62b8bb8SAmir Vadai } 723f62b8bb8SAmir Vadai #endif 724f62b8bb8SAmir Vadai 72588a85f99SAchiad Shochat static int map_bf_area(struct mlx5_core_dev *dev) 72688a85f99SAchiad Shochat { 72788a85f99SAchiad Shochat resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 72888a85f99SAchiad Shochat resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 72988a85f99SAchiad Shochat 73088a85f99SAchiad Shochat dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 73188a85f99SAchiad Shochat 73288a85f99SAchiad Shochat return dev->priv.bf_mapping ? 0 : -ENOMEM; 73388a85f99SAchiad Shochat } 73488a85f99SAchiad Shochat 73588a85f99SAchiad Shochat static void unmap_bf_area(struct mlx5_core_dev *dev) 73688a85f99SAchiad Shochat { 73788a85f99SAchiad Shochat if (dev->priv.bf_mapping) 73888a85f99SAchiad Shochat io_mapping_free(dev->priv.bf_mapping); 73988a85f99SAchiad Shochat } 74088a85f99SAchiad Shochat 741a31208b1SMajd Dibbiny static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 742a31208b1SMajd Dibbiny { 743a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 744a31208b1SMajd Dibbiny struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 745a31208b1SMajd Dibbiny 746a31208b1SMajd Dibbiny dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL); 747a31208b1SMajd Dibbiny if (!dev_ctx) 748a31208b1SMajd Dibbiny return; 749a31208b1SMajd Dibbiny 750a31208b1SMajd Dibbiny dev_ctx->intf = intf; 751a31208b1SMajd Dibbiny dev_ctx->context = intf->add(dev); 752a31208b1SMajd Dibbiny 753a31208b1SMajd Dibbiny if (dev_ctx->context) { 754a31208b1SMajd Dibbiny spin_lock_irq(&priv->ctx_lock); 755a31208b1SMajd Dibbiny list_add_tail(&dev_ctx->list, &priv->ctx_list); 756a31208b1SMajd Dibbiny spin_unlock_irq(&priv->ctx_lock); 757a31208b1SMajd Dibbiny } else { 758a31208b1SMajd Dibbiny kfree(dev_ctx); 759a31208b1SMajd Dibbiny } 760a31208b1SMajd Dibbiny } 761a31208b1SMajd Dibbiny 762a31208b1SMajd Dibbiny static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 763a31208b1SMajd Dibbiny { 764a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 765a31208b1SMajd Dibbiny struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 766a31208b1SMajd Dibbiny 767a31208b1SMajd Dibbiny list_for_each_entry(dev_ctx, &priv->ctx_list, list) 768a31208b1SMajd Dibbiny if (dev_ctx->intf == intf) { 769a31208b1SMajd Dibbiny spin_lock_irq(&priv->ctx_lock); 770a31208b1SMajd Dibbiny list_del(&dev_ctx->list); 771a31208b1SMajd Dibbiny spin_unlock_irq(&priv->ctx_lock); 772a31208b1SMajd Dibbiny 773a31208b1SMajd Dibbiny intf->remove(dev, dev_ctx->context); 774a31208b1SMajd Dibbiny kfree(dev_ctx); 775a31208b1SMajd Dibbiny return; 776a31208b1SMajd Dibbiny } 777a31208b1SMajd Dibbiny } 778a31208b1SMajd Dibbiny 779a31208b1SMajd Dibbiny static int mlx5_register_device(struct mlx5_core_dev *dev) 780e126ba97SEli Cohen { 781e126ba97SEli Cohen struct mlx5_priv *priv = &dev->priv; 782a31208b1SMajd Dibbiny struct mlx5_interface *intf; 783e126ba97SEli Cohen 784a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 785a31208b1SMajd Dibbiny list_add_tail(&priv->dev_list, &dev_list); 786a31208b1SMajd Dibbiny list_for_each_entry(intf, &intf_list, list) 787a31208b1SMajd Dibbiny mlx5_add_device(intf, priv); 788a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 789a31208b1SMajd Dibbiny 790a31208b1SMajd Dibbiny return 0; 791a31208b1SMajd Dibbiny } 792a31208b1SMajd Dibbiny 793a31208b1SMajd Dibbiny static void mlx5_unregister_device(struct mlx5_core_dev *dev) 794a31208b1SMajd Dibbiny { 795a31208b1SMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 796a31208b1SMajd Dibbiny struct mlx5_interface *intf; 797a31208b1SMajd Dibbiny 798a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 799a31208b1SMajd Dibbiny list_for_each_entry(intf, &intf_list, list) 800a31208b1SMajd Dibbiny mlx5_remove_device(intf, priv); 801a31208b1SMajd Dibbiny list_del(&priv->dev_list); 802a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 803a31208b1SMajd Dibbiny } 804a31208b1SMajd Dibbiny 805a31208b1SMajd Dibbiny int mlx5_register_interface(struct mlx5_interface *intf) 806a31208b1SMajd Dibbiny { 807a31208b1SMajd Dibbiny struct mlx5_priv *priv; 808a31208b1SMajd Dibbiny 809a31208b1SMajd Dibbiny if (!intf->add || !intf->remove) 810a31208b1SMajd Dibbiny return -EINVAL; 811a31208b1SMajd Dibbiny 812a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 813a31208b1SMajd Dibbiny list_add_tail(&intf->list, &intf_list); 814a31208b1SMajd Dibbiny list_for_each_entry(priv, &dev_list, dev_list) 815a31208b1SMajd Dibbiny mlx5_add_device(intf, priv); 816a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 817a31208b1SMajd Dibbiny 818a31208b1SMajd Dibbiny return 0; 819a31208b1SMajd Dibbiny } 820a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_register_interface); 821a31208b1SMajd Dibbiny 822a31208b1SMajd Dibbiny void mlx5_unregister_interface(struct mlx5_interface *intf) 823a31208b1SMajd Dibbiny { 824a31208b1SMajd Dibbiny struct mlx5_priv *priv; 825a31208b1SMajd Dibbiny 826a31208b1SMajd Dibbiny mutex_lock(&intf_mutex); 827a31208b1SMajd Dibbiny list_for_each_entry(priv, &dev_list, dev_list) 828a31208b1SMajd Dibbiny mlx5_remove_device(intf, priv); 829a31208b1SMajd Dibbiny list_del(&intf->list); 830a31208b1SMajd Dibbiny mutex_unlock(&intf_mutex); 831a31208b1SMajd Dibbiny } 832a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_unregister_interface); 833a31208b1SMajd Dibbiny 834a31208b1SMajd Dibbiny void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 835a31208b1SMajd Dibbiny { 836a31208b1SMajd Dibbiny struct mlx5_priv *priv = &mdev->priv; 837a31208b1SMajd Dibbiny struct mlx5_device_context *dev_ctx; 838a31208b1SMajd Dibbiny unsigned long flags; 839a31208b1SMajd Dibbiny void *result = NULL; 840a31208b1SMajd Dibbiny 841a31208b1SMajd Dibbiny spin_lock_irqsave(&priv->ctx_lock, flags); 842a31208b1SMajd Dibbiny 843a31208b1SMajd Dibbiny list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 844a31208b1SMajd Dibbiny if ((dev_ctx->intf->protocol == protocol) && 845a31208b1SMajd Dibbiny dev_ctx->intf->get_dev) { 846a31208b1SMajd Dibbiny result = dev_ctx->intf->get_dev(dev_ctx->context); 847a31208b1SMajd Dibbiny break; 848a31208b1SMajd Dibbiny } 849a31208b1SMajd Dibbiny 850a31208b1SMajd Dibbiny spin_unlock_irqrestore(&priv->ctx_lock, flags); 851a31208b1SMajd Dibbiny 852a31208b1SMajd Dibbiny return result; 853a31208b1SMajd Dibbiny } 854a31208b1SMajd Dibbiny EXPORT_SYMBOL(mlx5_get_protocol_dev); 855a31208b1SMajd Dibbiny 856a31208b1SMajd Dibbiny static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 857a31208b1SMajd Dibbiny { 858a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 859a31208b1SMajd Dibbiny int err = 0; 860a31208b1SMajd Dibbiny 861e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 862e126ba97SEli Cohen strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 863e126ba97SEli Cohen priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 864e126ba97SEli Cohen 865e126ba97SEli Cohen mutex_init(&priv->pgdir_mutex); 866e126ba97SEli Cohen INIT_LIST_HEAD(&priv->pgdir_list); 867e126ba97SEli Cohen spin_lock_init(&priv->mkey_lock); 868e126ba97SEli Cohen 869311c7c71SSaeed Mahameed mutex_init(&priv->alloc_mutex); 870311c7c71SSaeed Mahameed 871311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 872311c7c71SSaeed Mahameed 873e126ba97SEli Cohen priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); 874e126ba97SEli Cohen if (!priv->dbg_root) 875e126ba97SEli Cohen return -ENOMEM; 876e126ba97SEli Cohen 87789d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 878e126ba97SEli Cohen if (err) { 8791a91de28SJoe Perches dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 880e126ba97SEli Cohen goto err_dbg; 881e126ba97SEli Cohen } 882e126ba97SEli Cohen 883e126ba97SEli Cohen err = request_bar(pdev); 884e126ba97SEli Cohen if (err) { 8851a91de28SJoe Perches dev_err(&pdev->dev, "error requesting BARs, aborting\n"); 886e126ba97SEli Cohen goto err_disable; 887e126ba97SEli Cohen } 888e126ba97SEli Cohen 889e126ba97SEli Cohen pci_set_master(pdev); 890e126ba97SEli Cohen 891e126ba97SEli Cohen err = set_dma_caps(pdev); 892e126ba97SEli Cohen if (err) { 893e126ba97SEli Cohen dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); 894e126ba97SEli Cohen goto err_clr_master; 895e126ba97SEli Cohen } 896e126ba97SEli Cohen 897e126ba97SEli Cohen dev->iseg_base = pci_resource_start(dev->pdev, 0); 898e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 899e126ba97SEli Cohen if (!dev->iseg) { 900e126ba97SEli Cohen err = -ENOMEM; 901e126ba97SEli Cohen dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); 902e126ba97SEli Cohen goto err_clr_master; 903e126ba97SEli Cohen } 904a31208b1SMajd Dibbiny 905a31208b1SMajd Dibbiny return 0; 906a31208b1SMajd Dibbiny 907a31208b1SMajd Dibbiny err_clr_master: 908a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 909a31208b1SMajd Dibbiny release_bar(dev->pdev); 910a31208b1SMajd Dibbiny err_disable: 91189d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 912a31208b1SMajd Dibbiny 913a31208b1SMajd Dibbiny err_dbg: 914a31208b1SMajd Dibbiny debugfs_remove(priv->dbg_root); 915a31208b1SMajd Dibbiny return err; 916a31208b1SMajd Dibbiny } 917a31208b1SMajd Dibbiny 918a31208b1SMajd Dibbiny static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 919a31208b1SMajd Dibbiny { 920a31208b1SMajd Dibbiny iounmap(dev->iseg); 921a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 922a31208b1SMajd Dibbiny release_bar(dev->pdev); 92389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 924a31208b1SMajd Dibbiny debugfs_remove(priv->dbg_root); 925a31208b1SMajd Dibbiny } 926a31208b1SMajd Dibbiny 927a31208b1SMajd Dibbiny #define MLX5_IB_MOD "mlx5_ib" 928a31208b1SMajd Dibbiny static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 929a31208b1SMajd Dibbiny { 930a31208b1SMajd Dibbiny struct pci_dev *pdev = dev->pdev; 931a31208b1SMajd Dibbiny int err; 932a31208b1SMajd Dibbiny 93389d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 93489d44f0aSMajd Dibbiny if (dev->interface_state == MLX5_INTERFACE_STATE_UP) { 93589d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 93689d44f0aSMajd Dibbiny __func__); 93789d44f0aSMajd Dibbiny goto out; 93889d44f0aSMajd Dibbiny } 93989d44f0aSMajd Dibbiny 940e126ba97SEli Cohen dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 941e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 942e126ba97SEli Cohen 94389d44f0aSMajd Dibbiny /* on load removing any previous indication of internal error, device is 94489d44f0aSMajd Dibbiny * up 94589d44f0aSMajd Dibbiny */ 94689d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_UP; 94789d44f0aSMajd Dibbiny 948e126ba97SEli Cohen err = mlx5_cmd_init(dev); 949e126ba97SEli Cohen if (err) { 950e126ba97SEli Cohen dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); 95189d44f0aSMajd Dibbiny goto out_err; 952e126ba97SEli Cohen } 953e126ba97SEli Cohen 954e3297246SEli Cohen err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 955e3297246SEli Cohen if (err) { 956e3297246SEli Cohen dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", 957e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 958e3297246SEli Cohen goto out_err; 959e3297246SEli Cohen } 960e3297246SEli Cohen 961e126ba97SEli Cohen mlx5_pagealloc_init(dev); 962cd23b14bSEli Cohen 9630b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 964cd23b14bSEli Cohen if (err) { 965cd23b14bSEli Cohen dev_err(&pdev->dev, "enable hca failed\n"); 966cd23b14bSEli Cohen goto err_pagealloc_cleanup; 967cd23b14bSEli Cohen } 968cd23b14bSEli Cohen 969f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 970f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 971f62b8bb8SAmir Vadai if (err) { 972f62b8bb8SAmir Vadai dev_err(&pdev->dev, "failed to set issi\n"); 973f62b8bb8SAmir Vadai goto err_disable_hca; 974f62b8bb8SAmir Vadai } 975f62b8bb8SAmir Vadai #endif 976f62b8bb8SAmir Vadai 977cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 978cd23b14bSEli Cohen if (err) { 979cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate boot pages\n"); 980cd23b14bSEli Cohen goto err_disable_hca; 981cd23b14bSEli Cohen } 982cd23b14bSEli Cohen 983e126ba97SEli Cohen err = set_hca_ctrl(dev); 984e126ba97SEli Cohen if (err) { 985e126ba97SEli Cohen dev_err(&pdev->dev, "set_hca_ctrl failed\n"); 986cd23b14bSEli Cohen goto reclaim_boot_pages; 987e126ba97SEli Cohen } 988e126ba97SEli Cohen 989e126ba97SEli Cohen err = handle_hca_cap(dev); 990e126ba97SEli Cohen if (err) { 991e126ba97SEli Cohen dev_err(&pdev->dev, "handle_hca_cap failed\n"); 992cd23b14bSEli Cohen goto reclaim_boot_pages; 993e126ba97SEli Cohen } 994e126ba97SEli Cohen 995cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 996e126ba97SEli Cohen if (err) { 997cd23b14bSEli Cohen dev_err(&pdev->dev, "failed to allocate init pages\n"); 998cd23b14bSEli Cohen goto reclaim_boot_pages; 999e126ba97SEli Cohen } 1000e126ba97SEli Cohen 1001e126ba97SEli Cohen err = mlx5_pagealloc_start(dev); 1002e126ba97SEli Cohen if (err) { 1003e126ba97SEli Cohen dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); 1004cd23b14bSEli Cohen goto reclaim_boot_pages; 1005e126ba97SEli Cohen } 1006e126ba97SEli Cohen 1007e126ba97SEli Cohen err = mlx5_cmd_init_hca(dev); 1008e126ba97SEli Cohen if (err) { 1009e126ba97SEli Cohen dev_err(&pdev->dev, "init hca failed\n"); 1010e126ba97SEli Cohen goto err_pagealloc_stop; 1011e126ba97SEli Cohen } 1012e126ba97SEli Cohen 1013e126ba97SEli Cohen mlx5_start_health_poll(dev); 1014e126ba97SEli Cohen 1015938fe83cSSaeed Mahameed err = mlx5_query_hca_caps(dev); 1016e126ba97SEli Cohen if (err) { 1017e126ba97SEli Cohen dev_err(&pdev->dev, "query hca failed\n"); 1018e126ba97SEli Cohen goto err_stop_poll; 1019e126ba97SEli Cohen } 1020e126ba97SEli Cohen 1021211e6c80SMajd Dibbiny err = mlx5_query_board_id(dev); 1022e126ba97SEli Cohen if (err) { 1023211e6c80SMajd Dibbiny dev_err(&pdev->dev, "query board id failed\n"); 1024e126ba97SEli Cohen goto err_stop_poll; 1025e126ba97SEli Cohen } 1026e126ba97SEli Cohen 1027e126ba97SEli Cohen err = mlx5_enable_msix(dev); 1028e126ba97SEli Cohen if (err) { 1029e126ba97SEli Cohen dev_err(&pdev->dev, "enable msix failed\n"); 1030e126ba97SEli Cohen goto err_stop_poll; 1031e126ba97SEli Cohen } 1032e126ba97SEli Cohen 1033e126ba97SEli Cohen err = mlx5_eq_init(dev); 1034e126ba97SEli Cohen if (err) { 1035e126ba97SEli Cohen dev_err(&pdev->dev, "failed to initialize eq\n"); 1036e126ba97SEli Cohen goto disable_msix; 1037e126ba97SEli Cohen } 1038e126ba97SEli Cohen 1039e126ba97SEli Cohen err = mlx5_alloc_uuars(dev, &priv->uuari); 1040e126ba97SEli Cohen if (err) { 1041e126ba97SEli Cohen dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); 1042e126ba97SEli Cohen goto err_eq_cleanup; 1043e126ba97SEli Cohen } 1044e126ba97SEli Cohen 1045e126ba97SEli Cohen err = mlx5_start_eqs(dev); 1046e126ba97SEli Cohen if (err) { 1047e126ba97SEli Cohen dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); 1048e126ba97SEli Cohen goto err_free_uar; 1049e126ba97SEli Cohen } 1050e126ba97SEli Cohen 1051233d05d2SSaeed Mahameed err = alloc_comp_eqs(dev); 1052233d05d2SSaeed Mahameed if (err) { 1053233d05d2SSaeed Mahameed dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); 1054233d05d2SSaeed Mahameed goto err_stop_eqs; 1055233d05d2SSaeed Mahameed } 1056233d05d2SSaeed Mahameed 105788a85f99SAchiad Shochat if (map_bf_area(dev)) 105888a85f99SAchiad Shochat dev_err(&pdev->dev, "Failed to map blue flame area\n"); 105988a85f99SAchiad Shochat 1060db058a18SSaeed Mahameed err = mlx5_irq_set_affinity_hints(dev); 1061db058a18SSaeed Mahameed if (err) { 1062db058a18SSaeed Mahameed dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); 106388a85f99SAchiad Shochat goto err_unmap_bf_area; 1064db058a18SSaeed Mahameed } 1065db058a18SSaeed Mahameed 1066e126ba97SEli Cohen MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 1067e126ba97SEli Cohen 1068e126ba97SEli Cohen mlx5_init_cq_table(dev); 1069e126ba97SEli Cohen mlx5_init_qp_table(dev); 1070e126ba97SEli Cohen mlx5_init_srq_table(dev); 10713bcdb17aSSagi Grimberg mlx5_init_mr_table(dev); 1072e126ba97SEli Cohen 107386d722adSMaor Gottlieb err = mlx5_init_fs(dev); 107486d722adSMaor Gottlieb if (err) { 107586d722adSMaor Gottlieb dev_err(&pdev->dev, "Failed to init flow steering\n"); 107686d722adSMaor Gottlieb goto err_fs; 107786d722adSMaor Gottlieb } 1078073bb189SSaeed Mahameed #ifdef CONFIG_MLX5_CORE_EN 1079073bb189SSaeed Mahameed err = mlx5_eswitch_init(dev); 1080073bb189SSaeed Mahameed if (err) { 1081073bb189SSaeed Mahameed dev_err(&pdev->dev, "eswitch init failed %d\n", err); 1082073bb189SSaeed Mahameed goto err_reg_dev; 1083073bb189SSaeed Mahameed } 1084073bb189SSaeed Mahameed #endif 1085073bb189SSaeed Mahameed 1086fc50db98SEli Cohen err = mlx5_sriov_init(dev); 1087fc50db98SEli Cohen if (err) { 1088fc50db98SEli Cohen dev_err(&pdev->dev, "sriov init failed %d\n", err); 1089fc50db98SEli Cohen goto err_sriov; 1090fc50db98SEli Cohen } 1091fc50db98SEli Cohen 1092a31208b1SMajd Dibbiny err = mlx5_register_device(dev); 1093a31208b1SMajd Dibbiny if (err) { 1094a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1095a31208b1SMajd Dibbiny goto err_reg_dev; 1096a31208b1SMajd Dibbiny } 1097a31208b1SMajd Dibbiny 1098a31208b1SMajd Dibbiny err = request_module_nowait(MLX5_IB_MOD); 1099a31208b1SMajd Dibbiny if (err) 1100a31208b1SMajd Dibbiny pr_info("failed request module on %s\n", MLX5_IB_MOD); 1101a31208b1SMajd Dibbiny 110289d44f0aSMajd Dibbiny dev->interface_state = MLX5_INTERFACE_STATE_UP; 110389d44f0aSMajd Dibbiny out: 110489d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 110589d44f0aSMajd Dibbiny 1106e126ba97SEli Cohen return 0; 1107e126ba97SEli Cohen 1108fc50db98SEli Cohen err_sriov: 1109fc50db98SEli Cohen if (mlx5_sriov_cleanup(dev)) 1110fc50db98SEli Cohen dev_err(&dev->pdev->dev, "sriov cleanup failed\n"); 1111fc50db98SEli Cohen 1112073bb189SSaeed Mahameed #ifdef CONFIG_MLX5_CORE_EN 1113073bb189SSaeed Mahameed mlx5_eswitch_cleanup(dev->priv.eswitch); 1114073bb189SSaeed Mahameed #endif 1115a31208b1SMajd Dibbiny err_reg_dev: 111686d722adSMaor Gottlieb mlx5_cleanup_fs(dev); 111786d722adSMaor Gottlieb err_fs: 1118a31208b1SMajd Dibbiny mlx5_cleanup_mr_table(dev); 1119a31208b1SMajd Dibbiny mlx5_cleanup_srq_table(dev); 1120a31208b1SMajd Dibbiny mlx5_cleanup_qp_table(dev); 1121a31208b1SMajd Dibbiny mlx5_cleanup_cq_table(dev); 1122a31208b1SMajd Dibbiny mlx5_irq_clear_affinity_hints(dev); 1123a31208b1SMajd Dibbiny 112488a85f99SAchiad Shochat err_unmap_bf_area: 112588a85f99SAchiad Shochat unmap_bf_area(dev); 112688a85f99SAchiad Shochat 1127db058a18SSaeed Mahameed free_comp_eqs(dev); 1128db058a18SSaeed Mahameed 1129233d05d2SSaeed Mahameed err_stop_eqs: 1130233d05d2SSaeed Mahameed mlx5_stop_eqs(dev); 1131233d05d2SSaeed Mahameed 1132e126ba97SEli Cohen err_free_uar: 1133e126ba97SEli Cohen mlx5_free_uuars(dev, &priv->uuari); 1134e126ba97SEli Cohen 1135e126ba97SEli Cohen err_eq_cleanup: 1136e126ba97SEli Cohen mlx5_eq_cleanup(dev); 1137e126ba97SEli Cohen 1138e126ba97SEli Cohen disable_msix: 1139e126ba97SEli Cohen mlx5_disable_msix(dev); 1140e126ba97SEli Cohen 1141e126ba97SEli Cohen err_stop_poll: 1142e126ba97SEli Cohen mlx5_stop_health_poll(dev); 11431bde6e30SEli Cohen if (mlx5_cmd_teardown_hca(dev)) { 11441bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 114589d44f0aSMajd Dibbiny goto out_err; 11461bde6e30SEli Cohen } 1147e126ba97SEli Cohen 1148e126ba97SEli Cohen err_pagealloc_stop: 1149e126ba97SEli Cohen mlx5_pagealloc_stop(dev); 1150e126ba97SEli Cohen 1151cd23b14bSEli Cohen reclaim_boot_pages: 1152e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 1153e126ba97SEli Cohen 1154cd23b14bSEli Cohen err_disable_hca: 11550b107106SEli Cohen mlx5_core_disable_hca(dev, 0); 1156cd23b14bSEli Cohen 1157e126ba97SEli Cohen err_pagealloc_cleanup: 1158e126ba97SEli Cohen mlx5_pagealloc_cleanup(dev); 1159e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 1160e126ba97SEli Cohen 116189d44f0aSMajd Dibbiny out_err: 116289d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 116389d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 116489d44f0aSMajd Dibbiny 1165e126ba97SEli Cohen return err; 1166e126ba97SEli Cohen } 1167e126ba97SEli Cohen 1168a31208b1SMajd Dibbiny static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 1169e126ba97SEli Cohen { 117089d44f0aSMajd Dibbiny int err = 0; 1171e126ba97SEli Cohen 1172fc50db98SEli Cohen err = mlx5_sriov_cleanup(dev); 1173fc50db98SEli Cohen if (err) { 1174fc50db98SEli Cohen dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n", 1175fc50db98SEli Cohen __func__); 1176fc50db98SEli Cohen return err; 1177fc50db98SEli Cohen } 1178fc50db98SEli Cohen 117989d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 118089d44f0aSMajd Dibbiny if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) { 118189d44f0aSMajd Dibbiny dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", 118289d44f0aSMajd Dibbiny __func__); 118389d44f0aSMajd Dibbiny goto out; 118489d44f0aSMajd Dibbiny } 1185a31208b1SMajd Dibbiny mlx5_unregister_device(dev); 1186073bb189SSaeed Mahameed #ifdef CONFIG_MLX5_CORE_EN 1187073bb189SSaeed Mahameed mlx5_eswitch_cleanup(dev->priv.eswitch); 1188073bb189SSaeed Mahameed #endif 1189073bb189SSaeed Mahameed 119086d722adSMaor Gottlieb mlx5_cleanup_fs(dev); 1191a31208b1SMajd Dibbiny mlx5_cleanup_mr_table(dev); 1192e126ba97SEli Cohen mlx5_cleanup_srq_table(dev); 1193e126ba97SEli Cohen mlx5_cleanup_qp_table(dev); 1194e126ba97SEli Cohen mlx5_cleanup_cq_table(dev); 1195db058a18SSaeed Mahameed mlx5_irq_clear_affinity_hints(dev); 119688a85f99SAchiad Shochat unmap_bf_area(dev); 1197233d05d2SSaeed Mahameed free_comp_eqs(dev); 1198e126ba97SEli Cohen mlx5_stop_eqs(dev); 1199e126ba97SEli Cohen mlx5_free_uuars(dev, &priv->uuari); 1200e126ba97SEli Cohen mlx5_eq_cleanup(dev); 1201e126ba97SEli Cohen mlx5_disable_msix(dev); 1202e126ba97SEli Cohen mlx5_stop_health_poll(dev); 1203ac6ea6e8SEli Cohen err = mlx5_cmd_teardown_hca(dev); 1204ac6ea6e8SEli Cohen if (err) { 12051bde6e30SEli Cohen dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); 1206ac6ea6e8SEli Cohen goto out; 12071bde6e30SEli Cohen } 1208e126ba97SEli Cohen mlx5_pagealloc_stop(dev); 1209e126ba97SEli Cohen mlx5_reclaim_startup_pages(dev); 12100b107106SEli Cohen mlx5_core_disable_hca(dev, 0); 1211e126ba97SEli Cohen mlx5_pagealloc_cleanup(dev); 1212e126ba97SEli Cohen mlx5_cmd_cleanup(dev); 12139603b61dSJack Morgenstein 1214ac6ea6e8SEli Cohen out: 121589d44f0aSMajd Dibbiny dev->interface_state = MLX5_INTERFACE_STATE_DOWN; 121689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1217ac6ea6e8SEli Cohen return err; 12189603b61dSJack Morgenstein } 121964613d94SSaeed Mahameed 122089d44f0aSMajd Dibbiny void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 12214d2f9bbbSJack Morgenstein unsigned long param) 12229603b61dSJack Morgenstein { 12239603b61dSJack Morgenstein struct mlx5_priv *priv = &dev->priv; 12249603b61dSJack Morgenstein struct mlx5_device_context *dev_ctx; 12259603b61dSJack Morgenstein unsigned long flags; 12269603b61dSJack Morgenstein 12279603b61dSJack Morgenstein spin_lock_irqsave(&priv->ctx_lock, flags); 12289603b61dSJack Morgenstein 12299603b61dSJack Morgenstein list_for_each_entry(dev_ctx, &priv->ctx_list, list) 12309603b61dSJack Morgenstein if (dev_ctx->intf->event) 12314d2f9bbbSJack Morgenstein dev_ctx->intf->event(dev, dev_ctx->context, event, param); 12329603b61dSJack Morgenstein 12339603b61dSJack Morgenstein spin_unlock_irqrestore(&priv->ctx_lock, flags); 12349603b61dSJack Morgenstein } 12359603b61dSJack Morgenstein 12369603b61dSJack Morgenstein struct mlx5_core_event_handler { 12379603b61dSJack Morgenstein void (*event)(struct mlx5_core_dev *dev, 12389603b61dSJack Morgenstein enum mlx5_dev_event event, 12399603b61dSJack Morgenstein void *data); 12409603b61dSJack Morgenstein }; 12419603b61dSJack Morgenstein 1242f66f049fSEli Cohen 12439603b61dSJack Morgenstein static int init_one(struct pci_dev *pdev, 12449603b61dSJack Morgenstein const struct pci_device_id *id) 12459603b61dSJack Morgenstein { 12469603b61dSJack Morgenstein struct mlx5_core_dev *dev; 12479603b61dSJack Morgenstein struct mlx5_priv *priv; 12489603b61dSJack Morgenstein int err; 12499603b61dSJack Morgenstein 12509603b61dSJack Morgenstein dev = kzalloc(sizeof(*dev), GFP_KERNEL); 12519603b61dSJack Morgenstein if (!dev) { 12529603b61dSJack Morgenstein dev_err(&pdev->dev, "kzalloc failed\n"); 12539603b61dSJack Morgenstein return -ENOMEM; 12549603b61dSJack Morgenstein } 12559603b61dSJack Morgenstein priv = &dev->priv; 1256fc50db98SEli Cohen priv->pci_dev_data = id->driver_data; 12579603b61dSJack Morgenstein 12589603b61dSJack Morgenstein pci_set_drvdata(pdev, dev); 12599603b61dSJack Morgenstein 12609603b61dSJack Morgenstein if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) { 12619603b61dSJack Morgenstein pr_warn("selected profile out of range, selecting default (%d)\n", 12629603b61dSJack Morgenstein MLX5_DEFAULT_PROF); 12639603b61dSJack Morgenstein prof_sel = MLX5_DEFAULT_PROF; 12649603b61dSJack Morgenstein } 12659603b61dSJack Morgenstein dev->profile = &profile[prof_sel]; 1266a31208b1SMajd Dibbiny dev->pdev = pdev; 12679603b61dSJack Morgenstein dev->event = mlx5_core_event; 12689603b61dSJack Morgenstein 1269364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1270364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 127189d44f0aSMajd Dibbiny mutex_init(&dev->pci_status_mutex); 127289d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1273a31208b1SMajd Dibbiny err = mlx5_pci_init(dev, priv); 12749603b61dSJack Morgenstein if (err) { 1275a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); 1276a31208b1SMajd Dibbiny goto clean_dev; 12779603b61dSJack Morgenstein } 12789603b61dSJack Morgenstein 1279ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 1280ac6ea6e8SEli Cohen if (err) { 1281ac6ea6e8SEli Cohen dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); 1282ac6ea6e8SEli Cohen goto close_pci; 1283ac6ea6e8SEli Cohen } 1284ac6ea6e8SEli Cohen 1285a31208b1SMajd Dibbiny err = mlx5_load_one(dev, priv); 12869603b61dSJack Morgenstein if (err) { 1287a31208b1SMajd Dibbiny dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); 1288ac6ea6e8SEli Cohen goto clean_health; 12899603b61dSJack Morgenstein } 12909603b61dSJack Morgenstein 12919603b61dSJack Morgenstein return 0; 12929603b61dSJack Morgenstein 1293ac6ea6e8SEli Cohen clean_health: 1294ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1295a31208b1SMajd Dibbiny close_pci: 1296a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1297a31208b1SMajd Dibbiny clean_dev: 1298a31208b1SMajd Dibbiny pci_set_drvdata(pdev, NULL); 12999603b61dSJack Morgenstein kfree(dev); 1300a31208b1SMajd Dibbiny 13019603b61dSJack Morgenstein return err; 13029603b61dSJack Morgenstein } 1303a31208b1SMajd Dibbiny 13049603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13059603b61dSJack Morgenstein { 13069603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1307a31208b1SMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 13089603b61dSJack Morgenstein 1309a31208b1SMajd Dibbiny if (mlx5_unload_one(dev, priv)) { 1310a31208b1SMajd Dibbiny dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1311ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1312a31208b1SMajd Dibbiny return; 1313a31208b1SMajd Dibbiny } 1314ac6ea6e8SEli Cohen mlx5_health_cleanup(dev); 1315a31208b1SMajd Dibbiny mlx5_pci_close(dev, priv); 1316a31208b1SMajd Dibbiny pci_set_drvdata(pdev, NULL); 13179603b61dSJack Morgenstein kfree(dev); 13189603b61dSJack Morgenstein } 13199603b61dSJack Morgenstein 132089d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 132189d44f0aSMajd Dibbiny pci_channel_state_t state) 132289d44f0aSMajd Dibbiny { 132389d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 132489d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 132589d44f0aSMajd Dibbiny 132689d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 132789d44f0aSMajd Dibbiny mlx5_enter_error_state(dev); 132889d44f0aSMajd Dibbiny mlx5_unload_one(dev, priv); 132989d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 133089d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 133189d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 133289d44f0aSMajd Dibbiny } 133389d44f0aSMajd Dibbiny 133489d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 133589d44f0aSMajd Dibbiny { 133689d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 133789d44f0aSMajd Dibbiny int err = 0; 133889d44f0aSMajd Dibbiny 133989d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 134089d44f0aSMajd Dibbiny 134189d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 134289d44f0aSMajd Dibbiny if (err) { 134389d44f0aSMajd Dibbiny dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 134489d44f0aSMajd Dibbiny , __func__, err); 134589d44f0aSMajd Dibbiny return PCI_ERS_RESULT_DISCONNECT; 134689d44f0aSMajd Dibbiny } 134789d44f0aSMajd Dibbiny pci_set_master(pdev); 134889d44f0aSMajd Dibbiny pci_set_power_state(pdev, PCI_D0); 134989d44f0aSMajd Dibbiny pci_restore_state(pdev); 135089d44f0aSMajd Dibbiny 135189d44f0aSMajd Dibbiny return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 135289d44f0aSMajd Dibbiny } 135389d44f0aSMajd Dibbiny 135489d44f0aSMajd Dibbiny void mlx5_disable_device(struct mlx5_core_dev *dev) 135589d44f0aSMajd Dibbiny { 135689d44f0aSMajd Dibbiny mlx5_pci_err_detected(dev->pdev, 0); 135789d44f0aSMajd Dibbiny } 135889d44f0aSMajd Dibbiny 135989d44f0aSMajd Dibbiny /* wait for the device to show vital signs. For now we check 136089d44f0aSMajd Dibbiny * that we can read the device ID and that the health buffer 136189d44f0aSMajd Dibbiny * shows a non zero value which is different than 0xffffffff 136289d44f0aSMajd Dibbiny */ 136389d44f0aSMajd Dibbiny static void wait_vital(struct pci_dev *pdev) 136489d44f0aSMajd Dibbiny { 136589d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 136689d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 136789d44f0aSMajd Dibbiny const int niter = 100; 136889d44f0aSMajd Dibbiny u32 count; 136989d44f0aSMajd Dibbiny u16 did; 137089d44f0aSMajd Dibbiny int i; 137189d44f0aSMajd Dibbiny 137289d44f0aSMajd Dibbiny /* Wait for firmware to be ready after reset */ 137389d44f0aSMajd Dibbiny msleep(1000); 137489d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 137589d44f0aSMajd Dibbiny if (pci_read_config_word(pdev, 2, &did)) { 137689d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "failed reading config word\n"); 137789d44f0aSMajd Dibbiny break; 137889d44f0aSMajd Dibbiny } 137989d44f0aSMajd Dibbiny if (did == pdev->device) { 138089d44f0aSMajd Dibbiny dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 138189d44f0aSMajd Dibbiny break; 138289d44f0aSMajd Dibbiny } 138389d44f0aSMajd Dibbiny msleep(50); 138489d44f0aSMajd Dibbiny } 138589d44f0aSMajd Dibbiny if (i == niter) 138689d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 138789d44f0aSMajd Dibbiny 138889d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 138989d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 139089d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 139189d44f0aSMajd Dibbiny dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 139289d44f0aSMajd Dibbiny break; 139389d44f0aSMajd Dibbiny } 139489d44f0aSMajd Dibbiny msleep(50); 139589d44f0aSMajd Dibbiny } 139689d44f0aSMajd Dibbiny 139789d44f0aSMajd Dibbiny if (i == niter) 139889d44f0aSMajd Dibbiny dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 139989d44f0aSMajd Dibbiny } 140089d44f0aSMajd Dibbiny 140189d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 140289d44f0aSMajd Dibbiny { 140389d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 140489d44f0aSMajd Dibbiny struct mlx5_priv *priv = &dev->priv; 140589d44f0aSMajd Dibbiny int err; 140689d44f0aSMajd Dibbiny 140789d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s was called\n", __func__); 140889d44f0aSMajd Dibbiny 140989d44f0aSMajd Dibbiny pci_save_state(pdev); 141089d44f0aSMajd Dibbiny wait_vital(pdev); 141189d44f0aSMajd Dibbiny 141289d44f0aSMajd Dibbiny err = mlx5_load_one(dev, priv); 141389d44f0aSMajd Dibbiny if (err) 141489d44f0aSMajd Dibbiny dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 141589d44f0aSMajd Dibbiny , __func__, err); 141689d44f0aSMajd Dibbiny else 141789d44f0aSMajd Dibbiny dev_info(&pdev->dev, "%s: device recovered\n", __func__); 141889d44f0aSMajd Dibbiny } 141989d44f0aSMajd Dibbiny 142089d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 142189d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 142289d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 142389d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 142489d44f0aSMajd Dibbiny }; 142589d44f0aSMajd Dibbiny 14269603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 14271c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ 1428fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 14291c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ 1430fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 14311c755cc5SOr Gerlitz { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ 1432fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 14339603b61dSJack Morgenstein { 0, } 14349603b61dSJack Morgenstein }; 14359603b61dSJack Morgenstein 14369603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 14379603b61dSJack Morgenstein 14389603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 14399603b61dSJack Morgenstein .name = DRIVER_NAME, 14409603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 14419603b61dSJack Morgenstein .probe = init_one, 144289d44f0aSMajd Dibbiny .remove = remove_one, 1443fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1444fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 14459603b61dSJack Morgenstein }; 1446e126ba97SEli Cohen 1447e126ba97SEli Cohen static int __init init(void) 1448e126ba97SEli Cohen { 1449e126ba97SEli Cohen int err; 1450e126ba97SEli Cohen 1451e126ba97SEli Cohen mlx5_register_debugfs(); 1452e126ba97SEli Cohen 14539603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 14549603b61dSJack Morgenstein if (err) 1455ac6ea6e8SEli Cohen goto err_debug; 14569603b61dSJack Morgenstein 1457f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1458f62b8bb8SAmir Vadai mlx5e_init(); 1459f62b8bb8SAmir Vadai #endif 1460f62b8bb8SAmir Vadai 1461e126ba97SEli Cohen return 0; 1462e126ba97SEli Cohen 1463e126ba97SEli Cohen err_debug: 1464e126ba97SEli Cohen mlx5_unregister_debugfs(); 1465e126ba97SEli Cohen return err; 1466e126ba97SEli Cohen } 1467e126ba97SEli Cohen 1468e126ba97SEli Cohen static void __exit cleanup(void) 1469e126ba97SEli Cohen { 1470f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1471f62b8bb8SAmir Vadai mlx5e_cleanup(); 1472f62b8bb8SAmir Vadai #endif 14739603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1474e126ba97SEli Cohen mlx5_unregister_debugfs(); 1475e126ba97SEli Cohen } 1476e126ba97SEli Cohen 1477e126ba97SEli Cohen module_init(init); 1478e126ba97SEli Cohen module_exit(cleanup); 1479