1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33adec640eSChristoph Hellwig #include <linux/highmem.h> 34e126ba97SEli Cohen #include <linux/module.h> 35e126ba97SEli Cohen #include <linux/init.h> 36e126ba97SEli Cohen #include <linux/errno.h> 37e126ba97SEli Cohen #include <linux/pci.h> 38e126ba97SEli Cohen #include <linux/dma-mapping.h> 39e126ba97SEli Cohen #include <linux/slab.h> 40e126ba97SEli Cohen #include <linux/io-mapping.h> 41db058a18SSaeed Mahameed #include <linux/interrupt.h> 42e3297246SEli Cohen #include <linux/delay.h> 43e126ba97SEli Cohen #include <linux/mlx5/driver.h> 44e126ba97SEli Cohen #include <linux/mlx5/cq.h> 45e126ba97SEli Cohen #include <linux/mlx5/qp.h> 46e126ba97SEli Cohen #include <linux/debugfs.h> 47f66f049fSEli Cohen #include <linux/kmod.h> 48b775516bSEli Cohen #include <linux/mlx5/mlx5_ifc.h> 49c85023e1SHuy Nguyen #include <linux/mlx5/vport.h> 505a7b27ebSMaor Gottlieb #ifdef CONFIG_RFS_ACCEL 515a7b27ebSMaor Gottlieb #include <linux/cpu_rmap.h> 525a7b27ebSMaor Gottlieb #endif 53feae9087SOr Gerlitz #include <net/devlink.h> 54e126ba97SEli Cohen #include "mlx5_core.h" 55f2f3df55SSaeed Mahameed #include "lib/eq.h" 5616d76083SSaeed Mahameed #include "fs_core.h" 57eeb66cdbSSaeed Mahameed #include "lib/mpfs.h" 58073bb189SSaeed Mahameed #include "eswitch.h" 591f28d776SEran Ben Elisha #include "devlink.h" 6052ec462eSIlan Tayari #include "lib/mlx5.h" 61e29341fbSIlan Tayari #include "fpga/core.h" 6205564d0aSAviad Yehezkel #include "fpga/ipsec.h" 63bebb23e6SIlan Tayari #include "accel/ipsec.h" 641ae17322SIlya Lesokhin #include "accel/tls.h" 657c39afb3SFeras Daoud #include "lib/clock.h" 66358aa5ceSSaeed Mahameed #include "lib/vxlan.h" 670ccc171eSYevgeny Kliteynik #include "lib/geneve.h" 68fadd59fcSAviv Heller #include "lib/devcom.h" 69b25bbc2fSAlex Vesker #include "lib/pci_vsc.h" 7024406953SFeras Daoud #include "diag/fw_tracer.h" 71591905baSBodong Wang #include "ecpf.h" 72e126ba97SEli Cohen 73e126ba97SEli Cohen MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 74048f3143SEran Ben Elisha MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 75e126ba97SEli Cohen MODULE_LICENSE("Dual BSD/GPL"); 76e126ba97SEli Cohen MODULE_VERSION(DRIVER_VERSION); 77e126ba97SEli Cohen 78f663ad98SKamal Heib unsigned int mlx5_core_debug_mask; 79f663ad98SKamal Heib module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 80e126ba97SEli Cohen MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 81e126ba97SEli Cohen 829603b61dSJack Morgenstein #define MLX5_DEFAULT_PROF 2 83f663ad98SKamal Heib static unsigned int prof_sel = MLX5_DEFAULT_PROF; 84f663ad98SKamal Heib module_param_named(prof_sel, prof_sel, uint, 0444); 859603b61dSJack Morgenstein MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 869603b61dSJack Morgenstein 878737f818SDaniel Jurgens static u32 sw_owner_id[4]; 888737f818SDaniel Jurgens 89f91e6d89SEran Ben Elisha enum { 90f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_BE = 0x0, 91f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 92f91e6d89SEran Ben Elisha }; 93f91e6d89SEran Ben Elisha 949603b61dSJack Morgenstein static struct mlx5_profile profile[] = { 959603b61dSJack Morgenstein [0] = { 969603b61dSJack Morgenstein .mask = 0, 979603b61dSJack Morgenstein }, 989603b61dSJack Morgenstein [1] = { 999603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE, 1009603b61dSJack Morgenstein .log_max_qp = 12, 1019603b61dSJack Morgenstein }, 1029603b61dSJack Morgenstein [2] = { 1039603b61dSJack Morgenstein .mask = MLX5_PROF_MASK_QP_SIZE | 1049603b61dSJack Morgenstein MLX5_PROF_MASK_MR_CACHE, 1055f40b4edSMaor Gottlieb .log_max_qp = 18, 1069603b61dSJack Morgenstein .mr_cache[0] = { 1079603b61dSJack Morgenstein .size = 500, 1089603b61dSJack Morgenstein .limit = 250 1099603b61dSJack Morgenstein }, 1109603b61dSJack Morgenstein .mr_cache[1] = { 1119603b61dSJack Morgenstein .size = 500, 1129603b61dSJack Morgenstein .limit = 250 1139603b61dSJack Morgenstein }, 1149603b61dSJack Morgenstein .mr_cache[2] = { 1159603b61dSJack Morgenstein .size = 500, 1169603b61dSJack Morgenstein .limit = 250 1179603b61dSJack Morgenstein }, 1189603b61dSJack Morgenstein .mr_cache[3] = { 1199603b61dSJack Morgenstein .size = 500, 1209603b61dSJack Morgenstein .limit = 250 1219603b61dSJack Morgenstein }, 1229603b61dSJack Morgenstein .mr_cache[4] = { 1239603b61dSJack Morgenstein .size = 500, 1249603b61dSJack Morgenstein .limit = 250 1259603b61dSJack Morgenstein }, 1269603b61dSJack Morgenstein .mr_cache[5] = { 1279603b61dSJack Morgenstein .size = 500, 1289603b61dSJack Morgenstein .limit = 250 1299603b61dSJack Morgenstein }, 1309603b61dSJack Morgenstein .mr_cache[6] = { 1319603b61dSJack Morgenstein .size = 500, 1329603b61dSJack Morgenstein .limit = 250 1339603b61dSJack Morgenstein }, 1349603b61dSJack Morgenstein .mr_cache[7] = { 1359603b61dSJack Morgenstein .size = 500, 1369603b61dSJack Morgenstein .limit = 250 1379603b61dSJack Morgenstein }, 1389603b61dSJack Morgenstein .mr_cache[8] = { 1399603b61dSJack Morgenstein .size = 500, 1409603b61dSJack Morgenstein .limit = 250 1419603b61dSJack Morgenstein }, 1429603b61dSJack Morgenstein .mr_cache[9] = { 1439603b61dSJack Morgenstein .size = 500, 1449603b61dSJack Morgenstein .limit = 250 1459603b61dSJack Morgenstein }, 1469603b61dSJack Morgenstein .mr_cache[10] = { 1479603b61dSJack Morgenstein .size = 500, 1489603b61dSJack Morgenstein .limit = 250 1499603b61dSJack Morgenstein }, 1509603b61dSJack Morgenstein .mr_cache[11] = { 1519603b61dSJack Morgenstein .size = 500, 1529603b61dSJack Morgenstein .limit = 250 1539603b61dSJack Morgenstein }, 1549603b61dSJack Morgenstein .mr_cache[12] = { 1559603b61dSJack Morgenstein .size = 64, 1569603b61dSJack Morgenstein .limit = 32 1579603b61dSJack Morgenstein }, 1589603b61dSJack Morgenstein .mr_cache[13] = { 1599603b61dSJack Morgenstein .size = 32, 1609603b61dSJack Morgenstein .limit = 16 1619603b61dSJack Morgenstein }, 1629603b61dSJack Morgenstein .mr_cache[14] = { 1639603b61dSJack Morgenstein .size = 16, 1649603b61dSJack Morgenstein .limit = 8 1659603b61dSJack Morgenstein }, 1669603b61dSJack Morgenstein .mr_cache[15] = { 1679603b61dSJack Morgenstein .size = 8, 1689603b61dSJack Morgenstein .limit = 4 1699603b61dSJack Morgenstein }, 1709603b61dSJack Morgenstein }, 1719603b61dSJack Morgenstein }; 172e126ba97SEli Cohen 173e3297246SEli Cohen #define FW_INIT_TIMEOUT_MILI 2000 174e3297246SEli Cohen #define FW_INIT_WAIT_MS 2 175b8a92577SDaniel Jurgens #define FW_PRE_INIT_TIMEOUT_MILI 120000 176b8a92577SDaniel Jurgens #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 177e3297246SEli Cohen 178b8a92577SDaniel Jurgens static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 179b8a92577SDaniel Jurgens u32 warn_time_mili) 180e3297246SEli Cohen { 181b8a92577SDaniel Jurgens unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 182e3297246SEli Cohen unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 183e3297246SEli Cohen int err = 0; 184e3297246SEli Cohen 185b8a92577SDaniel Jurgens BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 186b8a92577SDaniel Jurgens 187e3297246SEli Cohen while (fw_initializing(dev)) { 188e3297246SEli Cohen if (time_after(jiffies, end)) { 189e3297246SEli Cohen err = -EBUSY; 190e3297246SEli Cohen break; 191e3297246SEli Cohen } 192b8a92577SDaniel Jurgens if (warn_time_mili && time_after(jiffies, warn)) { 193b8a92577SDaniel Jurgens mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 194b8a92577SDaniel Jurgens jiffies_to_msecs(end - warn) / 1000); 195b8a92577SDaniel Jurgens warn = jiffies + msecs_to_jiffies(warn_time_mili); 196b8a92577SDaniel Jurgens } 197e3297246SEli Cohen msleep(FW_INIT_WAIT_MS); 198e3297246SEli Cohen } 199e3297246SEli Cohen 200e3297246SEli Cohen return err; 201e3297246SEli Cohen } 202e3297246SEli Cohen 203012e50e1SHuy Nguyen static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 204012e50e1SHuy Nguyen { 205012e50e1SHuy Nguyen int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 206012e50e1SHuy Nguyen driver_version); 207012e50e1SHuy Nguyen u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; 208012e50e1SHuy Nguyen u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; 209012e50e1SHuy Nguyen int remaining_size = driver_ver_sz; 210012e50e1SHuy Nguyen char *string; 211012e50e1SHuy Nguyen 212012e50e1SHuy Nguyen if (!MLX5_CAP_GEN(dev, driver_version)) 213012e50e1SHuy Nguyen return; 214012e50e1SHuy Nguyen 215012e50e1SHuy Nguyen string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 216012e50e1SHuy Nguyen 217012e50e1SHuy Nguyen strncpy(string, "Linux", remaining_size); 218012e50e1SHuy Nguyen 219012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 220012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 221012e50e1SHuy Nguyen 222012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 223012e50e1SHuy Nguyen strncat(string, DRIVER_NAME, remaining_size); 224012e50e1SHuy Nguyen 225012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 226012e50e1SHuy Nguyen strncat(string, ",", remaining_size); 227012e50e1SHuy Nguyen 228012e50e1SHuy Nguyen remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229012e50e1SHuy Nguyen strncat(string, DRIVER_VERSION, remaining_size); 230012e50e1SHuy Nguyen 231012e50e1SHuy Nguyen /*Send the command*/ 232012e50e1SHuy Nguyen MLX5_SET(set_driver_version_in, in, opcode, 233012e50e1SHuy Nguyen MLX5_CMD_OP_SET_DRIVER_VERSION); 234012e50e1SHuy Nguyen 235012e50e1SHuy Nguyen mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 236012e50e1SHuy Nguyen } 237012e50e1SHuy Nguyen 238e126ba97SEli Cohen static int set_dma_caps(struct pci_dev *pdev) 239e126ba97SEli Cohen { 240e126ba97SEli Cohen int err; 241e126ba97SEli Cohen 242e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 243e126ba97SEli Cohen if (err) { 2441a91de28SJoe Perches dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 245e126ba97SEli Cohen err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 246e126ba97SEli Cohen if (err) { 2471a91de28SJoe Perches dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 248e126ba97SEli Cohen return err; 249e126ba97SEli Cohen } 250e126ba97SEli Cohen } 251e126ba97SEli Cohen 252e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 253e126ba97SEli Cohen if (err) { 254e126ba97SEli Cohen dev_warn(&pdev->dev, 2551a91de28SJoe Perches "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 256e126ba97SEli Cohen err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 257e126ba97SEli Cohen if (err) { 258e126ba97SEli Cohen dev_err(&pdev->dev, 2591a91de28SJoe Perches "Can't set consistent PCI DMA mask, aborting\n"); 260e126ba97SEli Cohen return err; 261e126ba97SEli Cohen } 262e126ba97SEli Cohen } 263e126ba97SEli Cohen 264e126ba97SEli Cohen dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 265e126ba97SEli Cohen return err; 266e126ba97SEli Cohen } 267e126ba97SEli Cohen 26889d44f0aSMajd Dibbiny static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 26989d44f0aSMajd Dibbiny { 27089d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 27189d44f0aSMajd Dibbiny int err = 0; 27289d44f0aSMajd Dibbiny 27389d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 27489d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 27589d44f0aSMajd Dibbiny err = pci_enable_device(pdev); 27689d44f0aSMajd Dibbiny if (!err) 27789d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_ENABLED; 27889d44f0aSMajd Dibbiny } 27989d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 28089d44f0aSMajd Dibbiny 28189d44f0aSMajd Dibbiny return err; 28289d44f0aSMajd Dibbiny } 28389d44f0aSMajd Dibbiny 28489d44f0aSMajd Dibbiny static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 28589d44f0aSMajd Dibbiny { 28689d44f0aSMajd Dibbiny struct pci_dev *pdev = dev->pdev; 28789d44f0aSMajd Dibbiny 28889d44f0aSMajd Dibbiny mutex_lock(&dev->pci_status_mutex); 28989d44f0aSMajd Dibbiny if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 29089d44f0aSMajd Dibbiny pci_disable_device(pdev); 29189d44f0aSMajd Dibbiny dev->pci_status = MLX5_PCI_STATUS_DISABLED; 29289d44f0aSMajd Dibbiny } 29389d44f0aSMajd Dibbiny mutex_unlock(&dev->pci_status_mutex); 29489d44f0aSMajd Dibbiny } 29589d44f0aSMajd Dibbiny 296e126ba97SEli Cohen static int request_bar(struct pci_dev *pdev) 297e126ba97SEli Cohen { 298e126ba97SEli Cohen int err = 0; 299e126ba97SEli Cohen 300e126ba97SEli Cohen if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3011a91de28SJoe Perches dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 302e126ba97SEli Cohen return -ENODEV; 303e126ba97SEli Cohen } 304e126ba97SEli Cohen 305e126ba97SEli Cohen err = pci_request_regions(pdev, DRIVER_NAME); 306e126ba97SEli Cohen if (err) 307e126ba97SEli Cohen dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 308e126ba97SEli Cohen 309e126ba97SEli Cohen return err; 310e126ba97SEli Cohen } 311e126ba97SEli Cohen 312e126ba97SEli Cohen static void release_bar(struct pci_dev *pdev) 313e126ba97SEli Cohen { 314e126ba97SEli Cohen pci_release_regions(pdev); 315e126ba97SEli Cohen } 316e126ba97SEli Cohen 317bd10838aSOr Gerlitz struct mlx5_reg_host_endianness { 318e126ba97SEli Cohen u8 he; 319e126ba97SEli Cohen u8 rsvd[15]; 320e126ba97SEli Cohen }; 321e126ba97SEli Cohen 32287b8de49SEli Cohen #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 32387b8de49SEli Cohen 32487b8de49SEli Cohen enum { 32587b8de49SEli Cohen MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 326c7a08ac7SEli Cohen MLX5_DEV_CAP_FLAG_DCT, 32787b8de49SEli Cohen }; 32887b8de49SEli Cohen 3292974ab6eSSaeed Mahameed static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 330c7a08ac7SEli Cohen { 331c7a08ac7SEli Cohen switch (size) { 332c7a08ac7SEli Cohen case 128: 333c7a08ac7SEli Cohen return 0; 334c7a08ac7SEli Cohen case 256: 335c7a08ac7SEli Cohen return 1; 336c7a08ac7SEli Cohen case 512: 337c7a08ac7SEli Cohen return 2; 338c7a08ac7SEli Cohen case 1024: 339c7a08ac7SEli Cohen return 3; 340c7a08ac7SEli Cohen case 2048: 341c7a08ac7SEli Cohen return 4; 342c7a08ac7SEli Cohen case 4096: 343c7a08ac7SEli Cohen return 5; 344c7a08ac7SEli Cohen default: 3452974ab6eSSaeed Mahameed mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 346c7a08ac7SEli Cohen return 0; 347c7a08ac7SEli Cohen } 348c7a08ac7SEli Cohen } 349c7a08ac7SEli Cohen 350b06e7de8SLeon Romanovsky static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 351b06e7de8SLeon Romanovsky enum mlx5_cap_type cap_type, 352938fe83cSSaeed Mahameed enum mlx5_cap_mode cap_mode) 353c7a08ac7SEli Cohen { 354b775516bSEli Cohen u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 355b775516bSEli Cohen int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 356938fe83cSSaeed Mahameed void *out, *hca_caps; 357938fe83cSSaeed Mahameed u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 358c7a08ac7SEli Cohen int err; 359c7a08ac7SEli Cohen 360b775516bSEli Cohen memset(in, 0, sizeof(in)); 361b775516bSEli Cohen out = kzalloc(out_sz, GFP_KERNEL); 362c7a08ac7SEli Cohen if (!out) 363c7a08ac7SEli Cohen return -ENOMEM; 364938fe83cSSaeed Mahameed 365b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 366b775516bSEli Cohen MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 367b775516bSEli Cohen err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 368c7a08ac7SEli Cohen if (err) { 369938fe83cSSaeed Mahameed mlx5_core_warn(dev, 370938fe83cSSaeed Mahameed "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 371938fe83cSSaeed Mahameed cap_type, cap_mode, err); 372c7a08ac7SEli Cohen goto query_ex; 373c7a08ac7SEli Cohen } 374c7a08ac7SEli Cohen 375938fe83cSSaeed Mahameed hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 376938fe83cSSaeed Mahameed 377938fe83cSSaeed Mahameed switch (cap_mode) { 378938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_MAX: 379701052c5SGal Pressman memcpy(dev->caps.hca_max[cap_type], hca_caps, 380938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 381938fe83cSSaeed Mahameed break; 382938fe83cSSaeed Mahameed case HCA_CAP_OPMOD_GET_CUR: 383701052c5SGal Pressman memcpy(dev->caps.hca_cur[cap_type], hca_caps, 384938fe83cSSaeed Mahameed MLX5_UN_SZ_BYTES(hca_cap_union)); 385938fe83cSSaeed Mahameed break; 386938fe83cSSaeed Mahameed default: 387938fe83cSSaeed Mahameed mlx5_core_warn(dev, 388938fe83cSSaeed Mahameed "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 389938fe83cSSaeed Mahameed cap_type, cap_mode); 390938fe83cSSaeed Mahameed err = -EINVAL; 391938fe83cSSaeed Mahameed break; 392938fe83cSSaeed Mahameed } 393c7a08ac7SEli Cohen query_ex: 394c7a08ac7SEli Cohen kfree(out); 395c7a08ac7SEli Cohen return err; 396c7a08ac7SEli Cohen } 397c7a08ac7SEli Cohen 398b06e7de8SLeon Romanovsky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 399b06e7de8SLeon Romanovsky { 400b06e7de8SLeon Romanovsky int ret; 401b06e7de8SLeon Romanovsky 402b06e7de8SLeon Romanovsky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 403b06e7de8SLeon Romanovsky if (ret) 404b06e7de8SLeon Romanovsky return ret; 405b06e7de8SLeon Romanovsky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 406b06e7de8SLeon Romanovsky } 407b06e7de8SLeon Romanovsky 408f91e6d89SEran Ben Elisha static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) 409c7a08ac7SEli Cohen { 410c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 411c7a08ac7SEli Cohen 412b775516bSEli Cohen MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 413f91e6d89SEran Ben Elisha MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 414c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 415c7a08ac7SEli Cohen } 41687b8de49SEli Cohen 417f91e6d89SEran Ben Elisha static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 418f91e6d89SEran Ben Elisha { 419f91e6d89SEran Ben Elisha void *set_ctx; 420f91e6d89SEran Ben Elisha void *set_hca_cap; 421f91e6d89SEran Ben Elisha int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 422f91e6d89SEran Ben Elisha int req_endianness; 423f91e6d89SEran Ben Elisha int err; 424f91e6d89SEran Ben Elisha 425f91e6d89SEran Ben Elisha if (MLX5_CAP_GEN(dev, atomic)) { 426b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 427f91e6d89SEran Ben Elisha if (err) 428f91e6d89SEran Ben Elisha return err; 429f91e6d89SEran Ben Elisha } else { 430f91e6d89SEran Ben Elisha return 0; 431f91e6d89SEran Ben Elisha } 432f91e6d89SEran Ben Elisha 433f91e6d89SEran Ben Elisha req_endianness = 434f91e6d89SEran Ben Elisha MLX5_CAP_ATOMIC(dev, 435bd10838aSOr Gerlitz supported_atomic_req_8B_endianness_mode_1); 436f91e6d89SEran Ben Elisha 437f91e6d89SEran Ben Elisha if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 438f91e6d89SEran Ben Elisha return 0; 439f91e6d89SEran Ben Elisha 440f91e6d89SEran Ben Elisha set_ctx = kzalloc(set_sz, GFP_KERNEL); 441f91e6d89SEran Ben Elisha if (!set_ctx) 442f91e6d89SEran Ben Elisha return -ENOMEM; 443f91e6d89SEran Ben Elisha 444f91e6d89SEran Ben Elisha set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 445f91e6d89SEran Ben Elisha 446f91e6d89SEran Ben Elisha /* Set requestor to host endianness */ 447bd10838aSOr Gerlitz MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 448f91e6d89SEran Ben Elisha MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 449f91e6d89SEran Ben Elisha 450f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 451f91e6d89SEran Ben Elisha 452f91e6d89SEran Ben Elisha kfree(set_ctx); 453f91e6d89SEran Ben Elisha return err; 454f91e6d89SEran Ben Elisha } 455f91e6d89SEran Ben Elisha 45646861e3eSMoni Shoua static int handle_hca_cap_odp(struct mlx5_core_dev *dev) 45746861e3eSMoni Shoua { 45846861e3eSMoni Shoua void *set_hca_cap; 459224d71ccSLeon Romanovsky void *set_ctx; 460224d71ccSLeon Romanovsky int set_sz; 461fca22e7eSMoni Shoua bool do_set = false; 46246861e3eSMoni Shoua int err; 46346861e3eSMoni Shoua 46437b6bb77SLeon Romanovsky if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 46537b6bb77SLeon Romanovsky !MLX5_CAP_GEN(dev, pg)) 46646861e3eSMoni Shoua return 0; 46746861e3eSMoni Shoua 46846861e3eSMoni Shoua err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 46946861e3eSMoni Shoua if (err) 47046861e3eSMoni Shoua return err; 47146861e3eSMoni Shoua 472224d71ccSLeon Romanovsky set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 47346861e3eSMoni Shoua set_ctx = kzalloc(set_sz, GFP_KERNEL); 47446861e3eSMoni Shoua if (!set_ctx) 47546861e3eSMoni Shoua return -ENOMEM; 47646861e3eSMoni Shoua 47746861e3eSMoni Shoua set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 47846861e3eSMoni Shoua memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 47946861e3eSMoni Shoua MLX5_ST_SZ_BYTES(odp_cap)); 48046861e3eSMoni Shoua 481fca22e7eSMoni Shoua #define ODP_CAP_SET_MAX(dev, field) \ 482fca22e7eSMoni Shoua do { \ 483fca22e7eSMoni Shoua u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 484fca22e7eSMoni Shoua if (_res) { \ 485fca22e7eSMoni Shoua do_set = true; \ 486fca22e7eSMoni Shoua MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 487fca22e7eSMoni Shoua } \ 488fca22e7eSMoni Shoua } while (0) 48946861e3eSMoni Shoua 490fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 491fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 492fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 493fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 494fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 495fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 496fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 497fca22e7eSMoni Shoua ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 49846861e3eSMoni Shoua 499fca22e7eSMoni Shoua if (do_set) 500fca22e7eSMoni Shoua err = set_caps(dev, set_ctx, set_sz, 501fca22e7eSMoni Shoua MLX5_SET_HCA_CAP_OP_MOD_ODP); 50246861e3eSMoni Shoua 50346861e3eSMoni Shoua kfree(set_ctx); 504fca22e7eSMoni Shoua 50546861e3eSMoni Shoua return err; 50646861e3eSMoni Shoua } 50746861e3eSMoni Shoua 508e126ba97SEli Cohen static int handle_hca_cap(struct mlx5_core_dev *dev) 509e126ba97SEli Cohen { 510b775516bSEli Cohen void *set_ctx = NULL; 511c7a08ac7SEli Cohen struct mlx5_profile *prof = dev->profile; 512c7a08ac7SEli Cohen int err = -ENOMEM; 513b775516bSEli Cohen int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 514938fe83cSSaeed Mahameed void *set_hca_cap; 515e126ba97SEli Cohen 516b775516bSEli Cohen set_ctx = kzalloc(set_sz, GFP_KERNEL); 517c7a08ac7SEli Cohen if (!set_ctx) 518e126ba97SEli Cohen goto query_ex; 519e126ba97SEli Cohen 520b06e7de8SLeon Romanovsky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 521c7a08ac7SEli Cohen if (err) 522e126ba97SEli Cohen goto query_ex; 523e126ba97SEli Cohen 524938fe83cSSaeed Mahameed set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 525938fe83cSSaeed Mahameed capability); 526701052c5SGal Pressman memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 527938fe83cSSaeed Mahameed MLX5_ST_SZ_BYTES(cmd_hca_cap)); 528938fe83cSSaeed Mahameed 529938fe83cSSaeed Mahameed mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 530707c4602SMajd Dibbiny mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 531938fe83cSSaeed Mahameed 128); 532c7a08ac7SEli Cohen /* we limit the size of the pkey table to 128 entries for now */ 533938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 5342974ab6eSSaeed Mahameed to_fw_pkey_sz(dev, 128)); 535e126ba97SEli Cohen 536883371c4SNoa Osherovich /* Check log_max_qp from HCA caps to set in current profile */ 537883371c4SNoa Osherovich if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 538883371c4SNoa Osherovich mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 539883371c4SNoa Osherovich profile[prof_sel].log_max_qp, 540883371c4SNoa Osherovich MLX5_CAP_GEN_MAX(dev, log_max_qp)); 541883371c4SNoa Osherovich profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 542883371c4SNoa Osherovich } 543c7a08ac7SEli Cohen if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 544938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 545938fe83cSSaeed Mahameed prof->log_max_qp); 546e126ba97SEli Cohen 547938fe83cSSaeed Mahameed /* disable cmdif checksum */ 548938fe83cSSaeed Mahameed MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 549c1868b82SEli Cohen 55091828bd8SMajd Dibbiny /* Enable 4K UAR only when HCA supports it and page size is bigger 55191828bd8SMajd Dibbiny * than 4K. 55291828bd8SMajd Dibbiny */ 55391828bd8SMajd Dibbiny if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 554f502d834SEli Cohen MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 555f502d834SEli Cohen 556fe1e1876SCarol L Soto MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 557fe1e1876SCarol L Soto 558f32f5bd2SDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 559f32f5bd2SDaniel Jurgens MLX5_SET(cmd_hca_cap, 560f32f5bd2SDaniel Jurgens set_hca_cap, 561f32f5bd2SDaniel Jurgens cache_line_128byte, 562c67f100eSDaniel Jurgens cache_line_size() >= 128 ? 1 : 0); 563f32f5bd2SDaniel Jurgens 564dd44572aSMoni Shoua if (MLX5_CAP_GEN_MAX(dev, dct)) 565dd44572aSMoni Shoua MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 566dd44572aSMoni Shoua 567c4b76d8dSDaniel Jurgens if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 568c4b76d8dSDaniel Jurgens MLX5_SET(cmd_hca_cap, 569c4b76d8dSDaniel Jurgens set_hca_cap, 570c4b76d8dSDaniel Jurgens num_vhca_ports, 571c4b76d8dSDaniel Jurgens MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 572c4b76d8dSDaniel Jurgens 573f91e6d89SEran Ben Elisha err = set_caps(dev, set_ctx, set_sz, 574f91e6d89SEran Ben Elisha MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 575e126ba97SEli Cohen 576e126ba97SEli Cohen query_ex: 577e126ba97SEli Cohen kfree(set_ctx); 578e126ba97SEli Cohen return err; 579e126ba97SEli Cohen } 580e126ba97SEli Cohen 58137b6bb77SLeon Romanovsky static int set_hca_cap(struct mlx5_core_dev *dev) 58237b6bb77SLeon Romanovsky { 58337b6bb77SLeon Romanovsky int err; 58437b6bb77SLeon Romanovsky 58537b6bb77SLeon Romanovsky err = handle_hca_cap(dev); 58637b6bb77SLeon Romanovsky if (err) { 58798a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap failed\n"); 58837b6bb77SLeon Romanovsky goto out; 58937b6bb77SLeon Romanovsky } 59037b6bb77SLeon Romanovsky 59137b6bb77SLeon Romanovsky err = handle_hca_cap_atomic(dev); 59237b6bb77SLeon Romanovsky if (err) { 59398a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 59437b6bb77SLeon Romanovsky goto out; 59537b6bb77SLeon Romanovsky } 59637b6bb77SLeon Romanovsky 59737b6bb77SLeon Romanovsky err = handle_hca_cap_odp(dev); 59837b6bb77SLeon Romanovsky if (err) { 59998a8e6fcSHuy Nguyen mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 60037b6bb77SLeon Romanovsky goto out; 60137b6bb77SLeon Romanovsky } 60237b6bb77SLeon Romanovsky 60337b6bb77SLeon Romanovsky out: 60437b6bb77SLeon Romanovsky return err; 60537b6bb77SLeon Romanovsky } 60637b6bb77SLeon Romanovsky 607e126ba97SEli Cohen static int set_hca_ctrl(struct mlx5_core_dev *dev) 608e126ba97SEli Cohen { 609bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_in; 610bd10838aSOr Gerlitz struct mlx5_reg_host_endianness he_out; 611e126ba97SEli Cohen int err; 612e126ba97SEli Cohen 613fc50db98SEli Cohen if (!mlx5_core_is_pf(dev)) 614fc50db98SEli Cohen return 0; 615fc50db98SEli Cohen 616e126ba97SEli Cohen memset(&he_in, 0, sizeof(he_in)); 617e126ba97SEli Cohen he_in.he = MLX5_SET_HOST_ENDIANNESS; 618e126ba97SEli Cohen err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 619e126ba97SEli Cohen &he_out, sizeof(he_out), 620e126ba97SEli Cohen MLX5_REG_HOST_ENDIANNESS, 0, 1); 621e126ba97SEli Cohen return err; 622e126ba97SEli Cohen } 623e126ba97SEli Cohen 624c85023e1SHuy Nguyen static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 625c85023e1SHuy Nguyen { 626c85023e1SHuy Nguyen int ret = 0; 627c85023e1SHuy Nguyen 628c85023e1SHuy Nguyen /* Disable local_lb by default */ 6298978cc92SEran Ben Elisha if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 630c85023e1SHuy Nguyen ret = mlx5_nic_vport_update_local_lb(dev, false); 631c85023e1SHuy Nguyen 632c85023e1SHuy Nguyen return ret; 633c85023e1SHuy Nguyen } 634c85023e1SHuy Nguyen 6350b107106SEli Cohen int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 636cd23b14bSEli Cohen { 637c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 638c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 639cd23b14bSEli Cohen 6400b107106SEli Cohen MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 6410b107106SEli Cohen MLX5_SET(enable_hca_in, in, function_id, func_id); 64222e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 64322e939a9SBodong Wang dev->caps.embedded_cpu); 644c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 645cd23b14bSEli Cohen } 646cd23b14bSEli Cohen 6470b107106SEli Cohen int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 648cd23b14bSEli Cohen { 649c4f287c4SSaeed Mahameed u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 650c4f287c4SSaeed Mahameed u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 651cd23b14bSEli Cohen 6520b107106SEli Cohen MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 6530b107106SEli Cohen MLX5_SET(disable_hca_in, in, function_id, func_id); 65422e939a9SBodong Wang MLX5_SET(enable_hca_in, in, embedded_cpu_function, 65522e939a9SBodong Wang dev->caps.embedded_cpu); 656c4f287c4SSaeed Mahameed return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 657cd23b14bSEli Cohen } 658cd23b14bSEli Cohen 6594a0475d5SMiroslav Lichvar u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 6604a0475d5SMiroslav Lichvar struct ptp_system_timestamp *sts) 661b0844444SEran Ben Elisha { 662b0844444SEran Ben Elisha u32 timer_h, timer_h1, timer_l; 663b0844444SEran Ben Elisha 664b0844444SEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 6654a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 666b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6674a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 668b0844444SEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 6694a0475d5SMiroslav Lichvar if (timer_h != timer_h1) { 6704a0475d5SMiroslav Lichvar /* wrap around */ 6714a0475d5SMiroslav Lichvar ptp_read_system_prets(sts); 672b0844444SEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 6734a0475d5SMiroslav Lichvar ptp_read_system_postts(sts); 6744a0475d5SMiroslav Lichvar } 675b0844444SEran Ben Elisha 676a5a1d1c2SThomas Gleixner return (u64)timer_l | (u64)timer_h1 << 32; 677b0844444SEran Ben Elisha } 678b0844444SEran Ben Elisha 679f62b8bb8SAmir Vadai static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 680f62b8bb8SAmir Vadai { 681c4f287c4SSaeed Mahameed u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 682c4f287c4SSaeed Mahameed u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 683f62b8bb8SAmir Vadai u32 sup_issi; 684c4f287c4SSaeed Mahameed int err; 685f62b8bb8SAmir Vadai 686f62b8bb8SAmir Vadai MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 687c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), 688f62b8bb8SAmir Vadai query_out, sizeof(query_out)); 689f62b8bb8SAmir Vadai if (err) { 690c4f287c4SSaeed Mahameed u32 syndrome; 691c4f287c4SSaeed Mahameed u8 status; 692c4f287c4SSaeed Mahameed 693c4f287c4SSaeed Mahameed mlx5_cmd_mbox_status(query_out, &status, &syndrome); 694f9c14e46SKamal Heib if (!status || syndrome == MLX5_DRIVER_SYND) { 695f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 696f9c14e46SKamal Heib err, status, syndrome); 697f9c14e46SKamal Heib return err; 698f62b8bb8SAmir Vadai } 699f62b8bb8SAmir Vadai 700f9c14e46SKamal Heib mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 701f9c14e46SKamal Heib dev->issi = 0; 702f9c14e46SKamal Heib return 0; 703f62b8bb8SAmir Vadai } 704f62b8bb8SAmir Vadai 705f62b8bb8SAmir Vadai sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 706f62b8bb8SAmir Vadai 707f62b8bb8SAmir Vadai if (sup_issi & (1 << 1)) { 708c4f287c4SSaeed Mahameed u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 709c4f287c4SSaeed Mahameed u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 710f62b8bb8SAmir Vadai 711f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 712f62b8bb8SAmir Vadai MLX5_SET(set_issi_in, set_in, current_issi, 1); 713c4f287c4SSaeed Mahameed err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), 714f62b8bb8SAmir Vadai set_out, sizeof(set_out)); 715f62b8bb8SAmir Vadai if (err) { 716f9c14e46SKamal Heib mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 717f9c14e46SKamal Heib err); 718f62b8bb8SAmir Vadai return err; 719f62b8bb8SAmir Vadai } 720f62b8bb8SAmir Vadai 721f62b8bb8SAmir Vadai dev->issi = 1; 722f62b8bb8SAmir Vadai 723f62b8bb8SAmir Vadai return 0; 724e74a1db0SHaggai Abramonvsky } else if (sup_issi & (1 << 0) || !sup_issi) { 725f62b8bb8SAmir Vadai return 0; 726f62b8bb8SAmir Vadai } 727f62b8bb8SAmir Vadai 7289eb78923SOr Gerlitz return -EOPNOTSUPP; 729f62b8bb8SAmir Vadai } 730f62b8bb8SAmir Vadai 73111f3b84dSSaeed Mahameed static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 73211f3b84dSSaeed Mahameed const struct pci_device_id *id) 733a31208b1SMajd Dibbiny { 734868bc06bSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 735a31208b1SMajd Dibbiny int err = 0; 736a31208b1SMajd Dibbiny 737d22663edSParav Pandit mutex_init(&dev->pci_status_mutex); 738e126ba97SEli Cohen pci_set_drvdata(dev->pdev, dev); 739e126ba97SEli Cohen 740aa8106f1SHuy Nguyen dev->bar_addr = pci_resource_start(pdev, 0); 741311c7c71SSaeed Mahameed priv->numa_node = dev_to_node(&dev->pdev->dev); 742311c7c71SSaeed Mahameed 74389d44f0aSMajd Dibbiny err = mlx5_pci_enable_device(dev); 744e126ba97SEli Cohen if (err) { 74598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 74611f3b84dSSaeed Mahameed return err; 747e126ba97SEli Cohen } 748e126ba97SEli Cohen 749e126ba97SEli Cohen err = request_bar(pdev); 750e126ba97SEli Cohen if (err) { 75198a8e6fcSHuy Nguyen mlx5_core_err(dev, "error requesting BARs, aborting\n"); 752e126ba97SEli Cohen goto err_disable; 753e126ba97SEli Cohen } 754e126ba97SEli Cohen 755e126ba97SEli Cohen pci_set_master(pdev); 756e126ba97SEli Cohen 757e126ba97SEli Cohen err = set_dma_caps(pdev); 758e126ba97SEli Cohen if (err) { 75998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 760e126ba97SEli Cohen goto err_clr_master; 761e126ba97SEli Cohen } 762e126ba97SEli Cohen 763ce4eee53SMichael Guralnik if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 764ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 765ce4eee53SMichael Guralnik pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 766ce4eee53SMichael Guralnik mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 767ce4eee53SMichael Guralnik 768aa8106f1SHuy Nguyen dev->iseg_base = dev->bar_addr; 769e126ba97SEli Cohen dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 770e126ba97SEli Cohen if (!dev->iseg) { 771e126ba97SEli Cohen err = -ENOMEM; 77298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 773e126ba97SEli Cohen goto err_clr_master; 774e126ba97SEli Cohen } 775a31208b1SMajd Dibbiny 776b25bbc2fSAlex Vesker mlx5_pci_vsc_init(dev); 777b25bbc2fSAlex Vesker 778a31208b1SMajd Dibbiny return 0; 779a31208b1SMajd Dibbiny 780a31208b1SMajd Dibbiny err_clr_master: 781a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 782a31208b1SMajd Dibbiny release_bar(dev->pdev); 783a31208b1SMajd Dibbiny err_disable: 78489d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 785a31208b1SMajd Dibbiny return err; 786a31208b1SMajd Dibbiny } 787a31208b1SMajd Dibbiny 788868bc06bSSaeed Mahameed static void mlx5_pci_close(struct mlx5_core_dev *dev) 789a31208b1SMajd Dibbiny { 790a31208b1SMajd Dibbiny iounmap(dev->iseg); 791a31208b1SMajd Dibbiny pci_clear_master(dev->pdev); 792a31208b1SMajd Dibbiny release_bar(dev->pdev); 79389d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 794a31208b1SMajd Dibbiny } 795a31208b1SMajd Dibbiny 796868bc06bSSaeed Mahameed static int mlx5_init_once(struct mlx5_core_dev *dev) 79759211bd3SMohamad Haj Yahia { 79859211bd3SMohamad Haj Yahia int err; 79959211bd3SMohamad Haj Yahia 800868bc06bSSaeed Mahameed dev->priv.devcom = mlx5_devcom_register_device(dev); 801868bc06bSSaeed Mahameed if (IS_ERR(dev->priv.devcom)) 80298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 803868bc06bSSaeed Mahameed dev->priv.devcom); 804fadd59fcSAviv Heller 80559211bd3SMohamad Haj Yahia err = mlx5_query_board_id(dev); 80659211bd3SMohamad Haj Yahia if (err) { 80798a8e6fcSHuy Nguyen mlx5_core_err(dev, "query board id failed\n"); 808fadd59fcSAviv Heller goto err_devcom; 80959211bd3SMohamad Haj Yahia } 81059211bd3SMohamad Haj Yahia 811561aa15aSYuval Avnery err = mlx5_irq_table_init(dev); 812561aa15aSYuval Avnery if (err) { 813561aa15aSYuval Avnery mlx5_core_err(dev, "failed to initialize irq table\n"); 814561aa15aSYuval Avnery goto err_devcom; 815561aa15aSYuval Avnery } 816561aa15aSYuval Avnery 817f2f3df55SSaeed Mahameed err = mlx5_eq_table_init(dev); 81859211bd3SMohamad Haj Yahia if (err) { 81998a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize eq\n"); 820561aa15aSYuval Avnery goto err_irq_cleanup; 82159211bd3SMohamad Haj Yahia } 82259211bd3SMohamad Haj Yahia 82369c1280bSSaeed Mahameed err = mlx5_events_init(dev); 82469c1280bSSaeed Mahameed if (err) { 82598a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize events\n"); 82669c1280bSSaeed Mahameed goto err_eq_cleanup; 82769c1280bSSaeed Mahameed } 82869c1280bSSaeed Mahameed 82902d92f79SSaeed Mahameed err = mlx5_cq_debugfs_init(dev); 83059211bd3SMohamad Haj Yahia if (err) { 83198a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to initialize cq debugfs\n"); 83269c1280bSSaeed Mahameed goto err_events_cleanup; 83359211bd3SMohamad Haj Yahia } 83459211bd3SMohamad Haj Yahia 83559211bd3SMohamad Haj Yahia mlx5_init_qp_table(dev); 83659211bd3SMohamad Haj Yahia 83759211bd3SMohamad Haj Yahia mlx5_init_mkey_table(dev); 83859211bd3SMohamad Haj Yahia 83952ec462eSIlan Tayari mlx5_init_reserved_gids(dev); 84052ec462eSIlan Tayari 8417c39afb3SFeras Daoud mlx5_init_clock(dev); 8427c39afb3SFeras Daoud 843358aa5ceSSaeed Mahameed dev->vxlan = mlx5_vxlan_create(dev); 8440ccc171eSYevgeny Kliteynik dev->geneve = mlx5_geneve_create(dev); 845358aa5ceSSaeed Mahameed 84659211bd3SMohamad Haj Yahia err = mlx5_init_rl_table(dev); 84759211bd3SMohamad Haj Yahia if (err) { 84898a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init rate limiting\n"); 84959211bd3SMohamad Haj Yahia goto err_tables_cleanup; 85059211bd3SMohamad Haj Yahia } 85159211bd3SMohamad Haj Yahia 852eeb66cdbSSaeed Mahameed err = mlx5_mpfs_init(dev); 853eeb66cdbSSaeed Mahameed if (err) { 85498a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 855eeb66cdbSSaeed Mahameed goto err_rl_cleanup; 856eeb66cdbSSaeed Mahameed } 857eeb66cdbSSaeed Mahameed 858c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_init(dev); 859c2d6e31aSMohamad Haj Yahia if (err) { 86098a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init sriov %d\n", err); 86186eec50bSBodong Wang goto err_mpfs_cleanup; 86286eec50bSBodong Wang } 86386eec50bSBodong Wang 86486eec50bSBodong Wang err = mlx5_eswitch_init(dev); 86586eec50bSBodong Wang if (err) { 86686eec50bSBodong Wang mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 86786eec50bSBodong Wang goto err_sriov_cleanup; 868c2d6e31aSMohamad Haj Yahia } 869c2d6e31aSMohamad Haj Yahia 8709410733cSIlan Tayari err = mlx5_fpga_init(dev); 8719410733cSIlan Tayari if (err) { 87298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 87386eec50bSBodong Wang goto err_eswitch_cleanup; 8749410733cSIlan Tayari } 8759410733cSIlan Tayari 87624406953SFeras Daoud dev->tracer = mlx5_fw_tracer_create(dev); 87724406953SFeras Daoud 87859211bd3SMohamad Haj Yahia return 0; 87959211bd3SMohamad Haj Yahia 880c2d6e31aSMohamad Haj Yahia err_eswitch_cleanup: 881c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 88286eec50bSBodong Wang err_sriov_cleanup: 88386eec50bSBodong Wang mlx5_sriov_cleanup(dev); 884eeb66cdbSSaeed Mahameed err_mpfs_cleanup: 885eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 886c2d6e31aSMohamad Haj Yahia err_rl_cleanup: 887c2d6e31aSMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 88859211bd3SMohamad Haj Yahia err_tables_cleanup: 8890ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 890358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 89159211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 89259211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 89302d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 89469c1280bSSaeed Mahameed err_events_cleanup: 89569c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 89659211bd3SMohamad Haj Yahia err_eq_cleanup: 897f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 898561aa15aSYuval Avnery err_irq_cleanup: 899561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 900fadd59fcSAviv Heller err_devcom: 901fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 90259211bd3SMohamad Haj Yahia 90359211bd3SMohamad Haj Yahia return err; 90459211bd3SMohamad Haj Yahia } 90559211bd3SMohamad Haj Yahia 90659211bd3SMohamad Haj Yahia static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 90759211bd3SMohamad Haj Yahia { 90824406953SFeras Daoud mlx5_fw_tracer_destroy(dev->tracer); 9099410733cSIlan Tayari mlx5_fpga_cleanup(dev); 910c2d6e31aSMohamad Haj Yahia mlx5_eswitch_cleanup(dev->priv.eswitch); 91186eec50bSBodong Wang mlx5_sriov_cleanup(dev); 912eeb66cdbSSaeed Mahameed mlx5_mpfs_cleanup(dev); 91359211bd3SMohamad Haj Yahia mlx5_cleanup_rl_table(dev); 9140ccc171eSYevgeny Kliteynik mlx5_geneve_destroy(dev->geneve); 915358aa5ceSSaeed Mahameed mlx5_vxlan_destroy(dev->vxlan); 9167c39afb3SFeras Daoud mlx5_cleanup_clock(dev); 91752ec462eSIlan Tayari mlx5_cleanup_reserved_gids(dev); 91859211bd3SMohamad Haj Yahia mlx5_cleanup_mkey_table(dev); 91959211bd3SMohamad Haj Yahia mlx5_cleanup_qp_table(dev); 92002d92f79SSaeed Mahameed mlx5_cq_debugfs_cleanup(dev); 92169c1280bSSaeed Mahameed mlx5_events_cleanup(dev); 922f2f3df55SSaeed Mahameed mlx5_eq_table_cleanup(dev); 923561aa15aSYuval Avnery mlx5_irq_table_cleanup(dev); 924fadd59fcSAviv Heller mlx5_devcom_unregister_device(dev->priv.devcom); 92559211bd3SMohamad Haj Yahia } 92659211bd3SMohamad Haj Yahia 927e161105eSSaeed Mahameed static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 928a31208b1SMajd Dibbiny { 929a31208b1SMajd Dibbiny int err; 930a31208b1SMajd Dibbiny 93198a8e6fcSHuy Nguyen mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 932e126ba97SEli Cohen fw_rev_min(dev), fw_rev_sub(dev)); 933e126ba97SEli Cohen 93400c6bcb0STal Gilboa /* Only PFs hold the relevant PCIe information for this query */ 93500c6bcb0STal Gilboa if (mlx5_core_is_pf(dev)) 93600c6bcb0STal Gilboa pcie_print_link_status(dev->pdev); 93700c6bcb0STal Gilboa 9386c780a02SEli Cohen /* wait for firmware to accept initialization segments configurations 9396c780a02SEli Cohen */ 940b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 9416c780a02SEli Cohen if (err) { 94298a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 9436c780a02SEli Cohen FW_PRE_INIT_TIMEOUT_MILI); 944e161105eSSaeed Mahameed return err; 9456c780a02SEli Cohen } 9466c780a02SEli Cohen 947e126ba97SEli Cohen err = mlx5_cmd_init(dev); 948e126ba97SEli Cohen if (err) { 94998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 950e161105eSSaeed Mahameed return err; 951e126ba97SEli Cohen } 952e126ba97SEli Cohen 953b8a92577SDaniel Jurgens err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 954e3297246SEli Cohen if (err) { 95598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 956e3297246SEli Cohen FW_INIT_TIMEOUT_MILI); 95755378a23SMohamad Haj Yahia goto err_cmd_cleanup; 958e3297246SEli Cohen } 959e3297246SEli Cohen 9600b107106SEli Cohen err = mlx5_core_enable_hca(dev, 0); 961cd23b14bSEli Cohen if (err) { 96298a8e6fcSHuy Nguyen mlx5_core_err(dev, "enable hca failed\n"); 96359211bd3SMohamad Haj Yahia goto err_cmd_cleanup; 964cd23b14bSEli Cohen } 965cd23b14bSEli Cohen 966f62b8bb8SAmir Vadai err = mlx5_core_set_issi(dev); 967f62b8bb8SAmir Vadai if (err) { 96898a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to set issi\n"); 969f62b8bb8SAmir Vadai goto err_disable_hca; 970f62b8bb8SAmir Vadai } 971f62b8bb8SAmir Vadai 972cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 1); 973cd23b14bSEli Cohen if (err) { 97498a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate boot pages\n"); 975cd23b14bSEli Cohen goto err_disable_hca; 976cd23b14bSEli Cohen } 977cd23b14bSEli Cohen 978e126ba97SEli Cohen err = set_hca_ctrl(dev); 979e126ba97SEli Cohen if (err) { 98098a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_ctrl failed\n"); 981cd23b14bSEli Cohen goto reclaim_boot_pages; 982e126ba97SEli Cohen } 983e126ba97SEli Cohen 98437b6bb77SLeon Romanovsky err = set_hca_cap(dev); 985e126ba97SEli Cohen if (err) { 98698a8e6fcSHuy Nguyen mlx5_core_err(dev, "set_hca_cap failed\n"); 98746861e3eSMoni Shoua goto reclaim_boot_pages; 98846861e3eSMoni Shoua } 98946861e3eSMoni Shoua 990cd23b14bSEli Cohen err = mlx5_satisfy_startup_pages(dev, 0); 991e126ba97SEli Cohen if (err) { 99298a8e6fcSHuy Nguyen mlx5_core_err(dev, "failed to allocate init pages\n"); 993cd23b14bSEli Cohen goto reclaim_boot_pages; 994e126ba97SEli Cohen } 995e126ba97SEli Cohen 9968737f818SDaniel Jurgens err = mlx5_cmd_init_hca(dev, sw_owner_id); 997e126ba97SEli Cohen if (err) { 99898a8e6fcSHuy Nguyen mlx5_core_err(dev, "init hca failed\n"); 9990cf53c12SSaeed Mahameed goto reclaim_boot_pages; 1000e126ba97SEli Cohen } 1001e126ba97SEli Cohen 1002012e50e1SHuy Nguyen mlx5_set_driver_version(dev); 1003012e50e1SHuy Nguyen 1004e126ba97SEli Cohen mlx5_start_health_poll(dev); 1005e126ba97SEli Cohen 1006bba1574cSDaniel Jurgens err = mlx5_query_hca_caps(dev); 1007bba1574cSDaniel Jurgens if (err) { 100898a8e6fcSHuy Nguyen mlx5_core_err(dev, "query hca failed\n"); 1009e161105eSSaeed Mahameed goto stop_health; 1010bba1574cSDaniel Jurgens } 1011bba1574cSDaniel Jurgens 1012e161105eSSaeed Mahameed return 0; 1013e161105eSSaeed Mahameed 1014e161105eSSaeed Mahameed stop_health: 1015e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1016e161105eSSaeed Mahameed reclaim_boot_pages: 1017e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1018e161105eSSaeed Mahameed err_disable_hca: 1019e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1020e161105eSSaeed Mahameed err_cmd_cleanup: 1021e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1022e161105eSSaeed Mahameed 1023e161105eSSaeed Mahameed return err; 1024e161105eSSaeed Mahameed } 1025e161105eSSaeed Mahameed 1026e161105eSSaeed Mahameed static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1027e161105eSSaeed Mahameed { 1028e161105eSSaeed Mahameed int err; 1029e161105eSSaeed Mahameed 1030e161105eSSaeed Mahameed mlx5_stop_health_poll(dev, boot); 1031e161105eSSaeed Mahameed err = mlx5_cmd_teardown_hca(dev); 1032259bbc57SMaor Gottlieb if (err) { 103398a8e6fcSHuy Nguyen mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1034e161105eSSaeed Mahameed return err; 1035e126ba97SEli Cohen } 1036e161105eSSaeed Mahameed mlx5_reclaim_startup_pages(dev); 1037e161105eSSaeed Mahameed mlx5_core_disable_hca(dev, 0); 1038e161105eSSaeed Mahameed mlx5_cmd_cleanup(dev); 1039e161105eSSaeed Mahameed 1040e161105eSSaeed Mahameed return 0; 1041259bbc57SMaor Gottlieb } 1042e126ba97SEli Cohen 1043a80d1b68SSaeed Mahameed static int mlx5_load(struct mlx5_core_dev *dev) 1044e161105eSSaeed Mahameed { 1045e161105eSSaeed Mahameed int err; 1046e161105eSSaeed Mahameed 104701187175SEli Cohen dev->priv.uar = mlx5_get_uars_page(dev); 104872f36be0SEran Ben Elisha if (IS_ERR(dev->priv.uar)) { 104998a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 105072f36be0SEran Ben Elisha err = PTR_ERR(dev->priv.uar); 1051a80d1b68SSaeed Mahameed return err; 1052e126ba97SEli Cohen } 1053e126ba97SEli Cohen 105469c1280bSSaeed Mahameed mlx5_events_start(dev); 10550cf53c12SSaeed Mahameed mlx5_pagealloc_start(dev); 10560cf53c12SSaeed Mahameed 1057e1706e62SYuval Avnery err = mlx5_irq_table_create(dev); 1058e1706e62SYuval Avnery if (err) { 1059e1706e62SYuval Avnery mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1060e1706e62SYuval Avnery goto err_irq_table; 1061e1706e62SYuval Avnery } 1062e1706e62SYuval Avnery 1063c8e21b3bSSaeed Mahameed err = mlx5_eq_table_create(dev); 1064e126ba97SEli Cohen if (err) { 106598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to create EQs\n"); 1066c8e21b3bSSaeed Mahameed goto err_eq_table; 1067e126ba97SEli Cohen } 1068e126ba97SEli Cohen 106924406953SFeras Daoud err = mlx5_fw_tracer_init(dev->tracer); 107024406953SFeras Daoud if (err) { 107198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init FW tracer\n"); 107224406953SFeras Daoud goto err_fw_tracer; 107324406953SFeras Daoud } 107424406953SFeras Daoud 107504e87170SMatan Barak err = mlx5_fpga_device_start(dev); 107604e87170SMatan Barak if (err) { 107798a8e6fcSHuy Nguyen mlx5_core_err(dev, "fpga device start failed %d\n", err); 107804e87170SMatan Barak goto err_fpga_start; 107904e87170SMatan Barak } 108004e87170SMatan Barak 108104e87170SMatan Barak err = mlx5_accel_ipsec_init(dev); 108204e87170SMatan Barak if (err) { 108398a8e6fcSHuy Nguyen mlx5_core_err(dev, "IPSec device start failed %d\n", err); 108404e87170SMatan Barak goto err_ipsec_start; 108504e87170SMatan Barak } 108604e87170SMatan Barak 10871ae17322SIlya Lesokhin err = mlx5_accel_tls_init(dev); 10881ae17322SIlya Lesokhin if (err) { 108998a8e6fcSHuy Nguyen mlx5_core_err(dev, "TLS device start failed %d\n", err); 10901ae17322SIlya Lesokhin goto err_tls_start; 10911ae17322SIlya Lesokhin } 10921ae17322SIlya Lesokhin 109386d722adSMaor Gottlieb err = mlx5_init_fs(dev); 109486d722adSMaor Gottlieb if (err) { 109598a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init flow steering\n"); 109686d722adSMaor Gottlieb goto err_fs; 109786d722adSMaor Gottlieb } 10981466cc5bSYevgeny Petrilin 1099c85023e1SHuy Nguyen err = mlx5_core_set_hca_defaults(dev); 1100c85023e1SHuy Nguyen if (err) { 110198a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to set hca defaults\n"); 110287883929SSaeed Mahameed goto err_sriov; 1103c85023e1SHuy Nguyen } 1104c85023e1SHuy Nguyen 1105c2d6e31aSMohamad Haj Yahia err = mlx5_sriov_attach(dev); 1106fc50db98SEli Cohen if (err) { 110798a8e6fcSHuy Nguyen mlx5_core_err(dev, "sriov init failed %d\n", err); 1108fc50db98SEli Cohen goto err_sriov; 1109fc50db98SEli Cohen } 1110fc50db98SEli Cohen 111122e939a9SBodong Wang err = mlx5_ec_init(dev); 111222e939a9SBodong Wang if (err) { 111398a8e6fcSHuy Nguyen mlx5_core_err(dev, "Failed to init embedded CPU\n"); 111422e939a9SBodong Wang goto err_ec; 111522e939a9SBodong Wang } 111622e939a9SBodong Wang 1117a80d1b68SSaeed Mahameed return 0; 1118a80d1b68SSaeed Mahameed 1119a80d1b68SSaeed Mahameed err_ec: 1120a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1121a80d1b68SSaeed Mahameed err_sriov: 1122a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1123a80d1b68SSaeed Mahameed err_fs: 1124a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1125a80d1b68SSaeed Mahameed err_tls_start: 1126a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1127a80d1b68SSaeed Mahameed err_ipsec_start: 1128a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1129a80d1b68SSaeed Mahameed err_fpga_start: 1130a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1131a80d1b68SSaeed Mahameed err_fw_tracer: 1132a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1133a80d1b68SSaeed Mahameed err_eq_table: 1134e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1135e1706e62SYuval Avnery err_irq_table: 1136a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1137a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1138a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1139a80d1b68SSaeed Mahameed return err; 1140a80d1b68SSaeed Mahameed } 1141a80d1b68SSaeed Mahameed 1142a80d1b68SSaeed Mahameed static void mlx5_unload(struct mlx5_core_dev *dev) 1143a80d1b68SSaeed Mahameed { 1144a80d1b68SSaeed Mahameed mlx5_ec_cleanup(dev); 1145a80d1b68SSaeed Mahameed mlx5_sriov_detach(dev); 1146a80d1b68SSaeed Mahameed mlx5_cleanup_fs(dev); 1147a80d1b68SSaeed Mahameed mlx5_accel_ipsec_cleanup(dev); 1148a80d1b68SSaeed Mahameed mlx5_accel_tls_cleanup(dev); 1149a80d1b68SSaeed Mahameed mlx5_fpga_device_stop(dev); 1150a80d1b68SSaeed Mahameed mlx5_fw_tracer_cleanup(dev->tracer); 1151a80d1b68SSaeed Mahameed mlx5_eq_table_destroy(dev); 1152e1706e62SYuval Avnery mlx5_irq_table_destroy(dev); 1153a80d1b68SSaeed Mahameed mlx5_pagealloc_stop(dev); 1154a80d1b68SSaeed Mahameed mlx5_events_stop(dev); 1155a80d1b68SSaeed Mahameed mlx5_put_uars_page(dev, dev->priv.uar); 1156a80d1b68SSaeed Mahameed } 1157a80d1b68SSaeed Mahameed 1158a80d1b68SSaeed Mahameed static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) 1159a80d1b68SSaeed Mahameed { 1160a80d1b68SSaeed Mahameed int err = 0; 1161a80d1b68SSaeed Mahameed 1162a80d1b68SSaeed Mahameed dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1163a80d1b68SSaeed Mahameed mutex_lock(&dev->intf_state_mutex); 1164a80d1b68SSaeed Mahameed if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1165a80d1b68SSaeed Mahameed mlx5_core_warn(dev, "interface is up, NOP\n"); 1166a80d1b68SSaeed Mahameed goto out; 1167a80d1b68SSaeed Mahameed } 1168a80d1b68SSaeed Mahameed /* remove any previous indication of internal error */ 1169a80d1b68SSaeed Mahameed dev->state = MLX5_DEVICE_STATE_UP; 1170a80d1b68SSaeed Mahameed 1171a80d1b68SSaeed Mahameed err = mlx5_function_setup(dev, boot); 1172a80d1b68SSaeed Mahameed if (err) 1173a80d1b68SSaeed Mahameed goto out; 1174a80d1b68SSaeed Mahameed 1175a80d1b68SSaeed Mahameed if (boot) { 1176a80d1b68SSaeed Mahameed err = mlx5_init_once(dev); 1177a80d1b68SSaeed Mahameed if (err) { 117898a8e6fcSHuy Nguyen mlx5_core_err(dev, "sw objs init failed\n"); 1179a80d1b68SSaeed Mahameed goto function_teardown; 1180a80d1b68SSaeed Mahameed } 1181a80d1b68SSaeed Mahameed } 1182a80d1b68SSaeed Mahameed 1183a80d1b68SSaeed Mahameed err = mlx5_load(dev); 1184a80d1b68SSaeed Mahameed if (err) 1185a80d1b68SSaeed Mahameed goto err_load; 1186a80d1b68SSaeed Mahameed 1187737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) { 1188737a234bSMohamad Haj Yahia mlx5_attach_device(dev); 1189737a234bSMohamad Haj Yahia } else { 1190a31208b1SMajd Dibbiny err = mlx5_register_device(dev); 1191a31208b1SMajd Dibbiny if (err) { 119298a8e6fcSHuy Nguyen mlx5_core_err(dev, "register device failed %d\n", err); 1193a31208b1SMajd Dibbiny goto err_reg_dev; 1194a31208b1SMajd Dibbiny } 1195737a234bSMohamad Haj Yahia } 1196a31208b1SMajd Dibbiny 11975fc7197dSMajd Dibbiny set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 119889d44f0aSMajd Dibbiny out: 119989d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 120089d44f0aSMajd Dibbiny 1201a80d1b68SSaeed Mahameed return err; 1202e126ba97SEli Cohen 120359211bd3SMohamad Haj Yahia err_reg_dev: 1204a80d1b68SSaeed Mahameed mlx5_unload(dev); 1205a80d1b68SSaeed Mahameed err_load: 120659211bd3SMohamad Haj Yahia if (boot) 120759211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 1208e161105eSSaeed Mahameed function_teardown: 1209e161105eSSaeed Mahameed mlx5_function_teardown(dev, boot); 121089d44f0aSMajd Dibbiny dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 121189d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 121289d44f0aSMajd Dibbiny 1213e126ba97SEli Cohen return err; 1214e126ba97SEli Cohen } 1215e126ba97SEli Cohen 1216868bc06bSSaeed Mahameed static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) 1217e126ba97SEli Cohen { 121889d44f0aSMajd Dibbiny int err = 0; 1219e126ba97SEli Cohen 12200000a5f2SParav Pandit if (cleanup) { 12210000a5f2SParav Pandit mlx5_unregister_device(dev); 122263cbc552SFeras Daoud mlx5_drain_health_wq(dev); 12230000a5f2SParav Pandit } 1224689a248dSDaniel Jurgens 122589d44f0aSMajd Dibbiny mutex_lock(&dev->intf_state_mutex); 1226b3cb5388SHuy Nguyen if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 122798a8e6fcSHuy Nguyen mlx5_core_warn(dev, "%s: interface is down, NOP\n", 122889d44f0aSMajd Dibbiny __func__); 122959211bd3SMohamad Haj Yahia if (cleanup) 123059211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 123189d44f0aSMajd Dibbiny goto out; 123289d44f0aSMajd Dibbiny } 12336b6adee3SMohamad Haj Yahia 12349ade8c7cSIlan Tayari clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 12359ade8c7cSIlan Tayari 1236737a234bSMohamad Haj Yahia if (mlx5_device_registered(dev)) 1237737a234bSMohamad Haj Yahia mlx5_detach_device(dev); 1238737a234bSMohamad Haj Yahia 1239a80d1b68SSaeed Mahameed mlx5_unload(dev); 1240a80d1b68SSaeed Mahameed 124159211bd3SMohamad Haj Yahia if (cleanup) 124259211bd3SMohamad Haj Yahia mlx5_cleanup_once(dev); 12430cf53c12SSaeed Mahameed 1244e161105eSSaeed Mahameed mlx5_function_teardown(dev, cleanup); 1245ac6ea6e8SEli Cohen out: 124689d44f0aSMajd Dibbiny mutex_unlock(&dev->intf_state_mutex); 1247ac6ea6e8SEli Cohen return err; 12489603b61dSJack Morgenstein } 124964613d94SSaeed Mahameed 125027b942fbSParav Pandit static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 12519603b61dSJack Morgenstein { 125211f3b84dSSaeed Mahameed struct mlx5_priv *priv = &dev->priv; 12539603b61dSJack Morgenstein int err; 12549603b61dSJack Morgenstein 125511f3b84dSSaeed Mahameed dev->profile = &profile[profile_idx]; 12569603b61dSJack Morgenstein 1257364d1798SEli Cohen INIT_LIST_HEAD(&priv->ctx_list); 1258364d1798SEli Cohen spin_lock_init(&priv->ctx_lock); 125989d44f0aSMajd Dibbiny mutex_init(&dev->intf_state_mutex); 1260d9aaed83SArtemy Kovalyov 126101187175SEli Cohen mutex_init(&priv->bfregs.reg_head.lock); 126201187175SEli Cohen mutex_init(&priv->bfregs.wc_head.lock); 126301187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 126401187175SEli Cohen INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 126501187175SEli Cohen 126611f3b84dSSaeed Mahameed mutex_init(&priv->alloc_mutex); 126711f3b84dSSaeed Mahameed mutex_init(&priv->pgdir_mutex); 126811f3b84dSSaeed Mahameed INIT_LIST_HEAD(&priv->pgdir_list); 126911f3b84dSSaeed Mahameed spin_lock_init(&priv->mkey_lock); 127011f3b84dSSaeed Mahameed 127127b942fbSParav Pandit priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 127227b942fbSParav Pandit mlx5_debugfs_root); 127311f3b84dSSaeed Mahameed if (!priv->dbg_root) { 127427b942fbSParav Pandit dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); 127511f3b84dSSaeed Mahameed return -ENOMEM; 12769603b61dSJack Morgenstein } 12779603b61dSJack Morgenstein 1278ac6ea6e8SEli Cohen err = mlx5_health_init(dev); 127952c368dcSSaeed Mahameed if (err) 128052c368dcSSaeed Mahameed goto err_health_init; 1281ac6ea6e8SEli Cohen 12820cf53c12SSaeed Mahameed err = mlx5_pagealloc_init(dev); 12830cf53c12SSaeed Mahameed if (err) 12840cf53c12SSaeed Mahameed goto err_pagealloc_init; 128559211bd3SMohamad Haj Yahia 128611f3b84dSSaeed Mahameed return 0; 128752c368dcSSaeed Mahameed 128852c368dcSSaeed Mahameed err_pagealloc_init: 128952c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 129052c368dcSSaeed Mahameed err_health_init: 129152c368dcSSaeed Mahameed debugfs_remove(dev->priv.dbg_root); 129252c368dcSSaeed Mahameed 129352c368dcSSaeed Mahameed return err; 129411f3b84dSSaeed Mahameed } 129511f3b84dSSaeed Mahameed 129611f3b84dSSaeed Mahameed static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 129711f3b84dSSaeed Mahameed { 129852c368dcSSaeed Mahameed mlx5_pagealloc_cleanup(dev); 129952c368dcSSaeed Mahameed mlx5_health_cleanup(dev); 130011f3b84dSSaeed Mahameed debugfs_remove_recursive(dev->priv.dbg_root); 130111f3b84dSSaeed Mahameed } 130211f3b84dSSaeed Mahameed 130311f3b84dSSaeed Mahameed #define MLX5_IB_MOD "mlx5_ib" 130411f3b84dSSaeed Mahameed static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) 130511f3b84dSSaeed Mahameed { 130611f3b84dSSaeed Mahameed struct mlx5_core_dev *dev; 130711f3b84dSSaeed Mahameed struct devlink *devlink; 130811f3b84dSSaeed Mahameed int err; 130911f3b84dSSaeed Mahameed 13101f28d776SEran Ben Elisha devlink = mlx5_devlink_alloc(); 131111f3b84dSSaeed Mahameed if (!devlink) { 13121f28d776SEran Ben Elisha dev_err(&pdev->dev, "devlink alloc failed\n"); 131311f3b84dSSaeed Mahameed return -ENOMEM; 131411f3b84dSSaeed Mahameed } 131511f3b84dSSaeed Mahameed 131611f3b84dSSaeed Mahameed dev = devlink_priv(devlink); 131727b942fbSParav Pandit dev->device = &pdev->dev; 131827b942fbSParav Pandit dev->pdev = pdev; 131911f3b84dSSaeed Mahameed 1320386e75afSHuy Nguyen dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1321386e75afSHuy Nguyen MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1322386e75afSHuy Nguyen 132327b942fbSParav Pandit err = mlx5_mdev_init(dev, prof_sel); 132411f3b84dSSaeed Mahameed if (err) 132511f3b84dSSaeed Mahameed goto mdev_init_err; 132611f3b84dSSaeed Mahameed 132711f3b84dSSaeed Mahameed err = mlx5_pci_init(dev, pdev, id); 13289603b61dSJack Morgenstein if (err) { 132998a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 133098a8e6fcSHuy Nguyen err); 133111f3b84dSSaeed Mahameed goto pci_init_err; 13329603b61dSJack Morgenstein } 13339603b61dSJack Morgenstein 1334868bc06bSSaeed Mahameed err = mlx5_load_one(dev, true); 13359603b61dSJack Morgenstein if (err) { 133698a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", 133798a8e6fcSHuy Nguyen err); 13380cf53c12SSaeed Mahameed goto err_load_one; 13399603b61dSJack Morgenstein } 134059211bd3SMohamad Haj Yahia 1341f82eed45SLeon Romanovsky request_module_nowait(MLX5_IB_MOD); 13429603b61dSJack Morgenstein 13431f28d776SEran Ben Elisha err = mlx5_devlink_register(devlink, &pdev->dev); 1344feae9087SOr Gerlitz if (err) 1345feae9087SOr Gerlitz goto clean_load; 1346feae9087SOr Gerlitz 13478b9d8baaSAlex Vesker err = mlx5_crdump_enable(dev); 13488b9d8baaSAlex Vesker if (err) 13498b9d8baaSAlex Vesker dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 13508b9d8baaSAlex Vesker 13515d47f6c8SDaniel Jurgens pci_save_state(pdev); 13529603b61dSJack Morgenstein return 0; 13539603b61dSJack Morgenstein 1354feae9087SOr Gerlitz clean_load: 1355868bc06bSSaeed Mahameed mlx5_unload_one(dev, true); 135652c368dcSSaeed Mahameed 13570cf53c12SSaeed Mahameed err_load_one: 1358868bc06bSSaeed Mahameed mlx5_pci_close(dev); 135911f3b84dSSaeed Mahameed pci_init_err: 136011f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 136111f3b84dSSaeed Mahameed mdev_init_err: 13621f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 1363a31208b1SMajd Dibbiny 13649603b61dSJack Morgenstein return err; 13659603b61dSJack Morgenstein } 1366a31208b1SMajd Dibbiny 13679603b61dSJack Morgenstein static void remove_one(struct pci_dev *pdev) 13689603b61dSJack Morgenstein { 13699603b61dSJack Morgenstein struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1370feae9087SOr Gerlitz struct devlink *devlink = priv_to_devlink(dev); 13719603b61dSJack Morgenstein 13728b9d8baaSAlex Vesker mlx5_crdump_disable(dev); 13731f28d776SEran Ben Elisha mlx5_devlink_unregister(devlink); 1374737a234bSMohamad Haj Yahia 1375868bc06bSSaeed Mahameed if (mlx5_unload_one(dev, true)) { 137698a8e6fcSHuy Nguyen mlx5_core_err(dev, "mlx5_unload_one failed\n"); 137752c368dcSSaeed Mahameed mlx5_health_flush(dev); 1378a31208b1SMajd Dibbiny return; 1379a31208b1SMajd Dibbiny } 1380737a234bSMohamad Haj Yahia 1381868bc06bSSaeed Mahameed mlx5_pci_close(dev); 138211f3b84dSSaeed Mahameed mlx5_mdev_uninit(dev); 13831f28d776SEran Ben Elisha mlx5_devlink_free(devlink); 13849603b61dSJack Morgenstein } 13859603b61dSJack Morgenstein 138689d44f0aSMajd Dibbiny static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 138789d44f0aSMajd Dibbiny pci_channel_state_t state) 138889d44f0aSMajd Dibbiny { 138989d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 139089d44f0aSMajd Dibbiny 139198a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 139204c0c1abSMohamad Haj Yahia 13938812c24dSMajd Dibbiny mlx5_enter_error_state(dev, false); 13943e5b72acSFeras Daoud mlx5_error_sw_reset(dev); 1395868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 13965e44fca5SDaniel Jurgens mlx5_drain_health_wq(dev); 139789d44f0aSMajd Dibbiny mlx5_pci_disable_device(dev); 139805ac2c0bSMohamad Haj Yahia 139989d44f0aSMajd Dibbiny return state == pci_channel_io_perm_failure ? 140089d44f0aSMajd Dibbiny PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 140189d44f0aSMajd Dibbiny } 140289d44f0aSMajd Dibbiny 1403d57847dcSDaniel Jurgens /* wait for the device to show vital signs by waiting 1404d57847dcSDaniel Jurgens * for the health counter to start counting. 140589d44f0aSMajd Dibbiny */ 1406d57847dcSDaniel Jurgens static int wait_vital(struct pci_dev *pdev) 140789d44f0aSMajd Dibbiny { 140889d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 140989d44f0aSMajd Dibbiny struct mlx5_core_health *health = &dev->priv.health; 141089d44f0aSMajd Dibbiny const int niter = 100; 1411d57847dcSDaniel Jurgens u32 last_count = 0; 141289d44f0aSMajd Dibbiny u32 count; 141389d44f0aSMajd Dibbiny int i; 141489d44f0aSMajd Dibbiny 141589d44f0aSMajd Dibbiny for (i = 0; i < niter; i++) { 141689d44f0aSMajd Dibbiny count = ioread32be(health->health_counter); 141789d44f0aSMajd Dibbiny if (count && count != 0xffffffff) { 1418d57847dcSDaniel Jurgens if (last_count && last_count != count) { 141998a8e6fcSHuy Nguyen mlx5_core_info(dev, 142098a8e6fcSHuy Nguyen "wait vital counter value 0x%x after %d iterations\n", 142198a8e6fcSHuy Nguyen count, i); 1422d57847dcSDaniel Jurgens return 0; 1423d57847dcSDaniel Jurgens } 1424d57847dcSDaniel Jurgens last_count = count; 142589d44f0aSMajd Dibbiny } 142689d44f0aSMajd Dibbiny msleep(50); 142789d44f0aSMajd Dibbiny } 142889d44f0aSMajd Dibbiny 1429d57847dcSDaniel Jurgens return -ETIMEDOUT; 143089d44f0aSMajd Dibbiny } 143189d44f0aSMajd Dibbiny 14321061c90fSMohamad Haj Yahia static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 14331061c90fSMohamad Haj Yahia { 14341061c90fSMohamad Haj Yahia struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 14351061c90fSMohamad Haj Yahia int err; 14361061c90fSMohamad Haj Yahia 143798a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 14381061c90fSMohamad Haj Yahia 14391061c90fSMohamad Haj Yahia err = mlx5_pci_enable_device(dev); 14401061c90fSMohamad Haj Yahia if (err) { 144198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 144298a8e6fcSHuy Nguyen __func__, err); 14431061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14441061c90fSMohamad Haj Yahia } 14451061c90fSMohamad Haj Yahia 14461061c90fSMohamad Haj Yahia pci_set_master(pdev); 14471061c90fSMohamad Haj Yahia pci_restore_state(pdev); 14485d47f6c8SDaniel Jurgens pci_save_state(pdev); 14491061c90fSMohamad Haj Yahia 14501061c90fSMohamad Haj Yahia if (wait_vital(pdev)) { 145198a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 14521061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_DISCONNECT; 14531061c90fSMohamad Haj Yahia } 14541061c90fSMohamad Haj Yahia 14551061c90fSMohamad Haj Yahia return PCI_ERS_RESULT_RECOVERED; 14561061c90fSMohamad Haj Yahia } 14571061c90fSMohamad Haj Yahia 145889d44f0aSMajd Dibbiny static void mlx5_pci_resume(struct pci_dev *pdev) 145989d44f0aSMajd Dibbiny { 146089d44f0aSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 146189d44f0aSMajd Dibbiny int err; 146289d44f0aSMajd Dibbiny 146398a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s was called\n", __func__); 146489d44f0aSMajd Dibbiny 1465868bc06bSSaeed Mahameed err = mlx5_load_one(dev, false); 146689d44f0aSMajd Dibbiny if (err) 146798a8e6fcSHuy Nguyen mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 146898a8e6fcSHuy Nguyen __func__, err); 146989d44f0aSMajd Dibbiny else 147098a8e6fcSHuy Nguyen mlx5_core_info(dev, "%s: device recovered\n", __func__); 147189d44f0aSMajd Dibbiny } 147289d44f0aSMajd Dibbiny 147389d44f0aSMajd Dibbiny static const struct pci_error_handlers mlx5_err_handler = { 147489d44f0aSMajd Dibbiny .error_detected = mlx5_pci_err_detected, 147589d44f0aSMajd Dibbiny .slot_reset = mlx5_pci_slot_reset, 147689d44f0aSMajd Dibbiny .resume = mlx5_pci_resume 147789d44f0aSMajd Dibbiny }; 147889d44f0aSMajd Dibbiny 14798812c24dSMajd Dibbiny static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 14808812c24dSMajd Dibbiny { 1481fcd29ad1SFeras Daoud bool fast_teardown = false, force_teardown = false; 1482fcd29ad1SFeras Daoud int ret = 1; 14838812c24dSMajd Dibbiny 1484fcd29ad1SFeras Daoud fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1485fcd29ad1SFeras Daoud force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1486fcd29ad1SFeras Daoud 1487fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1488fcd29ad1SFeras Daoud mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1489fcd29ad1SFeras Daoud 1490fcd29ad1SFeras Daoud if (!fast_teardown && !force_teardown) 14918812c24dSMajd Dibbiny return -EOPNOTSUPP; 14928812c24dSMajd Dibbiny 14938812c24dSMajd Dibbiny if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 14948812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 14958812c24dSMajd Dibbiny return -EAGAIN; 14968812c24dSMajd Dibbiny } 14978812c24dSMajd Dibbiny 1498d2aa060dSHuy Nguyen /* Panic tear down fw command will stop the PCI bus communication 1499d2aa060dSHuy Nguyen * with the HCA, so the health polll is no longer needed. 1500d2aa060dSHuy Nguyen */ 1501d2aa060dSHuy Nguyen mlx5_drain_health_wq(dev); 150276d5581cSJack Morgenstein mlx5_stop_health_poll(dev, false); 1503d2aa060dSHuy Nguyen 1504fcd29ad1SFeras Daoud ret = mlx5_cmd_fast_teardown_hca(dev); 1505fcd29ad1SFeras Daoud if (!ret) 1506fcd29ad1SFeras Daoud goto succeed; 1507fcd29ad1SFeras Daoud 15088812c24dSMajd Dibbiny ret = mlx5_cmd_force_teardown_hca(dev); 1509fcd29ad1SFeras Daoud if (!ret) 1510fcd29ad1SFeras Daoud goto succeed; 1511fcd29ad1SFeras Daoud 15128812c24dSMajd Dibbiny mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1513d2aa060dSHuy Nguyen mlx5_start_health_poll(dev); 15148812c24dSMajd Dibbiny return ret; 15158812c24dSMajd Dibbiny 1516fcd29ad1SFeras Daoud succeed: 15178812c24dSMajd Dibbiny mlx5_enter_error_state(dev, true); 15188812c24dSMajd Dibbiny 15191ef903bfSDaniel Jurgens /* Some platforms requiring freeing the IRQ's in the shutdown 15201ef903bfSDaniel Jurgens * flow. If they aren't freed they can't be allocated after 15211ef903bfSDaniel Jurgens * kexec. There is no need to cleanup the mlx5_core software 15221ef903bfSDaniel Jurgens * contexts. 15231ef903bfSDaniel Jurgens */ 15241ef903bfSDaniel Jurgens mlx5_core_eq_free_irqs(dev); 15251ef903bfSDaniel Jurgens 15268812c24dSMajd Dibbiny return 0; 15278812c24dSMajd Dibbiny } 15288812c24dSMajd Dibbiny 15295fc7197dSMajd Dibbiny static void shutdown(struct pci_dev *pdev) 15305fc7197dSMajd Dibbiny { 15315fc7197dSMajd Dibbiny struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 15328812c24dSMajd Dibbiny int err; 15335fc7197dSMajd Dibbiny 153498a8e6fcSHuy Nguyen mlx5_core_info(dev, "Shutdown was called\n"); 15358812c24dSMajd Dibbiny err = mlx5_try_fast_unload(dev); 15368812c24dSMajd Dibbiny if (err) 1537868bc06bSSaeed Mahameed mlx5_unload_one(dev, false); 15385fc7197dSMajd Dibbiny mlx5_pci_disable_device(dev); 15395fc7197dSMajd Dibbiny } 15405fc7197dSMajd Dibbiny 15419603b61dSJack Morgenstein static const struct pci_device_id mlx5_core_pci_table[] = { 1542bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1543fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1544bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1545fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1546bbad7c21SMyron Stowe { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1547fc50db98SEli Cohen { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 15487092fe86SMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 154964dbbdfeSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1550d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1551d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1552d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1553d0dd989fSMajd Dibbiny { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 155485327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 155585327a9cSEran Ben Elisha { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 15562e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 15572e9d3e83SNoa Osherovich { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 15589603b61dSJack Morgenstein { 0, } 15599603b61dSJack Morgenstein }; 15609603b61dSJack Morgenstein 15619603b61dSJack Morgenstein MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 15629603b61dSJack Morgenstein 156304c0c1abSMohamad Haj Yahia void mlx5_disable_device(struct mlx5_core_dev *dev) 156404c0c1abSMohamad Haj Yahia { 1565b3bd076fSMoshe Shemesh mlx5_error_sw_reset(dev); 1566b3bd076fSMoshe Shemesh mlx5_unload_one(dev, false); 156704c0c1abSMohamad Haj Yahia } 156804c0c1abSMohamad Haj Yahia 156904c0c1abSMohamad Haj Yahia void mlx5_recover_device(struct mlx5_core_dev *dev) 157004c0c1abSMohamad Haj Yahia { 157104c0c1abSMohamad Haj Yahia mlx5_pci_disable_device(dev); 157204c0c1abSMohamad Haj Yahia if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 157304c0c1abSMohamad Haj Yahia mlx5_pci_resume(dev->pdev); 157404c0c1abSMohamad Haj Yahia } 157504c0c1abSMohamad Haj Yahia 15769603b61dSJack Morgenstein static struct pci_driver mlx5_core_driver = { 15779603b61dSJack Morgenstein .name = DRIVER_NAME, 15789603b61dSJack Morgenstein .id_table = mlx5_core_pci_table, 15799603b61dSJack Morgenstein .probe = init_one, 158089d44f0aSMajd Dibbiny .remove = remove_one, 15815fc7197dSMajd Dibbiny .shutdown = shutdown, 1582fc50db98SEli Cohen .err_handler = &mlx5_err_handler, 1583fc50db98SEli Cohen .sriov_configure = mlx5_core_sriov_configure, 15849603b61dSJack Morgenstein }; 1585e126ba97SEli Cohen 1586f663ad98SKamal Heib static void mlx5_core_verify_params(void) 1587f663ad98SKamal Heib { 1588f663ad98SKamal Heib if (prof_sel >= ARRAY_SIZE(profile)) { 1589f663ad98SKamal Heib pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1590f663ad98SKamal Heib prof_sel, 1591f663ad98SKamal Heib ARRAY_SIZE(profile) - 1, 1592f663ad98SKamal Heib MLX5_DEFAULT_PROF); 1593f663ad98SKamal Heib prof_sel = MLX5_DEFAULT_PROF; 1594f663ad98SKamal Heib } 1595f663ad98SKamal Heib } 1596f663ad98SKamal Heib 1597e126ba97SEli Cohen static int __init init(void) 1598e126ba97SEli Cohen { 1599e126ba97SEli Cohen int err; 1600e126ba97SEli Cohen 16018737f818SDaniel Jurgens get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 16028737f818SDaniel Jurgens 1603f663ad98SKamal Heib mlx5_core_verify_params(); 1604c778dd31STariq Toukan mlx5_accel_ipsec_build_fs_cmds(); 1605e126ba97SEli Cohen mlx5_register_debugfs(); 1606e126ba97SEli Cohen 16079603b61dSJack Morgenstein err = pci_register_driver(&mlx5_core_driver); 16089603b61dSJack Morgenstein if (err) 1609ac6ea6e8SEli Cohen goto err_debug; 16109603b61dSJack Morgenstein 1611f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1612f62b8bb8SAmir Vadai mlx5e_init(); 1613f62b8bb8SAmir Vadai #endif 1614f62b8bb8SAmir Vadai 1615e126ba97SEli Cohen return 0; 1616e126ba97SEli Cohen 1617e126ba97SEli Cohen err_debug: 1618e126ba97SEli Cohen mlx5_unregister_debugfs(); 1619e126ba97SEli Cohen return err; 1620e126ba97SEli Cohen } 1621e126ba97SEli Cohen 1622e126ba97SEli Cohen static void __exit cleanup(void) 1623e126ba97SEli Cohen { 1624f62b8bb8SAmir Vadai #ifdef CONFIG_MLX5_CORE_EN 1625f62b8bb8SAmir Vadai mlx5e_cleanup(); 1626f62b8bb8SAmir Vadai #endif 16279603b61dSJack Morgenstein pci_unregister_driver(&mlx5_core_driver); 1628e126ba97SEli Cohen mlx5_unregister_debugfs(); 1629e126ba97SEli Cohen } 1630e126ba97SEli Cohen 1631e126ba97SEli Cohen module_init(init); 1632e126ba97SEli Cohen module_exit(cleanup); 1633