1ae904beaSFeras Daoud /* 2ae904beaSFeras Daoud * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3ae904beaSFeras Daoud * 4ae904beaSFeras Daoud * This software is available to you under a choice of one of two 5ae904beaSFeras Daoud * licenses. You may choose to be licensed under the terms of the GNU 6ae904beaSFeras Daoud * General Public License (GPL) Version 2, available from the file 7ae904beaSFeras Daoud * COPYING in the main directory of this source tree, or the 8ae904beaSFeras Daoud * OpenIB.org BSD license below: 9ae904beaSFeras Daoud * 10ae904beaSFeras Daoud * Redistribution and use in source and binary forms, with or 11ae904beaSFeras Daoud * without modification, are permitted provided that the following 12ae904beaSFeras Daoud * conditions are met: 13ae904beaSFeras Daoud * 14ae904beaSFeras Daoud * - Redistributions of source code must retain the above 15ae904beaSFeras Daoud * copyright notice, this list of conditions and the following 16ae904beaSFeras Daoud * disclaimer. 17ae904beaSFeras Daoud * 18ae904beaSFeras Daoud * - Redistributions in binary form must reproduce the above 19ae904beaSFeras Daoud * copyright notice, this list of conditions and the following 20ae904beaSFeras Daoud * disclaimer in the documentation and/or other materials 21ae904beaSFeras Daoud * provided with the distribution. 22ae904beaSFeras Daoud * 23ae904beaSFeras Daoud * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24ae904beaSFeras Daoud * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25ae904beaSFeras Daoud * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26ae904beaSFeras Daoud * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27ae904beaSFeras Daoud * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28ae904beaSFeras Daoud * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29ae904beaSFeras Daoud * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30ae904beaSFeras Daoud * SOFTWARE. 31ae904beaSFeras Daoud */ 32ae904beaSFeras Daoud 33ae904beaSFeras Daoud #include <linux/clocksource.h> 3424d33d2cSFeras Daoud #include <linux/highmem.h> 3590bf1c8dSEran Ben Elisha #include <linux/ptp_clock_kernel.h> 3624d33d2cSFeras Daoud #include <rdma/mlx5-abi.h> 3741069256SSaeed Mahameed #include "lib/eq.h" 38ae904beaSFeras Daoud #include "en.h" 399afe9a53SOr Gerlitz #include "clock.h" 40ae904beaSFeras Daoud 41ae904beaSFeras Daoud enum { 427c39afb3SFeras Daoud MLX5_CYCLES_SHIFT = 23 43ae904beaSFeras Daoud }; 44ae904beaSFeras Daoud 45ae904beaSFeras Daoud enum { 467c39afb3SFeras Daoud MLX5_PIN_MODE_IN = 0x0, 477c39afb3SFeras Daoud MLX5_PIN_MODE_OUT = 0x1, 48ae904beaSFeras Daoud }; 49ae904beaSFeras Daoud 50ae904beaSFeras Daoud enum { 517c39afb3SFeras Daoud MLX5_OUT_PATTERN_PULSE = 0x0, 527c39afb3SFeras Daoud MLX5_OUT_PATTERN_PERIODIC = 0x1, 53ae904beaSFeras Daoud }; 54ae904beaSFeras Daoud 55ae904beaSFeras Daoud enum { 567c39afb3SFeras Daoud MLX5_EVENT_MODE_DISABLE = 0x0, 577c39afb3SFeras Daoud MLX5_EVENT_MODE_REPETETIVE = 0x1, 587c39afb3SFeras Daoud MLX5_EVENT_MODE_ONCE_TILL_ARM = 0x2, 59ae904beaSFeras Daoud }; 60ae904beaSFeras Daoud 61ae904beaSFeras Daoud enum { 627c39afb3SFeras Daoud MLX5_MTPPS_FS_ENABLE = BIT(0x0), 637c39afb3SFeras Daoud MLX5_MTPPS_FS_PATTERN = BIT(0x2), 647c39afb3SFeras Daoud MLX5_MTPPS_FS_PIN_MODE = BIT(0x3), 657c39afb3SFeras Daoud MLX5_MTPPS_FS_TIME_STAMP = BIT(0x4), 667c39afb3SFeras Daoud MLX5_MTPPS_FS_OUT_PULSE_DURATION = BIT(0x5), 677c39afb3SFeras Daoud MLX5_MTPPS_FS_ENH_OUT_PER_ADJ = BIT(0x7), 68ae904beaSFeras Daoud }; 69ae904beaSFeras Daoud 7090bf1c8dSEran Ben Elisha static u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 7190bf1c8dSEran Ben Elisha struct ptp_system_timestamp *sts) 7290bf1c8dSEran Ben Elisha { 7390bf1c8dSEran Ben Elisha u32 timer_h, timer_h1, timer_l; 7490bf1c8dSEran Ben Elisha 7590bf1c8dSEran Ben Elisha timer_h = ioread32be(&dev->iseg->internal_timer_h); 7690bf1c8dSEran Ben Elisha ptp_read_system_prets(sts); 7790bf1c8dSEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 7890bf1c8dSEran Ben Elisha ptp_read_system_postts(sts); 7990bf1c8dSEran Ben Elisha timer_h1 = ioread32be(&dev->iseg->internal_timer_h); 8090bf1c8dSEran Ben Elisha if (timer_h != timer_h1) { 8190bf1c8dSEran Ben Elisha /* wrap around */ 8290bf1c8dSEran Ben Elisha ptp_read_system_prets(sts); 8390bf1c8dSEran Ben Elisha timer_l = ioread32be(&dev->iseg->internal_timer_l); 8490bf1c8dSEran Ben Elisha ptp_read_system_postts(sts); 8590bf1c8dSEran Ben Elisha } 8690bf1c8dSEran Ben Elisha 8790bf1c8dSEran Ben Elisha return (u64)timer_l | (u64)timer_h1 << 32; 8890bf1c8dSEran Ben Elisha } 8990bf1c8dSEran Ben Elisha 907c39afb3SFeras Daoud static u64 read_internal_timer(const struct cyclecounter *cc) 91ae904beaSFeras Daoud { 927c39afb3SFeras Daoud struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles); 937c39afb3SFeras Daoud struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, 947c39afb3SFeras Daoud clock); 95ae904beaSFeras Daoud 964a0475d5SMiroslav Lichvar return mlx5_read_internal_timer(mdev, NULL) & cc->mask; 97ae904beaSFeras Daoud } 98ae904beaSFeras Daoud 9924d33d2cSFeras Daoud static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev) 10024d33d2cSFeras Daoud { 10124d33d2cSFeras Daoud struct mlx5_ib_clock_info *clock_info = mdev->clock_info; 10224d33d2cSFeras Daoud struct mlx5_clock *clock = &mdev->clock; 10324d33d2cSFeras Daoud u32 sign; 10424d33d2cSFeras Daoud 10524d33d2cSFeras Daoud if (!clock_info) 10624d33d2cSFeras Daoud return; 10724d33d2cSFeras Daoud 10824d33d2cSFeras Daoud sign = smp_load_acquire(&clock_info->sign); 10924d33d2cSFeras Daoud smp_store_mb(clock_info->sign, 11024d33d2cSFeras Daoud sign | MLX5_IB_CLOCK_INFO_KERNEL_UPDATING); 11124d33d2cSFeras Daoud 11224d33d2cSFeras Daoud clock_info->cycles = clock->tc.cycle_last; 11324d33d2cSFeras Daoud clock_info->mult = clock->cycles.mult; 11424d33d2cSFeras Daoud clock_info->nsec = clock->tc.nsec; 11524d33d2cSFeras Daoud clock_info->frac = clock->tc.frac; 11624d33d2cSFeras Daoud 11724d33d2cSFeras Daoud smp_store_release(&clock_info->sign, 11824d33d2cSFeras Daoud sign + MLX5_IB_CLOCK_INFO_KERNEL_UPDATING * 2); 11924d33d2cSFeras Daoud } 12024d33d2cSFeras Daoud 1217c39afb3SFeras Daoud static void mlx5_pps_out(struct work_struct *work) 122ae904beaSFeras Daoud { 1237c39afb3SFeras Daoud struct mlx5_pps *pps_info = container_of(work, struct mlx5_pps, 124ae904beaSFeras Daoud out_work); 1257c39afb3SFeras Daoud struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, 126ae904beaSFeras Daoud pps_info); 1277c39afb3SFeras Daoud struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, 1287c39afb3SFeras Daoud clock); 129ae904beaSFeras Daoud u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 130ae904beaSFeras Daoud unsigned long flags; 131ae904beaSFeras Daoud int i; 132ae904beaSFeras Daoud 1337c39afb3SFeras Daoud for (i = 0; i < clock->ptp_info.n_pins; i++) { 134ae904beaSFeras Daoud u64 tstart; 135ae904beaSFeras Daoud 13664109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 1377c39afb3SFeras Daoud tstart = clock->pps_info.start[i]; 1387c39afb3SFeras Daoud clock->pps_info.start[i] = 0; 13964109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 140ae904beaSFeras Daoud if (!tstart) 141ae904beaSFeras Daoud continue; 142ae904beaSFeras Daoud 143ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pin, i); 144ae904beaSFeras Daoud MLX5_SET64(mtpps_reg, in, time_stamp, tstart); 1457c39afb3SFeras Daoud MLX5_SET(mtpps_reg, in, field_select, MLX5_MTPPS_FS_TIME_STAMP); 1467c39afb3SFeras Daoud mlx5_set_mtpps(mdev, in, sizeof(in)); 147ae904beaSFeras Daoud } 148ae904beaSFeras Daoud } 149ae904beaSFeras Daoud 1507c39afb3SFeras Daoud static void mlx5_timestamp_overflow(struct work_struct *work) 151ae904beaSFeras Daoud { 152ae904beaSFeras Daoud struct delayed_work *dwork = to_delayed_work(work); 153fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 154fb609b51SEran Ben Elisha struct mlx5_clock *clock; 155ae904beaSFeras Daoud unsigned long flags; 156ae904beaSFeras Daoud 157fb609b51SEran Ben Elisha clock = container_of(dwork, struct mlx5_clock, overflow_work); 158fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 15964109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 1607c39afb3SFeras Daoud timecounter_read(&clock->tc); 161fb609b51SEran Ben Elisha mlx5_update_clock_info_page(mdev); 16264109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 1637c39afb3SFeras Daoud schedule_delayed_work(&clock->overflow_work, clock->overflow_period); 164ae904beaSFeras Daoud } 165ae904beaSFeras Daoud 166fb609b51SEran Ben Elisha static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) 167ae904beaSFeras Daoud { 168fb609b51SEran Ben Elisha struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); 169ae904beaSFeras Daoud u64 ns = timespec64_to_ns(ts); 170fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 171ae904beaSFeras Daoud unsigned long flags; 172ae904beaSFeras Daoud 173fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 17464109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 1757c39afb3SFeras Daoud timecounter_init(&clock->tc, &clock->cycles, ns); 176fb609b51SEran Ben Elisha mlx5_update_clock_info_page(mdev); 17764109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 178ae904beaSFeras Daoud 179ae904beaSFeras Daoud return 0; 180ae904beaSFeras Daoud } 181ae904beaSFeras Daoud 1824a0475d5SMiroslav Lichvar static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 1834a0475d5SMiroslav Lichvar struct ptp_system_timestamp *sts) 184ae904beaSFeras Daoud { 185fb609b51SEran Ben Elisha struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); 186fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 187ae904beaSFeras Daoud unsigned long flags; 1884a0475d5SMiroslav Lichvar u64 cycles, ns; 189ae904beaSFeras Daoud 190fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 19164109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 1924a0475d5SMiroslav Lichvar cycles = mlx5_read_internal_timer(mdev, sts); 1934a0475d5SMiroslav Lichvar ns = timecounter_cyc2time(&clock->tc, cycles); 19464109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 195ae904beaSFeras Daoud 196ae904beaSFeras Daoud *ts = ns_to_timespec64(ns); 197ae904beaSFeras Daoud 198ae904beaSFeras Daoud return 0; 199ae904beaSFeras Daoud } 200ae904beaSFeras Daoud 2017c39afb3SFeras Daoud static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 202ae904beaSFeras Daoud { 203fb609b51SEran Ben Elisha struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); 204fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 205ae904beaSFeras Daoud unsigned long flags; 206ae904beaSFeras Daoud 207fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 20864109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 2097c39afb3SFeras Daoud timecounter_adjtime(&clock->tc, delta); 210fb609b51SEran Ben Elisha mlx5_update_clock_info_page(mdev); 21164109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 212ae904beaSFeras Daoud 213ae904beaSFeras Daoud return 0; 214ae904beaSFeras Daoud } 215ae904beaSFeras Daoud 2167c39afb3SFeras Daoud static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta) 217ae904beaSFeras Daoud { 218fb609b51SEran Ben Elisha struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); 219fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 220ae904beaSFeras Daoud unsigned long flags; 221ae904beaSFeras Daoud int neg_adj = 0; 222fb609b51SEran Ben Elisha u32 diff; 223fb609b51SEran Ben Elisha u64 adj; 224fb609b51SEran Ben Elisha 225ae904beaSFeras Daoud 226ae904beaSFeras Daoud if (delta < 0) { 227ae904beaSFeras Daoud neg_adj = 1; 228ae904beaSFeras Daoud delta = -delta; 229ae904beaSFeras Daoud } 230ae904beaSFeras Daoud 2317c39afb3SFeras Daoud adj = clock->nominal_c_mult; 232ae904beaSFeras Daoud adj *= delta; 233ae904beaSFeras Daoud diff = div_u64(adj, 1000000000ULL); 234ae904beaSFeras Daoud 235fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 23664109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 2377c39afb3SFeras Daoud timecounter_read(&clock->tc); 2387c39afb3SFeras Daoud clock->cycles.mult = neg_adj ? clock->nominal_c_mult - diff : 2397c39afb3SFeras Daoud clock->nominal_c_mult + diff; 240fb609b51SEran Ben Elisha mlx5_update_clock_info_page(mdev); 24164109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 242ae904beaSFeras Daoud 243ae904beaSFeras Daoud return 0; 244ae904beaSFeras Daoud } 245ae904beaSFeras Daoud 2467c39afb3SFeras Daoud static int mlx5_extts_configure(struct ptp_clock_info *ptp, 247ae904beaSFeras Daoud struct ptp_clock_request *rq, 248ae904beaSFeras Daoud int on) 249ae904beaSFeras Daoud { 2507c39afb3SFeras Daoud struct mlx5_clock *clock = 2517c39afb3SFeras Daoud container_of(ptp, struct mlx5_clock, ptp_info); 2527c39afb3SFeras Daoud struct mlx5_core_dev *mdev = 2537c39afb3SFeras Daoud container_of(clock, struct mlx5_core_dev, clock); 254ae904beaSFeras Daoud u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 255ae904beaSFeras Daoud u32 field_select = 0; 256ae904beaSFeras Daoud u8 pin_mode = 0; 257ae904beaSFeras Daoud u8 pattern = 0; 258ae904beaSFeras Daoud int pin = -1; 259ae904beaSFeras Daoud int err = 0; 260ae904beaSFeras Daoud 2617c39afb3SFeras Daoud if (!MLX5_PPS_CAP(mdev)) 262ae904beaSFeras Daoud return -EOPNOTSUPP; 263ae904beaSFeras Daoud 2642e0645a0SJacob Keller /* Reject requests with unsupported flags */ 2652e0645a0SJacob Keller if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 2662e0645a0SJacob Keller PTP_RISING_EDGE | 2676138e687SRichard Cochran PTP_FALLING_EDGE | 2686138e687SRichard Cochran PTP_STRICT_FLAGS)) 2692e0645a0SJacob Keller return -EOPNOTSUPP; 2702e0645a0SJacob Keller 271ca12cf5aSRichard Cochran /* Reject requests to enable time stamping on both edges. */ 272ca12cf5aSRichard Cochran if ((rq->extts.flags & PTP_STRICT_FLAGS) && 273ca12cf5aSRichard Cochran (rq->extts.flags & PTP_ENABLE_FEATURE) && 274ca12cf5aSRichard Cochran (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 275ca12cf5aSRichard Cochran return -EOPNOTSUPP; 276ca12cf5aSRichard Cochran 2777c39afb3SFeras Daoud if (rq->extts.index >= clock->ptp_info.n_pins) 278ae904beaSFeras Daoud return -EINVAL; 279ae904beaSFeras Daoud 2807c39afb3SFeras Daoud pin = ptp_find_pin(clock->ptp, PTP_PF_EXTTS, rq->extts.index); 281ae904beaSFeras Daoud if (pin < 0) 282ae904beaSFeras Daoud return -EBUSY; 28388c8cf92SEran Ben Elisha 28488c8cf92SEran Ben Elisha if (on) { 2857c39afb3SFeras Daoud pin_mode = MLX5_PIN_MODE_IN; 286ae904beaSFeras Daoud pattern = !!(rq->extts.flags & PTP_FALLING_EDGE); 2877c39afb3SFeras Daoud field_select = MLX5_MTPPS_FS_PIN_MODE | 2887c39afb3SFeras Daoud MLX5_MTPPS_FS_PATTERN | 2897c39afb3SFeras Daoud MLX5_MTPPS_FS_ENABLE; 290ae904beaSFeras Daoud } else { 2917c39afb3SFeras Daoud field_select = MLX5_MTPPS_FS_ENABLE; 292ae904beaSFeras Daoud } 293ae904beaSFeras Daoud 294ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pin, pin); 295ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pin_mode, pin_mode); 296ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pattern, pattern); 297ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, enable, on); 298ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, field_select, field_select); 299ae904beaSFeras Daoud 3007c39afb3SFeras Daoud err = mlx5_set_mtpps(mdev, in, sizeof(in)); 301ae904beaSFeras Daoud if (err) 302ae904beaSFeras Daoud return err; 303ae904beaSFeras Daoud 3047c39afb3SFeras Daoud return mlx5_set_mtppse(mdev, pin, 0, 3057c39afb3SFeras Daoud MLX5_EVENT_MODE_REPETETIVE & on); 306ae904beaSFeras Daoud } 307ae904beaSFeras Daoud 3087c39afb3SFeras Daoud static int mlx5_perout_configure(struct ptp_clock_info *ptp, 309ae904beaSFeras Daoud struct ptp_clock_request *rq, 310ae904beaSFeras Daoud int on) 311ae904beaSFeras Daoud { 3127c39afb3SFeras Daoud struct mlx5_clock *clock = 3137c39afb3SFeras Daoud container_of(ptp, struct mlx5_clock, ptp_info); 3147c39afb3SFeras Daoud struct mlx5_core_dev *mdev = 3157c39afb3SFeras Daoud container_of(clock, struct mlx5_core_dev, clock); 316ae904beaSFeras Daoud u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 317ae904beaSFeras Daoud u64 nsec_now, nsec_delta, time_stamp = 0; 318ae904beaSFeras Daoud u64 cycles_now, cycles_delta; 319ae904beaSFeras Daoud struct timespec64 ts; 320ae904beaSFeras Daoud unsigned long flags; 321ae904beaSFeras Daoud u32 field_select = 0; 322ae904beaSFeras Daoud u8 pin_mode = 0; 323ae904beaSFeras Daoud u8 pattern = 0; 324ae904beaSFeras Daoud int pin = -1; 325ae904beaSFeras Daoud int err = 0; 326ae904beaSFeras Daoud s64 ns; 327ae904beaSFeras Daoud 3287c39afb3SFeras Daoud if (!MLX5_PPS_CAP(mdev)) 329ae904beaSFeras Daoud return -EOPNOTSUPP; 330ae904beaSFeras Daoud 3317f9048f1SJacob Keller /* Reject requests with unsupported flags */ 3327f9048f1SJacob Keller if (rq->perout.flags) 3337f9048f1SJacob Keller return -EOPNOTSUPP; 3347f9048f1SJacob Keller 3357c39afb3SFeras Daoud if (rq->perout.index >= clock->ptp_info.n_pins) 336ae904beaSFeras Daoud return -EINVAL; 337ae904beaSFeras Daoud 3387c39afb3SFeras Daoud pin = ptp_find_pin(clock->ptp, PTP_PF_PEROUT, 339ae904beaSFeras Daoud rq->perout.index); 340ae904beaSFeras Daoud if (pin < 0) 341ae904beaSFeras Daoud return -EBUSY; 342ae904beaSFeras Daoud 34388c8cf92SEran Ben Elisha if (on) { 3447c39afb3SFeras Daoud pin_mode = MLX5_PIN_MODE_OUT; 3457c39afb3SFeras Daoud pattern = MLX5_OUT_PATTERN_PERIODIC; 346ae904beaSFeras Daoud ts.tv_sec = rq->perout.period.sec; 347ae904beaSFeras Daoud ts.tv_nsec = rq->perout.period.nsec; 348ae904beaSFeras Daoud ns = timespec64_to_ns(&ts); 349ae904beaSFeras Daoud 350ae904beaSFeras Daoud if ((ns >> 1) != 500000000LL) 351ae904beaSFeras Daoud return -EINVAL; 352ae904beaSFeras Daoud 353ae904beaSFeras Daoud ts.tv_sec = rq->perout.start.sec; 354ae904beaSFeras Daoud ts.tv_nsec = rq->perout.start.nsec; 355ae904beaSFeras Daoud ns = timespec64_to_ns(&ts); 3564a0475d5SMiroslav Lichvar cycles_now = mlx5_read_internal_timer(mdev, NULL); 35764109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 3587c39afb3SFeras Daoud nsec_now = timecounter_cyc2time(&clock->tc, cycles_now); 359ae904beaSFeras Daoud nsec_delta = ns - nsec_now; 3607c39afb3SFeras Daoud cycles_delta = div64_u64(nsec_delta << clock->cycles.shift, 3617c39afb3SFeras Daoud clock->cycles.mult); 36264109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 363ae904beaSFeras Daoud time_stamp = cycles_now + cycles_delta; 3647c39afb3SFeras Daoud field_select = MLX5_MTPPS_FS_PIN_MODE | 3657c39afb3SFeras Daoud MLX5_MTPPS_FS_PATTERN | 3667c39afb3SFeras Daoud MLX5_MTPPS_FS_ENABLE | 3677c39afb3SFeras Daoud MLX5_MTPPS_FS_TIME_STAMP; 368ae904beaSFeras Daoud } else { 3697c39afb3SFeras Daoud field_select = MLX5_MTPPS_FS_ENABLE; 370ae904beaSFeras Daoud } 371ae904beaSFeras Daoud 372ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pin, pin); 373ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pin_mode, pin_mode); 374ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, pattern, pattern); 375ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, enable, on); 376ae904beaSFeras Daoud MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp); 377ae904beaSFeras Daoud MLX5_SET(mtpps_reg, in, field_select, field_select); 378ae904beaSFeras Daoud 3797c39afb3SFeras Daoud err = mlx5_set_mtpps(mdev, in, sizeof(in)); 380ae904beaSFeras Daoud if (err) 381ae904beaSFeras Daoud return err; 382ae904beaSFeras Daoud 3837c39afb3SFeras Daoud return mlx5_set_mtppse(mdev, pin, 0, 3847c39afb3SFeras Daoud MLX5_EVENT_MODE_REPETETIVE & on); 385ae904beaSFeras Daoud } 386ae904beaSFeras Daoud 3877c39afb3SFeras Daoud static int mlx5_pps_configure(struct ptp_clock_info *ptp, 388ae904beaSFeras Daoud struct ptp_clock_request *rq, 389ae904beaSFeras Daoud int on) 390ae904beaSFeras Daoud { 3917c39afb3SFeras Daoud struct mlx5_clock *clock = 3927c39afb3SFeras Daoud container_of(ptp, struct mlx5_clock, ptp_info); 393ae904beaSFeras Daoud 3947c39afb3SFeras Daoud clock->pps_info.enabled = !!on; 395ae904beaSFeras Daoud return 0; 396ae904beaSFeras Daoud } 397ae904beaSFeras Daoud 3987c39afb3SFeras Daoud static int mlx5_ptp_enable(struct ptp_clock_info *ptp, 399ae904beaSFeras Daoud struct ptp_clock_request *rq, 400ae904beaSFeras Daoud int on) 401ae904beaSFeras Daoud { 402ae904beaSFeras Daoud switch (rq->type) { 403ae904beaSFeras Daoud case PTP_CLK_REQ_EXTTS: 4047c39afb3SFeras Daoud return mlx5_extts_configure(ptp, rq, on); 405ae904beaSFeras Daoud case PTP_CLK_REQ_PEROUT: 4067c39afb3SFeras Daoud return mlx5_perout_configure(ptp, rq, on); 407ae904beaSFeras Daoud case PTP_CLK_REQ_PPS: 4087c39afb3SFeras Daoud return mlx5_pps_configure(ptp, rq, on); 409ae904beaSFeras Daoud default: 410ae904beaSFeras Daoud return -EOPNOTSUPP; 411ae904beaSFeras Daoud } 412ae904beaSFeras Daoud return 0; 413ae904beaSFeras Daoud } 414ae904beaSFeras Daoud 415071995c8SEran Ben Elisha enum { 416071995c8SEran Ben Elisha MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = BIT(0), 417071995c8SEran Ben Elisha MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = BIT(1), 418071995c8SEran Ben Elisha }; 419071995c8SEran Ben Elisha 4207c39afb3SFeras Daoud static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 421ae904beaSFeras Daoud enum ptp_pin_function func, unsigned int chan) 422ae904beaSFeras Daoud { 423071995c8SEran Ben Elisha struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, 424071995c8SEran Ben Elisha ptp_info); 425071995c8SEran Ben Elisha 426071995c8SEran Ben Elisha switch (func) { 427071995c8SEran Ben Elisha case PTP_PF_NONE: 428071995c8SEran Ben Elisha return 0; 429071995c8SEran Ben Elisha case PTP_PF_EXTTS: 430071995c8SEran Ben Elisha return !(clock->pps_info.pin_caps[pin] & 431071995c8SEran Ben Elisha MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN); 432071995c8SEran Ben Elisha case PTP_PF_PEROUT: 433071995c8SEran Ben Elisha return !(clock->pps_info.pin_caps[pin] & 434071995c8SEran Ben Elisha MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT); 435071995c8SEran Ben Elisha default: 436071995c8SEran Ben Elisha return -EOPNOTSUPP; 437071995c8SEran Ben Elisha } 438071995c8SEran Ben Elisha 439071995c8SEran Ben Elisha return -EOPNOTSUPP; 440ae904beaSFeras Daoud } 441ae904beaSFeras Daoud 4427c39afb3SFeras Daoud static const struct ptp_clock_info mlx5_ptp_clock_info = { 443ae904beaSFeras Daoud .owner = THIS_MODULE, 444aac2df7fSEran Ben Elisha .name = "mlx5_ptp", 445ae904beaSFeras Daoud .max_adj = 100000000, 446ae904beaSFeras Daoud .n_alarm = 0, 447ae904beaSFeras Daoud .n_ext_ts = 0, 448ae904beaSFeras Daoud .n_per_out = 0, 449ae904beaSFeras Daoud .n_pins = 0, 450ae904beaSFeras Daoud .pps = 0, 4517c39afb3SFeras Daoud .adjfreq = mlx5_ptp_adjfreq, 4527c39afb3SFeras Daoud .adjtime = mlx5_ptp_adjtime, 4534a0475d5SMiroslav Lichvar .gettimex64 = mlx5_ptp_gettimex, 4547c39afb3SFeras Daoud .settime64 = mlx5_ptp_settime, 455ae904beaSFeras Daoud .enable = NULL, 456ae904beaSFeras Daoud .verify = NULL, 457ae904beaSFeras Daoud }; 458ae904beaSFeras Daoud 459ed56d749SEran Ben Elisha static int mlx5_query_mtpps_pin_mode(struct mlx5_core_dev *mdev, u8 pin, 460ed56d749SEran Ben Elisha u32 *mtpps, u32 mtpps_size) 461ed56d749SEran Ben Elisha { 462ed56d749SEran Ben Elisha u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {}; 463ed56d749SEran Ben Elisha 464ed56d749SEran Ben Elisha MLX5_SET(mtpps_reg, in, pin, pin); 465ed56d749SEran Ben Elisha 466ed56d749SEran Ben Elisha return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps, 467ed56d749SEran Ben Elisha mtpps_size, MLX5_REG_MTPPS, 0, 0); 468ed56d749SEran Ben Elisha } 469ed56d749SEran Ben Elisha 470ed56d749SEran Ben Elisha static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin) 471ed56d749SEran Ben Elisha { 472fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); 473fb609b51SEran Ben Elisha 474ed56d749SEran Ben Elisha u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {}; 475ed56d749SEran Ben Elisha u8 mode; 476ed56d749SEran Ben Elisha int err; 477ed56d749SEran Ben Elisha 478ed56d749SEran Ben Elisha err = mlx5_query_mtpps_pin_mode(mdev, pin, out, sizeof(out)); 479ed56d749SEran Ben Elisha if (err || !MLX5_GET(mtpps_reg, out, enable)) 480ed56d749SEran Ben Elisha return PTP_PF_NONE; 481ed56d749SEran Ben Elisha 482ed56d749SEran Ben Elisha mode = MLX5_GET(mtpps_reg, out, pin_mode); 483ed56d749SEran Ben Elisha 484ed56d749SEran Ben Elisha if (mode == MLX5_PIN_MODE_IN) 485ed56d749SEran Ben Elisha return PTP_PF_EXTTS; 486ed56d749SEran Ben Elisha else if (mode == MLX5_PIN_MODE_OUT) 487ed56d749SEran Ben Elisha return PTP_PF_PEROUT; 488ed56d749SEran Ben Elisha 489ed56d749SEran Ben Elisha return PTP_PF_NONE; 490ed56d749SEran Ben Elisha } 491ed56d749SEran Ben Elisha 4927c39afb3SFeras Daoud static int mlx5_init_pin_config(struct mlx5_clock *clock) 493ae904beaSFeras Daoud { 494ae904beaSFeras Daoud int i; 495ae904beaSFeras Daoud 4967c39afb3SFeras Daoud clock->ptp_info.pin_config = 4976396bb22SKees Cook kcalloc(clock->ptp_info.n_pins, 4986396bb22SKees Cook sizeof(*clock->ptp_info.pin_config), 4996396bb22SKees Cook GFP_KERNEL); 5007c39afb3SFeras Daoud if (!clock->ptp_info.pin_config) 501ae904beaSFeras Daoud return -ENOMEM; 5027c39afb3SFeras Daoud clock->ptp_info.enable = mlx5_ptp_enable; 5037c39afb3SFeras Daoud clock->ptp_info.verify = mlx5_ptp_verify; 5047c39afb3SFeras Daoud clock->ptp_info.pps = 1; 505ae904beaSFeras Daoud 5067c39afb3SFeras Daoud for (i = 0; i < clock->ptp_info.n_pins; i++) { 5077c39afb3SFeras Daoud snprintf(clock->ptp_info.pin_config[i].name, 5087c39afb3SFeras Daoud sizeof(clock->ptp_info.pin_config[i].name), 509ae904beaSFeras Daoud "mlx5_pps%d", i); 5107c39afb3SFeras Daoud clock->ptp_info.pin_config[i].index = i; 511ed56d749SEran Ben Elisha clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(clock, i); 51288c8cf92SEran Ben Elisha clock->ptp_info.pin_config[i].chan = 0; 513ae904beaSFeras Daoud } 514ae904beaSFeras Daoud 515ae904beaSFeras Daoud return 0; 516ae904beaSFeras Daoud } 517ae904beaSFeras Daoud 5187c39afb3SFeras Daoud static void mlx5_get_pps_caps(struct mlx5_core_dev *mdev) 519ae904beaSFeras Daoud { 5207c39afb3SFeras Daoud struct mlx5_clock *clock = &mdev->clock; 521ae904beaSFeras Daoud u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; 522ae904beaSFeras Daoud 5237c39afb3SFeras Daoud mlx5_query_mtpps(mdev, out, sizeof(out)); 524ae904beaSFeras Daoud 5257c39afb3SFeras Daoud clock->ptp_info.n_pins = MLX5_GET(mtpps_reg, out, 526ae904beaSFeras Daoud cap_number_of_pps_pins); 5277c39afb3SFeras Daoud clock->ptp_info.n_ext_ts = MLX5_GET(mtpps_reg, out, 528ae904beaSFeras Daoud cap_max_num_of_pps_in_pins); 5297c39afb3SFeras Daoud clock->ptp_info.n_per_out = MLX5_GET(mtpps_reg, out, 530ae904beaSFeras Daoud cap_max_num_of_pps_out_pins); 531ae904beaSFeras Daoud 5327c39afb3SFeras Daoud clock->pps_info.pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode); 5337c39afb3SFeras Daoud clock->pps_info.pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode); 5347c39afb3SFeras Daoud clock->pps_info.pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode); 5357c39afb3SFeras Daoud clock->pps_info.pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode); 5367c39afb3SFeras Daoud clock->pps_info.pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode); 5377c39afb3SFeras Daoud clock->pps_info.pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode); 5387c39afb3SFeras Daoud clock->pps_info.pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode); 5397c39afb3SFeras Daoud clock->pps_info.pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode); 540ae904beaSFeras Daoud } 541ae904beaSFeras Daoud 54241069256SSaeed Mahameed static int mlx5_pps_event(struct notifier_block *nb, 54341069256SSaeed Mahameed unsigned long type, void *data) 544ae904beaSFeras Daoud { 54541069256SSaeed Mahameed struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb); 5467c39afb3SFeras Daoud struct ptp_clock_event ptp_event; 547ae904beaSFeras Daoud u64 cycles_now, cycles_delta; 54841069256SSaeed Mahameed u64 nsec_now, nsec_delta, ns; 54941069256SSaeed Mahameed struct mlx5_eqe *eqe = data; 5507c39afb3SFeras Daoud int pin = eqe->data.pps.pin; 551fb609b51SEran Ben Elisha struct mlx5_core_dev *mdev; 55241069256SSaeed Mahameed struct timespec64 ts; 553ae904beaSFeras Daoud unsigned long flags; 554ae904beaSFeras Daoud 555fb609b51SEran Ben Elisha mdev = container_of(clock, struct mlx5_core_dev, clock); 556fb609b51SEran Ben Elisha 5577c39afb3SFeras Daoud switch (clock->ptp_info.pin_config[pin].func) { 558ae904beaSFeras Daoud case PTP_PF_EXTTS: 559afc98a0bSFeras Daoud ptp_event.index = pin; 5600d2ffdc8SEran Ben Elisha ptp_event.timestamp = 5610d2ffdc8SEran Ben Elisha mlx5_timecounter_cyc2time(clock, 562afc98a0bSFeras Daoud be64_to_cpu(eqe->data.pps.time_stamp)); 5637c39afb3SFeras Daoud if (clock->pps_info.enabled) { 5647c39afb3SFeras Daoud ptp_event.type = PTP_CLOCK_PPSUSR; 565afc98a0bSFeras Daoud ptp_event.pps_times.ts_real = 566afc98a0bSFeras Daoud ns_to_timespec64(ptp_event.timestamp); 567ae904beaSFeras Daoud } else { 5687c39afb3SFeras Daoud ptp_event.type = PTP_CLOCK_EXTTS; 569ae904beaSFeras Daoud } 57041069256SSaeed Mahameed /* TODOL clock->ptp can be NULL if ptp_clock_register failes */ 5717c39afb3SFeras Daoud ptp_clock_event(clock->ptp, &ptp_event); 572ae904beaSFeras Daoud break; 573ae904beaSFeras Daoud case PTP_PF_PEROUT: 5744a0475d5SMiroslav Lichvar mlx5_ptp_gettimex(&clock->ptp_info, &ts, NULL); 5754a0475d5SMiroslav Lichvar cycles_now = mlx5_read_internal_timer(mdev, NULL); 576ae904beaSFeras Daoud ts.tv_sec += 1; 577ae904beaSFeras Daoud ts.tv_nsec = 0; 578ae904beaSFeras Daoud ns = timespec64_to_ns(&ts); 57964109f1dSShay Agroskin write_seqlock_irqsave(&clock->lock, flags); 5807c39afb3SFeras Daoud nsec_now = timecounter_cyc2time(&clock->tc, cycles_now); 581ae904beaSFeras Daoud nsec_delta = ns - nsec_now; 5827c39afb3SFeras Daoud cycles_delta = div64_u64(nsec_delta << clock->cycles.shift, 5837c39afb3SFeras Daoud clock->cycles.mult); 5847c39afb3SFeras Daoud clock->pps_info.start[pin] = cycles_now + cycles_delta; 58564109f1dSShay Agroskin write_sequnlock_irqrestore(&clock->lock, flags); 58687f3495cSEran Ben Elisha schedule_work(&clock->pps_info.out_work); 587ae904beaSFeras Daoud break; 588ae904beaSFeras Daoud default: 58941069256SSaeed Mahameed mlx5_core_err(mdev, " Unhandled clock PPS event, func %d\n", 59041069256SSaeed Mahameed clock->ptp_info.pin_config[pin].func); 591ae904beaSFeras Daoud } 59241069256SSaeed Mahameed 59341069256SSaeed Mahameed return NOTIFY_OK; 594ae904beaSFeras Daoud } 595ae904beaSFeras Daoud 5967c39afb3SFeras Daoud void mlx5_init_clock(struct mlx5_core_dev *mdev) 597ae904beaSFeras Daoud { 5987c39afb3SFeras Daoud struct mlx5_clock *clock = &mdev->clock; 59933180beeSAriel Levkovich u64 overflow_cycles; 600ae904beaSFeras Daoud u64 ns; 601ae904beaSFeras Daoud u64 frac = 0; 602ae904beaSFeras Daoud u32 dev_freq; 603ae904beaSFeras Daoud 6047c39afb3SFeras Daoud dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz); 605ae904beaSFeras Daoud if (!dev_freq) { 6067c39afb3SFeras Daoud mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n"); 607ae904beaSFeras Daoud return; 608ae904beaSFeras Daoud } 60964109f1dSShay Agroskin seqlock_init(&clock->lock); 6107c39afb3SFeras Daoud clock->cycles.read = read_internal_timer; 6117c39afb3SFeras Daoud clock->cycles.shift = MLX5_CYCLES_SHIFT; 6127c39afb3SFeras Daoud clock->cycles.mult = clocksource_khz2mult(dev_freq, 6137c39afb3SFeras Daoud clock->cycles.shift); 6147c39afb3SFeras Daoud clock->nominal_c_mult = clock->cycles.mult; 6157c39afb3SFeras Daoud clock->cycles.mask = CLOCKSOURCE_MASK(41); 616ae904beaSFeras Daoud 6177c39afb3SFeras Daoud timecounter_init(&clock->tc, &clock->cycles, 618ae904beaSFeras Daoud ktime_to_ns(ktime_get_real())); 619ae904beaSFeras Daoud 620ae904beaSFeras Daoud /* Calculate period in seconds to call the overflow watchdog - to make 6215d867836SMiroslav Lichvar * sure counter is checked at least twice every wrap around. 62233180beeSAriel Levkovich * The period is calculated as the minimum between max HW cycles count 62333180beeSAriel Levkovich * (The clock source mask) and max amount of cycles that can be 62433180beeSAriel Levkovich * multiplied by clock multiplier where the result doesn't exceed 62533180beeSAriel Levkovich * 64bits. 626ae904beaSFeras Daoud */ 62733180beeSAriel Levkovich overflow_cycles = div64_u64(~0ULL >> 1, clock->cycles.mult); 6285d867836SMiroslav Lichvar overflow_cycles = min(overflow_cycles, div_u64(clock->cycles.mask, 3)); 62933180beeSAriel Levkovich 63033180beeSAriel Levkovich ns = cyclecounter_cyc2ns(&clock->cycles, overflow_cycles, 631ae904beaSFeras Daoud frac, &frac); 63233180beeSAriel Levkovich do_div(ns, NSEC_PER_SEC / HZ); 6337c39afb3SFeras Daoud clock->overflow_period = ns; 634ae904beaSFeras Daoud 635ddcdc368SJason Gunthorpe mdev->clock_info = 636ddcdc368SJason Gunthorpe (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL); 637ddcdc368SJason Gunthorpe if (mdev->clock_info) { 63824d33d2cSFeras Daoud mdev->clock_info->nsec = clock->tc.nsec; 63924d33d2cSFeras Daoud mdev->clock_info->cycles = clock->tc.cycle_last; 64024d33d2cSFeras Daoud mdev->clock_info->mask = clock->cycles.mask; 64124d33d2cSFeras Daoud mdev->clock_info->mult = clock->nominal_c_mult; 64224d33d2cSFeras Daoud mdev->clock_info->shift = clock->cycles.shift; 64324d33d2cSFeras Daoud mdev->clock_info->frac = clock->tc.frac; 644ddcdc368SJason Gunthorpe mdev->clock_info->overflow_period = clock->overflow_period; 64524d33d2cSFeras Daoud } 64624d33d2cSFeras Daoud 6477c39afb3SFeras Daoud INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); 6487c39afb3SFeras Daoud INIT_DELAYED_WORK(&clock->overflow_work, mlx5_timestamp_overflow); 6497c39afb3SFeras Daoud if (clock->overflow_period) 6507c39afb3SFeras Daoud schedule_delayed_work(&clock->overflow_work, 0); 651ae904beaSFeras Daoud else 6527c39afb3SFeras Daoud mlx5_core_warn(mdev, "invalid overflow period, overflow_work is not scheduled\n"); 653ae904beaSFeras Daoud 654ae904beaSFeras Daoud /* Configure the PHC */ 6557c39afb3SFeras Daoud clock->ptp_info = mlx5_ptp_clock_info; 656ae904beaSFeras Daoud 657ae904beaSFeras Daoud /* Initialize 1PPS data structures */ 6587c39afb3SFeras Daoud if (MLX5_PPS_CAP(mdev)) 6597c39afb3SFeras Daoud mlx5_get_pps_caps(mdev); 6607c39afb3SFeras Daoud if (clock->ptp_info.n_pins) 6617c39afb3SFeras Daoud mlx5_init_pin_config(clock); 662ae904beaSFeras Daoud 6637c39afb3SFeras Daoud clock->ptp = ptp_clock_register(&clock->ptp_info, 6647c39afb3SFeras Daoud &mdev->pdev->dev); 6657c39afb3SFeras Daoud if (IS_ERR(clock->ptp)) { 6667c39afb3SFeras Daoud mlx5_core_warn(mdev, "ptp_clock_register failed %ld\n", 6677c39afb3SFeras Daoud PTR_ERR(clock->ptp)); 6687c39afb3SFeras Daoud clock->ptp = NULL; 669ae904beaSFeras Daoud } 67041069256SSaeed Mahameed 67141069256SSaeed Mahameed MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); 67241069256SSaeed Mahameed mlx5_eq_notifier_register(mdev, &clock->pps_nb); 673ae904beaSFeras Daoud } 674ae904beaSFeras Daoud 6757c39afb3SFeras Daoud void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) 676ae904beaSFeras Daoud { 6777c39afb3SFeras Daoud struct mlx5_clock *clock = &mdev->clock; 678ae904beaSFeras Daoud 6797c39afb3SFeras Daoud if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) 680ae904beaSFeras Daoud return; 681ae904beaSFeras Daoud 68241069256SSaeed Mahameed mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); 6837c39afb3SFeras Daoud if (clock->ptp) { 6847c39afb3SFeras Daoud ptp_clock_unregister(clock->ptp); 6857c39afb3SFeras Daoud clock->ptp = NULL; 686ae904beaSFeras Daoud } 687ae904beaSFeras Daoud 6887c39afb3SFeras Daoud cancel_work_sync(&clock->pps_info.out_work); 6897c39afb3SFeras Daoud cancel_delayed_work_sync(&clock->overflow_work); 69024d33d2cSFeras Daoud 69124d33d2cSFeras Daoud if (mdev->clock_info) { 692ddcdc368SJason Gunthorpe free_page((unsigned long)mdev->clock_info); 69324d33d2cSFeras Daoud mdev->clock_info = NULL; 69424d33d2cSFeras Daoud } 69524d33d2cSFeras Daoud 6967c39afb3SFeras Daoud kfree(clock->ptp_info.pin_config); 697ae904beaSFeras Daoud } 698