194db3317SEli Cohen /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
294db3317SEli Cohen /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
394db3317SEli Cohen 
494db3317SEli Cohen #ifndef __MLX5_LAG_MPESW_H__
594db3317SEli Cohen #define __MLX5_LAG_MPESW_H__
694db3317SEli Cohen 
794db3317SEli Cohen #include "lag.h"
894db3317SEli Cohen #include "mlx5_core.h"
994db3317SEli Cohen 
1094db3317SEli Cohen struct lag_mpesw {
1194db3317SEli Cohen 	struct work_struct mpesw_work;
12*73af3711SRoi Dayan 	u32 pf_metadata[MLX5_MAX_PORTS];
1394db3317SEli Cohen };
1494db3317SEli Cohen 
15199abf33SRoi Dayan enum mpesw_op {
16199abf33SRoi Dayan 	MLX5_MPESW_OP_ENABLE,
17199abf33SRoi Dayan 	MLX5_MPESW_OP_DISABLE,
18199abf33SRoi Dayan };
19199abf33SRoi Dayan 
20199abf33SRoi Dayan struct mlx5_mpesw_work_st {
21199abf33SRoi Dayan 	struct work_struct work;
22199abf33SRoi Dayan 	struct mlx5_lag    *lag;
23199abf33SRoi Dayan 	enum mpesw_op      op;
24199abf33SRoi Dayan 	struct completion  comp;
25199abf33SRoi Dayan 	int result;
26199abf33SRoi Dayan };
27199abf33SRoi Dayan 
282afcfae7SRoi Dayan int mlx5_lag_mpesw_do_mirred(struct mlx5_core_dev *mdev,
292afcfae7SRoi Dayan 			     struct net_device *out_dev,
302afcfae7SRoi Dayan 			     struct netlink_ext_ack *extack);
318ce81fc0SRoi Dayan bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
32a32327a3SRoi Dayan void mlx5_lag_mpesw_disable(struct mlx5_core_dev *dev);
33a32327a3SRoi Dayan int mlx5_lag_mpesw_enable(struct mlx5_core_dev *dev);
3494db3317SEli Cohen 
3594db3317SEli Cohen #endif /* __MLX5_LAG_MPESW_H__ */
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