1 /* 2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_verbs.h> 34 #include <linux/mlx5/fs.h> 35 #include "en.h" 36 #include "en/params.h" 37 #include "ipoib.h" 38 39 #define IB_DEFAULT_Q_KEY 0xb1b 40 #define MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE 9 41 42 static int mlx5i_open(struct net_device *netdev); 43 static int mlx5i_close(struct net_device *netdev); 44 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu); 45 46 static const struct net_device_ops mlx5i_netdev_ops = { 47 .ndo_open = mlx5i_open, 48 .ndo_stop = mlx5i_close, 49 .ndo_get_stats64 = mlx5i_get_stats, 50 .ndo_init = mlx5i_dev_init, 51 .ndo_uninit = mlx5i_dev_cleanup, 52 .ndo_change_mtu = mlx5i_change_mtu, 53 .ndo_do_ioctl = mlx5i_ioctl, 54 }; 55 56 /* IPoIB mlx5 netdev profile */ 57 static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev, 58 struct mlx5e_params *params) 59 { 60 /* Override RQ params as IPoIB supports only LINKED LIST RQ for now */ 61 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, false); 62 mlx5e_set_rq_type(mdev, params); 63 mlx5e_init_rq_type_params(mdev, params); 64 65 /* RQ size in ipoib by default is 512 */ 66 params->log_rq_mtu_frames = is_kdump_kernel() ? 67 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 68 MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE; 69 70 params->lro_en = false; 71 params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN; 72 params->tunneled_offload_en = false; 73 } 74 75 /* Called directly after IPoIB netdevice was created to initialize SW structs */ 76 int mlx5i_init(struct mlx5_core_dev *mdev, struct net_device *netdev) 77 { 78 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 79 80 netif_carrier_off(netdev); 81 mlx5e_set_netdev_mtu_boundaries(priv); 82 netdev->mtu = netdev->max_mtu; 83 84 mlx5e_build_nic_params(priv, NULL, netdev->mtu); 85 mlx5i_build_nic_params(mdev, &priv->channels.params); 86 87 mlx5e_timestamp_init(priv); 88 89 /* netdev init */ 90 netdev->hw_features |= NETIF_F_SG; 91 netdev->hw_features |= NETIF_F_IP_CSUM; 92 netdev->hw_features |= NETIF_F_IPV6_CSUM; 93 netdev->hw_features |= NETIF_F_GRO; 94 netdev->hw_features |= NETIF_F_TSO; 95 netdev->hw_features |= NETIF_F_TSO6; 96 netdev->hw_features |= NETIF_F_RXCSUM; 97 netdev->hw_features |= NETIF_F_RXHASH; 98 99 netdev->netdev_ops = &mlx5i_netdev_ops; 100 netdev->ethtool_ops = &mlx5i_ethtool_ops; 101 102 return 0; 103 } 104 105 /* Called directly before IPoIB netdevice is destroyed to cleanup SW structs */ 106 void mlx5i_cleanup(struct mlx5e_priv *priv) 107 { 108 mlx5e_priv_cleanup(priv); 109 } 110 111 static void mlx5i_grp_sw_update_stats(struct mlx5e_priv *priv) 112 { 113 struct mlx5e_sw_stats s = { 0 }; 114 int i, j; 115 116 for (i = 0; i < priv->max_nch; i++) { 117 struct mlx5e_channel_stats *channel_stats; 118 struct mlx5e_rq_stats *rq_stats; 119 120 channel_stats = &priv->channel_stats[i]; 121 rq_stats = &channel_stats->rq; 122 123 s.rx_packets += rq_stats->packets; 124 s.rx_bytes += rq_stats->bytes; 125 126 for (j = 0; j < priv->max_opened_tc; j++) { 127 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 128 129 s.tx_packets += sq_stats->packets; 130 s.tx_bytes += sq_stats->bytes; 131 s.tx_queue_dropped += sq_stats->dropped; 132 } 133 } 134 135 memcpy(&priv->stats.sw, &s, sizeof(s)); 136 } 137 138 void mlx5i_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 139 { 140 struct mlx5e_priv *priv = mlx5i_epriv(dev); 141 struct mlx5e_sw_stats *sstats = &priv->stats.sw; 142 143 mlx5i_grp_sw_update_stats(priv); 144 145 stats->rx_packets = sstats->rx_packets; 146 stats->rx_bytes = sstats->rx_bytes; 147 stats->tx_packets = sstats->tx_packets; 148 stats->tx_bytes = sstats->tx_bytes; 149 stats->tx_dropped = sstats->tx_queue_dropped; 150 } 151 152 int mlx5i_init_underlay_qp(struct mlx5e_priv *priv) 153 { 154 struct mlx5_core_dev *mdev = priv->mdev; 155 struct mlx5i_priv *ipriv = priv->ppriv; 156 int ret; 157 158 { 159 u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; 160 u32 *qpc; 161 162 qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc); 163 164 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 165 MLX5_SET(qpc, qpc, primary_address_path.pkey_index, 166 ipriv->pkey_index); 167 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 168 MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY); 169 170 MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP); 171 MLX5_SET(rst2init_qp_in, in, qpn, ipriv->qpn); 172 ret = mlx5_cmd_exec_in(mdev, rst2init_qp, in); 173 if (ret) 174 goto err_qp_modify_to_err; 175 } 176 { 177 u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; 178 179 MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP); 180 MLX5_SET(init2rtr_qp_in, in, qpn, ipriv->qpn); 181 ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, in); 182 if (ret) 183 goto err_qp_modify_to_err; 184 } 185 { 186 u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; 187 188 MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP); 189 MLX5_SET(rtr2rts_qp_in, in, qpn, ipriv->qpn); 190 ret = mlx5_cmd_exec_in(mdev, rtr2rts_qp, in); 191 if (ret) 192 goto err_qp_modify_to_err; 193 } 194 return 0; 195 196 err_qp_modify_to_err: 197 { 198 u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {}; 199 200 MLX5_SET(qp_2err_in, in, opcode, MLX5_CMD_OP_2ERR_QP); 201 MLX5_SET(qp_2err_in, in, qpn, ipriv->qpn); 202 mlx5_cmd_exec_in(mdev, qp_2err, in); 203 } 204 return ret; 205 } 206 207 void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv) 208 { 209 struct mlx5i_priv *ipriv = priv->ppriv; 210 struct mlx5_core_dev *mdev = priv->mdev; 211 u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {}; 212 213 MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP); 214 MLX5_SET(qp_2rst_in, in, qpn, ipriv->qpn); 215 mlx5_cmd_exec_in(mdev, qp_2rst, in); 216 } 217 218 #define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2 219 220 int mlx5i_create_underlay_qp(struct mlx5e_priv *priv) 221 { 222 unsigned char *dev_addr = priv->netdev->dev_addr; 223 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 224 u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {}; 225 struct mlx5i_priv *ipriv = priv->ppriv; 226 void *addr_path; 227 int qpn = 0; 228 int ret = 0; 229 void *qpc; 230 231 if (MLX5_CAP_GEN(priv->mdev, mkey_by_name)) { 232 qpn = (dev_addr[1] << 16) + (dev_addr[2] << 8) + dev_addr[3]; 233 MLX5_SET(create_qp_in, in, input_qpn, qpn); 234 } 235 236 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 237 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(priv->mdev)); 238 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD); 239 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 240 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 241 MLX5_QP_ENHANCED_ULP_STATELESS_MODE); 242 243 addr_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 244 MLX5_SET(ads, addr_path, vhca_port_num, 1); 245 MLX5_SET(ads, addr_path, grh, 1); 246 247 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 248 ret = mlx5_cmd_exec_inout(priv->mdev, create_qp, in, out); 249 if (ret) 250 return ret; 251 252 ipriv->qpn = MLX5_GET(create_qp_out, out, qpn); 253 254 return 0; 255 } 256 257 void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn) 258 { 259 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; 260 261 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); 262 MLX5_SET(destroy_qp_in, in, qpn, qpn); 263 mlx5_cmd_exec_in(mdev, destroy_qp, in); 264 } 265 266 int mlx5i_update_nic_rx(struct mlx5e_priv *priv) 267 { 268 return mlx5e_refresh_tirs(priv, true, true); 269 } 270 271 int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn) 272 { 273 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 274 void *tisc; 275 276 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 277 278 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); 279 280 return mlx5e_create_tis(mdev, in, tisn); 281 } 282 283 static int mlx5i_init_tx(struct mlx5e_priv *priv) 284 { 285 struct mlx5i_priv *ipriv = priv->ppriv; 286 int err; 287 288 err = mlx5i_create_underlay_qp(priv); 289 if (err) { 290 mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err); 291 return err; 292 } 293 294 err = mlx5i_create_tis(priv->mdev, ipriv->qpn, &priv->tisn[0][0]); 295 if (err) { 296 mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err); 297 goto err_destroy_underlay_qp; 298 } 299 300 return 0; 301 302 err_destroy_underlay_qp: 303 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn); 304 return err; 305 } 306 307 static void mlx5i_cleanup_tx(struct mlx5e_priv *priv) 308 { 309 struct mlx5i_priv *ipriv = priv->ppriv; 310 311 mlx5e_destroy_tis(priv->mdev, priv->tisn[0][0]); 312 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn); 313 } 314 315 static int mlx5i_create_flow_steering(struct mlx5e_priv *priv) 316 { 317 struct ttc_params ttc_params = {}; 318 int tt, err; 319 320 priv->fs.ns = mlx5_get_flow_namespace(priv->mdev, 321 MLX5_FLOW_NAMESPACE_KERNEL); 322 323 if (!priv->fs.ns) 324 return -EINVAL; 325 326 err = mlx5e_arfs_create_tables(priv); 327 if (err) { 328 netdev_err(priv->netdev, "Failed to create arfs tables, err=%d\n", 329 err); 330 priv->netdev->hw_features &= ~NETIF_F_NTUPLE; 331 } 332 333 mlx5e_set_ttc_basic_params(priv, &ttc_params); 334 mlx5e_set_inner_ttc_ft_params(&ttc_params); 335 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 336 ttc_params.indir_tirn[tt] = priv->inner_indir_tir[tt].tirn; 337 338 err = mlx5e_create_inner_ttc_table(priv, &ttc_params, &priv->fs.inner_ttc); 339 if (err) { 340 netdev_err(priv->netdev, "Failed to create inner ttc table, err=%d\n", 341 err); 342 goto err_destroy_arfs_tables; 343 } 344 345 mlx5e_set_ttc_ft_params(&ttc_params); 346 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 347 ttc_params.indir_tirn[tt] = priv->indir_tir[tt].tirn; 348 349 err = mlx5e_create_ttc_table(priv, &ttc_params, &priv->fs.ttc); 350 if (err) { 351 netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n", 352 err); 353 goto err_destroy_inner_ttc_table; 354 } 355 356 return 0; 357 358 err_destroy_inner_ttc_table: 359 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc); 360 err_destroy_arfs_tables: 361 mlx5e_arfs_destroy_tables(priv); 362 363 return err; 364 } 365 366 static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv) 367 { 368 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc); 369 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc); 370 mlx5e_arfs_destroy_tables(priv); 371 } 372 373 static int mlx5i_init_rx(struct mlx5e_priv *priv) 374 { 375 struct mlx5_core_dev *mdev = priv->mdev; 376 u16 max_nch = priv->max_nch; 377 int err; 378 379 mlx5e_create_q_counters(priv); 380 381 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 382 if (err) { 383 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 384 goto err_destroy_q_counters; 385 } 386 387 err = mlx5e_create_indirect_rqt(priv); 388 if (err) 389 goto err_close_drop_rq; 390 391 err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch); 392 if (err) 393 goto err_destroy_indirect_rqts; 394 395 err = mlx5e_create_indirect_tirs(priv, true); 396 if (err) 397 goto err_destroy_direct_rqts; 398 399 err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch); 400 if (err) 401 goto err_destroy_indirect_tirs; 402 403 err = mlx5i_create_flow_steering(priv); 404 if (err) 405 goto err_destroy_direct_tirs; 406 407 return 0; 408 409 err_destroy_direct_tirs: 410 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch); 411 err_destroy_indirect_tirs: 412 mlx5e_destroy_indirect_tirs(priv); 413 err_destroy_direct_rqts: 414 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch); 415 err_destroy_indirect_rqts: 416 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 417 err_close_drop_rq: 418 mlx5e_close_drop_rq(&priv->drop_rq); 419 err_destroy_q_counters: 420 mlx5e_destroy_q_counters(priv); 421 return err; 422 } 423 424 static void mlx5i_cleanup_rx(struct mlx5e_priv *priv) 425 { 426 u16 max_nch = priv->max_nch; 427 428 mlx5i_destroy_flow_steering(priv); 429 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch); 430 mlx5e_destroy_indirect_tirs(priv); 431 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch); 432 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 433 mlx5e_close_drop_rq(&priv->drop_rq); 434 mlx5e_destroy_q_counters(priv); 435 } 436 437 /* The stats groups order is opposite to the update_stats() order calls */ 438 static mlx5e_stats_grp_t mlx5i_stats_grps[] = { 439 &MLX5E_STATS_GRP(sw), 440 &MLX5E_STATS_GRP(qcnt), 441 &MLX5E_STATS_GRP(vnic_env), 442 &MLX5E_STATS_GRP(vport), 443 &MLX5E_STATS_GRP(802_3), 444 &MLX5E_STATS_GRP(2863), 445 &MLX5E_STATS_GRP(2819), 446 &MLX5E_STATS_GRP(phy), 447 &MLX5E_STATS_GRP(pcie), 448 &MLX5E_STATS_GRP(per_prio), 449 &MLX5E_STATS_GRP(pme), 450 &MLX5E_STATS_GRP(channels), 451 &MLX5E_STATS_GRP(per_port_buff_congest), 452 }; 453 454 static unsigned int mlx5i_stats_grps_num(struct mlx5e_priv *priv) 455 { 456 return ARRAY_SIZE(mlx5i_stats_grps); 457 } 458 459 static const struct mlx5e_profile mlx5i_nic_profile = { 460 .init = mlx5i_init, 461 .cleanup = mlx5i_cleanup, 462 .init_tx = mlx5i_init_tx, 463 .cleanup_tx = mlx5i_cleanup_tx, 464 .init_rx = mlx5i_init_rx, 465 .cleanup_rx = mlx5i_cleanup_rx, 466 .enable = NULL, /* mlx5i_enable */ 467 .disable = NULL, /* mlx5i_disable */ 468 .update_rx = mlx5i_update_nic_rx, 469 .update_stats = NULL, /* mlx5i_update_stats */ 470 .update_carrier = NULL, /* no HW update in IB link */ 471 .rx_handlers = &mlx5i_rx_handlers, 472 .max_tc = MLX5I_MAX_NUM_TC, 473 .rq_groups = MLX5E_NUM_RQ_GROUPS(REGULAR), 474 .stats_grps = mlx5i_stats_grps, 475 .stats_grps_num = mlx5i_stats_grps_num, 476 .rx_ptp_support = false, 477 }; 478 479 /* mlx5i netdev NDos */ 480 481 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu) 482 { 483 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 484 struct mlx5e_params new_params; 485 int err = 0; 486 487 mutex_lock(&priv->state_lock); 488 489 new_params = priv->channels.params; 490 new_params.sw_mtu = new_mtu; 491 492 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 493 if (err) 494 goto out; 495 496 netdev->mtu = new_params.sw_mtu; 497 498 out: 499 mutex_unlock(&priv->state_lock); 500 return err; 501 } 502 503 int mlx5i_dev_init(struct net_device *dev) 504 { 505 struct mlx5e_priv *priv = mlx5i_epriv(dev); 506 struct mlx5i_priv *ipriv = priv->ppriv; 507 508 /* Set dev address using underlay QP */ 509 dev->dev_addr[1] = (ipriv->qpn >> 16) & 0xff; 510 dev->dev_addr[2] = (ipriv->qpn >> 8) & 0xff; 511 dev->dev_addr[3] = (ipriv->qpn) & 0xff; 512 513 /* Add QPN to net-device mapping to HT */ 514 mlx5i_pkey_add_qpn(dev, ipriv->qpn); 515 516 return 0; 517 } 518 519 int mlx5i_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 520 { 521 struct mlx5e_priv *priv = mlx5i_epriv(dev); 522 523 switch (cmd) { 524 case SIOCSHWTSTAMP: 525 return mlx5e_hwstamp_set(priv, ifr); 526 case SIOCGHWTSTAMP: 527 return mlx5e_hwstamp_get(priv, ifr); 528 default: 529 return -EOPNOTSUPP; 530 } 531 } 532 533 void mlx5i_dev_cleanup(struct net_device *dev) 534 { 535 struct mlx5e_priv *priv = mlx5i_epriv(dev); 536 struct mlx5i_priv *ipriv = priv->ppriv; 537 538 mlx5i_uninit_underlay_qp(priv); 539 540 /* Delete QPN to net-device mapping from HT */ 541 mlx5i_pkey_del_qpn(dev, ipriv->qpn); 542 } 543 544 static int mlx5i_open(struct net_device *netdev) 545 { 546 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 547 struct mlx5i_priv *ipriv = epriv->ppriv; 548 struct mlx5_core_dev *mdev = epriv->mdev; 549 int err; 550 551 mutex_lock(&epriv->state_lock); 552 553 set_bit(MLX5E_STATE_OPENED, &epriv->state); 554 555 err = mlx5i_init_underlay_qp(epriv); 556 if (err) { 557 mlx5_core_warn(mdev, "prepare underlay qp state failed, %d\n", err); 558 goto err_clear_state_opened_flag; 559 } 560 561 err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn); 562 if (err) { 563 mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err); 564 goto err_reset_qp; 565 } 566 567 err = mlx5e_open_channels(epriv, &epriv->channels); 568 if (err) 569 goto err_remove_fs_underlay_qp; 570 571 epriv->profile->update_rx(epriv); 572 mlx5e_activate_priv_channels(epriv); 573 574 mutex_unlock(&epriv->state_lock); 575 return 0; 576 577 err_remove_fs_underlay_qp: 578 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn); 579 err_reset_qp: 580 mlx5i_uninit_underlay_qp(epriv); 581 err_clear_state_opened_flag: 582 clear_bit(MLX5E_STATE_OPENED, &epriv->state); 583 mutex_unlock(&epriv->state_lock); 584 return err; 585 } 586 587 static int mlx5i_close(struct net_device *netdev) 588 { 589 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 590 struct mlx5i_priv *ipriv = epriv->ppriv; 591 struct mlx5_core_dev *mdev = epriv->mdev; 592 593 /* May already be CLOSED in case a previous configuration operation 594 * (e.g RX/TX queue size change) that involves close&open failed. 595 */ 596 mutex_lock(&epriv->state_lock); 597 598 if (!test_bit(MLX5E_STATE_OPENED, &epriv->state)) 599 goto unlock; 600 601 clear_bit(MLX5E_STATE_OPENED, &epriv->state); 602 603 netif_carrier_off(epriv->netdev); 604 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn); 605 mlx5e_deactivate_priv_channels(epriv); 606 mlx5e_close_channels(&epriv->channels); 607 mlx5i_uninit_underlay_qp(epriv); 608 unlock: 609 mutex_unlock(&epriv->state_lock); 610 return 0; 611 } 612 613 /* IPoIB RDMA netdev callbacks */ 614 static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca, 615 union ib_gid *gid, u16 lid, int set_qkey, 616 u32 qkey) 617 { 618 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 619 struct mlx5_core_dev *mdev = epriv->mdev; 620 struct mlx5i_priv *ipriv = epriv->ppriv; 621 int err; 622 623 mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qpn, 624 gid->raw); 625 err = mlx5_core_attach_mcg(mdev, gid, ipriv->qpn); 626 if (err) 627 mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n", 628 ipriv->qpn, gid->raw); 629 630 if (set_qkey) { 631 mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n", 632 netdev->name, qkey); 633 ipriv->qkey = qkey; 634 } 635 636 return err; 637 } 638 639 static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca, 640 union ib_gid *gid, u16 lid) 641 { 642 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 643 struct mlx5_core_dev *mdev = epriv->mdev; 644 struct mlx5i_priv *ipriv = epriv->ppriv; 645 int err; 646 647 mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qpn, 648 gid->raw); 649 650 err = mlx5_core_detach_mcg(mdev, gid, ipriv->qpn); 651 if (err) 652 mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n", 653 ipriv->qpn, gid->raw); 654 655 return err; 656 } 657 658 static int mlx5i_xmit(struct net_device *dev, struct sk_buff *skb, 659 struct ib_ah *address, u32 dqpn) 660 { 661 struct mlx5e_priv *epriv = mlx5i_epriv(dev); 662 struct mlx5e_txqsq *sq = epriv->txq2sq[skb_get_queue_mapping(skb)]; 663 struct mlx5_ib_ah *mah = to_mah(address); 664 struct mlx5i_priv *ipriv = epriv->ppriv; 665 666 mlx5i_sq_xmit(sq, skb, &mah->av, dqpn, ipriv->qkey, netdev_xmit_more()); 667 668 return NETDEV_TX_OK; 669 } 670 671 static void mlx5i_set_pkey_index(struct net_device *netdev, int id) 672 { 673 struct mlx5i_priv *ipriv = netdev_priv(netdev); 674 675 ipriv->pkey_index = (u16)id; 676 } 677 678 static int mlx5i_check_required_hca_cap(struct mlx5_core_dev *mdev) 679 { 680 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 681 return -EOPNOTSUPP; 682 683 if (!MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) { 684 mlx5_core_warn(mdev, "IPoIB enhanced offloads are not supported\n"); 685 return -EOPNOTSUPP; 686 } 687 688 return 0; 689 } 690 691 static void mlx5_rdma_netdev_free(struct net_device *netdev) 692 { 693 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 694 struct mlx5_core_dev *mdev = priv->mdev; 695 struct mlx5i_priv *ipriv = priv->ppriv; 696 const struct mlx5e_profile *profile = priv->profile; 697 698 mlx5e_detach_netdev(priv); 699 profile->cleanup(priv); 700 701 if (!ipriv->sub_interface) { 702 mlx5i_pkey_qpn_ht_cleanup(netdev); 703 mlx5e_destroy_mdev_resources(mdev); 704 } 705 } 706 707 static bool mlx5_is_sub_interface(struct mlx5_core_dev *mdev) 708 { 709 return mdev->mlx5e_res.hw_objs.pdn != 0; 710 } 711 712 static const struct mlx5e_profile *mlx5_get_profile(struct mlx5_core_dev *mdev) 713 { 714 if (mlx5_is_sub_interface(mdev)) 715 return mlx5i_pkey_get_profile(); 716 return &mlx5i_nic_profile; 717 } 718 719 static int mlx5_rdma_setup_rn(struct ib_device *ibdev, u32 port_num, 720 struct net_device *netdev, void *param) 721 { 722 struct mlx5_core_dev *mdev = (struct mlx5_core_dev *)param; 723 const struct mlx5e_profile *prof = mlx5_get_profile(mdev); 724 struct mlx5i_priv *ipriv; 725 struct mlx5e_priv *epriv; 726 struct rdma_netdev *rn; 727 int err; 728 729 ipriv = netdev_priv(netdev); 730 epriv = mlx5i_epriv(netdev); 731 732 ipriv->sub_interface = mlx5_is_sub_interface(mdev); 733 if (!ipriv->sub_interface) { 734 err = mlx5i_pkey_qpn_ht_init(netdev); 735 if (err) { 736 mlx5_core_warn(mdev, "allocate qpn_to_netdev ht failed\n"); 737 return err; 738 } 739 740 /* This should only be called once per mdev */ 741 err = mlx5e_create_mdev_resources(mdev); 742 if (err) 743 goto destroy_ht; 744 } 745 746 err = mlx5e_priv_init(epriv, netdev, mdev); 747 if (err) 748 goto destroy_mdev_resources; 749 750 epriv->profile = prof; 751 epriv->ppriv = ipriv; 752 753 prof->init(mdev, netdev); 754 755 err = mlx5e_attach_netdev(epriv); 756 if (err) 757 goto detach; 758 netif_carrier_off(netdev); 759 760 /* set rdma_netdev func pointers */ 761 rn = &ipriv->rn; 762 rn->hca = ibdev; 763 rn->send = mlx5i_xmit; 764 rn->attach_mcast = mlx5i_attach_mcast; 765 rn->detach_mcast = mlx5i_detach_mcast; 766 rn->set_id = mlx5i_set_pkey_index; 767 768 netdev->priv_destructor = mlx5_rdma_netdev_free; 769 netdev->needs_free_netdev = 1; 770 771 return 0; 772 773 detach: 774 prof->cleanup(epriv); 775 if (ipriv->sub_interface) 776 return err; 777 destroy_mdev_resources: 778 mlx5e_destroy_mdev_resources(mdev); 779 destroy_ht: 780 mlx5i_pkey_qpn_ht_cleanup(netdev); 781 return err; 782 } 783 784 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 785 struct ib_device *device, 786 struct rdma_netdev_alloc_params *params) 787 { 788 int nch; 789 int rc; 790 791 rc = mlx5i_check_required_hca_cap(mdev); 792 if (rc) 793 return rc; 794 795 nch = mlx5e_get_max_num_channels(mdev); 796 797 *params = (struct rdma_netdev_alloc_params){ 798 .sizeof_priv = sizeof(struct mlx5i_priv) + 799 sizeof(struct mlx5e_priv), 800 .txqs = nch * MLX5E_MAX_NUM_TC, 801 .rxqs = nch, 802 .param = mdev, 803 .initialize_rdma_netdev = mlx5_rdma_setup_rn, 804 }; 805 806 return 0; 807 } 808 EXPORT_SYMBOL(mlx5_rdma_rn_get_params); 809