1 /* 2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_verbs.h> 34 #include <linux/mlx5/fs.h> 35 #include "en.h" 36 #include "ipoib.h" 37 38 #define IB_DEFAULT_Q_KEY 0xb1b 39 #define MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE 9 40 41 static int mlx5i_open(struct net_device *netdev); 42 static int mlx5i_close(struct net_device *netdev); 43 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu); 44 45 static const struct net_device_ops mlx5i_netdev_ops = { 46 .ndo_open = mlx5i_open, 47 .ndo_stop = mlx5i_close, 48 .ndo_get_stats64 = mlx5i_get_stats, 49 .ndo_init = mlx5i_dev_init, 50 .ndo_uninit = mlx5i_dev_cleanup, 51 .ndo_change_mtu = mlx5i_change_mtu, 52 .ndo_do_ioctl = mlx5i_ioctl, 53 }; 54 55 /* IPoIB mlx5 netdev profile */ 56 static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev, 57 struct mlx5e_params *params) 58 { 59 /* Override RQ params as IPoIB supports only LINKED LIST RQ for now */ 60 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, false); 61 mlx5e_set_rq_type(mdev, params); 62 mlx5e_init_rq_type_params(mdev, params); 63 64 /* RQ size in ipoib by default is 512 */ 65 params->log_rq_mtu_frames = is_kdump_kernel() ? 66 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 67 MLX5I_PARAMS_DEFAULT_LOG_RQ_SIZE; 68 69 params->lro_en = false; 70 params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN; 71 params->tunneled_offload_en = false; 72 } 73 74 /* Called directly after IPoIB netdevice was created to initialize SW structs */ 75 int mlx5i_init(struct mlx5_core_dev *mdev, 76 struct net_device *netdev, 77 const struct mlx5e_profile *profile, 78 void *ppriv) 79 { 80 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 81 int err; 82 83 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv); 84 if (err) 85 return err; 86 87 mlx5e_set_netdev_mtu_boundaries(priv); 88 netdev->mtu = netdev->max_mtu; 89 90 mlx5e_build_nic_params(priv, NULL, &priv->rss_params, &priv->channels.params, 91 netdev->mtu); 92 mlx5i_build_nic_params(mdev, &priv->channels.params); 93 94 mlx5e_timestamp_init(priv); 95 96 /* netdev init */ 97 netdev->hw_features |= NETIF_F_SG; 98 netdev->hw_features |= NETIF_F_IP_CSUM; 99 netdev->hw_features |= NETIF_F_IPV6_CSUM; 100 netdev->hw_features |= NETIF_F_GRO; 101 netdev->hw_features |= NETIF_F_TSO; 102 netdev->hw_features |= NETIF_F_TSO6; 103 netdev->hw_features |= NETIF_F_RXCSUM; 104 netdev->hw_features |= NETIF_F_RXHASH; 105 106 netdev->netdev_ops = &mlx5i_netdev_ops; 107 netdev->ethtool_ops = &mlx5i_ethtool_ops; 108 109 return 0; 110 } 111 112 /* Called directly before IPoIB netdevice is destroyed to cleanup SW structs */ 113 void mlx5i_cleanup(struct mlx5e_priv *priv) 114 { 115 mlx5e_netdev_cleanup(priv->netdev, priv); 116 } 117 118 static void mlx5i_grp_sw_update_stats(struct mlx5e_priv *priv) 119 { 120 struct mlx5e_sw_stats s = { 0 }; 121 int i, j; 122 123 for (i = 0; i < priv->max_nch; i++) { 124 struct mlx5e_channel_stats *channel_stats; 125 struct mlx5e_rq_stats *rq_stats; 126 127 channel_stats = &priv->channel_stats[i]; 128 rq_stats = &channel_stats->rq; 129 130 s.rx_packets += rq_stats->packets; 131 s.rx_bytes += rq_stats->bytes; 132 133 for (j = 0; j < priv->max_opened_tc; j++) { 134 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 135 136 s.tx_packets += sq_stats->packets; 137 s.tx_bytes += sq_stats->bytes; 138 s.tx_queue_dropped += sq_stats->dropped; 139 } 140 } 141 142 memcpy(&priv->stats.sw, &s, sizeof(s)); 143 } 144 145 void mlx5i_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 146 { 147 struct mlx5e_priv *priv = mlx5i_epriv(dev); 148 struct mlx5e_sw_stats *sstats = &priv->stats.sw; 149 150 mlx5i_grp_sw_update_stats(priv); 151 152 stats->rx_packets = sstats->rx_packets; 153 stats->rx_bytes = sstats->rx_bytes; 154 stats->tx_packets = sstats->tx_packets; 155 stats->tx_bytes = sstats->tx_bytes; 156 stats->tx_dropped = sstats->tx_queue_dropped; 157 } 158 159 int mlx5i_init_underlay_qp(struct mlx5e_priv *priv) 160 { 161 struct mlx5_core_dev *mdev = priv->mdev; 162 struct mlx5i_priv *ipriv = priv->ppriv; 163 int ret; 164 165 { 166 u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; 167 u32 *qpc; 168 169 qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc); 170 171 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 172 MLX5_SET(qpc, qpc, primary_address_path.pkey_index, 173 ipriv->pkey_index); 174 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 175 MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY); 176 177 MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP); 178 MLX5_SET(rst2init_qp_in, in, qpn, ipriv->qpn); 179 ret = mlx5_cmd_exec_in(mdev, rst2init_qp, in); 180 if (ret) 181 goto err_qp_modify_to_err; 182 } 183 { 184 u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; 185 186 MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP); 187 MLX5_SET(init2rtr_qp_in, in, qpn, ipriv->qpn); 188 ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, in); 189 if (ret) 190 goto err_qp_modify_to_err; 191 } 192 { 193 u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; 194 195 MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP); 196 MLX5_SET(rtr2rts_qp_in, in, qpn, ipriv->qpn); 197 ret = mlx5_cmd_exec_in(mdev, rtr2rts_qp, in); 198 if (ret) 199 goto err_qp_modify_to_err; 200 } 201 return 0; 202 203 err_qp_modify_to_err: 204 { 205 u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {}; 206 207 MLX5_SET(qp_2err_in, in, opcode, MLX5_CMD_OP_2ERR_QP); 208 MLX5_SET(qp_2err_in, in, qpn, ipriv->qpn); 209 mlx5_cmd_exec_in(mdev, qp_2err, in); 210 } 211 return ret; 212 } 213 214 void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv) 215 { 216 struct mlx5i_priv *ipriv = priv->ppriv; 217 struct mlx5_core_dev *mdev = priv->mdev; 218 u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {}; 219 220 MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP); 221 MLX5_SET(qp_2rst_in, in, qpn, ipriv->qpn); 222 mlx5_cmd_exec_in(mdev, qp_2rst, in); 223 } 224 225 #define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2 226 227 int mlx5i_create_underlay_qp(struct mlx5e_priv *priv) 228 { 229 unsigned char *dev_addr = priv->netdev->dev_addr; 230 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 231 u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {}; 232 struct mlx5i_priv *ipriv = priv->ppriv; 233 void *addr_path; 234 int qpn = 0; 235 int ret = 0; 236 void *qpc; 237 238 if (MLX5_CAP_GEN(priv->mdev, mkey_by_name)) { 239 qpn = (dev_addr[1] << 16) + (dev_addr[2] << 8) + dev_addr[3]; 240 MLX5_SET(create_qp_in, in, input_qpn, qpn); 241 } 242 243 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 244 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD); 245 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 246 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 247 MLX5_QP_ENHANCED_ULP_STATELESS_MODE); 248 249 addr_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 250 MLX5_SET(ads, addr_path, vhca_port_num, 1); 251 MLX5_SET(ads, addr_path, grh, 1); 252 253 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 254 ret = mlx5_cmd_exec_inout(priv->mdev, create_qp, in, out); 255 if (ret) 256 return ret; 257 258 ipriv->qpn = MLX5_GET(create_qp_out, out, qpn); 259 260 return 0; 261 } 262 263 void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn) 264 { 265 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; 266 267 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); 268 MLX5_SET(destroy_qp_in, in, qpn, qpn); 269 mlx5_cmd_exec_in(mdev, destroy_qp, in); 270 } 271 272 int mlx5i_update_nic_rx(struct mlx5e_priv *priv) 273 { 274 return mlx5e_refresh_tirs(priv, true, true); 275 } 276 277 int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn) 278 { 279 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 280 void *tisc; 281 282 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 283 284 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); 285 286 return mlx5e_create_tis(mdev, in, tisn); 287 } 288 289 static int mlx5i_init_tx(struct mlx5e_priv *priv) 290 { 291 struct mlx5i_priv *ipriv = priv->ppriv; 292 int err; 293 294 err = mlx5i_create_underlay_qp(priv); 295 if (err) { 296 mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err); 297 return err; 298 } 299 300 err = mlx5i_create_tis(priv->mdev, ipriv->qpn, &priv->tisn[0][0]); 301 if (err) { 302 mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err); 303 goto err_destroy_underlay_qp; 304 } 305 306 return 0; 307 308 err_destroy_underlay_qp: 309 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn); 310 return err; 311 } 312 313 static void mlx5i_cleanup_tx(struct mlx5e_priv *priv) 314 { 315 struct mlx5i_priv *ipriv = priv->ppriv; 316 317 mlx5e_destroy_tis(priv->mdev, priv->tisn[0][0]); 318 mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn); 319 } 320 321 static int mlx5i_create_flow_steering(struct mlx5e_priv *priv) 322 { 323 struct ttc_params ttc_params = {}; 324 int tt, err; 325 326 priv->fs.ns = mlx5_get_flow_namespace(priv->mdev, 327 MLX5_FLOW_NAMESPACE_KERNEL); 328 329 if (!priv->fs.ns) 330 return -EINVAL; 331 332 err = mlx5e_arfs_create_tables(priv); 333 if (err) { 334 netdev_err(priv->netdev, "Failed to create arfs tables, err=%d\n", 335 err); 336 priv->netdev->hw_features &= ~NETIF_F_NTUPLE; 337 } 338 339 mlx5e_set_ttc_basic_params(priv, &ttc_params); 340 mlx5e_set_inner_ttc_ft_params(&ttc_params); 341 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 342 ttc_params.indir_tirn[tt] = priv->inner_indir_tir[tt].tirn; 343 344 err = mlx5e_create_inner_ttc_table(priv, &ttc_params, &priv->fs.inner_ttc); 345 if (err) { 346 netdev_err(priv->netdev, "Failed to create inner ttc table, err=%d\n", 347 err); 348 goto err_destroy_arfs_tables; 349 } 350 351 mlx5e_set_ttc_ft_params(&ttc_params); 352 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 353 ttc_params.indir_tirn[tt] = priv->indir_tir[tt].tirn; 354 355 err = mlx5e_create_ttc_table(priv, &ttc_params, &priv->fs.ttc); 356 if (err) { 357 netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n", 358 err); 359 goto err_destroy_inner_ttc_table; 360 } 361 362 return 0; 363 364 err_destroy_inner_ttc_table: 365 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc); 366 err_destroy_arfs_tables: 367 mlx5e_arfs_destroy_tables(priv); 368 369 return err; 370 } 371 372 static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv) 373 { 374 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc); 375 mlx5e_destroy_inner_ttc_table(priv, &priv->fs.inner_ttc); 376 mlx5e_arfs_destroy_tables(priv); 377 } 378 379 static int mlx5i_init_rx(struct mlx5e_priv *priv) 380 { 381 struct mlx5_core_dev *mdev = priv->mdev; 382 int err; 383 384 mlx5e_create_q_counters(priv); 385 386 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 387 if (err) { 388 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 389 goto err_destroy_q_counters; 390 } 391 392 err = mlx5e_create_indirect_rqt(priv); 393 if (err) 394 goto err_close_drop_rq; 395 396 err = mlx5e_create_direct_rqts(priv, priv->direct_tir); 397 if (err) 398 goto err_destroy_indirect_rqts; 399 400 err = mlx5e_create_indirect_tirs(priv, true); 401 if (err) 402 goto err_destroy_direct_rqts; 403 404 err = mlx5e_create_direct_tirs(priv, priv->direct_tir); 405 if (err) 406 goto err_destroy_indirect_tirs; 407 408 err = mlx5i_create_flow_steering(priv); 409 if (err) 410 goto err_destroy_direct_tirs; 411 412 return 0; 413 414 err_destroy_direct_tirs: 415 mlx5e_destroy_direct_tirs(priv, priv->direct_tir); 416 err_destroy_indirect_tirs: 417 mlx5e_destroy_indirect_tirs(priv); 418 err_destroy_direct_rqts: 419 mlx5e_destroy_direct_rqts(priv, priv->direct_tir); 420 err_destroy_indirect_rqts: 421 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 422 err_close_drop_rq: 423 mlx5e_close_drop_rq(&priv->drop_rq); 424 err_destroy_q_counters: 425 mlx5e_destroy_q_counters(priv); 426 return err; 427 } 428 429 static void mlx5i_cleanup_rx(struct mlx5e_priv *priv) 430 { 431 mlx5i_destroy_flow_steering(priv); 432 mlx5e_destroy_direct_tirs(priv, priv->direct_tir); 433 mlx5e_destroy_indirect_tirs(priv); 434 mlx5e_destroy_direct_rqts(priv, priv->direct_tir); 435 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 436 mlx5e_close_drop_rq(&priv->drop_rq); 437 mlx5e_destroy_q_counters(priv); 438 } 439 440 /* The stats groups order is opposite to the update_stats() order calls */ 441 static mlx5e_stats_grp_t mlx5i_stats_grps[] = { 442 &MLX5E_STATS_GRP(sw), 443 &MLX5E_STATS_GRP(qcnt), 444 &MLX5E_STATS_GRP(vnic_env), 445 &MLX5E_STATS_GRP(vport), 446 &MLX5E_STATS_GRP(802_3), 447 &MLX5E_STATS_GRP(2863), 448 &MLX5E_STATS_GRP(2819), 449 &MLX5E_STATS_GRP(phy), 450 &MLX5E_STATS_GRP(pcie), 451 &MLX5E_STATS_GRP(per_prio), 452 &MLX5E_STATS_GRP(pme), 453 &MLX5E_STATS_GRP(channels), 454 &MLX5E_STATS_GRP(per_port_buff_congest), 455 }; 456 457 static unsigned int mlx5i_stats_grps_num(struct mlx5e_priv *priv) 458 { 459 return ARRAY_SIZE(mlx5i_stats_grps); 460 } 461 462 static const struct mlx5e_profile mlx5i_nic_profile = { 463 .init = mlx5i_init, 464 .cleanup = mlx5i_cleanup, 465 .init_tx = mlx5i_init_tx, 466 .cleanup_tx = mlx5i_cleanup_tx, 467 .init_rx = mlx5i_init_rx, 468 .cleanup_rx = mlx5i_cleanup_rx, 469 .enable = NULL, /* mlx5i_enable */ 470 .disable = NULL, /* mlx5i_disable */ 471 .update_rx = mlx5i_update_nic_rx, 472 .update_stats = NULL, /* mlx5i_update_stats */ 473 .update_carrier = NULL, /* no HW update in IB link */ 474 .rx_handlers = &mlx5i_rx_handlers, 475 .max_tc = MLX5I_MAX_NUM_TC, 476 .rq_groups = MLX5E_NUM_RQ_GROUPS(REGULAR), 477 .stats_grps = mlx5i_stats_grps, 478 .stats_grps_num = mlx5i_stats_grps_num, 479 }; 480 481 /* mlx5i netdev NDos */ 482 483 static int mlx5i_change_mtu(struct net_device *netdev, int new_mtu) 484 { 485 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 486 struct mlx5e_channels new_channels = {}; 487 struct mlx5e_params *params; 488 int err = 0; 489 490 mutex_lock(&priv->state_lock); 491 492 params = &priv->channels.params; 493 494 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 495 params->sw_mtu = new_mtu; 496 netdev->mtu = params->sw_mtu; 497 goto out; 498 } 499 500 new_channels.params = *params; 501 new_channels.params.sw_mtu = new_mtu; 502 503 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 504 if (err) 505 goto out; 506 507 netdev->mtu = new_channels.params.sw_mtu; 508 509 out: 510 mutex_unlock(&priv->state_lock); 511 return err; 512 } 513 514 int mlx5i_dev_init(struct net_device *dev) 515 { 516 struct mlx5e_priv *priv = mlx5i_epriv(dev); 517 struct mlx5i_priv *ipriv = priv->ppriv; 518 519 /* Set dev address using underlay QP */ 520 dev->dev_addr[1] = (ipriv->qpn >> 16) & 0xff; 521 dev->dev_addr[2] = (ipriv->qpn >> 8) & 0xff; 522 dev->dev_addr[3] = (ipriv->qpn) & 0xff; 523 524 /* Add QPN to net-device mapping to HT */ 525 mlx5i_pkey_add_qpn(dev, ipriv->qpn); 526 527 return 0; 528 } 529 530 int mlx5i_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 531 { 532 struct mlx5e_priv *priv = mlx5i_epriv(dev); 533 534 switch (cmd) { 535 case SIOCSHWTSTAMP: 536 return mlx5e_hwstamp_set(priv, ifr); 537 case SIOCGHWTSTAMP: 538 return mlx5e_hwstamp_get(priv, ifr); 539 default: 540 return -EOPNOTSUPP; 541 } 542 } 543 544 void mlx5i_dev_cleanup(struct net_device *dev) 545 { 546 struct mlx5e_priv *priv = mlx5i_epriv(dev); 547 struct mlx5i_priv *ipriv = priv->ppriv; 548 549 mlx5i_uninit_underlay_qp(priv); 550 551 /* Delete QPN to net-device mapping from HT */ 552 mlx5i_pkey_del_qpn(dev, ipriv->qpn); 553 } 554 555 static int mlx5i_open(struct net_device *netdev) 556 { 557 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 558 struct mlx5i_priv *ipriv = epriv->ppriv; 559 struct mlx5_core_dev *mdev = epriv->mdev; 560 int err; 561 562 mutex_lock(&epriv->state_lock); 563 564 set_bit(MLX5E_STATE_OPENED, &epriv->state); 565 566 err = mlx5i_init_underlay_qp(epriv); 567 if (err) { 568 mlx5_core_warn(mdev, "prepare underlay qp state failed, %d\n", err); 569 goto err_clear_state_opened_flag; 570 } 571 572 err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn); 573 if (err) { 574 mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err); 575 goto err_reset_qp; 576 } 577 578 err = mlx5e_open_channels(epriv, &epriv->channels); 579 if (err) 580 goto err_remove_fs_underlay_qp; 581 582 epriv->profile->update_rx(epriv); 583 mlx5e_activate_priv_channels(epriv); 584 585 mutex_unlock(&epriv->state_lock); 586 return 0; 587 588 err_remove_fs_underlay_qp: 589 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn); 590 err_reset_qp: 591 mlx5i_uninit_underlay_qp(epriv); 592 err_clear_state_opened_flag: 593 clear_bit(MLX5E_STATE_OPENED, &epriv->state); 594 mutex_unlock(&epriv->state_lock); 595 return err; 596 } 597 598 static int mlx5i_close(struct net_device *netdev) 599 { 600 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 601 struct mlx5i_priv *ipriv = epriv->ppriv; 602 struct mlx5_core_dev *mdev = epriv->mdev; 603 604 /* May already be CLOSED in case a previous configuration operation 605 * (e.g RX/TX queue size change) that involves close&open failed. 606 */ 607 mutex_lock(&epriv->state_lock); 608 609 if (!test_bit(MLX5E_STATE_OPENED, &epriv->state)) 610 goto unlock; 611 612 clear_bit(MLX5E_STATE_OPENED, &epriv->state); 613 614 netif_carrier_off(epriv->netdev); 615 mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn); 616 mlx5e_deactivate_priv_channels(epriv); 617 mlx5e_close_channels(&epriv->channels); 618 mlx5i_uninit_underlay_qp(epriv); 619 unlock: 620 mutex_unlock(&epriv->state_lock); 621 return 0; 622 } 623 624 /* IPoIB RDMA netdev callbacks */ 625 static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca, 626 union ib_gid *gid, u16 lid, int set_qkey, 627 u32 qkey) 628 { 629 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 630 struct mlx5_core_dev *mdev = epriv->mdev; 631 struct mlx5i_priv *ipriv = epriv->ppriv; 632 int err; 633 634 mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qpn, 635 gid->raw); 636 err = mlx5_core_attach_mcg(mdev, gid, ipriv->qpn); 637 if (err) 638 mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n", 639 ipriv->qpn, gid->raw); 640 641 if (set_qkey) { 642 mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n", 643 netdev->name, qkey); 644 ipriv->qkey = qkey; 645 } 646 647 return err; 648 } 649 650 static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca, 651 union ib_gid *gid, u16 lid) 652 { 653 struct mlx5e_priv *epriv = mlx5i_epriv(netdev); 654 struct mlx5_core_dev *mdev = epriv->mdev; 655 struct mlx5i_priv *ipriv = epriv->ppriv; 656 int err; 657 658 mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qpn, 659 gid->raw); 660 661 err = mlx5_core_detach_mcg(mdev, gid, ipriv->qpn); 662 if (err) 663 mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n", 664 ipriv->qpn, gid->raw); 665 666 return err; 667 } 668 669 static int mlx5i_xmit(struct net_device *dev, struct sk_buff *skb, 670 struct ib_ah *address, u32 dqpn) 671 { 672 struct mlx5e_priv *epriv = mlx5i_epriv(dev); 673 struct mlx5e_txqsq *sq = epriv->txq2sq[skb_get_queue_mapping(skb)]; 674 struct mlx5_ib_ah *mah = to_mah(address); 675 struct mlx5i_priv *ipriv = epriv->ppriv; 676 677 mlx5i_sq_xmit(sq, skb, &mah->av, dqpn, ipriv->qkey, netdev_xmit_more()); 678 679 return NETDEV_TX_OK; 680 } 681 682 static void mlx5i_set_pkey_index(struct net_device *netdev, int id) 683 { 684 struct mlx5i_priv *ipriv = netdev_priv(netdev); 685 686 ipriv->pkey_index = (u16)id; 687 } 688 689 static int mlx5i_check_required_hca_cap(struct mlx5_core_dev *mdev) 690 { 691 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 692 return -EOPNOTSUPP; 693 694 if (!MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) { 695 mlx5_core_warn(mdev, "IPoIB enhanced offloads are not supported\n"); 696 return -EOPNOTSUPP; 697 } 698 699 return 0; 700 } 701 702 static void mlx5_rdma_netdev_free(struct net_device *netdev) 703 { 704 struct mlx5e_priv *priv = mlx5i_epriv(netdev); 705 struct mlx5i_priv *ipriv = priv->ppriv; 706 const struct mlx5e_profile *profile = priv->profile; 707 708 mlx5e_detach_netdev(priv); 709 profile->cleanup(priv); 710 711 if (!ipriv->sub_interface) { 712 mlx5i_pkey_qpn_ht_cleanup(netdev); 713 mlx5e_destroy_mdev_resources(priv->mdev); 714 } 715 } 716 717 static bool mlx5_is_sub_interface(struct mlx5_core_dev *mdev) 718 { 719 return mdev->mlx5e_res.pdn != 0; 720 } 721 722 static const struct mlx5e_profile *mlx5_get_profile(struct mlx5_core_dev *mdev) 723 { 724 if (mlx5_is_sub_interface(mdev)) 725 return mlx5i_pkey_get_profile(); 726 return &mlx5i_nic_profile; 727 } 728 729 static int mlx5_rdma_setup_rn(struct ib_device *ibdev, u8 port_num, 730 struct net_device *netdev, void *param) 731 { 732 struct mlx5_core_dev *mdev = (struct mlx5_core_dev *)param; 733 const struct mlx5e_profile *prof = mlx5_get_profile(mdev); 734 struct mlx5i_priv *ipriv; 735 struct mlx5e_priv *epriv; 736 struct rdma_netdev *rn; 737 int err; 738 739 ipriv = netdev_priv(netdev); 740 epriv = mlx5i_epriv(netdev); 741 742 ipriv->sub_interface = mlx5_is_sub_interface(mdev); 743 if (!ipriv->sub_interface) { 744 err = mlx5i_pkey_qpn_ht_init(netdev); 745 if (err) { 746 mlx5_core_warn(mdev, "allocate qpn_to_netdev ht failed\n"); 747 return err; 748 } 749 750 /* This should only be called once per mdev */ 751 err = mlx5e_create_mdev_resources(mdev); 752 if (err) 753 goto destroy_ht; 754 } 755 756 prof->init(mdev, netdev, prof, ipriv); 757 758 err = mlx5e_attach_netdev(epriv); 759 if (err) 760 goto detach; 761 netif_carrier_off(netdev); 762 763 /* set rdma_netdev func pointers */ 764 rn = &ipriv->rn; 765 rn->hca = ibdev; 766 rn->send = mlx5i_xmit; 767 rn->attach_mcast = mlx5i_attach_mcast; 768 rn->detach_mcast = mlx5i_detach_mcast; 769 rn->set_id = mlx5i_set_pkey_index; 770 771 netdev->priv_destructor = mlx5_rdma_netdev_free; 772 netdev->needs_free_netdev = 1; 773 774 return 0; 775 776 detach: 777 prof->cleanup(epriv); 778 if (ipriv->sub_interface) 779 return err; 780 mlx5e_destroy_mdev_resources(mdev); 781 destroy_ht: 782 mlx5i_pkey_qpn_ht_cleanup(netdev); 783 return err; 784 } 785 786 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 787 struct ib_device *device, 788 struct rdma_netdev_alloc_params *params) 789 { 790 int nch; 791 int rc; 792 793 rc = mlx5i_check_required_hca_cap(mdev); 794 if (rc) 795 return rc; 796 797 nch = mlx5e_get_max_num_channels(mdev); 798 799 *params = (struct rdma_netdev_alloc_params){ 800 .sizeof_priv = sizeof(struct mlx5i_priv) + 801 sizeof(struct mlx5e_priv), 802 .txqs = nch * MLX5E_MAX_NUM_TC, 803 .rxqs = nch, 804 .param = mdev, 805 .initialize_rdma_netdev = mlx5_rdma_setup_rn, 806 }; 807 808 return 0; 809 } 810 EXPORT_SYMBOL(mlx5_rdma_rn_get_params); 811