1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/random.h> 35 #include <linux/vmalloc.h> 36 #include <linux/hardirq.h> 37 #include <linux/mlx5/driver.h> 38 #include <linux/kern_levels.h> 39 #include "mlx5_core.h" 40 #include "lib/eq.h" 41 #include "lib/mlx5.h" 42 #include "lib/events.h" 43 #include "lib/pci_vsc.h" 44 #include "lib/tout.h" 45 #include "diag/fw_tracer.h" 46 #include "diag/reporter_vnic.h" 47 48 enum { 49 MAX_MISSES = 3, 50 }; 51 52 enum { 53 MLX5_DROP_HEALTH_WORK, 54 }; 55 56 enum { 57 MLX5_SENSOR_NO_ERR = 0, 58 MLX5_SENSOR_PCI_COMM_ERR = 1, 59 MLX5_SENSOR_PCI_ERR = 2, 60 MLX5_SENSOR_NIC_DISABLED = 3, 61 MLX5_SENSOR_NIC_SW_RESET = 4, 62 MLX5_SENSOR_FW_SYND_RFR = 5, 63 }; 64 65 enum { 66 MLX5_SEVERITY_MASK = 0x7, 67 MLX5_SEVERITY_VALID_MASK = 0x8, 68 }; 69 70 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev) 71 { 72 return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 7; 73 } 74 75 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state) 76 { 77 u32 cur_cmdq_addr_l_sz; 78 79 cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz); 80 iowrite32be((cur_cmdq_addr_l_sz & 0xFFFFF000) | 81 state << MLX5_NIC_IFC_OFFSET, 82 &dev->iseg->cmdq_addr_l_sz); 83 } 84 85 static bool sensor_pci_not_working(struct mlx5_core_dev *dev) 86 { 87 struct mlx5_core_health *health = &dev->priv.health; 88 struct health_buffer __iomem *h = health->health; 89 90 /* Offline PCI reads return 0xffffffff */ 91 return (ioread32be(&h->fw_ver) == 0xffffffff); 92 } 93 94 static int mlx5_health_get_rfr(u8 rfr_severity) 95 { 96 return rfr_severity >> MLX5_RFR_BIT_OFFSET; 97 } 98 99 static bool sensor_fw_synd_rfr(struct mlx5_core_dev *dev) 100 { 101 struct mlx5_core_health *health = &dev->priv.health; 102 struct health_buffer __iomem *h = health->health; 103 u8 synd = ioread8(&h->synd); 104 u8 rfr; 105 106 rfr = mlx5_health_get_rfr(ioread8(&h->rfr_severity)); 107 108 if (rfr && synd) 109 mlx5_core_dbg(dev, "FW requests reset, synd: %d\n", synd); 110 return rfr && synd; 111 } 112 113 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev) 114 { 115 if (sensor_pci_not_working(dev)) 116 return MLX5_SENSOR_PCI_COMM_ERR; 117 if (pci_channel_offline(dev->pdev)) 118 return MLX5_SENSOR_PCI_ERR; 119 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED) 120 return MLX5_SENSOR_NIC_DISABLED; 121 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_SW_RESET) 122 return MLX5_SENSOR_NIC_SW_RESET; 123 if (sensor_fw_synd_rfr(dev)) 124 return MLX5_SENSOR_FW_SYND_RFR; 125 126 return MLX5_SENSOR_NO_ERR; 127 } 128 129 static int lock_sem_sw_reset(struct mlx5_core_dev *dev, bool lock) 130 { 131 enum mlx5_vsc_state state; 132 int ret; 133 134 if (!mlx5_core_is_pf(dev)) 135 return -EBUSY; 136 137 /* Try to lock GW access, this stage doesn't return 138 * EBUSY because locked GW does not mean that other PF 139 * already started the reset. 140 */ 141 ret = mlx5_vsc_gw_lock(dev); 142 if (ret == -EBUSY) 143 return -EINVAL; 144 if (ret) 145 return ret; 146 147 state = lock ? MLX5_VSC_LOCK : MLX5_VSC_UNLOCK; 148 /* At this stage, if the return status == EBUSY, then we know 149 * for sure that another PF started the reset, so don't allow 150 * another reset. 151 */ 152 ret = mlx5_vsc_sem_set_space(dev, MLX5_SEMAPHORE_SW_RESET, state); 153 if (ret) 154 mlx5_core_warn(dev, "Failed to lock SW reset semaphore\n"); 155 156 /* Unlock GW access */ 157 mlx5_vsc_gw_unlock(dev); 158 159 return ret; 160 } 161 162 static bool reset_fw_if_needed(struct mlx5_core_dev *dev) 163 { 164 bool supported = (ioread32be(&dev->iseg->initializing) >> 165 MLX5_FW_RESET_SUPPORTED_OFFSET) & 1; 166 u32 fatal_error; 167 168 if (!supported) 169 return false; 170 171 /* The reset only needs to be issued by one PF. The health buffer is 172 * shared between all functions, and will be cleared during a reset. 173 * Check again to avoid a redundant 2nd reset. If the fatal errors was 174 * PCI related a reset won't help. 175 */ 176 fatal_error = mlx5_health_check_fatal_sensors(dev); 177 if (fatal_error == MLX5_SENSOR_PCI_COMM_ERR || 178 fatal_error == MLX5_SENSOR_NIC_DISABLED || 179 fatal_error == MLX5_SENSOR_NIC_SW_RESET) { 180 mlx5_core_warn(dev, "Not issuing FW reset. Either it's already done or won't help."); 181 return false; 182 } 183 184 mlx5_core_warn(dev, "Issuing FW Reset\n"); 185 /* Write the NIC interface field to initiate the reset, the command 186 * interface address also resides here, don't overwrite it. 187 */ 188 mlx5_set_nic_state(dev, MLX5_NIC_IFC_SW_RESET); 189 190 return true; 191 } 192 193 static void enter_error_state(struct mlx5_core_dev *dev, bool force) 194 { 195 if (mlx5_health_check_fatal_sensors(dev) || force) { /* protected state setting */ 196 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 197 mlx5_cmd_flush(dev); 198 } 199 200 mlx5_notifier_call_chain(dev->priv.events, MLX5_DEV_EVENT_SYS_ERROR, (void *)1); 201 } 202 203 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force) 204 { 205 bool err_detected = false; 206 207 /* Mark the device as fatal in order to abort FW commands */ 208 if ((mlx5_health_check_fatal_sensors(dev) || force) && 209 dev->state == MLX5_DEVICE_STATE_UP) { 210 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 211 err_detected = true; 212 } 213 mutex_lock(&dev->intf_state_mutex); 214 if (!err_detected && dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 215 goto unlock;/* a previous error is still being handled */ 216 217 enter_error_state(dev, force); 218 unlock: 219 mutex_unlock(&dev->intf_state_mutex); 220 } 221 222 void mlx5_error_sw_reset(struct mlx5_core_dev *dev) 223 { 224 unsigned long end, delay_ms = mlx5_tout_ms(dev, PCI_TOGGLE); 225 int lock = -EBUSY; 226 227 mutex_lock(&dev->intf_state_mutex); 228 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) 229 goto unlock; 230 231 mlx5_core_err(dev, "start\n"); 232 233 if (mlx5_health_check_fatal_sensors(dev) == MLX5_SENSOR_FW_SYND_RFR) { 234 /* Get cr-dump and reset FW semaphore */ 235 lock = lock_sem_sw_reset(dev, true); 236 237 if (lock == -EBUSY) { 238 delay_ms = mlx5_tout_ms(dev, FULL_CRDUMP); 239 goto recover_from_sw_reset; 240 } 241 /* Execute SW reset */ 242 reset_fw_if_needed(dev); 243 } 244 245 recover_from_sw_reset: 246 /* Recover from SW reset */ 247 end = jiffies + msecs_to_jiffies(delay_ms); 248 do { 249 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED) 250 break; 251 if (pci_channel_offline(dev->pdev)) { 252 mlx5_core_err(dev, "PCI channel offline, stop waiting for NIC IFC\n"); 253 goto unlock; 254 } 255 256 msleep(20); 257 } while (!time_after(jiffies, end)); 258 259 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) { 260 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n", 261 mlx5_get_nic_state(dev), delay_ms); 262 } 263 264 /* Release FW semaphore if you are the lock owner */ 265 if (!lock) 266 lock_sem_sw_reset(dev, false); 267 268 mlx5_core_err(dev, "end\n"); 269 270 unlock: 271 mutex_unlock(&dev->intf_state_mutex); 272 } 273 274 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev) 275 { 276 u8 nic_interface = mlx5_get_nic_state(dev); 277 278 switch (nic_interface) { 279 case MLX5_NIC_IFC_FULL: 280 mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n"); 281 break; 282 283 case MLX5_NIC_IFC_DISABLED: 284 mlx5_core_warn(dev, "starting teardown\n"); 285 break; 286 287 case MLX5_NIC_IFC_NO_DRAM_NIC: 288 mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n"); 289 break; 290 291 case MLX5_NIC_IFC_SW_RESET: 292 /* The IFC mode field is 3 bits, so it will read 0x7 in 2 cases: 293 * 1. PCI has been disabled (ie. PCI-AER, PF driver unloaded 294 * and this is a VF), this is not recoverable by SW reset. 295 * Logging of this is handled elsewhere. 296 * 2. FW reset has been issued by another function, driver can 297 * be reloaded to recover after the mode switches to 298 * MLX5_NIC_IFC_DISABLED. 299 */ 300 if (dev->priv.health.fatal_error != MLX5_SENSOR_PCI_COMM_ERR) 301 mlx5_core_warn(dev, "NIC SW reset in progress\n"); 302 break; 303 304 default: 305 mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n", 306 nic_interface); 307 } 308 309 mlx5_disable_device(dev); 310 } 311 312 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev) 313 { 314 unsigned long end; 315 316 end = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FW_RESET)); 317 while (sensor_pci_not_working(dev)) { 318 if (time_after(jiffies, end)) 319 return -ETIMEDOUT; 320 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 321 mlx5_core_warn(dev, "device is being removed, stop waiting for PCI\n"); 322 return -ENODEV; 323 } 324 if (pci_channel_offline(dev->pdev)) { 325 mlx5_core_err(dev, "PCI channel offline, stop waiting for PCI\n"); 326 return -EACCES; 327 } 328 msleep(100); 329 } 330 return 0; 331 } 332 333 static int mlx5_health_try_recover(struct mlx5_core_dev *dev) 334 { 335 mlx5_core_warn(dev, "handling bad device here\n"); 336 mlx5_handle_bad_state(dev); 337 if (mlx5_health_wait_pci_up(dev)) { 338 mlx5_core_err(dev, "health recovery flow aborted, PCI reads still not working\n"); 339 return -EIO; 340 } 341 mlx5_core_err(dev, "starting health recovery flow\n"); 342 if (mlx5_recover_device(dev) || mlx5_health_check_fatal_sensors(dev)) { 343 mlx5_core_err(dev, "health recovery failed\n"); 344 return -EIO; 345 } 346 347 mlx5_core_info(dev, "health recovery succeeded\n"); 348 return 0; 349 } 350 351 static const char *hsynd_str(u8 synd) 352 { 353 switch (synd) { 354 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR: 355 return "firmware internal error"; 356 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC: 357 return "irisc not responding"; 358 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR: 359 return "unrecoverable hardware error"; 360 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR: 361 return "firmware CRC error"; 362 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR: 363 return "ICM fetch PCI error"; 364 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR: 365 return "HW fatal error\n"; 366 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN: 367 return "async EQ buffer overrun"; 368 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR: 369 return "EQ error"; 370 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV: 371 return "Invalid EQ referenced"; 372 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR: 373 return "FFSER error"; 374 case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR: 375 return "High temperature"; 376 default: 377 return "unrecognized error"; 378 } 379 } 380 381 static const char *mlx5_loglevel_str(int level) 382 { 383 switch (level) { 384 case LOGLEVEL_EMERG: 385 return "EMERGENCY"; 386 case LOGLEVEL_ALERT: 387 return "ALERT"; 388 case LOGLEVEL_CRIT: 389 return "CRITICAL"; 390 case LOGLEVEL_ERR: 391 return "ERROR"; 392 case LOGLEVEL_WARNING: 393 return "WARNING"; 394 case LOGLEVEL_NOTICE: 395 return "NOTICE"; 396 case LOGLEVEL_INFO: 397 return "INFO"; 398 case LOGLEVEL_DEBUG: 399 return "DEBUG"; 400 } 401 return "Unknown log level"; 402 } 403 404 static int mlx5_health_get_severity(u8 rfr_severity) 405 { 406 return rfr_severity & MLX5_SEVERITY_VALID_MASK ? 407 rfr_severity & MLX5_SEVERITY_MASK : LOGLEVEL_ERR; 408 } 409 410 static void print_health_info(struct mlx5_core_dev *dev) 411 { 412 struct mlx5_core_health *health = &dev->priv.health; 413 struct health_buffer __iomem *h = health->health; 414 u8 rfr_severity; 415 int severity; 416 int i; 417 418 /* If the syndrome is 0, the device is OK and no need to print buffer */ 419 if (!ioread8(&h->synd)) 420 return; 421 422 if (ioread32be(&h->fw_ver) == 0xFFFFFFFF) { 423 mlx5_log(dev, LOGLEVEL_ERR, "PCI slot is unavailable\n"); 424 return; 425 } 426 427 rfr_severity = ioread8(&h->rfr_severity); 428 severity = mlx5_health_get_severity(rfr_severity); 429 mlx5_log(dev, severity, "Health issue observed, %s, severity(%d) %s:\n", 430 hsynd_str(ioread8(&h->synd)), severity, mlx5_loglevel_str(severity)); 431 432 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++) 433 mlx5_log(dev, severity, "assert_var[%d] 0x%08x\n", i, 434 ioread32be(h->assert_var + i)); 435 436 mlx5_log(dev, severity, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr)); 437 mlx5_log(dev, severity, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra)); 438 mlx5_log(dev, severity, "fw_ver %d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), 439 fw_rev_sub(dev)); 440 mlx5_log(dev, severity, "time %u\n", ioread32be(&h->time)); 441 mlx5_log(dev, severity, "hw_id 0x%08x\n", ioread32be(&h->hw_id)); 442 mlx5_log(dev, severity, "rfr %d\n", mlx5_health_get_rfr(rfr_severity)); 443 mlx5_log(dev, severity, "severity %d (%s)\n", severity, mlx5_loglevel_str(severity)); 444 mlx5_log(dev, severity, "irisc_index %d\n", ioread8(&h->irisc_index)); 445 mlx5_log(dev, severity, "synd 0x%x: %s\n", ioread8(&h->synd), 446 hsynd_str(ioread8(&h->synd))); 447 mlx5_log(dev, severity, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd)); 448 mlx5_log(dev, severity, "raw fw_ver 0x%08x\n", ioread32be(&h->fw_ver)); 449 } 450 451 static int 452 mlx5_fw_reporter_diagnose(struct devlink_health_reporter *reporter, 453 struct devlink_fmsg *fmsg, 454 struct netlink_ext_ack *extack) 455 { 456 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter); 457 struct mlx5_core_health *health = &dev->priv.health; 458 struct health_buffer __iomem *h = health->health; 459 u8 synd; 460 int err; 461 462 synd = ioread8(&h->synd); 463 err = devlink_fmsg_u8_pair_put(fmsg, "Syndrome", synd); 464 if (err || !synd) 465 return err; 466 return devlink_fmsg_string_pair_put(fmsg, "Description", hsynd_str(synd)); 467 } 468 469 struct mlx5_fw_reporter_ctx { 470 u8 err_synd; 471 int miss_counter; 472 }; 473 474 static int 475 mlx5_fw_reporter_ctx_pairs_put(struct devlink_fmsg *fmsg, 476 struct mlx5_fw_reporter_ctx *fw_reporter_ctx) 477 { 478 int err; 479 480 err = devlink_fmsg_u8_pair_put(fmsg, "syndrome", 481 fw_reporter_ctx->err_synd); 482 if (err) 483 return err; 484 err = devlink_fmsg_u32_pair_put(fmsg, "fw_miss_counter", 485 fw_reporter_ctx->miss_counter); 486 if (err) 487 return err; 488 return 0; 489 } 490 491 static int 492 mlx5_fw_reporter_heath_buffer_data_put(struct mlx5_core_dev *dev, 493 struct devlink_fmsg *fmsg) 494 { 495 struct mlx5_core_health *health = &dev->priv.health; 496 struct health_buffer __iomem *h = health->health; 497 u8 rfr_severity; 498 int err; 499 int i; 500 501 if (!ioread8(&h->synd)) 502 return 0; 503 504 err = devlink_fmsg_pair_nest_start(fmsg, "health buffer"); 505 if (err) 506 return err; 507 err = devlink_fmsg_obj_nest_start(fmsg); 508 if (err) 509 return err; 510 err = devlink_fmsg_arr_pair_nest_start(fmsg, "assert_var"); 511 if (err) 512 return err; 513 514 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++) { 515 err = devlink_fmsg_u32_put(fmsg, ioread32be(h->assert_var + i)); 516 if (err) 517 return err; 518 } 519 err = devlink_fmsg_arr_pair_nest_end(fmsg); 520 if (err) 521 return err; 522 err = devlink_fmsg_u32_pair_put(fmsg, "assert_exit_ptr", 523 ioread32be(&h->assert_exit_ptr)); 524 if (err) 525 return err; 526 err = devlink_fmsg_u32_pair_put(fmsg, "assert_callra", 527 ioread32be(&h->assert_callra)); 528 if (err) 529 return err; 530 err = devlink_fmsg_u32_pair_put(fmsg, "time", ioread32be(&h->time)); 531 if (err) 532 return err; 533 err = devlink_fmsg_u32_pair_put(fmsg, "hw_id", ioread32be(&h->hw_id)); 534 if (err) 535 return err; 536 rfr_severity = ioread8(&h->rfr_severity); 537 err = devlink_fmsg_u8_pair_put(fmsg, "rfr", mlx5_health_get_rfr(rfr_severity)); 538 if (err) 539 return err; 540 err = devlink_fmsg_u8_pair_put(fmsg, "severity", mlx5_health_get_severity(rfr_severity)); 541 if (err) 542 return err; 543 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_index", 544 ioread8(&h->irisc_index)); 545 if (err) 546 return err; 547 err = devlink_fmsg_u8_pair_put(fmsg, "synd", ioread8(&h->synd)); 548 if (err) 549 return err; 550 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", 551 ioread16be(&h->ext_synd)); 552 if (err) 553 return err; 554 err = devlink_fmsg_u32_pair_put(fmsg, "raw_fw_ver", 555 ioread32be(&h->fw_ver)); 556 if (err) 557 return err; 558 err = devlink_fmsg_obj_nest_end(fmsg); 559 if (err) 560 return err; 561 return devlink_fmsg_pair_nest_end(fmsg); 562 } 563 564 static int 565 mlx5_fw_reporter_dump(struct devlink_health_reporter *reporter, 566 struct devlink_fmsg *fmsg, void *priv_ctx, 567 struct netlink_ext_ack *extack) 568 { 569 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter); 570 int err; 571 572 err = mlx5_fw_tracer_trigger_core_dump_general(dev); 573 if (err) 574 return err; 575 576 if (priv_ctx) { 577 struct mlx5_fw_reporter_ctx *fw_reporter_ctx = priv_ctx; 578 579 err = mlx5_fw_reporter_ctx_pairs_put(fmsg, fw_reporter_ctx); 580 if (err) 581 return err; 582 } 583 584 err = mlx5_fw_reporter_heath_buffer_data_put(dev, fmsg); 585 if (err) 586 return err; 587 return mlx5_fw_tracer_get_saved_traces_objects(dev->tracer, fmsg); 588 } 589 590 static void mlx5_fw_reporter_err_work(struct work_struct *work) 591 { 592 struct mlx5_fw_reporter_ctx fw_reporter_ctx; 593 struct mlx5_core_health *health; 594 595 health = container_of(work, struct mlx5_core_health, report_work); 596 597 if (IS_ERR_OR_NULL(health->fw_reporter)) 598 return; 599 600 fw_reporter_ctx.err_synd = health->synd; 601 fw_reporter_ctx.miss_counter = health->miss_counter; 602 if (fw_reporter_ctx.err_synd) { 603 devlink_health_report(health->fw_reporter, 604 "FW syndrome reported", &fw_reporter_ctx); 605 return; 606 } 607 if (fw_reporter_ctx.miss_counter) 608 devlink_health_report(health->fw_reporter, 609 "FW miss counter reported", 610 &fw_reporter_ctx); 611 } 612 613 static const struct devlink_health_reporter_ops mlx5_fw_reporter_ops = { 614 .name = "fw", 615 .diagnose = mlx5_fw_reporter_diagnose, 616 .dump = mlx5_fw_reporter_dump, 617 }; 618 619 static int 620 mlx5_fw_fatal_reporter_recover(struct devlink_health_reporter *reporter, 621 void *priv_ctx, 622 struct netlink_ext_ack *extack) 623 { 624 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter); 625 626 return mlx5_health_try_recover(dev); 627 } 628 629 static int 630 mlx5_fw_fatal_reporter_dump(struct devlink_health_reporter *reporter, 631 struct devlink_fmsg *fmsg, void *priv_ctx, 632 struct netlink_ext_ack *extack) 633 { 634 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter); 635 u32 crdump_size = dev->priv.health.crdump_size; 636 u32 *cr_data; 637 int err; 638 639 if (!mlx5_core_is_pf(dev)) 640 return -EPERM; 641 642 cr_data = kvmalloc(crdump_size, GFP_KERNEL); 643 if (!cr_data) 644 return -ENOMEM; 645 err = mlx5_crdump_collect(dev, cr_data); 646 if (err) 647 goto free_data; 648 649 if (priv_ctx) { 650 struct mlx5_fw_reporter_ctx *fw_reporter_ctx = priv_ctx; 651 652 err = mlx5_fw_reporter_ctx_pairs_put(fmsg, fw_reporter_ctx); 653 if (err) 654 goto free_data; 655 } 656 657 err = devlink_fmsg_binary_pair_put(fmsg, "crdump_data", cr_data, crdump_size); 658 659 free_data: 660 kvfree(cr_data); 661 return err; 662 } 663 664 static void mlx5_fw_fatal_reporter_err_work(struct work_struct *work) 665 { 666 struct mlx5_fw_reporter_ctx fw_reporter_ctx; 667 struct mlx5_core_health *health; 668 struct mlx5_core_dev *dev; 669 struct devlink *devlink; 670 struct mlx5_priv *priv; 671 672 health = container_of(work, struct mlx5_core_health, fatal_report_work); 673 priv = container_of(health, struct mlx5_priv, health); 674 dev = container_of(priv, struct mlx5_core_dev, priv); 675 devlink = priv_to_devlink(dev); 676 677 mutex_lock(&dev->intf_state_mutex); 678 if (test_bit(MLX5_DROP_HEALTH_WORK, &health->flags)) { 679 mlx5_core_err(dev, "health works are not permitted at this stage\n"); 680 mutex_unlock(&dev->intf_state_mutex); 681 return; 682 } 683 mutex_unlock(&dev->intf_state_mutex); 684 enter_error_state(dev, false); 685 if (IS_ERR_OR_NULL(health->fw_fatal_reporter)) { 686 devl_lock(devlink); 687 if (mlx5_health_try_recover(dev)) 688 mlx5_core_err(dev, "health recovery failed\n"); 689 devl_unlock(devlink); 690 return; 691 } 692 fw_reporter_ctx.err_synd = health->synd; 693 fw_reporter_ctx.miss_counter = health->miss_counter; 694 if (devlink_health_report(health->fw_fatal_reporter, 695 "FW fatal error reported", &fw_reporter_ctx) == -ECANCELED) { 696 /* If recovery wasn't performed, due to grace period, 697 * unload the driver. This ensures that the driver 698 * closes all its resources and it is not subjected to 699 * requests from the kernel. 700 */ 701 mlx5_core_err(dev, "Driver is in error state. Unloading\n"); 702 mlx5_unload_one(dev, false); 703 } 704 } 705 706 static const struct devlink_health_reporter_ops mlx5_fw_fatal_reporter_ops = { 707 .name = "fw_fatal", 708 .recover = mlx5_fw_fatal_reporter_recover, 709 .dump = mlx5_fw_fatal_reporter_dump, 710 }; 711 712 #define MLX5_FW_REPORTER_ECPF_GRACEFUL_PERIOD 180000 713 #define MLX5_FW_REPORTER_PF_GRACEFUL_PERIOD 60000 714 #define MLX5_FW_REPORTER_VF_GRACEFUL_PERIOD 30000 715 #define MLX5_FW_REPORTER_DEFAULT_GRACEFUL_PERIOD MLX5_FW_REPORTER_VF_GRACEFUL_PERIOD 716 717 void mlx5_fw_reporters_create(struct mlx5_core_dev *dev) 718 { 719 struct mlx5_core_health *health = &dev->priv.health; 720 struct devlink *devlink = priv_to_devlink(dev); 721 u64 grace_period; 722 723 if (mlx5_core_is_ecpf(dev)) { 724 grace_period = MLX5_FW_REPORTER_ECPF_GRACEFUL_PERIOD; 725 } else if (mlx5_core_is_pf(dev)) { 726 grace_period = MLX5_FW_REPORTER_PF_GRACEFUL_PERIOD; 727 } else { 728 /* VF or SF */ 729 grace_period = MLX5_FW_REPORTER_DEFAULT_GRACEFUL_PERIOD; 730 } 731 732 health->fw_reporter = 733 devl_health_reporter_create(devlink, &mlx5_fw_reporter_ops, 734 0, dev); 735 if (IS_ERR(health->fw_reporter)) 736 mlx5_core_warn(dev, "Failed to create fw reporter, err = %ld\n", 737 PTR_ERR(health->fw_reporter)); 738 739 health->fw_fatal_reporter = 740 devl_health_reporter_create(devlink, 741 &mlx5_fw_fatal_reporter_ops, 742 grace_period, 743 dev); 744 if (IS_ERR(health->fw_fatal_reporter)) 745 mlx5_core_warn(dev, "Failed to create fw fatal reporter, err = %ld\n", 746 PTR_ERR(health->fw_fatal_reporter)); 747 } 748 749 static void mlx5_fw_reporters_destroy(struct mlx5_core_dev *dev) 750 { 751 struct mlx5_core_health *health = &dev->priv.health; 752 753 if (!IS_ERR_OR_NULL(health->fw_reporter)) 754 devlink_health_reporter_destroy(health->fw_reporter); 755 756 if (!IS_ERR_OR_NULL(health->fw_fatal_reporter)) 757 devlink_health_reporter_destroy(health->fw_fatal_reporter); 758 } 759 760 static unsigned long get_next_poll_jiffies(struct mlx5_core_dev *dev) 761 { 762 unsigned long next; 763 764 get_random_bytes(&next, sizeof(next)); 765 next %= HZ; 766 next += jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, HEALTH_POLL_INTERVAL)); 767 768 return next; 769 } 770 771 void mlx5_trigger_health_work(struct mlx5_core_dev *dev) 772 { 773 struct mlx5_core_health *health = &dev->priv.health; 774 775 if (!mlx5_dev_is_lightweight(dev)) 776 queue_work(health->wq, &health->fatal_report_work); 777 } 778 779 #define MLX5_MSEC_PER_HOUR (MSEC_PER_SEC * 60 * 60) 780 static void mlx5_health_log_ts_update(struct work_struct *work) 781 { 782 struct delayed_work *dwork = to_delayed_work(work); 783 u32 out[MLX5_ST_SZ_DW(mrtc_reg)] = {}; 784 u32 in[MLX5_ST_SZ_DW(mrtc_reg)] = {}; 785 struct mlx5_core_health *health; 786 struct mlx5_core_dev *dev; 787 struct mlx5_priv *priv; 788 u64 now_us; 789 790 health = container_of(dwork, struct mlx5_core_health, update_fw_log_ts_work); 791 priv = container_of(health, struct mlx5_priv, health); 792 dev = container_of(priv, struct mlx5_core_dev, priv); 793 794 now_us = ktime_to_us(ktime_get_real()); 795 796 MLX5_SET(mrtc_reg, in, time_h, now_us >> 32); 797 MLX5_SET(mrtc_reg, in, time_l, now_us & 0xFFFFFFFF); 798 mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MRTC, 0, 1); 799 800 queue_delayed_work(health->wq, &health->update_fw_log_ts_work, 801 msecs_to_jiffies(MLX5_MSEC_PER_HOUR)); 802 } 803 804 static void poll_health(struct timer_list *t) 805 { 806 struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer); 807 struct mlx5_core_health *health = &dev->priv.health; 808 struct health_buffer __iomem *h = health->health; 809 u32 fatal_error; 810 u8 prev_synd; 811 u32 count; 812 813 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 814 goto out; 815 816 fatal_error = mlx5_health_check_fatal_sensors(dev); 817 818 if (fatal_error && !health->fatal_error) { 819 mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error); 820 dev->priv.health.fatal_error = fatal_error; 821 print_health_info(dev); 822 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 823 mlx5_trigger_health_work(dev); 824 return; 825 } 826 827 count = ioread32be(health->health_counter); 828 if (count == health->prev) 829 ++health->miss_counter; 830 else 831 health->miss_counter = 0; 832 833 health->prev = count; 834 if (health->miss_counter == MAX_MISSES) { 835 mlx5_core_err(dev, "device's health compromised - reached miss count\n"); 836 print_health_info(dev); 837 queue_work(health->wq, &health->report_work); 838 } 839 840 prev_synd = health->synd; 841 health->synd = ioread8(&h->synd); 842 if (health->synd && health->synd != prev_synd) 843 queue_work(health->wq, &health->report_work); 844 845 out: 846 mod_timer(&health->timer, get_next_poll_jiffies(dev)); 847 } 848 849 void mlx5_start_health_poll(struct mlx5_core_dev *dev) 850 { 851 u64 poll_interval_ms = mlx5_tout_ms(dev, HEALTH_POLL_INTERVAL); 852 struct mlx5_core_health *health = &dev->priv.health; 853 854 timer_setup(&health->timer, poll_health, 0); 855 health->fatal_error = MLX5_SENSOR_NO_ERR; 856 clear_bit(MLX5_DROP_HEALTH_WORK, &health->flags); 857 health->health = &dev->iseg->health; 858 health->health_counter = &dev->iseg->health_counter; 859 860 health->timer.expires = jiffies + msecs_to_jiffies(poll_interval_ms); 861 add_timer(&health->timer); 862 } 863 864 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health) 865 { 866 struct mlx5_core_health *health = &dev->priv.health; 867 868 if (disable_health) 869 set_bit(MLX5_DROP_HEALTH_WORK, &health->flags); 870 871 del_timer_sync(&health->timer); 872 } 873 874 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev) 875 { 876 struct mlx5_core_health *health = &dev->priv.health; 877 878 if (mlx5_core_is_pf(dev) && MLX5_CAP_MCAM_REG(dev, mrtc)) 879 queue_delayed_work(health->wq, &health->update_fw_log_ts_work, 0); 880 } 881 882 void mlx5_drain_health_wq(struct mlx5_core_dev *dev) 883 { 884 struct mlx5_core_health *health = &dev->priv.health; 885 886 set_bit(MLX5_DROP_HEALTH_WORK, &health->flags); 887 cancel_delayed_work_sync(&health->update_fw_log_ts_work); 888 cancel_work_sync(&health->report_work); 889 cancel_work_sync(&health->fatal_report_work); 890 } 891 892 void mlx5_health_cleanup(struct mlx5_core_dev *dev) 893 { 894 struct mlx5_core_health *health = &dev->priv.health; 895 896 cancel_delayed_work_sync(&health->update_fw_log_ts_work); 897 destroy_workqueue(health->wq); 898 mlx5_reporter_vnic_destroy(dev); 899 mlx5_fw_reporters_destroy(dev); 900 } 901 902 int mlx5_health_init(struct mlx5_core_dev *dev) 903 { 904 struct devlink *devlink = priv_to_devlink(dev); 905 struct mlx5_core_health *health; 906 char *name; 907 908 if (!mlx5_dev_is_lightweight(dev)) { 909 devl_lock(devlink); 910 mlx5_fw_reporters_create(dev); 911 devl_unlock(devlink); 912 } 913 mlx5_reporter_vnic_create(dev); 914 915 health = &dev->priv.health; 916 name = kmalloc(64, GFP_KERNEL); 917 if (!name) 918 goto out_err; 919 920 strcpy(name, "mlx5_health"); 921 strcat(name, dev_name(dev->device)); 922 health->wq = create_singlethread_workqueue(name); 923 kfree(name); 924 if (!health->wq) 925 goto out_err; 926 INIT_WORK(&health->fatal_report_work, mlx5_fw_fatal_reporter_err_work); 927 INIT_WORK(&health->report_work, mlx5_fw_reporter_err_work); 928 INIT_DELAYED_WORK(&health->update_fw_log_ts_work, mlx5_health_log_ts_update); 929 930 return 0; 931 932 out_err: 933 mlx5_reporter_vnic_destroy(dev); 934 mlx5_fw_reporters_destroy(dev); 935 return -ENOMEM; 936 } 937