1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */ 3 4 #include <devlink.h> 5 6 #include "fw_reset.h" 7 #include "diag/fw_tracer.h" 8 #include "lib/tout.h" 9 10 enum { 11 MLX5_FW_RESET_FLAGS_RESET_REQUESTED, 12 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 13 MLX5_FW_RESET_FLAGS_PENDING_COMP, 14 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, 15 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED 16 }; 17 18 struct mlx5_fw_reset { 19 struct mlx5_core_dev *dev; 20 struct mlx5_nb nb; 21 struct workqueue_struct *wq; 22 struct work_struct fw_live_patch_work; 23 struct work_struct reset_request_work; 24 struct work_struct reset_reload_work; 25 struct work_struct reset_now_work; 26 struct work_struct reset_abort_work; 27 unsigned long reset_flags; 28 struct timer_list timer; 29 struct completion done; 30 int ret; 31 }; 32 33 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id, 34 struct devlink_param_gset_ctx *ctx) 35 { 36 struct mlx5_core_dev *dev = devlink_priv(devlink); 37 struct mlx5_fw_reset *fw_reset; 38 39 fw_reset = dev->priv.fw_reset; 40 41 if (ctx->val.vbool) 42 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 43 else 44 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 45 return 0; 46 } 47 48 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id, 49 struct devlink_param_gset_ctx *ctx) 50 { 51 struct mlx5_core_dev *dev = devlink_priv(devlink); 52 struct mlx5_fw_reset *fw_reset; 53 54 fw_reset = dev->priv.fw_reset; 55 56 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 57 &fw_reset->reset_flags); 58 return 0; 59 } 60 61 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level, 62 u8 reset_type_sel, u8 sync_resp, bool sync_start) 63 { 64 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 65 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 66 67 MLX5_SET(mfrl_reg, in, reset_level, reset_level); 68 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 69 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp); 70 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start); 71 72 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1); 73 } 74 75 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level, 76 u8 *reset_type, u8 *reset_state) 77 { 78 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 79 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 80 int err; 81 82 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0); 83 if (err) 84 return err; 85 86 if (reset_level) 87 *reset_level = MLX5_GET(mfrl_reg, out, reset_level); 88 if (reset_type) 89 *reset_type = MLX5_GET(mfrl_reg, out, reset_type); 90 if (reset_state) 91 *reset_state = MLX5_GET(mfrl_reg, out, reset_state); 92 93 return 0; 94 } 95 96 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type) 97 { 98 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL); 99 } 100 101 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev, 102 struct netlink_ext_ack *extack) 103 { 104 u8 reset_state; 105 106 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state)) 107 goto out; 108 109 switch (reset_state) { 110 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION: 111 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS: 112 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered"); 113 return -EBUSY; 114 case MLX5_MFRL_REG_RESET_STATE_TIMEOUT: 115 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout"); 116 return -ETIMEDOUT; 117 case MLX5_MFRL_REG_RESET_STATE_NACK: 118 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset"); 119 return -EPERM; 120 } 121 122 out: 123 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed"); 124 return -EIO; 125 } 126 127 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel, 128 struct netlink_ext_ack *extack) 129 { 130 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 131 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 132 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 133 int err; 134 135 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 136 137 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3); 138 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 139 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1); 140 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out), 141 MLX5_REG_MFRL, 0, 1, false); 142 if (!err) 143 return 0; 144 145 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 146 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) 147 return mlx5_fw_reset_get_reset_state_err(dev, extack); 148 149 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed"); 150 return mlx5_cmd_check(dev, err, in, out); 151 } 152 153 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev) 154 { 155 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false); 156 } 157 158 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev) 159 { 160 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 161 162 /* if this is the driver that initiated the fw reset, devlink completed the reload */ 163 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { 164 complete(&fw_reset->done); 165 } else { 166 mlx5_unload_one(dev, false); 167 if (mlx5_health_wait_pci_up(dev)) 168 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n"); 169 else 170 mlx5_load_one(dev); 171 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0, 172 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 173 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE)); 174 } 175 } 176 177 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev) 178 { 179 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 180 181 del_timer_sync(&fw_reset->timer); 182 } 183 184 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health) 185 { 186 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 187 188 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 189 mlx5_core_warn(dev, "Reset request was already cleared\n"); 190 return -EALREADY; 191 } 192 193 mlx5_stop_sync_reset_poll(dev); 194 if (poll_health) 195 mlx5_start_health_poll(dev); 196 return 0; 197 } 198 199 static void mlx5_sync_reset_reload_work(struct work_struct *work) 200 { 201 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 202 reset_reload_work); 203 struct mlx5_core_dev *dev = fw_reset->dev; 204 205 mlx5_sync_reset_clear_reset_requested(dev, false); 206 mlx5_enter_error_state(dev, true); 207 mlx5_fw_reset_complete_reload(dev); 208 } 209 210 #define MLX5_RESET_POLL_INTERVAL (HZ / 10) 211 static void poll_sync_reset(struct timer_list *t) 212 { 213 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer); 214 struct mlx5_core_dev *dev = fw_reset->dev; 215 u32 fatal_error; 216 217 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) 218 return; 219 220 fatal_error = mlx5_health_check_fatal_sensors(dev); 221 222 if (fatal_error) { 223 mlx5_core_warn(dev, "Got Device Reset\n"); 224 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 225 queue_work(fw_reset->wq, &fw_reset->reset_reload_work); 226 else 227 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n"); 228 return; 229 } 230 231 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL)); 232 } 233 234 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev) 235 { 236 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 237 238 timer_setup(&fw_reset->timer, poll_sync_reset, 0); 239 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL); 240 add_timer(&fw_reset->timer); 241 } 242 243 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev) 244 { 245 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false); 246 } 247 248 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev) 249 { 250 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false); 251 } 252 253 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev) 254 { 255 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 256 257 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 258 mlx5_core_warn(dev, "Reset request was already set\n"); 259 return -EALREADY; 260 } 261 mlx5_stop_health_poll(dev, true); 262 mlx5_start_sync_reset_poll(dev); 263 return 0; 264 } 265 266 static void mlx5_fw_live_patch_event(struct work_struct *work) 267 { 268 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 269 fw_live_patch_work); 270 struct mlx5_core_dev *dev = fw_reset->dev; 271 272 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev), 273 fw_rev_min(dev), fw_rev_sub(dev)); 274 275 if (mlx5_fw_tracer_reload(dev->tracer)) 276 mlx5_core_err(dev, "Failed to reload FW tracer\n"); 277 } 278 279 static void mlx5_sync_reset_request_event(struct work_struct *work) 280 { 281 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 282 reset_request_work); 283 struct mlx5_core_dev *dev = fw_reset->dev; 284 int err; 285 286 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags)) { 287 err = mlx5_fw_reset_set_reset_sync_nack(dev); 288 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s", 289 err ? "Failed" : "Sent"); 290 return; 291 } 292 if (mlx5_sync_reset_set_reset_requested(dev)) 293 return; 294 295 err = mlx5_fw_reset_set_reset_sync_ack(dev); 296 if (err) 297 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err); 298 else 299 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n"); 300 } 301 302 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) 303 { 304 struct pci_bus *bridge_bus = dev->pdev->bus; 305 struct pci_dev *bridge = bridge_bus->self; 306 u16 reg16, dev_id, sdev_id; 307 unsigned long timeout; 308 struct pci_dev *sdev; 309 int cap, err; 310 u32 reg32; 311 312 /* Check that all functions under the pci bridge are PFs of 313 * this device otherwise fail this function. 314 */ 315 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id); 316 if (err) 317 return err; 318 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 319 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id); 320 if (err) 321 return err; 322 if (sdev_id != dev_id) 323 return -EPERM; 324 } 325 326 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); 327 if (!cap) 328 return -EOPNOTSUPP; 329 330 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 331 pci_save_state(sdev); 332 pci_cfg_access_lock(sdev); 333 } 334 /* PCI link toggle */ 335 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16); 336 if (err) 337 return err; 338 reg16 |= PCI_EXP_LNKCTL_LD; 339 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); 340 if (err) 341 return err; 342 msleep(500); 343 reg16 &= ~PCI_EXP_LNKCTL_LD; 344 err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); 345 if (err) 346 return err; 347 348 /* Check link */ 349 err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, ®32); 350 if (err) 351 return err; 352 if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) { 353 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32); 354 msleep(1000); 355 goto restore; 356 } 357 358 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE)); 359 do { 360 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16); 361 if (err) 362 return err; 363 if (reg16 & PCI_EXP_LNKSTA_DLLLA) 364 break; 365 msleep(20); 366 } while (!time_after(jiffies, timeout)); 367 368 if (reg16 & PCI_EXP_LNKSTA_DLLLA) { 369 mlx5_core_info(dev, "PCI Link up\n"); 370 } else { 371 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n", 372 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 373 err = -ETIMEDOUT; 374 goto restore; 375 } 376 377 do { 378 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16); 379 if (err) 380 return err; 381 if (reg16 == dev_id) 382 break; 383 msleep(20); 384 } while (!time_after(jiffies, timeout)); 385 386 if (reg16 == dev_id) { 387 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n"); 388 } else { 389 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n", 390 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 391 err = -ETIMEDOUT; 392 } 393 394 restore: 395 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 396 pci_cfg_access_unlock(sdev); 397 pci_restore_state(sdev); 398 } 399 400 return err; 401 } 402 403 static void mlx5_sync_reset_now_event(struct work_struct *work) 404 { 405 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 406 reset_now_work); 407 struct mlx5_core_dev *dev = fw_reset->dev; 408 int err; 409 410 if (mlx5_sync_reset_clear_reset_requested(dev, false)) 411 return; 412 413 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n"); 414 415 err = mlx5_cmd_fast_teardown_hca(dev); 416 if (err) { 417 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err); 418 goto done; 419 } 420 421 err = mlx5_pci_link_toggle(dev); 422 if (err) { 423 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err); 424 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags); 425 } 426 427 mlx5_enter_error_state(dev, true); 428 done: 429 fw_reset->ret = err; 430 mlx5_fw_reset_complete_reload(dev); 431 } 432 433 static void mlx5_sync_reset_abort_event(struct work_struct *work) 434 { 435 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 436 reset_abort_work); 437 struct mlx5_core_dev *dev = fw_reset->dev; 438 439 if (mlx5_sync_reset_clear_reset_requested(dev, true)) 440 return; 441 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n"); 442 } 443 444 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe) 445 { 446 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe; 447 u8 sync_event_rst_type; 448 449 sync_fw_update_eqe = &eqe->data.sync_fw_update; 450 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK; 451 switch (sync_event_rst_type) { 452 case MLX5_SYNC_RST_STATE_RESET_REQUEST: 453 queue_work(fw_reset->wq, &fw_reset->reset_request_work); 454 break; 455 case MLX5_SYNC_RST_STATE_RESET_NOW: 456 queue_work(fw_reset->wq, &fw_reset->reset_now_work); 457 break; 458 case MLX5_SYNC_RST_STATE_RESET_ABORT: 459 queue_work(fw_reset->wq, &fw_reset->reset_abort_work); 460 break; 461 } 462 } 463 464 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data) 465 { 466 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb); 467 struct mlx5_eqe *eqe = data; 468 469 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 470 return NOTIFY_DONE; 471 472 switch (eqe->sub_type) { 473 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT: 474 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work); 475 break; 476 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT: 477 mlx5_sync_reset_events_handle(fw_reset, eqe); 478 break; 479 default: 480 return NOTIFY_DONE; 481 } 482 483 return NOTIFY_OK; 484 } 485 486 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev) 487 { 488 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE); 489 unsigned long timeout = msecs_to_jiffies(pci_sync_update_timeout); 490 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 491 int err; 492 493 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) { 494 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n", 495 pci_sync_update_timeout / 1000); 496 err = -ETIMEDOUT; 497 goto out; 498 } 499 err = fw_reset->ret; 500 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) { 501 mlx5_unload_one_devl_locked(dev, false); 502 mlx5_load_one_devl_locked(dev, false); 503 } 504 out: 505 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 506 return err; 507 } 508 509 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev) 510 { 511 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 512 513 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT); 514 mlx5_eq_notifier_register(dev, &fw_reset->nb); 515 } 516 517 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev) 518 { 519 mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb); 520 } 521 522 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev) 523 { 524 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 525 526 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags); 527 cancel_work_sync(&fw_reset->fw_live_patch_work); 528 cancel_work_sync(&fw_reset->reset_request_work); 529 cancel_work_sync(&fw_reset->reset_reload_work); 530 cancel_work_sync(&fw_reset->reset_now_work); 531 cancel_work_sync(&fw_reset->reset_abort_work); 532 } 533 534 static const struct devlink_param mlx5_fw_reset_devlink_params[] = { 535 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME), 536 mlx5_fw_reset_enable_remote_dev_reset_get, 537 mlx5_fw_reset_enable_remote_dev_reset_set, NULL), 538 }; 539 540 int mlx5_fw_reset_init(struct mlx5_core_dev *dev) 541 { 542 struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL); 543 int err; 544 545 if (!fw_reset) 546 return -ENOMEM; 547 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events"); 548 if (!fw_reset->wq) { 549 kfree(fw_reset); 550 return -ENOMEM; 551 } 552 553 fw_reset->dev = dev; 554 dev->priv.fw_reset = fw_reset; 555 556 err = devl_params_register(priv_to_devlink(dev), 557 mlx5_fw_reset_devlink_params, 558 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 559 if (err) { 560 destroy_workqueue(fw_reset->wq); 561 kfree(fw_reset); 562 return err; 563 } 564 565 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event); 566 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event); 567 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work); 568 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event); 569 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event); 570 571 init_completion(&fw_reset->done); 572 return 0; 573 } 574 575 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev) 576 { 577 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 578 579 devl_params_unregister(priv_to_devlink(dev), 580 mlx5_fw_reset_devlink_params, 581 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 582 destroy_workqueue(fw_reset->wq); 583 kfree(dev->priv.fw_reset); 584 } 585