1 /*
2  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #include <linux/mlx5/device.h>
35 
36 #include "fpga/core.h"
37 #include "fpga/conn.h"
38 #include "fpga/sdk.h"
39 
40 struct mlx5_fpga_conn *
41 mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
42 			  struct mlx5_fpga_conn_attr *attr)
43 {
44 	return mlx5_fpga_conn_create(fdev, attr, MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP);
45 }
46 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_create);
47 
48 void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn)
49 {
50 	mlx5_fpga_conn_destroy(conn);
51 }
52 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_destroy);
53 
54 int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
55 			       struct mlx5_fpga_dma_buf *buf)
56 {
57 	return mlx5_fpga_conn_send(conn, buf);
58 }
59 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_sendmsg);
60 
61 static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size,
62 				  u64 addr, u8 *buf)
63 {
64 	size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
65 	size_t bytes_done = 0;
66 	u8 actual_size;
67 	int err;
68 
69 	if (!fdev->mdev)
70 		return -ENOTCONN;
71 
72 	while (bytes_done < size) {
73 		actual_size = min(max_size, (size - bytes_done));
74 
75 		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
76 					   addr + bytes_done,
77 					   buf + bytes_done, false);
78 		if (err) {
79 			mlx5_fpga_err(fdev, "Failed to read over I2C: %d\n",
80 				      err);
81 			break;
82 		}
83 
84 		bytes_done += actual_size;
85 	}
86 
87 	return err;
88 }
89 
90 static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size,
91 				   u64 addr, u8 *buf)
92 {
93 	size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
94 	size_t bytes_done = 0;
95 	u8 actual_size;
96 	int err;
97 
98 	if (!fdev->mdev)
99 		return -ENOTCONN;
100 
101 	while (bytes_done < size) {
102 		actual_size = min(max_size, (size - bytes_done));
103 
104 		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
105 					   addr + bytes_done,
106 					   buf + bytes_done, true);
107 		if (err) {
108 			mlx5_fpga_err(fdev, "Failed to write FPGA crspace\n");
109 			break;
110 		}
111 
112 		bytes_done += actual_size;
113 	}
114 
115 	return err;
116 }
117 
118 int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
119 		       void *buf, enum mlx5_fpga_access_type access_type)
120 {
121 	int ret;
122 
123 	switch (access_type) {
124 	case MLX5_FPGA_ACCESS_TYPE_I2C:
125 		ret = mlx5_fpga_mem_read_i2c(fdev, size, addr, buf);
126 		if (ret)
127 			return ret;
128 		break;
129 	default:
130 		mlx5_fpga_warn(fdev, "Unexpected read access_type %u\n",
131 			       access_type);
132 		return -EACCES;
133 	}
134 
135 	return size;
136 }
137 EXPORT_SYMBOL(mlx5_fpga_mem_read);
138 
139 int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
140 			void *buf, enum mlx5_fpga_access_type access_type)
141 {
142 	int ret;
143 
144 	switch (access_type) {
145 	case MLX5_FPGA_ACCESS_TYPE_I2C:
146 		ret = mlx5_fpga_mem_write_i2c(fdev, size, addr, buf);
147 		if (ret)
148 			return ret;
149 		break;
150 	default:
151 		mlx5_fpga_warn(fdev, "Unexpected write access_type %u\n",
152 			       access_type);
153 		return -EACCES;
154 	}
155 
156 	return size;
157 }
158 EXPORT_SYMBOL(mlx5_fpga_mem_write);
159 
160 int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf)
161 {
162 	return mlx5_fpga_sbu_caps(fdev->mdev, buf, size);
163 }
164 EXPORT_SYMBOL(mlx5_fpga_get_sbu_caps);
165