1 /* 2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_ESWITCH_H__ 34 #define __MLX5_ESWITCH_H__ 35 36 #include <linux/if_ether.h> 37 #include <linux/if_link.h> 38 #include <linux/atomic.h> 39 #include <linux/xarray.h> 40 #include <net/devlink.h> 41 #include <linux/mlx5/device.h> 42 #include <linux/mlx5/eswitch.h> 43 #include <linux/mlx5/vport.h> 44 #include <linux/mlx5/fs.h> 45 #include "lib/mpfs.h" 46 #include "lib/fs_chains.h" 47 #include "sf/sf.h" 48 #include "en/tc_ct.h" 49 #include "en/tc/sample.h" 50 51 enum mlx5_mapped_obj_type { 52 MLX5_MAPPED_OBJ_CHAIN, 53 MLX5_MAPPED_OBJ_SAMPLE, 54 MLX5_MAPPED_OBJ_INT_PORT_METADATA, 55 MLX5_MAPPED_OBJ_ACT_MISS, 56 }; 57 58 struct mlx5_mapped_obj { 59 enum mlx5_mapped_obj_type type; 60 union { 61 u32 chain; 62 u64 act_miss_cookie; 63 struct { 64 u32 group_id; 65 u32 rate; 66 u32 trunc_size; 67 u32 tunnel_id; 68 } sample; 69 u32 int_port_metadata; 70 }; 71 }; 72 73 #ifdef CONFIG_MLX5_ESWITCH 74 75 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 76 77 #define MLX5_MAX_UC_PER_VPORT(dev) \ 78 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) 79 80 #define MLX5_MAX_MC_PER_VPORT(dev) \ 81 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) 82 83 #define mlx5_esw_has_fwd_fdb(dev) \ 84 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) 85 86 #define esw_chains(esw) \ 87 ((esw)->fdb_table.offloads.esw_chains_priv) 88 89 enum { 90 MAPPING_TYPE_CHAIN, 91 MAPPING_TYPE_TUNNEL, 92 MAPPING_TYPE_TUNNEL_ENC_OPTS, 93 MAPPING_TYPE_LABELS, 94 MAPPING_TYPE_ZONE, 95 MAPPING_TYPE_INT_PORT, 96 }; 97 98 struct vport_ingress { 99 struct mlx5_flow_table *acl; 100 struct mlx5_flow_handle *allow_rule; 101 struct { 102 struct mlx5_flow_group *allow_spoofchk_only_grp; 103 struct mlx5_flow_group *allow_untagged_spoofchk_grp; 104 struct mlx5_flow_group *allow_untagged_only_grp; 105 struct mlx5_flow_group *drop_grp; 106 struct mlx5_flow_handle *drop_rule; 107 struct mlx5_fc *drop_counter; 108 } legacy; 109 struct { 110 /* Optional group to add an FTE to do internal priority 111 * tagging on ingress packets. 112 */ 113 struct mlx5_flow_group *metadata_prio_tag_grp; 114 /* Group to add default match-all FTE entry to tag ingress 115 * packet with metadata. 116 */ 117 struct mlx5_flow_group *metadata_allmatch_grp; 118 /* Optional group to add a drop all rule */ 119 struct mlx5_flow_group *drop_grp; 120 struct mlx5_modify_hdr *modify_metadata; 121 struct mlx5_flow_handle *modify_metadata_rule; 122 struct mlx5_flow_handle *drop_rule; 123 } offloads; 124 }; 125 126 enum vport_egress_acl_type { 127 VPORT_EGRESS_ACL_TYPE_DEFAULT, 128 VPORT_EGRESS_ACL_TYPE_SHARED_FDB, 129 }; 130 131 struct vport_egress { 132 struct mlx5_flow_table *acl; 133 enum vport_egress_acl_type type; 134 struct mlx5_flow_handle *allowed_vlan; 135 struct mlx5_flow_group *vlan_grp; 136 union { 137 struct { 138 struct mlx5_flow_group *drop_grp; 139 struct mlx5_flow_handle *drop_rule; 140 struct mlx5_fc *drop_counter; 141 } legacy; 142 struct { 143 struct mlx5_flow_group *fwd_grp; 144 struct mlx5_flow_handle *fwd_rule; 145 struct xarray bounce_rules; 146 struct mlx5_flow_group *bounce_grp; 147 } offloads; 148 }; 149 }; 150 151 struct mlx5_vport_drop_stats { 152 u64 rx_dropped; 153 u64 tx_dropped; 154 }; 155 156 struct mlx5_vport_info { 157 u8 mac[ETH_ALEN]; 158 u16 vlan; 159 u64 node_guid; 160 int link_state; 161 u8 qos; 162 u8 spoofchk: 1; 163 u8 trusted: 1; 164 u8 roce_enabled: 1; 165 u8 mig_enabled: 1; 166 u8 ipsec_crypto_enabled: 1; 167 u8 ipsec_packet_enabled: 1; 168 }; 169 170 /* Vport context events */ 171 enum mlx5_eswitch_vport_event { 172 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), 173 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), 174 MLX5_VPORT_PROMISC_CHANGE = BIT(3), 175 }; 176 177 struct mlx5_vport; 178 179 struct mlx5_devlink_port { 180 struct devlink_port dl_port; 181 struct mlx5_vport *vport; 182 }; 183 184 static inline void mlx5_devlink_port_init(struct mlx5_devlink_port *dl_port, 185 struct mlx5_vport *vport) 186 { 187 dl_port->vport = vport; 188 } 189 190 static inline struct mlx5_devlink_port *mlx5_devlink_port_get(struct devlink_port *dl_port) 191 { 192 return container_of(dl_port, struct mlx5_devlink_port, dl_port); 193 } 194 195 static inline struct mlx5_vport *mlx5_devlink_port_vport_get(struct devlink_port *dl_port) 196 { 197 return mlx5_devlink_port_get(dl_port)->vport; 198 } 199 200 struct mlx5_vport { 201 struct mlx5_core_dev *dev; 202 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; 203 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; 204 struct mlx5_flow_handle *promisc_rule; 205 struct mlx5_flow_handle *allmulti_rule; 206 struct work_struct vport_change_handler; 207 208 struct vport_ingress ingress; 209 struct vport_egress egress; 210 u32 default_metadata; 211 u32 metadata; 212 213 struct mlx5_vport_info info; 214 215 struct { 216 bool enabled; 217 u32 esw_tsar_ix; 218 u32 bw_share; 219 u32 min_rate; 220 u32 max_rate; 221 struct mlx5_esw_rate_group *group; 222 } qos; 223 224 u16 vport; 225 bool enabled; 226 enum mlx5_eswitch_vport_event enabled_events; 227 int index; 228 struct mlx5_devlink_port *dl_port; 229 }; 230 231 struct mlx5_esw_indir_table; 232 233 struct mlx5_eswitch_fdb { 234 union { 235 struct legacy_fdb { 236 struct mlx5_flow_table *fdb; 237 struct mlx5_flow_group *addr_grp; 238 struct mlx5_flow_group *allmulti_grp; 239 struct mlx5_flow_group *promisc_grp; 240 struct mlx5_flow_table *vepa_fdb; 241 struct mlx5_flow_handle *vepa_uplink_rule; 242 struct mlx5_flow_handle *vepa_star_rule; 243 } legacy; 244 245 struct offloads_fdb { 246 struct mlx5_flow_namespace *ns; 247 struct mlx5_flow_table *tc_miss_table; 248 struct mlx5_flow_table *slow_fdb; 249 struct mlx5_flow_group *send_to_vport_grp; 250 struct mlx5_flow_group *send_to_vport_meta_grp; 251 struct mlx5_flow_group *peer_miss_grp; 252 struct mlx5_flow_handle **peer_miss_rules[MLX5_MAX_PORTS]; 253 struct mlx5_flow_group *miss_grp; 254 struct mlx5_flow_handle **send_to_vport_meta_rules; 255 struct mlx5_flow_handle *miss_rule_uni; 256 struct mlx5_flow_handle *miss_rule_multi; 257 258 struct mlx5_fs_chains *esw_chains_priv; 259 struct { 260 DECLARE_HASHTABLE(table, 8); 261 /* Protects vports.table */ 262 struct mutex lock; 263 } vports; 264 265 struct mlx5_esw_indir_table *indir; 266 267 } offloads; 268 }; 269 u32 flags; 270 }; 271 272 struct mlx5_esw_offload { 273 struct mlx5_flow_table *ft_offloads_restore; 274 struct mlx5_flow_group *restore_group; 275 struct mlx5_modify_hdr *restore_copy_hdr_id; 276 struct mapping_ctx *reg_c0_obj_pool; 277 278 struct mlx5_flow_table *ft_offloads; 279 struct mlx5_flow_group *vport_rx_group; 280 struct mlx5_flow_group *vport_rx_drop_group; 281 struct mlx5_flow_handle *vport_rx_drop_rule; 282 struct mlx5_flow_table *ft_ipsec_tx_pol; 283 struct xarray vport_reps; 284 struct list_head peer_flows[MLX5_MAX_PORTS]; 285 struct mutex peer_mutex; 286 struct mutex encap_tbl_lock; /* protects encap_tbl */ 287 DECLARE_HASHTABLE(encap_tbl, 8); 288 struct mutex decap_tbl_lock; /* protects decap_tbl */ 289 DECLARE_HASHTABLE(decap_tbl, 8); 290 struct mod_hdr_tbl mod_hdr; 291 DECLARE_HASHTABLE(termtbl_tbl, 8); 292 struct mutex termtbl_mutex; /* protects termtbl hash */ 293 struct xarray vhca_map; 294 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; 295 u8 inline_mode; 296 atomic64_t num_flows; 297 u64 num_block_encap; 298 u64 num_block_mode; 299 enum devlink_eswitch_encap_mode encap; 300 struct ida vport_metadata_ida; 301 unsigned int host_number; /* ECPF supports one external host */ 302 }; 303 304 /* E-Switch MC FDB table hash node */ 305 struct esw_mc_addr { /* SRIOV only */ 306 struct l2addr_node node; 307 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ 308 u32 refcnt; 309 }; 310 311 struct mlx5_host_work { 312 struct work_struct work; 313 struct mlx5_eswitch *esw; 314 }; 315 316 struct mlx5_esw_functions { 317 struct mlx5_nb nb; 318 u16 num_vfs; 319 u16 num_ec_vfs; 320 }; 321 322 enum { 323 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), 324 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), 325 MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2), 326 }; 327 328 struct mlx5_esw_bridge_offloads; 329 330 enum { 331 MLX5_ESW_FDB_CREATED = BIT(0), 332 }; 333 334 struct dentry; 335 336 struct mlx5_eswitch { 337 struct mlx5_core_dev *dev; 338 struct mlx5_nb nb; 339 struct mlx5_eswitch_fdb fdb_table; 340 /* legacy data structures */ 341 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; 342 struct esw_mc_addr mc_promisc; 343 /* end of legacy */ 344 struct dentry *debugfs_root; 345 struct workqueue_struct *work_queue; 346 struct xarray vports; 347 u32 flags; 348 int total_vports; 349 int enabled_vports; 350 /* Synchronize between vport change events 351 * and async SRIOV admin state changes 352 */ 353 struct mutex state_lock; 354 355 /* Protects eswitch mode change that occurs via one or more 356 * user commands, i.e. sriov state change, devlink commands. 357 */ 358 struct rw_semaphore mode_lock; 359 atomic64_t user_count; 360 361 struct { 362 u32 root_tsar_ix; 363 struct mlx5_esw_rate_group *group0; 364 struct list_head groups; /* Protected by esw->state_lock */ 365 366 /* Protected by esw->state_lock. 367 * Initially 0, meaning no QoS users and QoS is disabled. 368 */ 369 refcount_t refcnt; 370 } qos; 371 372 struct mlx5_esw_bridge_offloads *br_offloads; 373 struct mlx5_esw_offload offloads; 374 int mode; 375 u16 manager_vport; 376 u16 first_host_vport; 377 u8 num_peers; 378 struct mlx5_esw_functions esw_funcs; 379 struct { 380 u32 large_group_num; 381 } params; 382 struct blocking_notifier_head n_head; 383 struct xarray paired; 384 struct mlx5_devcom_comp_dev *devcom; 385 u16 enabled_ipsec_vf_count; 386 }; 387 388 void esw_offloads_disable(struct mlx5_eswitch *esw); 389 int esw_offloads_enable(struct mlx5_eswitch *esw); 390 void esw_offloads_cleanup(struct mlx5_eswitch *esw); 391 int esw_offloads_init(struct mlx5_eswitch *esw); 392 393 struct mlx5_flow_handle * 394 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num); 395 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule); 396 397 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); 398 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); 399 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); 400 401 int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps); 402 403 /* E-Switch API */ 404 int mlx5_eswitch_init(struct mlx5_core_dev *dev); 405 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); 406 407 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) 408 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs); 409 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); 410 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf); 411 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw); 412 void mlx5_eswitch_disable(struct mlx5_eswitch *esw); 413 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key); 414 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw); 415 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw); 416 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, 417 u16 vport, const u8 *mac); 418 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, 419 u16 vport, int link_state); 420 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 421 u16 vport, u16 vlan, u8 qos); 422 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, 423 u16 vport, bool spoofchk); 424 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, 425 u16 vport_num, bool setting); 426 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, 427 u32 max_rate, u32 min_rate); 428 int mlx5_esw_qos_vport_update_group(struct mlx5_eswitch *esw, 429 struct mlx5_vport *vport, 430 struct mlx5_esw_rate_group *group, 431 struct netlink_ext_ack *extack); 432 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); 433 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); 434 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, 435 u16 vport, struct ifla_vf_info *ivi); 436 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, 437 u16 vport, 438 struct ifla_vf_stats *vf_stats); 439 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); 440 441 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, 442 bool other_vport, void *in); 443 444 struct mlx5_flow_spec; 445 struct mlx5_esw_flow_attr; 446 struct mlx5_termtbl_handle; 447 448 bool 449 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, 450 struct mlx5_flow_attr *attr, 451 struct mlx5_flow_act *flow_act, 452 struct mlx5_flow_spec *spec); 453 454 struct mlx5_flow_handle * 455 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, 456 struct mlx5_flow_table *ft, 457 struct mlx5_flow_spec *spec, 458 struct mlx5_esw_flow_attr *attr, 459 struct mlx5_flow_act *flow_act, 460 struct mlx5_flow_destination *dest, 461 int num_dest); 462 463 void 464 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, 465 struct mlx5_termtbl_handle *tt); 466 467 void 468 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); 469 470 struct mlx5_flow_handle * 471 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, 472 struct mlx5_flow_spec *spec, 473 struct mlx5_flow_attr *attr); 474 struct mlx5_flow_handle * 475 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, 476 struct mlx5_flow_spec *spec, 477 struct mlx5_flow_attr *attr); 478 void 479 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, 480 struct mlx5_flow_handle *rule, 481 struct mlx5_flow_attr *attr); 482 void 483 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, 484 struct mlx5_flow_handle *rule, 485 struct mlx5_flow_attr *attr); 486 487 struct mlx5_flow_handle * 488 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, 489 struct mlx5_flow_destination *dest); 490 491 enum { 492 SET_VLAN_STRIP = BIT(0), 493 SET_VLAN_INSERT = BIT(1) 494 }; 495 496 enum mlx5_flow_match_level { 497 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, 498 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, 499 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, 500 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, 501 }; 502 503 /* current maximum for flow based vport multicasting */ 504 #define MLX5_MAX_FLOW_FWD_VPORTS 32 505 506 enum { 507 MLX5_ESW_DEST_ENCAP = BIT(0), 508 MLX5_ESW_DEST_ENCAP_VALID = BIT(1), 509 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), 510 }; 511 512 struct mlx5_esw_flow_attr { 513 struct mlx5_eswitch_rep *in_rep; 514 struct mlx5_core_dev *in_mdev; 515 struct mlx5_core_dev *counter_dev; 516 struct mlx5e_tc_int_port *dest_int_port; 517 struct mlx5e_tc_int_port *int_port; 518 519 int split_count; 520 int out_count; 521 522 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; 523 u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; 524 u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; 525 u8 total_vlan; 526 struct { 527 u32 flags; 528 struct mlx5_eswitch_rep *rep; 529 struct mlx5_pkt_reformat *pkt_reformat; 530 struct mlx5_core_dev *mdev; 531 struct mlx5_termtbl_handle *termtbl; 532 int src_port_rewrite_act_id; 533 } dests[MLX5_MAX_FLOW_FWD_VPORTS]; 534 struct mlx5_rx_tun_attr *rx_tun_attr; 535 struct ethhdr eth; 536 struct mlx5_pkt_reformat *decap_pkt_reformat; 537 }; 538 539 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, 540 struct netlink_ext_ack *extack); 541 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); 542 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, 543 struct netlink_ext_ack *extack); 544 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); 545 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, 546 enum devlink_eswitch_encap_mode encap, 547 struct netlink_ext_ack *extack); 548 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, 549 enum devlink_eswitch_encap_mode *encap); 550 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port, 551 u8 *hw_addr, int *hw_addr_len, 552 struct netlink_ext_ack *extack); 553 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port, 554 const u8 *hw_addr, int hw_addr_len, 555 struct netlink_ext_ack *extack); 556 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled, 557 struct netlink_ext_ack *extack); 558 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable, 559 struct netlink_ext_ack *extack); 560 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled, 561 struct netlink_ext_ack *extack); 562 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable, 563 struct netlink_ext_ack *extack); 564 #ifdef CONFIG_XFRM_OFFLOAD 565 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled, 566 struct netlink_ext_ack *extack); 567 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable, 568 struct netlink_ext_ack *extack); 569 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled, 570 struct netlink_ext_ack *extack); 571 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port, bool enable, 572 struct netlink_ext_ack *extack); 573 #endif /* CONFIG_XFRM_OFFLOAD */ 574 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); 575 576 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 577 u16 vport, u16 vlan, u8 qos, u8 set_flags); 578 579 static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw) 580 { 581 return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) && 582 MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan)); 583 } 584 585 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, 586 u8 vlan_depth) 587 { 588 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && 589 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); 590 591 if (vlan_depth == 1) 592 return ret; 593 594 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && 595 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); 596 } 597 598 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, 599 struct mlx5_core_dev *dev1); 600 601 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); 602 603 #define MLX5_DEBUG_ESWITCH_MASK BIT(3) 604 605 #define esw_info(__dev, format, ...) \ 606 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 607 608 #define esw_warn(__dev, format, ...) \ 609 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 610 611 #define esw_debug(dev, format, ...) \ 612 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) 613 614 static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) 615 { 616 return esw && MLX5_ESWITCH_MANAGER(esw->dev); 617 } 618 619 /* The returned number is valid only when the dev is eswitch manager. */ 620 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) 621 { 622 return mlx5_core_is_ecpf_esw_manager(dev) ? 623 MLX5_VPORT_ECPF : MLX5_VPORT_PF; 624 } 625 626 static inline bool 627 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) 628 { 629 return esw->manager_vport == vport_num; 630 } 631 632 static inline bool mlx5_esw_is_owner(struct mlx5_eswitch *esw, u16 vport_num, 633 u16 esw_owner_vhca_id) 634 { 635 return esw_owner_vhca_id == MLX5_CAP_GEN(esw->dev, vhca_id) || 636 (vport_num == MLX5_VPORT_UPLINK && mlx5_lag_is_master(esw->dev)); 637 } 638 639 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) 640 { 641 return mlx5_core_is_ecpf_esw_manager(dev) ? 642 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; 643 } 644 645 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) 646 { 647 return mlx5_core_is_ecpf_esw_manager(dev); 648 } 649 650 static inline unsigned int 651 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 652 u16 vport_num) 653 { 654 return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; 655 } 656 657 static inline u16 658 mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) 659 { 660 return dl_port_index & 0xffff; 661 } 662 663 static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw) 664 { 665 return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED; 666 } 667 668 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ 669 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); 670 671 /* Each mark identifies eswitch vport type. 672 * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using 673 * a single mark. 674 * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. 675 * MLX5_ESW_VPT_SF identifies SF vport. 676 */ 677 #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 678 #define MLX5_ESW_VPT_VF XA_MARK_1 679 #define MLX5_ESW_VPT_SF XA_MARK_2 680 681 /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. 682 * Borrowed the idea from xa_for_each_marked() but with support for desired last element. 683 */ 684 685 #define mlx5_esw_for_each_vport(esw, index, vport) \ 686 xa_for_each(&((esw)->vports), index, vport) 687 688 #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ 689 for (index = 0, entry = xa_find(xa, &index, last, filter); \ 690 entry; entry = xa_find_after(xa, &index, last, filter)) 691 692 #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ 693 mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) 694 695 #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ 696 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) 697 698 #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ 699 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) 700 701 /* This macro should only be used if EC SRIOV is enabled. 702 * 703 * Because there were no more marks available on the xarray this uses a 704 * for_each_range approach. The range is only valid when EC SRIOV is enabled 705 */ 706 #define mlx5_esw_for_each_ec_vf_vport(esw, index, vport, last) \ 707 xa_for_each_range(&((esw)->vports), \ 708 index, \ 709 vport, \ 710 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base), \ 711 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\ 712 (last) - 1) 713 714 struct mlx5_eswitch *__must_check 715 mlx5_devlink_eswitch_get(struct devlink *devlink); 716 717 struct mlx5_eswitch *mlx5_devlink_eswitch_nocheck_get(struct devlink *devlink); 718 719 struct mlx5_vport *__must_check 720 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); 721 722 bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 723 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 724 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 725 726 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); 727 728 int 729 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, 730 enum mlx5_eswitch_vport_event enabled_events); 731 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); 732 733 int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 734 enum mlx5_eswitch_vport_event enabled_events); 735 void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 736 737 int 738 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, 739 struct mlx5_vport *vport); 740 void 741 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, 742 struct mlx5_vport *vport); 743 744 struct esw_vport_tbl_namespace { 745 int max_fte; 746 int max_num_groups; 747 u32 flags; 748 }; 749 750 struct mlx5_vport_tbl_attr { 751 u32 chain; 752 u16 prio; 753 u16 vport; 754 struct esw_vport_tbl_namespace *vport_ns; 755 }; 756 757 struct mlx5_flow_table * 758 mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 759 void 760 mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 761 762 struct mlx5_flow_handle * 763 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); 764 765 void mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw, 766 u32 *flow_group_in, 767 int match_params); 768 769 void mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw, 770 u16 vport, 771 struct mlx5_flow_spec *spec); 772 773 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 774 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 775 776 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 777 struct mlx5_devlink_port *dl_port, 778 u32 controller, u32 sfnum); 779 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 780 781 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 782 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 783 784 int mlx5_eswitch_load_sf_vport(struct mlx5_eswitch *esw, u16 vport_num, 785 enum mlx5_eswitch_vport_event enabled_events, 786 struct mlx5_devlink_port *dl_port, u32 controller, u32 sfnum); 787 void mlx5_eswitch_unload_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 788 789 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, 790 enum mlx5_eswitch_vport_event enabled_events); 791 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); 792 793 int mlx5_esw_offloads_pf_vf_devlink_port_init(struct mlx5_eswitch *esw, 794 struct mlx5_vport *vport); 795 void mlx5_esw_offloads_pf_vf_devlink_port_cleanup(struct mlx5_eswitch *esw, 796 struct mlx5_vport *vport); 797 798 int mlx5_esw_offloads_sf_devlink_port_init(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 799 struct mlx5_devlink_port *dl_port, 800 u32 controller, u32 sfnum); 801 void mlx5_esw_offloads_sf_devlink_port_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 802 803 int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 804 void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 805 struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); 806 807 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); 808 809 int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num); 810 void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num); 811 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); 812 813 /** 814 * mlx5_esw_event_info - Indicates eswitch mode changed/changing. 815 * 816 * @new_mode: New mode of eswitch. 817 */ 818 struct mlx5_esw_event_info { 819 u16 new_mode; 820 }; 821 822 int mlx5_esw_event_notifier_register(struct mlx5_eswitch *esw, struct notifier_block *n); 823 void mlx5_esw_event_notifier_unregister(struct mlx5_eswitch *esw, struct notifier_block *n); 824 825 bool mlx5_esw_hold(struct mlx5_core_dev *dev); 826 void mlx5_esw_release(struct mlx5_core_dev *dev); 827 void mlx5_esw_get(struct mlx5_core_dev *dev); 828 void mlx5_esw_put(struct mlx5_core_dev *dev); 829 int mlx5_esw_try_lock(struct mlx5_eswitch *esw); 830 void mlx5_esw_unlock(struct mlx5_eswitch *esw); 831 832 void esw_vport_change_handle_locked(struct mlx5_vport *vport); 833 834 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); 835 836 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 837 struct mlx5_eswitch *slave_esw, int max_slaves); 838 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 839 struct mlx5_eswitch *slave_esw); 840 int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw); 841 842 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev); 843 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); 844 845 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev); 846 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev); 847 848 static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw) 849 { 850 if (mlx5_esw_allowed(esw)) 851 return esw->esw_funcs.num_vfs; 852 853 return 0; 854 } 855 856 static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw) 857 { 858 if (mlx5_esw_allowed(esw)) 859 return esw->num_peers; 860 return 0; 861 } 862 863 static inline struct mlx5_flow_table * 864 mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw) 865 { 866 return esw->fdb_table.offloads.slow_fdb; 867 } 868 869 int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule, 870 struct mlx5_esw_flow_attr *esw_attr, int attr_idx); 871 bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev); 872 void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev); 873 bool mlx5_esw_ipsec_vf_offload_supported(struct mlx5_core_dev *dev); 874 int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev *dev, 875 struct mlx5_vport *vport); 876 int mlx5_esw_ipsec_vf_crypto_offload_supported(struct mlx5_core_dev *dev, 877 u16 vport_num); 878 int mlx5_esw_ipsec_vf_crypto_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 879 bool enable); 880 int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 881 bool enable); 882 int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev, 883 u16 vport_num); 884 void mlx5_esw_vport_ipsec_offload_enable(struct mlx5_eswitch *esw); 885 void mlx5_esw_vport_ipsec_offload_disable(struct mlx5_eswitch *esw); 886 887 #else /* CONFIG_MLX5_ESWITCH */ 888 /* eswitch API stubs */ 889 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } 890 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} 891 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } 892 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {} 893 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} 894 static inline void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key) {} 895 static inline void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) {} 896 static inline bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw) { return false; } 897 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } 898 static inline 899 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } 900 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) 901 { 902 return ERR_PTR(-EOPNOTSUPP); 903 } 904 905 static inline struct mlx5_flow_handle * 906 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) 907 { 908 return ERR_PTR(-EOPNOTSUPP); 909 } 910 911 static inline unsigned int 912 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 913 u16 vport_num) 914 { 915 return vport_num; 916 } 917 918 static inline int 919 mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 920 struct mlx5_eswitch *slave_esw, int max_slaves) 921 { 922 return 0; 923 } 924 925 static inline void 926 mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 927 struct mlx5_eswitch *slave_esw) {} 928 929 static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw) { return 0; } 930 931 static inline int 932 mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw) 933 { 934 return 0; 935 } 936 937 static inline bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev) 938 { 939 return true; 940 } 941 942 static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) 943 { 944 } 945 946 static inline int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev) { return 0; } 947 static inline void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev) {} 948 static inline bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev) 949 { 950 return false; 951 } 952 953 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {} 954 #endif /* CONFIG_MLX5_ESWITCH */ 955 956 #endif /* __MLX5_ESWITCH_H__ */ 957