1 /* 2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_ESWITCH_H__ 34 #define __MLX5_ESWITCH_H__ 35 36 #include <linux/if_ether.h> 37 #include <linux/if_link.h> 38 #include <net/devlink.h> 39 #include <linux/mlx5/device.h> 40 #include <linux/mlx5/eswitch.h> 41 #include <linux/mlx5/fs.h> 42 #include "lib/mpfs.h" 43 44 #ifdef CONFIG_MLX5_ESWITCH 45 46 #define MLX5_MAX_UC_PER_VPORT(dev) \ 47 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) 48 49 #define MLX5_MAX_MC_PER_VPORT(dev) \ 50 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) 51 52 #define FDB_UPLINK_VPORT 0xffff 53 54 #define MLX5_MIN_BW_SHARE 1 55 56 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ 57 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) 58 59 #define mlx5_esw_has_fwd_fdb(dev) \ 60 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) 61 62 #define FDB_MAX_CHAIN 3 63 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) 64 #define FDB_MAX_PRIO 16 65 66 struct vport_ingress { 67 struct mlx5_flow_table *acl; 68 struct mlx5_flow_group *allow_untagged_spoofchk_grp; 69 struct mlx5_flow_group *allow_spoofchk_only_grp; 70 struct mlx5_flow_group *allow_untagged_only_grp; 71 struct mlx5_flow_group *drop_grp; 72 struct mlx5_flow_handle *allow_rule; 73 struct mlx5_flow_handle *drop_rule; 74 struct mlx5_fc *drop_counter; 75 }; 76 77 struct vport_egress { 78 struct mlx5_flow_table *acl; 79 struct mlx5_flow_group *allowed_vlans_grp; 80 struct mlx5_flow_group *drop_grp; 81 struct mlx5_flow_handle *allowed_vlan; 82 struct mlx5_flow_handle *drop_rule; 83 struct mlx5_fc *drop_counter; 84 }; 85 86 struct mlx5_vport_drop_stats { 87 u64 rx_dropped; 88 u64 tx_dropped; 89 }; 90 91 struct mlx5_vport_info { 92 u8 mac[ETH_ALEN]; 93 u16 vlan; 94 u8 qos; 95 u64 node_guid; 96 int link_state; 97 u32 min_rate; 98 u32 max_rate; 99 bool spoofchk; 100 bool trusted; 101 }; 102 103 struct mlx5_vport { 104 struct mlx5_core_dev *dev; 105 int vport; 106 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; 107 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; 108 struct mlx5_flow_handle *promisc_rule; 109 struct mlx5_flow_handle *allmulti_rule; 110 struct work_struct vport_change_handler; 111 112 struct vport_ingress ingress; 113 struct vport_egress egress; 114 115 struct mlx5_vport_info info; 116 117 struct { 118 bool enabled; 119 u32 esw_tsar_ix; 120 u32 bw_share; 121 } qos; 122 123 bool enabled; 124 u16 enabled_events; 125 }; 126 127 enum offloads_fdb_flags { 128 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), 129 }; 130 131 extern const unsigned int ESW_POOLS[4]; 132 133 #define PRIO_LEVELS 2 134 struct mlx5_eswitch_fdb { 135 union { 136 struct legacy_fdb { 137 struct mlx5_flow_table *fdb; 138 struct mlx5_flow_group *addr_grp; 139 struct mlx5_flow_group *allmulti_grp; 140 struct mlx5_flow_group *promisc_grp; 141 } legacy; 142 143 struct offloads_fdb { 144 struct mlx5_flow_table *slow_fdb; 145 struct mlx5_flow_group *send_to_vport_grp; 146 struct mlx5_flow_group *peer_miss_grp; 147 struct mlx5_flow_handle **peer_miss_rules; 148 struct mlx5_flow_group *miss_grp; 149 struct mlx5_flow_handle *miss_rule_uni; 150 struct mlx5_flow_handle *miss_rule_multi; 151 int vlan_push_pop_refcount; 152 153 struct { 154 struct mlx5_flow_table *fdb; 155 u32 num_rules; 156 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; 157 /* Protects fdb_prio table */ 158 struct mutex fdb_prio_lock; 159 160 int fdb_left[ARRAY_SIZE(ESW_POOLS)]; 161 } offloads; 162 }; 163 u32 flags; 164 }; 165 166 struct mlx5_esw_offload { 167 struct mlx5_flow_table *ft_offloads; 168 struct mlx5_flow_group *vport_rx_group; 169 struct mlx5_eswitch_rep *vport_reps; 170 struct list_head peer_flows; 171 struct mutex peer_mutex; 172 DECLARE_HASHTABLE(encap_tbl, 8); 173 DECLARE_HASHTABLE(mod_hdr_tbl, 8); 174 u8 inline_mode; 175 u64 num_flows; 176 u8 encap; 177 }; 178 179 /* E-Switch MC FDB table hash node */ 180 struct esw_mc_addr { /* SRIOV only */ 181 struct l2addr_node node; 182 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ 183 u32 refcnt; 184 }; 185 186 struct mlx5_eswitch { 187 struct mlx5_core_dev *dev; 188 struct mlx5_nb nb; 189 struct mlx5_eswitch_fdb fdb_table; 190 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; 191 struct workqueue_struct *work_queue; 192 struct mlx5_vport *vports; 193 int total_vports; 194 int enabled_vports; 195 /* Synchronize between vport change events 196 * and async SRIOV admin state changes 197 */ 198 struct mutex state_lock; 199 struct esw_mc_addr mc_promisc; 200 201 struct { 202 bool enabled; 203 u32 root_tsar_id; 204 } qos; 205 206 struct mlx5_esw_offload offloads; 207 int mode; 208 int nvports; 209 }; 210 211 void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports); 212 int esw_offloads_init(struct mlx5_eswitch *esw, int nvports); 213 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); 214 int esw_offloads_init_reps(struct mlx5_eswitch *esw); 215 216 /* E-Switch API */ 217 int mlx5_eswitch_init(struct mlx5_core_dev *dev); 218 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); 219 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode); 220 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw); 221 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, 222 int vport, u8 mac[ETH_ALEN]); 223 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, 224 int vport, int link_state); 225 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 226 int vport, u16 vlan, u8 qos); 227 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, 228 int vport, bool spoofchk); 229 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, 230 int vport_num, bool setting); 231 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport, 232 u32 max_rate, u32 min_rate); 233 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, 234 int vport, struct ifla_vf_info *ivi); 235 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, 236 int vport, 237 struct ifla_vf_stats *vf_stats); 238 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); 239 240 struct mlx5_flow_spec; 241 struct mlx5_esw_flow_attr; 242 243 struct mlx5_flow_handle * 244 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, 245 struct mlx5_flow_spec *spec, 246 struct mlx5_esw_flow_attr *attr); 247 struct mlx5_flow_handle * 248 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, 249 struct mlx5_flow_spec *spec, 250 struct mlx5_esw_flow_attr *attr); 251 void 252 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, 253 struct mlx5_flow_handle *rule, 254 struct mlx5_esw_flow_attr *attr); 255 void 256 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, 257 struct mlx5_flow_handle *rule, 258 struct mlx5_esw_flow_attr *attr); 259 260 bool 261 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); 262 263 u16 264 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); 265 266 u32 267 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); 268 269 struct mlx5_flow_handle * 270 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, 271 struct mlx5_flow_destination *dest); 272 273 enum { 274 SET_VLAN_STRIP = BIT(0), 275 SET_VLAN_INSERT = BIT(1) 276 }; 277 278 enum mlx5_flow_match_level { 279 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, 280 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, 281 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, 282 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, 283 }; 284 285 /* current maximum for flow based vport multicasting */ 286 #define MLX5_MAX_FLOW_FWD_VPORTS 2 287 288 enum { 289 MLX5_ESW_DEST_ENCAP = BIT(0), 290 MLX5_ESW_DEST_ENCAP_VALID = BIT(1), 291 }; 292 293 struct mlx5_esw_flow_attr { 294 struct mlx5_eswitch_rep *in_rep; 295 struct mlx5_core_dev *in_mdev; 296 struct mlx5_core_dev *counter_dev; 297 298 int split_count; 299 int out_count; 300 301 int action; 302 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; 303 u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; 304 u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; 305 u8 total_vlan; 306 bool vlan_handled; 307 struct { 308 u32 flags; 309 struct mlx5_eswitch_rep *rep; 310 struct mlx5_core_dev *mdev; 311 u32 encap_id; 312 } dests[MLX5_MAX_FLOW_FWD_VPORTS]; 313 u32 mod_hdr_id; 314 u8 match_level; 315 struct mlx5_fc *counter; 316 u32 chain; 317 u16 prio; 318 u32 dest_chain; 319 struct mlx5e_tc_flow_parse_attr *parse_attr; 320 }; 321 322 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, 323 struct netlink_ext_ack *extack); 324 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); 325 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, 326 struct netlink_ext_ack *extack); 327 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); 328 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); 329 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap, 330 struct netlink_ext_ack *extack); 331 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap); 332 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); 333 334 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, 335 struct mlx5_esw_flow_attr *attr); 336 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, 337 struct mlx5_esw_flow_attr *attr); 338 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 339 int vport, u16 vlan, u8 qos, u8 set_flags); 340 341 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, 342 u8 vlan_depth) 343 { 344 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && 345 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); 346 347 if (vlan_depth == 1) 348 return ret; 349 350 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && 351 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); 352 } 353 354 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, 355 struct mlx5_core_dev *dev1); 356 357 #define MLX5_DEBUG_ESWITCH_MASK BIT(3) 358 359 #define esw_info(dev, format, ...) \ 360 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) 361 362 #define esw_warn(dev, format, ...) \ 363 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) 364 365 #define esw_debug(dev, format, ...) \ 366 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) 367 #else /* CONFIG_MLX5_ESWITCH */ 368 /* eswitch API stubs */ 369 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } 370 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} 371 static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; } 372 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {} 373 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } 374 375 #define FDB_MAX_CHAIN 1 376 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) 377 #define FDB_MAX_PRIO 1 378 379 #endif /* CONFIG_MLX5_ESWITCH */ 380 381 #endif /* __MLX5_ESWITCH_H__ */ 382