1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_STATS_H__ 33 #define __MLX5_EN_STATS_H__ 34 35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ 36 (*(u64 *)((char *)ptr + dsc[i].offset)) 37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ 38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) 39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ 40 (*(u32 *)((char *)ptr + dsc[i].offset)) 41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ 42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) 43 44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) 45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) 46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) 47 48 struct counter_desc { 49 char format[ETH_GSTRING_LEN]; 50 int offset; /* Byte offset */ 51 }; 52 53 struct mlx5e_sw_stats { 54 u64 rx_packets; 55 u64 rx_bytes; 56 u64 tx_packets; 57 u64 tx_bytes; 58 u64 tx_tso_packets; 59 u64 tx_tso_bytes; 60 u64 tx_tso_inner_packets; 61 u64 tx_tso_inner_bytes; 62 u64 rx_lro_packets; 63 u64 rx_lro_bytes; 64 u64 rx_csum_unnecessary; 65 u64 rx_csum_none; 66 u64 rx_csum_complete; 67 u64 rx_csum_unnecessary_inner; 68 u64 rx_xdp_drop; 69 u64 rx_xdp_tx; 70 u64 rx_xdp_tx_full; 71 u64 tx_csum_partial; 72 u64 tx_csum_partial_inner; 73 u64 tx_queue_stopped; 74 u64 tx_queue_wake; 75 u64 tx_queue_dropped; 76 u64 tx_xmit_more; 77 u64 rx_wqe_err; 78 u64 rx_mpwqe_filler; 79 u64 rx_buff_alloc_err; 80 u64 rx_cqe_compress_blks; 81 u64 rx_cqe_compress_pkts; 82 u64 rx_page_reuse; 83 u64 rx_cache_reuse; 84 u64 rx_cache_full; 85 u64 rx_cache_empty; 86 u64 rx_cache_busy; 87 88 /* Special handling counters */ 89 u64 link_down_events_phy; 90 }; 91 92 static const struct counter_desc sw_stats_desc[] = { 93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) }, 94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) }, 95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) }, 96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) }, 97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) }, 98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) }, 99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) }, 100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) }, 101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) }, 102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) }, 103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) }, 104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) }, 105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) }, 106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) }, 107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) }, 108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) }, 109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) }, 110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) }, 111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) }, 112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) }, 113 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) }, 114 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) }, 115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) }, 116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) }, 117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) }, 118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) }, 119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 121 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) }, 122 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) }, 123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) }, 124 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) }, 125 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) }, 126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) }, 127 }; 128 129 struct mlx5e_qcounter_stats { 130 u32 rx_out_of_buffer; 131 }; 132 133 static const struct counter_desc q_stats_desc[] = { 134 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) }, 135 }; 136 137 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) 138 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ 139 vstats->query_vport_out, c) 140 141 struct mlx5e_vport_stats { 142 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)]; 143 }; 144 145 static const struct counter_desc vport_stats_desc[] = { 146 { "rx_vport_unicast_packets", 147 VPORT_COUNTER_OFF(received_eth_unicast.packets) }, 148 { "rx_vport_unicast_bytes", 149 VPORT_COUNTER_OFF(received_eth_unicast.octets) }, 150 { "tx_vport_unicast_packets", 151 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) }, 152 { "tx_vport_unicast_bytes", 153 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) }, 154 { "rx_vport_multicast_packets", 155 VPORT_COUNTER_OFF(received_eth_multicast.packets) }, 156 { "rx_vport_multicast_bytes", 157 VPORT_COUNTER_OFF(received_eth_multicast.octets) }, 158 { "tx_vport_multicast_packets", 159 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) }, 160 { "tx_vport_multicast_bytes", 161 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) }, 162 { "rx_vport_broadcast_packets", 163 VPORT_COUNTER_OFF(received_eth_broadcast.packets) }, 164 { "rx_vport_broadcast_bytes", 165 VPORT_COUNTER_OFF(received_eth_broadcast.octets) }, 166 { "tx_vport_broadcast_packets", 167 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) }, 168 { "tx_vport_broadcast_bytes", 169 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) }, 170 { "rx_vport_rdma_unicast_packets", 171 VPORT_COUNTER_OFF(received_ib_unicast.packets) }, 172 { "rx_vport_rdma_unicast_bytes", 173 VPORT_COUNTER_OFF(received_ib_unicast.octets) }, 174 { "tx_vport_rdma_unicast_packets", 175 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) }, 176 { "tx_vport_rdma_unicast_bytes", 177 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) }, 178 { "rx_vport_rdma_multicast_packets", 179 VPORT_COUNTER_OFF(received_ib_multicast.packets) }, 180 { "rx_vport_rdma_multicast_bytes", 181 VPORT_COUNTER_OFF(received_ib_multicast.octets) }, 182 { "tx_vport_rdma_multicast_packets", 183 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) }, 184 { "tx_vport_rdma_multicast_bytes", 185 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) }, 186 }; 187 188 #define PPORT_802_3_OFF(c) \ 189 MLX5_BYTE_OFF(ppcnt_reg, \ 190 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 191 #define PPORT_802_3_GET(pstats, c) \ 192 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \ 193 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 194 #define PPORT_2863_OFF(c) \ 195 MLX5_BYTE_OFF(ppcnt_reg, \ 196 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 197 #define PPORT_2863_GET(pstats, c) \ 198 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \ 199 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 200 #define PPORT_2819_OFF(c) \ 201 MLX5_BYTE_OFF(ppcnt_reg, \ 202 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 203 #define PPORT_2819_GET(pstats, c) \ 204 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \ 205 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 206 #define PPORT_PHY_STATISTICAL_OFF(c) \ 207 MLX5_BYTE_OFF(ppcnt_reg, \ 208 counter_set.phys_layer_statistical_cntrs.c##_high) 209 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ 210 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ 211 counter_set.phys_layer_statistical_cntrs.c##_high) 212 #define PPORT_PER_PRIO_OFF(c) \ 213 MLX5_BYTE_OFF(ppcnt_reg, \ 214 counter_set.eth_per_prio_grp_data_layout.c##_high) 215 #define PPORT_PER_PRIO_GET(pstats, prio, c) \ 216 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ 217 counter_set.eth_per_prio_grp_data_layout.c##_high) 218 #define NUM_PPORT_PRIO 8 219 220 struct mlx5e_pport_stats { 221 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 222 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 223 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 224 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 225 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 226 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 227 }; 228 229 static const struct counter_desc pport_802_3_stats_desc[] = { 230 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) }, 231 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) }, 232 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) }, 233 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) }, 234 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) }, 235 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) }, 236 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) }, 237 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) }, 238 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) }, 239 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) }, 240 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) }, 241 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) }, 242 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) }, 243 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) }, 244 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) }, 245 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) }, 246 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) }, 247 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) }, 248 }; 249 250 static const struct counter_desc pport_2863_stats_desc[] = { 251 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) }, 252 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) }, 253 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) }, 254 }; 255 256 static const struct counter_desc pport_2819_stats_desc[] = { 257 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) }, 258 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) }, 259 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) }, 260 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) }, 261 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) }, 262 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) }, 263 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) }, 264 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) }, 265 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) }, 266 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) }, 267 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) }, 268 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) }, 269 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) }, 270 }; 271 272 static const struct counter_desc pport_phy_statistical_stats_desc[] = { 273 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) }, 274 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) }, 275 }; 276 277 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = { 278 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) }, 279 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) }, 280 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) }, 281 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) }, 282 }; 283 284 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 285 /* %s is "global" or "prio{i}" */ 286 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) }, 287 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) }, 288 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) }, 289 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) }, 290 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, 291 }; 292 293 #define PCIE_PERF_OFF(c) \ 294 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c) 295 #define PCIE_PERF_GET(pcie_stats, c) \ 296 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 297 counter_set.pcie_perf_cntrs_grp_data_layout.c) 298 299 struct mlx5e_pcie_stats { 300 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)]; 301 }; 302 303 static const struct counter_desc pcie_perf_stats_desc[] = { 304 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) }, 305 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) }, 306 }; 307 308 struct mlx5e_rq_stats { 309 u64 packets; 310 u64 bytes; 311 u64 csum_complete; 312 u64 csum_unnecessary_inner; 313 u64 csum_none; 314 u64 lro_packets; 315 u64 lro_bytes; 316 u64 xdp_drop; 317 u64 xdp_tx; 318 u64 xdp_tx_full; 319 u64 wqe_err; 320 u64 mpwqe_filler; 321 u64 buff_alloc_err; 322 u64 cqe_compress_blks; 323 u64 cqe_compress_pkts; 324 u64 page_reuse; 325 u64 cache_reuse; 326 u64 cache_full; 327 u64 cache_empty; 328 u64 cache_busy; 329 }; 330 331 static const struct counter_desc rq_stats_desc[] = { 332 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) }, 333 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) }, 334 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) }, 335 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 336 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) }, 337 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) }, 338 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) }, 339 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) }, 340 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) }, 341 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) }, 342 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) }, 343 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) }, 344 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 345 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 346 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 347 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) }, 348 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) }, 349 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) }, 350 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) }, 351 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) }, 352 }; 353 354 struct mlx5e_sq_stats { 355 /* commonly accessed in data path */ 356 u64 packets; 357 u64 bytes; 358 u64 xmit_more; 359 u64 tso_packets; 360 u64 tso_bytes; 361 u64 tso_inner_packets; 362 u64 tso_inner_bytes; 363 u64 csum_partial_inner; 364 u64 nop; 365 /* less likely accessed in data path */ 366 u64 csum_none; 367 u64 stopped; 368 u64 wake; 369 u64 dropped; 370 }; 371 372 static const struct counter_desc sq_stats_desc[] = { 373 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) }, 374 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) }, 375 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) }, 376 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) }, 377 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) }, 378 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) }, 379 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) }, 380 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) }, 381 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) }, 382 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) }, 383 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) }, 384 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) }, 385 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) }, 386 }; 387 388 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc) 389 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc) 390 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc) 391 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc) 392 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc) 393 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc) 394 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) \ 395 (ARRAY_SIZE(pport_phy_statistical_stats_desc) * \ 396 MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group)) 397 #define NUM_PCIE_PERF_COUNTERS(priv) \ 398 (ARRAY_SIZE(pcie_perf_stats_desc) * \ 399 MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 400 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \ 401 ARRAY_SIZE(pport_per_prio_traffic_stats_desc) 402 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS \ 403 ARRAY_SIZE(pport_per_prio_pfc_stats_desc) 404 #define NUM_PPORT_COUNTERS(priv) (NUM_PPORT_802_3_COUNTERS + \ 405 NUM_PPORT_2863_COUNTERS + \ 406 NUM_PPORT_2819_COUNTERS + \ 407 NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) + \ 408 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \ 409 NUM_PPORT_PRIO) 410 #define NUM_PCIE_COUNTERS(priv) NUM_PCIE_PERF_COUNTERS(priv) 411 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc) 412 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc) 413 414 struct mlx5e_stats { 415 struct mlx5e_sw_stats sw; 416 struct mlx5e_qcounter_stats qcnt; 417 struct mlx5e_vport_stats vport; 418 struct mlx5e_pport_stats pport; 419 struct rtnl_link_stats64 vf_vport; 420 struct mlx5e_pcie_stats pcie; 421 }; 422 423 static const struct counter_desc mlx5e_pme_status_desc[] = { 424 { "module_unplug", 8 }, 425 }; 426 427 static const struct counter_desc mlx5e_pme_error_desc[] = { 428 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */ 429 { "module_high_temp", 48 }, /* high temperature */ 430 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */ 431 }; 432 433 #endif /* __MLX5_EN_STATS_H__ */ 434