1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_EN_STATS_H__ 34 #define __MLX5_EN_STATS_H__ 35 36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ 37 (*(u64 *)((char *)ptr + dsc[i].offset)) 38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ 39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) 40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ 41 (*(u32 *)((char *)ptr + dsc[i].offset)) 42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ 43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) 44 45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) 46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) 47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) 48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld) 49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld) 50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld) 51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld) 52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld) 53 54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld) 55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld) 56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld) 57 58 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld) 59 60 struct counter_desc { 61 char format[ETH_GSTRING_LEN]; 62 size_t offset; /* Byte offset */ 63 }; 64 65 enum { 66 MLX5E_NDO_UPDATE_STATS = BIT(0x1), 67 }; 68 69 struct mlx5e_priv; 70 struct mlx5e_stats_grp { 71 u16 update_stats_mask; 72 int (*get_num_stats)(struct mlx5e_priv *priv); 73 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx); 74 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx); 75 void (*update_stats)(struct mlx5e_priv *priv); 76 }; 77 78 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t; 79 80 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name 81 82 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \ 83 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv) 84 85 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \ 86 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv) 87 88 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \ 89 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx) 90 91 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \ 92 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx) 93 94 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp 95 96 #define MLX5E_DECLARE_STATS_GRP(grp) \ 97 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp) 98 99 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \ 100 MLX5E_DECLARE_STATS_GRP(grp) = { \ 101 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \ 102 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \ 103 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \ 104 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \ 105 .update_stats_mask = mask, \ 106 } 107 108 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv); 109 void mlx5e_stats_update(struct mlx5e_priv *priv); 110 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx); 111 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data); 112 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv); 113 114 void mlx5e_stats_pause_get(struct mlx5e_priv *priv, 115 struct ethtool_pause_stats *pause_stats); 116 117 /* Concrete NIC Stats */ 118 119 struct mlx5e_sw_stats { 120 u64 rx_packets; 121 u64 rx_bytes; 122 u64 tx_packets; 123 u64 tx_bytes; 124 u64 tx_tso_packets; 125 u64 tx_tso_bytes; 126 u64 tx_tso_inner_packets; 127 u64 tx_tso_inner_bytes; 128 u64 tx_added_vlan_packets; 129 u64 tx_nop; 130 u64 tx_mpwqe_blks; 131 u64 tx_mpwqe_pkts; 132 u64 rx_lro_packets; 133 u64 rx_lro_bytes; 134 u64 rx_mcast_packets; 135 u64 rx_ecn_mark; 136 u64 rx_removed_vlan_packets; 137 u64 rx_csum_unnecessary; 138 u64 rx_csum_none; 139 u64 rx_csum_complete; 140 u64 rx_csum_complete_tail; 141 u64 rx_csum_complete_tail_slow; 142 u64 rx_csum_unnecessary_inner; 143 u64 rx_xdp_drop; 144 u64 rx_xdp_redirect; 145 u64 rx_xdp_tx_xmit; 146 u64 rx_xdp_tx_mpwqe; 147 u64 rx_xdp_tx_inlnw; 148 u64 rx_xdp_tx_nops; 149 u64 rx_xdp_tx_full; 150 u64 rx_xdp_tx_err; 151 u64 rx_xdp_tx_cqe; 152 u64 tx_csum_none; 153 u64 tx_csum_partial; 154 u64 tx_csum_partial_inner; 155 u64 tx_queue_stopped; 156 u64 tx_queue_dropped; 157 u64 tx_xmit_more; 158 u64 tx_recover; 159 u64 tx_cqes; 160 u64 tx_queue_wake; 161 u64 tx_cqe_err; 162 u64 tx_xdp_xmit; 163 u64 tx_xdp_mpwqe; 164 u64 tx_xdp_inlnw; 165 u64 tx_xdp_nops; 166 u64 tx_xdp_full; 167 u64 tx_xdp_err; 168 u64 tx_xdp_cqes; 169 u64 rx_wqe_err; 170 u64 rx_mpwqe_filler_cqes; 171 u64 rx_mpwqe_filler_strides; 172 u64 rx_oversize_pkts_sw_drop; 173 u64 rx_buff_alloc_err; 174 u64 rx_cqe_compress_blks; 175 u64 rx_cqe_compress_pkts; 176 u64 rx_cache_reuse; 177 u64 rx_cache_full; 178 u64 rx_cache_empty; 179 u64 rx_cache_busy; 180 u64 rx_cache_waive; 181 u64 rx_congst_umr; 182 u64 rx_arfs_err; 183 u64 rx_recover; 184 u64 ch_events; 185 u64 ch_poll; 186 u64 ch_arm; 187 u64 ch_aff_change; 188 u64 ch_force_irq; 189 u64 ch_eq_rearm; 190 191 #ifdef CONFIG_MLX5_EN_TLS 192 u64 tx_tls_encrypted_packets; 193 u64 tx_tls_encrypted_bytes; 194 u64 tx_tls_ctx; 195 u64 tx_tls_ooo; 196 u64 tx_tls_dump_packets; 197 u64 tx_tls_dump_bytes; 198 u64 tx_tls_resync_bytes; 199 u64 tx_tls_skip_no_sync_data; 200 u64 tx_tls_drop_no_sync_data; 201 u64 tx_tls_drop_bypass_req; 202 203 u64 rx_tls_decrypted_packets; 204 u64 rx_tls_decrypted_bytes; 205 u64 rx_tls_ctx; 206 u64 rx_tls_del; 207 u64 rx_tls_resync_req_pkt; 208 u64 rx_tls_resync_req_start; 209 u64 rx_tls_resync_req_end; 210 u64 rx_tls_resync_req_skip; 211 u64 rx_tls_resync_res_ok; 212 u64 rx_tls_resync_res_skip; 213 u64 rx_tls_err; 214 #endif 215 216 u64 rx_xsk_packets; 217 u64 rx_xsk_bytes; 218 u64 rx_xsk_csum_complete; 219 u64 rx_xsk_csum_unnecessary; 220 u64 rx_xsk_csum_unnecessary_inner; 221 u64 rx_xsk_csum_none; 222 u64 rx_xsk_ecn_mark; 223 u64 rx_xsk_removed_vlan_packets; 224 u64 rx_xsk_xdp_drop; 225 u64 rx_xsk_xdp_redirect; 226 u64 rx_xsk_wqe_err; 227 u64 rx_xsk_mpwqe_filler_cqes; 228 u64 rx_xsk_mpwqe_filler_strides; 229 u64 rx_xsk_oversize_pkts_sw_drop; 230 u64 rx_xsk_buff_alloc_err; 231 u64 rx_xsk_cqe_compress_blks; 232 u64 rx_xsk_cqe_compress_pkts; 233 u64 rx_xsk_congst_umr; 234 u64 rx_xsk_arfs_err; 235 u64 tx_xsk_xmit; 236 u64 tx_xsk_mpwqe; 237 u64 tx_xsk_inlnw; 238 u64 tx_xsk_full; 239 u64 tx_xsk_err; 240 u64 tx_xsk_cqes; 241 }; 242 243 struct mlx5e_qcounter_stats { 244 u32 rx_out_of_buffer; 245 u32 rx_if_down_packets; 246 }; 247 248 struct mlx5e_vnic_env_stats { 249 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)]; 250 }; 251 252 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ 253 vstats->query_vport_out, c) 254 255 struct mlx5e_vport_stats { 256 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)]; 257 }; 258 259 #define PPORT_802_3_GET(pstats, c) \ 260 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \ 261 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 262 #define PPORT_2863_GET(pstats, c) \ 263 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \ 264 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 265 #define PPORT_2819_GET(pstats, c) \ 266 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \ 267 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 268 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ 269 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ 270 counter_set.phys_layer_statistical_cntrs.c##_high) 271 #define PPORT_PER_PRIO_GET(pstats, prio, c) \ 272 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ 273 counter_set.eth_per_prio_grp_data_layout.c##_high) 274 #define NUM_PPORT_PRIO 8 275 #define PPORT_ETH_EXT_GET(pstats, c) \ 276 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \ 277 counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 278 279 struct mlx5e_pport_stats { 280 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 281 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 282 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 283 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 284 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 285 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 286 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 287 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 288 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 289 }; 290 291 #define PCIE_PERF_GET(pcie_stats, c) \ 292 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 293 counter_set.pcie_perf_cntrs_grp_data_layout.c) 294 295 #define PCIE_PERF_GET64(pcie_stats, c) \ 296 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 297 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 298 299 struct mlx5e_pcie_stats { 300 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)]; 301 }; 302 303 struct mlx5e_rq_stats { 304 u64 packets; 305 u64 bytes; 306 u64 csum_complete; 307 u64 csum_complete_tail; 308 u64 csum_complete_tail_slow; 309 u64 csum_unnecessary; 310 u64 csum_unnecessary_inner; 311 u64 csum_none; 312 u64 lro_packets; 313 u64 lro_bytes; 314 u64 mcast_packets; 315 u64 ecn_mark; 316 u64 removed_vlan_packets; 317 u64 xdp_drop; 318 u64 xdp_redirect; 319 u64 wqe_err; 320 u64 mpwqe_filler_cqes; 321 u64 mpwqe_filler_strides; 322 u64 oversize_pkts_sw_drop; 323 u64 buff_alloc_err; 324 u64 cqe_compress_blks; 325 u64 cqe_compress_pkts; 326 u64 cache_reuse; 327 u64 cache_full; 328 u64 cache_empty; 329 u64 cache_busy; 330 u64 cache_waive; 331 u64 congst_umr; 332 u64 arfs_err; 333 u64 recover; 334 #ifdef CONFIG_MLX5_EN_TLS 335 u64 tls_decrypted_packets; 336 u64 tls_decrypted_bytes; 337 u64 tls_ctx; 338 u64 tls_del; 339 u64 tls_resync_req_pkt; 340 u64 tls_resync_req_start; 341 u64 tls_resync_req_end; 342 u64 tls_resync_req_skip; 343 u64 tls_resync_res_ok; 344 u64 tls_resync_res_skip; 345 u64 tls_err; 346 #endif 347 }; 348 349 struct mlx5e_sq_stats { 350 /* commonly accessed in data path */ 351 u64 packets; 352 u64 bytes; 353 u64 xmit_more; 354 u64 tso_packets; 355 u64 tso_bytes; 356 u64 tso_inner_packets; 357 u64 tso_inner_bytes; 358 u64 csum_partial; 359 u64 csum_partial_inner; 360 u64 added_vlan_packets; 361 u64 nop; 362 u64 mpwqe_blks; 363 u64 mpwqe_pkts; 364 #ifdef CONFIG_MLX5_EN_TLS 365 u64 tls_encrypted_packets; 366 u64 tls_encrypted_bytes; 367 u64 tls_ctx; 368 u64 tls_ooo; 369 u64 tls_dump_packets; 370 u64 tls_dump_bytes; 371 u64 tls_resync_bytes; 372 u64 tls_skip_no_sync_data; 373 u64 tls_drop_no_sync_data; 374 u64 tls_drop_bypass_req; 375 #endif 376 /* less likely accessed in data path */ 377 u64 csum_none; 378 u64 stopped; 379 u64 dropped; 380 u64 recover; 381 /* dirtied @completion */ 382 u64 cqes ____cacheline_aligned_in_smp; 383 u64 wake; 384 u64 cqe_err; 385 }; 386 387 struct mlx5e_xdpsq_stats { 388 u64 xmit; 389 u64 mpwqe; 390 u64 inlnw; 391 u64 nops; 392 u64 full; 393 u64 err; 394 /* dirtied @completion */ 395 u64 cqes ____cacheline_aligned_in_smp; 396 }; 397 398 struct mlx5e_ch_stats { 399 u64 events; 400 u64 poll; 401 u64 arm; 402 u64 aff_change; 403 u64 force_irq; 404 u64 eq_rearm; 405 }; 406 407 struct mlx5e_ptp_cq_stats { 408 u64 cqe; 409 u64 err_cqe; 410 u64 abort; 411 u64 abort_abs_diff_ns; 412 }; 413 414 struct mlx5e_stats { 415 struct mlx5e_sw_stats sw; 416 struct mlx5e_qcounter_stats qcnt; 417 struct mlx5e_vnic_env_stats vnic; 418 struct mlx5e_vport_stats vport; 419 struct mlx5e_pport_stats pport; 420 struct rtnl_link_stats64 vf_vport; 421 struct mlx5e_pcie_stats pcie; 422 }; 423 424 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[]; 425 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv); 426 427 extern MLX5E_DECLARE_STATS_GRP(sw); 428 extern MLX5E_DECLARE_STATS_GRP(qcnt); 429 extern MLX5E_DECLARE_STATS_GRP(vnic_env); 430 extern MLX5E_DECLARE_STATS_GRP(vport); 431 extern MLX5E_DECLARE_STATS_GRP(802_3); 432 extern MLX5E_DECLARE_STATS_GRP(2863); 433 extern MLX5E_DECLARE_STATS_GRP(2819); 434 extern MLX5E_DECLARE_STATS_GRP(phy); 435 extern MLX5E_DECLARE_STATS_GRP(eth_ext); 436 extern MLX5E_DECLARE_STATS_GRP(pcie); 437 extern MLX5E_DECLARE_STATS_GRP(per_prio); 438 extern MLX5E_DECLARE_STATS_GRP(pme); 439 extern MLX5E_DECLARE_STATS_GRP(channels); 440 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest); 441 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw); 442 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw); 443 444 #endif /* __MLX5_EN_STATS_H__ */ 445