1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_EN_STATS_H__ 34 #define __MLX5_EN_STATS_H__ 35 36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ 37 (*(u64 *)((char *)ptr + dsc[i].offset)) 38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ 39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) 40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ 41 (*(u32 *)((char *)ptr + dsc[i].offset)) 42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ 43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) 44 45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) 46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) 47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) 48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld) 49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld) 50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld) 51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld) 52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld) 53 54 struct counter_desc { 55 char format[ETH_GSTRING_LEN]; 56 size_t offset; /* Byte offset */ 57 }; 58 59 enum { 60 MLX5E_NDO_UPDATE_STATS = BIT(0x1), 61 }; 62 63 struct mlx5e_priv; 64 struct mlx5e_stats_grp { 65 u16 update_stats_mask; 66 int (*get_num_stats)(struct mlx5e_priv *priv); 67 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx); 68 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx); 69 void (*update_stats)(struct mlx5e_priv *priv); 70 }; 71 72 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t; 73 74 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name 75 76 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \ 77 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv) 78 79 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \ 80 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv) 81 82 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \ 83 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx) 84 85 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \ 86 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx) 87 88 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp 89 90 #define MLX5E_DECLARE_STATS_GRP(grp) \ 91 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp) 92 93 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \ 94 MLX5E_DECLARE_STATS_GRP(grp) = { \ 95 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \ 96 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \ 97 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \ 98 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \ 99 .update_stats_mask = mask, \ 100 } 101 102 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv); 103 void mlx5e_stats_update(struct mlx5e_priv *priv); 104 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx); 105 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data); 106 107 /* Concrete NIC Stats */ 108 109 struct mlx5e_sw_stats { 110 u64 rx_packets; 111 u64 rx_bytes; 112 u64 tx_packets; 113 u64 tx_bytes; 114 u64 tx_tso_packets; 115 u64 tx_tso_bytes; 116 u64 tx_tso_inner_packets; 117 u64 tx_tso_inner_bytes; 118 u64 tx_added_vlan_packets; 119 u64 tx_nop; 120 u64 rx_lro_packets; 121 u64 rx_lro_bytes; 122 u64 rx_ecn_mark; 123 u64 rx_removed_vlan_packets; 124 u64 rx_csum_unnecessary; 125 u64 rx_csum_none; 126 u64 rx_csum_complete; 127 u64 rx_csum_complete_tail; 128 u64 rx_csum_complete_tail_slow; 129 u64 rx_csum_unnecessary_inner; 130 u64 rx_xdp_drop; 131 u64 rx_xdp_redirect; 132 u64 rx_xdp_tx_xmit; 133 u64 rx_xdp_tx_mpwqe; 134 u64 rx_xdp_tx_inlnw; 135 u64 rx_xdp_tx_nops; 136 u64 rx_xdp_tx_full; 137 u64 rx_xdp_tx_err; 138 u64 rx_xdp_tx_cqe; 139 u64 tx_csum_none; 140 u64 tx_csum_partial; 141 u64 tx_csum_partial_inner; 142 u64 tx_queue_stopped; 143 u64 tx_queue_dropped; 144 u64 tx_xmit_more; 145 u64 tx_recover; 146 u64 tx_cqes; 147 u64 tx_queue_wake; 148 u64 tx_cqe_err; 149 u64 tx_xdp_xmit; 150 u64 tx_xdp_mpwqe; 151 u64 tx_xdp_inlnw; 152 u64 tx_xdp_nops; 153 u64 tx_xdp_full; 154 u64 tx_xdp_err; 155 u64 tx_xdp_cqes; 156 u64 rx_wqe_err; 157 u64 rx_mpwqe_filler_cqes; 158 u64 rx_mpwqe_filler_strides; 159 u64 rx_oversize_pkts_sw_drop; 160 u64 rx_buff_alloc_err; 161 u64 rx_cqe_compress_blks; 162 u64 rx_cqe_compress_pkts; 163 u64 rx_cache_reuse; 164 u64 rx_cache_full; 165 u64 rx_cache_empty; 166 u64 rx_cache_busy; 167 u64 rx_cache_waive; 168 u64 rx_congst_umr; 169 u64 rx_arfs_err; 170 u64 rx_recover; 171 u64 ch_events; 172 u64 ch_poll; 173 u64 ch_arm; 174 u64 ch_aff_change; 175 u64 ch_force_irq; 176 u64 ch_eq_rearm; 177 178 #ifdef CONFIG_MLX5_EN_TLS 179 u64 tx_tls_encrypted_packets; 180 u64 tx_tls_encrypted_bytes; 181 u64 tx_tls_ctx; 182 u64 tx_tls_ooo; 183 u64 tx_tls_dump_packets; 184 u64 tx_tls_dump_bytes; 185 u64 tx_tls_resync_bytes; 186 u64 tx_tls_skip_no_sync_data; 187 u64 tx_tls_drop_no_sync_data; 188 u64 tx_tls_drop_bypass_req; 189 #endif 190 191 u64 rx_xsk_packets; 192 u64 rx_xsk_bytes; 193 u64 rx_xsk_csum_complete; 194 u64 rx_xsk_csum_unnecessary; 195 u64 rx_xsk_csum_unnecessary_inner; 196 u64 rx_xsk_csum_none; 197 u64 rx_xsk_ecn_mark; 198 u64 rx_xsk_removed_vlan_packets; 199 u64 rx_xsk_xdp_drop; 200 u64 rx_xsk_xdp_redirect; 201 u64 rx_xsk_wqe_err; 202 u64 rx_xsk_mpwqe_filler_cqes; 203 u64 rx_xsk_mpwqe_filler_strides; 204 u64 rx_xsk_oversize_pkts_sw_drop; 205 u64 rx_xsk_buff_alloc_err; 206 u64 rx_xsk_cqe_compress_blks; 207 u64 rx_xsk_cqe_compress_pkts; 208 u64 rx_xsk_congst_umr; 209 u64 rx_xsk_arfs_err; 210 u64 tx_xsk_xmit; 211 u64 tx_xsk_mpwqe; 212 u64 tx_xsk_inlnw; 213 u64 tx_xsk_full; 214 u64 tx_xsk_err; 215 u64 tx_xsk_cqes; 216 }; 217 218 struct mlx5e_qcounter_stats { 219 u32 rx_out_of_buffer; 220 u32 rx_if_down_packets; 221 }; 222 223 struct mlx5e_vnic_env_stats { 224 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)]; 225 }; 226 227 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ 228 vstats->query_vport_out, c) 229 230 struct mlx5e_vport_stats { 231 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)]; 232 }; 233 234 #define PPORT_802_3_GET(pstats, c) \ 235 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \ 236 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 237 #define PPORT_2863_GET(pstats, c) \ 238 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \ 239 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 240 #define PPORT_2819_GET(pstats, c) \ 241 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \ 242 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 243 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ 244 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ 245 counter_set.phys_layer_statistical_cntrs.c##_high) 246 #define PPORT_PER_PRIO_GET(pstats, prio, c) \ 247 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ 248 counter_set.eth_per_prio_grp_data_layout.c##_high) 249 #define NUM_PPORT_PRIO 8 250 #define PPORT_ETH_EXT_GET(pstats, c) \ 251 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \ 252 counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 253 254 struct mlx5e_pport_stats { 255 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 256 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 257 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 258 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 259 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 260 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 261 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 262 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 263 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 264 }; 265 266 #define PCIE_PERF_GET(pcie_stats, c) \ 267 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 268 counter_set.pcie_perf_cntrs_grp_data_layout.c) 269 270 #define PCIE_PERF_GET64(pcie_stats, c) \ 271 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 272 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 273 274 struct mlx5e_pcie_stats { 275 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)]; 276 }; 277 278 struct mlx5e_rq_stats { 279 u64 packets; 280 u64 bytes; 281 u64 csum_complete; 282 u64 csum_complete_tail; 283 u64 csum_complete_tail_slow; 284 u64 csum_unnecessary; 285 u64 csum_unnecessary_inner; 286 u64 csum_none; 287 u64 lro_packets; 288 u64 lro_bytes; 289 u64 ecn_mark; 290 u64 removed_vlan_packets; 291 u64 xdp_drop; 292 u64 xdp_redirect; 293 u64 wqe_err; 294 u64 mpwqe_filler_cqes; 295 u64 mpwqe_filler_strides; 296 u64 oversize_pkts_sw_drop; 297 u64 buff_alloc_err; 298 u64 cqe_compress_blks; 299 u64 cqe_compress_pkts; 300 u64 cache_reuse; 301 u64 cache_full; 302 u64 cache_empty; 303 u64 cache_busy; 304 u64 cache_waive; 305 u64 congst_umr; 306 u64 arfs_err; 307 u64 recover; 308 }; 309 310 struct mlx5e_sq_stats { 311 /* commonly accessed in data path */ 312 u64 packets; 313 u64 bytes; 314 u64 xmit_more; 315 u64 tso_packets; 316 u64 tso_bytes; 317 u64 tso_inner_packets; 318 u64 tso_inner_bytes; 319 u64 csum_partial; 320 u64 csum_partial_inner; 321 u64 added_vlan_packets; 322 u64 nop; 323 #ifdef CONFIG_MLX5_EN_TLS 324 u64 tls_encrypted_packets; 325 u64 tls_encrypted_bytes; 326 u64 tls_ctx; 327 u64 tls_ooo; 328 u64 tls_dump_packets; 329 u64 tls_dump_bytes; 330 u64 tls_resync_bytes; 331 u64 tls_skip_no_sync_data; 332 u64 tls_drop_no_sync_data; 333 u64 tls_drop_bypass_req; 334 #endif 335 /* less likely accessed in data path */ 336 u64 csum_none; 337 u64 stopped; 338 u64 dropped; 339 u64 recover; 340 /* dirtied @completion */ 341 u64 cqes ____cacheline_aligned_in_smp; 342 u64 wake; 343 u64 cqe_err; 344 }; 345 346 struct mlx5e_xdpsq_stats { 347 u64 xmit; 348 u64 mpwqe; 349 u64 inlnw; 350 u64 nops; 351 u64 full; 352 u64 err; 353 /* dirtied @completion */ 354 u64 cqes ____cacheline_aligned_in_smp; 355 }; 356 357 struct mlx5e_ch_stats { 358 u64 events; 359 u64 poll; 360 u64 arm; 361 u64 aff_change; 362 u64 force_irq; 363 u64 eq_rearm; 364 }; 365 366 struct mlx5e_stats { 367 struct mlx5e_sw_stats sw; 368 struct mlx5e_qcounter_stats qcnt; 369 struct mlx5e_vnic_env_stats vnic; 370 struct mlx5e_vport_stats vport; 371 struct mlx5e_pport_stats pport; 372 struct rtnl_link_stats64 vf_vport; 373 struct mlx5e_pcie_stats pcie; 374 }; 375 376 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[]; 377 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv); 378 379 extern MLX5E_DECLARE_STATS_GRP(sw); 380 extern MLX5E_DECLARE_STATS_GRP(qcnt); 381 extern MLX5E_DECLARE_STATS_GRP(vnic_env); 382 extern MLX5E_DECLARE_STATS_GRP(vport); 383 extern MLX5E_DECLARE_STATS_GRP(802_3); 384 extern MLX5E_DECLARE_STATS_GRP(2863); 385 extern MLX5E_DECLARE_STATS_GRP(2819); 386 extern MLX5E_DECLARE_STATS_GRP(phy); 387 extern MLX5E_DECLARE_STATS_GRP(eth_ext); 388 extern MLX5E_DECLARE_STATS_GRP(pcie); 389 extern MLX5E_DECLARE_STATS_GRP(per_prio); 390 extern MLX5E_DECLARE_STATS_GRP(pme); 391 extern MLX5E_DECLARE_STATS_GRP(channels); 392 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest); 393 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw); 394 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw); 395 396 #endif /* __MLX5_EN_STATS_H__ */ 397