19218b44dSGal Pressman /* 29218b44dSGal Pressman * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 39218b44dSGal Pressman * 49218b44dSGal Pressman * This software is available to you under a choice of one of two 59218b44dSGal Pressman * licenses. You may choose to be licensed under the terms of the GNU 69218b44dSGal Pressman * General Public License (GPL) Version 2, available from the file 79218b44dSGal Pressman * COPYING in the main directory of this source tree, or the 89218b44dSGal Pressman * OpenIB.org BSD license below: 99218b44dSGal Pressman * 109218b44dSGal Pressman * Redistribution and use in source and binary forms, with or 119218b44dSGal Pressman * without modification, are permitted provided that the following 129218b44dSGal Pressman * conditions are met: 139218b44dSGal Pressman * 149218b44dSGal Pressman * - Redistributions of source code must retain the above 159218b44dSGal Pressman * copyright notice, this list of conditions and the following 169218b44dSGal Pressman * disclaimer. 179218b44dSGal Pressman * 189218b44dSGal Pressman * - Redistributions in binary form must reproduce the above 199218b44dSGal Pressman * copyright notice, this list of conditions and the following 209218b44dSGal Pressman * disclaimer in the documentation and/or other materials 219218b44dSGal Pressman * provided with the distribution. 229218b44dSGal Pressman * 239218b44dSGal Pressman * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 249218b44dSGal Pressman * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 259218b44dSGal Pressman * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 269218b44dSGal Pressman * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 279218b44dSGal Pressman * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 289218b44dSGal Pressman * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 299218b44dSGal Pressman * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 309218b44dSGal Pressman * SOFTWARE. 319218b44dSGal Pressman */ 329218b44dSGal Pressman #ifndef __MLX5_EN_STATS_H__ 339218b44dSGal Pressman #define __MLX5_EN_STATS_H__ 349218b44dSGal Pressman 359218b44dSGal Pressman #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ 369218b44dSGal Pressman (*(u64 *)((char *)ptr + dsc[i].offset)) 379218b44dSGal Pressman #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ 389218b44dSGal Pressman be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) 399218b44dSGal Pressman #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ 409218b44dSGal Pressman (*(u32 *)((char *)ptr + dsc[i].offset)) 419218b44dSGal Pressman #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ 420f7f3481SGal Pressman be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) 439218b44dSGal Pressman 449218b44dSGal Pressman #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) 45bfe6d8d1SGal Pressman #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) 46bfe6d8d1SGal Pressman #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) 4757d689a8SEran Ben Elisha #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld) 489218b44dSGal Pressman 499218b44dSGal Pressman struct counter_desc { 50bfe6d8d1SGal Pressman char format[ETH_GSTRING_LEN]; 519da5106cSGal Pressman size_t offset; /* Byte offset */ 529218b44dSGal Pressman }; 539218b44dSGal Pressman 549218b44dSGal Pressman struct mlx5e_sw_stats { 559218b44dSGal Pressman u64 rx_packets; 569218b44dSGal Pressman u64 rx_bytes; 579218b44dSGal Pressman u64 tx_packets; 589218b44dSGal Pressman u64 tx_bytes; 59bfe6d8d1SGal Pressman u64 tx_tso_packets; 60bfe6d8d1SGal Pressman u64 tx_tso_bytes; 61bfe6d8d1SGal Pressman u64 tx_tso_inner_packets; 62bfe6d8d1SGal Pressman u64 tx_tso_inner_bytes; 63f24686e8SGal Pressman u64 tx_added_vlan_packets; 64bfe6d8d1SGal Pressman u64 rx_lro_packets; 65bfe6d8d1SGal Pressman u64 rx_lro_bytes; 66f24686e8SGal Pressman u64 rx_removed_vlan_packets; 67bfe6d8d1SGal Pressman u64 rx_csum_unnecessary; 689218b44dSGal Pressman u64 rx_csum_none; 69bfe6d8d1SGal Pressman u64 rx_csum_complete; 70bfe6d8d1SGal Pressman u64 rx_csum_unnecessary_inner; 7186994156SRana Shahout u64 rx_xdp_drop; 72b5503b99SSaeed Mahameed u64 rx_xdp_tx; 73b5503b99SSaeed Mahameed u64 rx_xdp_tx_full; 74603e1f5bSGal Pressman u64 tx_csum_none; 75bfe6d8d1SGal Pressman u64 tx_csum_partial; 76bfe6d8d1SGal Pressman u64 tx_csum_partial_inner; 779218b44dSGal Pressman u64 tx_queue_stopped; 789218b44dSGal Pressman u64 tx_queue_wake; 799218b44dSGal Pressman u64 tx_queue_dropped; 80c8cf78feSTariq Toukan u64 tx_xmit_more; 819218b44dSGal Pressman u64 rx_wqe_err; 829218b44dSGal Pressman u64 rx_mpwqe_filler; 839218b44dSGal Pressman u64 rx_buff_alloc_err; 847219ab34STariq Toukan u64 rx_cqe_compress_blks; 857219ab34STariq Toukan u64 rx_cqe_compress_pkts; 86accd5883STariq Toukan u64 rx_page_reuse; 874415a031STariq Toukan u64 rx_cache_reuse; 884415a031STariq Toukan u64 rx_cache_full; 894415a031STariq Toukan u64 rx_cache_empty; 904415a031STariq Toukan u64 rx_cache_busy; 9170871f1eSTariq Toukan u64 rx_cache_waive; 9257d689a8SEran Ben Elisha u64 ch_eq_rearm; 93121fcdc8SGal Pressman 94121fcdc8SGal Pressman /* Special handling counters */ 95bfe6d8d1SGal Pressman u64 link_down_events_phy; 969218b44dSGal Pressman }; 979218b44dSGal Pressman 989218b44dSGal Pressman struct mlx5e_qcounter_stats { 999218b44dSGal Pressman u32 rx_out_of_buffer; 1009218b44dSGal Pressman }; 1019218b44dSGal Pressman 1025c298143SMoshe Shemesh struct mlx5e_vnic_env_stats { 1035c298143SMoshe Shemesh __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)]; 1045c298143SMoshe Shemesh }; 1055c298143SMoshe Shemesh 1069218b44dSGal Pressman #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ 1079218b44dSGal Pressman vstats->query_vport_out, c) 1089218b44dSGal Pressman 1099218b44dSGal Pressman struct mlx5e_vport_stats { 1109218b44dSGal Pressman __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)]; 1119218b44dSGal Pressman }; 1129218b44dSGal Pressman 1139218b44dSGal Pressman #define PPORT_802_3_GET(pstats, c) \ 1149218b44dSGal Pressman MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \ 1159218b44dSGal Pressman counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 1169218b44dSGal Pressman #define PPORT_2863_GET(pstats, c) \ 1179218b44dSGal Pressman MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \ 1189218b44dSGal Pressman counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 1199218b44dSGal Pressman #define PPORT_2819_GET(pstats, c) \ 1209218b44dSGal Pressman MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \ 1219218b44dSGal Pressman counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 1225db0a4f6SGal Pressman #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ 1235db0a4f6SGal Pressman MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ 1245db0a4f6SGal Pressman counter_set.phys_layer_statistical_cntrs.c##_high) 125cf678570SGal Pressman #define PPORT_PER_PRIO_GET(pstats, prio, c) \ 126cf678570SGal Pressman MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ 127cf678570SGal Pressman counter_set.eth_per_prio_grp_data_layout.c##_high) 128cf678570SGal Pressman #define NUM_PPORT_PRIO 8 129068aef33SGal Pressman #define PPORT_ETH_EXT_GET(pstats, c) \ 130068aef33SGal Pressman MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \ 131068aef33SGal Pressman counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 1329218b44dSGal Pressman 1339218b44dSGal Pressman struct mlx5e_pport_stats { 1349218b44dSGal Pressman __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 1359218b44dSGal Pressman __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 1369218b44dSGal Pressman __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 137cf678570SGal Pressman __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 138121fcdc8SGal Pressman __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 1395db0a4f6SGal Pressman __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 140068aef33SGal Pressman __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 1419218b44dSGal Pressman }; 1429218b44dSGal Pressman 1430f7f3481SGal Pressman #define PCIE_PERF_GET(pcie_stats, c) \ 1440f7f3481SGal Pressman MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 1450f7f3481SGal Pressman counter_set.pcie_perf_cntrs_grp_data_layout.c) 1460f7f3481SGal Pressman 147efae7f78SEran Ben Elisha #define PCIE_PERF_GET64(pcie_stats, c) \ 148efae7f78SEran Ben Elisha MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 149efae7f78SEran Ben Elisha counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 150efae7f78SEran Ben Elisha 1510f7f3481SGal Pressman struct mlx5e_pcie_stats { 1520f7f3481SGal Pressman __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)]; 1530f7f3481SGal Pressman }; 1540f7f3481SGal Pressman 1559218b44dSGal Pressman struct mlx5e_rq_stats { 1569218b44dSGal Pressman u64 packets; 1579218b44dSGal Pressman u64 bytes; 158bfe6d8d1SGal Pressman u64 csum_complete; 159603e1f5bSGal Pressman u64 csum_unnecessary; 160bfe6d8d1SGal Pressman u64 csum_unnecessary_inner; 1611b223dd3SSaeed Mahameed u64 csum_none; 1629218b44dSGal Pressman u64 lro_packets; 1639218b44dSGal Pressman u64 lro_bytes; 164f24686e8SGal Pressman u64 removed_vlan_packets; 16586994156SRana Shahout u64 xdp_drop; 166b5503b99SSaeed Mahameed u64 xdp_tx; 167b5503b99SSaeed Mahameed u64 xdp_tx_full; 1689218b44dSGal Pressman u64 wqe_err; 1699218b44dSGal Pressman u64 mpwqe_filler; 1709218b44dSGal Pressman u64 buff_alloc_err; 1717219ab34STariq Toukan u64 cqe_compress_blks; 1727219ab34STariq Toukan u64 cqe_compress_pkts; 173accd5883STariq Toukan u64 page_reuse; 1744415a031STariq Toukan u64 cache_reuse; 1754415a031STariq Toukan u64 cache_full; 1764415a031STariq Toukan u64 cache_empty; 1774415a031STariq Toukan u64 cache_busy; 17870871f1eSTariq Toukan u64 cache_waive; 1799218b44dSGal Pressman }; 1809218b44dSGal Pressman 1819218b44dSGal Pressman struct mlx5e_sq_stats { 1829218b44dSGal Pressman /* commonly accessed in data path */ 1839218b44dSGal Pressman u64 packets; 1849218b44dSGal Pressman u64 bytes; 185c8cf78feSTariq Toukan u64 xmit_more; 1869218b44dSGal Pressman u64 tso_packets; 1879218b44dSGal Pressman u64 tso_bytes; 1889218b44dSGal Pressman u64 tso_inner_packets; 1899218b44dSGal Pressman u64 tso_inner_bytes; 190603e1f5bSGal Pressman u64 csum_partial; 191bfe6d8d1SGal Pressman u64 csum_partial_inner; 192f24686e8SGal Pressman u64 added_vlan_packets; 1939218b44dSGal Pressman u64 nop; 1949218b44dSGal Pressman /* less likely accessed in data path */ 195bfe6d8d1SGal Pressman u64 csum_none; 1969218b44dSGal Pressman u64 stopped; 1979218b44dSGal Pressman u64 wake; 1989218b44dSGal Pressman u64 dropped; 1999218b44dSGal Pressman }; 2009218b44dSGal Pressman 20157d689a8SEran Ben Elisha struct mlx5e_ch_stats { 20257d689a8SEran Ben Elisha u64 eq_rearm; 20357d689a8SEran Ben Elisha }; 20457d689a8SEran Ben Elisha 2059218b44dSGal Pressman struct mlx5e_stats { 2069218b44dSGal Pressman struct mlx5e_sw_stats sw; 2079218b44dSGal Pressman struct mlx5e_qcounter_stats qcnt; 2085c298143SMoshe Shemesh struct mlx5e_vnic_env_stats vnic; 2099218b44dSGal Pressman struct mlx5e_vport_stats vport; 2109218b44dSGal Pressman struct mlx5e_pport_stats pport; 211370bad0fSOr Gerlitz struct rtnl_link_stats64 vf_vport; 2120f7f3481SGal Pressman struct mlx5e_pcie_stats pcie; 2139218b44dSGal Pressman }; 2149218b44dSGal Pressman 21519386177SKamal Heib enum { 21619386177SKamal Heib MLX5E_NDO_UPDATE_STATS = BIT(0x1), 21719386177SKamal Heib }; 21819386177SKamal Heib 219c0752f2bSKamal Heib struct mlx5e_priv; 220c0752f2bSKamal Heib struct mlx5e_stats_grp { 22119386177SKamal Heib u16 update_stats_mask; 222c0752f2bSKamal Heib int (*get_num_stats)(struct mlx5e_priv *priv); 223c0752f2bSKamal Heib int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx); 224c0752f2bSKamal Heib int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx); 22519386177SKamal Heib void (*update_stats)(struct mlx5e_priv *priv); 226c0752f2bSKamal Heib }; 227c0752f2bSKamal Heib 228c0752f2bSKamal Heib extern const struct mlx5e_stats_grp mlx5e_stats_grps[]; 229c0752f2bSKamal Heib extern const int mlx5e_num_stats_grps; 230c0752f2bSKamal Heib 2319218b44dSGal Pressman #endif /* __MLX5_EN_STATS_H__ */ 232