1c0752f2bSKamal Heib /* 2c0752f2bSKamal Heib * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3c0752f2bSKamal Heib * 4c0752f2bSKamal Heib * This software is available to you under a choice of one of two 5c0752f2bSKamal Heib * licenses. You may choose to be licensed under the terms of the GNU 6c0752f2bSKamal Heib * General Public License (GPL) Version 2, available from the file 7c0752f2bSKamal Heib * COPYING in the main directory of this source tree, or the 8c0752f2bSKamal Heib * OpenIB.org BSD license below: 9c0752f2bSKamal Heib * 10c0752f2bSKamal Heib * Redistribution and use in source and binary forms, with or 11c0752f2bSKamal Heib * without modification, are permitted provided that the following 12c0752f2bSKamal Heib * conditions are met: 13c0752f2bSKamal Heib * 14c0752f2bSKamal Heib * - Redistributions of source code must retain the above 15c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 16c0752f2bSKamal Heib * disclaimer. 17c0752f2bSKamal Heib * 18c0752f2bSKamal Heib * - Redistributions in binary form must reproduce the above 19c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 20c0752f2bSKamal Heib * disclaimer in the documentation and/or other materials 21c0752f2bSKamal Heib * provided with the distribution. 22c0752f2bSKamal Heib * 23c0752f2bSKamal Heib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24c0752f2bSKamal Heib * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25c0752f2bSKamal Heib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26c0752f2bSKamal Heib * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27c0752f2bSKamal Heib * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28c0752f2bSKamal Heib * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29c0752f2bSKamal Heib * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30c0752f2bSKamal Heib * SOFTWARE. 31c0752f2bSKamal Heib */ 32c0752f2bSKamal Heib 33c0752f2bSKamal Heib #include "en.h" 34e185d43fSKamal Heib #include "en_accel/ipsec.h" 35c0752f2bSKamal Heib 36c0752f2bSKamal Heib static const struct counter_desc sw_stats_desc[] = { 37c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) }, 38c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) }, 39c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) }, 40c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) }, 41c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) }, 42c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) }, 43c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) }, 44c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) }, 45f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) }, 46bf239741SIlya Lesokhin 47bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 48bf239741SIlya Lesokhin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) }, 49bf239741SIlya Lesokhin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) }, 50bf239741SIlya Lesokhin #endif 51bf239741SIlya Lesokhin 52c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) }, 53c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) }, 54f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) }, 55c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) }, 56c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) }, 57c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) }, 58c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) }, 59c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) }, 60c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) }, 61c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) }, 62c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) }, 63c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) }, 64c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) }, 65c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) }, 66c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) }, 67c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) }, 68c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) }, 6916cc14d8SEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) }, 70db75373cSEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) }, 71c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) }, 72c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) }, 73c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) }, 74c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 75c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 76c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) }, 77c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) }, 78c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) }, 79c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) }, 80c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) }, 81c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) }, 8257d689a8SEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) }, 83c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) }, 84c0752f2bSKamal Heib }; 85c0752f2bSKamal Heib 86c0752f2bSKamal Heib #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc) 87c0752f2bSKamal Heib 88c0752f2bSKamal Heib static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv) 89c0752f2bSKamal Heib { 90c0752f2bSKamal Heib return NUM_SW_COUNTERS; 91c0752f2bSKamal Heib } 92c0752f2bSKamal Heib 93c0752f2bSKamal Heib static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 94c0752f2bSKamal Heib { 95c0752f2bSKamal Heib int i; 96c0752f2bSKamal Heib 97c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 98c0752f2bSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format); 99c0752f2bSKamal Heib return idx; 100c0752f2bSKamal Heib } 101c0752f2bSKamal Heib 102c0752f2bSKamal Heib static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 103c0752f2bSKamal Heib { 104c0752f2bSKamal Heib int i; 105c0752f2bSKamal Heib 106c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 107c0752f2bSKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i); 108c0752f2bSKamal Heib return idx; 109c0752f2bSKamal Heib } 110c0752f2bSKamal Heib 11119386177SKamal Heib static void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv) 11219386177SKamal Heib { 11319386177SKamal Heib struct mlx5e_sw_stats temp, *s = &temp; 11419386177SKamal Heib struct mlx5e_rq_stats *rq_stats; 11519386177SKamal Heib struct mlx5e_sq_stats *sq_stats; 11619386177SKamal Heib struct mlx5e_ch_stats *ch_stats; 11719386177SKamal Heib int i, j; 11819386177SKamal Heib 11919386177SKamal Heib memset(s, 0, sizeof(*s)); 12019386177SKamal Heib for (i = 0; i < priv->channels.num; i++) { 12119386177SKamal Heib struct mlx5e_channel *c = priv->channels.c[i]; 12219386177SKamal Heib 12319386177SKamal Heib rq_stats = &c->rq.stats; 12419386177SKamal Heib ch_stats = &c->stats; 12519386177SKamal Heib 12619386177SKamal Heib s->rx_packets += rq_stats->packets; 12719386177SKamal Heib s->rx_bytes += rq_stats->bytes; 12819386177SKamal Heib s->rx_lro_packets += rq_stats->lro_packets; 12919386177SKamal Heib s->rx_lro_bytes += rq_stats->lro_bytes; 13019386177SKamal Heib s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets; 13119386177SKamal Heib s->rx_csum_none += rq_stats->csum_none; 13219386177SKamal Heib s->rx_csum_complete += rq_stats->csum_complete; 13319386177SKamal Heib s->rx_csum_unnecessary += rq_stats->csum_unnecessary; 13419386177SKamal Heib s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; 13519386177SKamal Heib s->rx_xdp_drop += rq_stats->xdp_drop; 13619386177SKamal Heib s->rx_xdp_tx += rq_stats->xdp_tx; 13719386177SKamal Heib s->rx_xdp_tx_full += rq_stats->xdp_tx_full; 13819386177SKamal Heib s->rx_wqe_err += rq_stats->wqe_err; 13919386177SKamal Heib s->rx_mpwqe_filler += rq_stats->mpwqe_filler; 14019386177SKamal Heib s->rx_buff_alloc_err += rq_stats->buff_alloc_err; 14119386177SKamal Heib s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; 14219386177SKamal Heib s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; 14319386177SKamal Heib s->rx_page_reuse += rq_stats->page_reuse; 14419386177SKamal Heib s->rx_cache_reuse += rq_stats->cache_reuse; 14519386177SKamal Heib s->rx_cache_full += rq_stats->cache_full; 14619386177SKamal Heib s->rx_cache_empty += rq_stats->cache_empty; 14719386177SKamal Heib s->rx_cache_busy += rq_stats->cache_busy; 14819386177SKamal Heib s->rx_cache_waive += rq_stats->cache_waive; 14919386177SKamal Heib s->ch_eq_rearm += ch_stats->eq_rearm; 15019386177SKamal Heib 15119386177SKamal Heib for (j = 0; j < priv->channels.params.num_tc; j++) { 15219386177SKamal Heib sq_stats = &c->sq[j].stats; 15319386177SKamal Heib 15419386177SKamal Heib s->tx_packets += sq_stats->packets; 15519386177SKamal Heib s->tx_bytes += sq_stats->bytes; 15619386177SKamal Heib s->tx_tso_packets += sq_stats->tso_packets; 15719386177SKamal Heib s->tx_tso_bytes += sq_stats->tso_bytes; 15819386177SKamal Heib s->tx_tso_inner_packets += sq_stats->tso_inner_packets; 15919386177SKamal Heib s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; 16019386177SKamal Heib s->tx_added_vlan_packets += sq_stats->added_vlan_packets; 16119386177SKamal Heib s->tx_queue_stopped += sq_stats->stopped; 16219386177SKamal Heib s->tx_queue_wake += sq_stats->wake; 16319386177SKamal Heib s->tx_queue_dropped += sq_stats->dropped; 16416cc14d8SEran Ben Elisha s->tx_cqe_err += sq_stats->cqe_err; 165db75373cSEran Ben Elisha s->tx_recover += sq_stats->recover; 16619386177SKamal Heib s->tx_xmit_more += sq_stats->xmit_more; 16719386177SKamal Heib s->tx_csum_partial_inner += sq_stats->csum_partial_inner; 16819386177SKamal Heib s->tx_csum_none += sq_stats->csum_none; 16919386177SKamal Heib s->tx_csum_partial += sq_stats->csum_partial; 170bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 171bf239741SIlya Lesokhin s->tx_tls_ooo += sq_stats->tls_ooo; 172bf239741SIlya Lesokhin s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes; 173bf239741SIlya Lesokhin #endif 17419386177SKamal Heib } 17519386177SKamal Heib } 17619386177SKamal Heib 17719386177SKamal Heib s->link_down_events_phy = MLX5_GET(ppcnt_reg, 17819386177SKamal Heib priv->stats.pport.phy_counters, 17919386177SKamal Heib counter_set.phys_layer_cntrs.link_down_events); 18019386177SKamal Heib memcpy(&priv->stats.sw, s, sizeof(*s)); 18119386177SKamal Heib } 18219386177SKamal Heib 183fd8dcdb8SKamal Heib static const struct counter_desc q_stats_desc[] = { 184fd8dcdb8SKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) }, 185fd8dcdb8SKamal Heib }; 186fd8dcdb8SKamal Heib 1877cbaf9a3SMoshe Shemesh static const struct counter_desc drop_rq_stats_desc[] = { 1887cbaf9a3SMoshe Shemesh { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) }, 1897cbaf9a3SMoshe Shemesh }; 1907cbaf9a3SMoshe Shemesh 191fd8dcdb8SKamal Heib #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc) 1927cbaf9a3SMoshe Shemesh #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc) 193fd8dcdb8SKamal Heib 194fd8dcdb8SKamal Heib static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv) 195fd8dcdb8SKamal Heib { 1967cbaf9a3SMoshe Shemesh int num_stats = 0; 1977cbaf9a3SMoshe Shemesh 1987cbaf9a3SMoshe Shemesh if (priv->q_counter) 1997cbaf9a3SMoshe Shemesh num_stats += NUM_Q_COUNTERS; 2007cbaf9a3SMoshe Shemesh 2017cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter) 2027cbaf9a3SMoshe Shemesh num_stats += NUM_DROP_RQ_COUNTERS; 2037cbaf9a3SMoshe Shemesh 2047cbaf9a3SMoshe Shemesh return num_stats; 205fd8dcdb8SKamal Heib } 206fd8dcdb8SKamal Heib 207fd8dcdb8SKamal Heib static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 208fd8dcdb8SKamal Heib { 209fd8dcdb8SKamal Heib int i; 210fd8dcdb8SKamal Heib 211fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 2127cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2137cbaf9a3SMoshe Shemesh q_stats_desc[i].format); 2147cbaf9a3SMoshe Shemesh 2157cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 2167cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2177cbaf9a3SMoshe Shemesh drop_rq_stats_desc[i].format); 2187cbaf9a3SMoshe Shemesh 219fd8dcdb8SKamal Heib return idx; 220fd8dcdb8SKamal Heib } 221fd8dcdb8SKamal Heib 222fd8dcdb8SKamal Heib static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 223fd8dcdb8SKamal Heib { 224fd8dcdb8SKamal Heib int i; 225fd8dcdb8SKamal Heib 226fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 2277cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 2287cbaf9a3SMoshe Shemesh q_stats_desc, i); 2297cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 2307cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 2317cbaf9a3SMoshe Shemesh drop_rq_stats_desc, i); 232fd8dcdb8SKamal Heib return idx; 233fd8dcdb8SKamal Heib } 234fd8dcdb8SKamal Heib 23519386177SKamal Heib static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv) 23619386177SKamal Heib { 23719386177SKamal Heib struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; 23819386177SKamal Heib u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; 23919386177SKamal Heib 2407cbaf9a3SMoshe Shemesh if (priv->q_counter && 2417cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, 2427cbaf9a3SMoshe Shemesh sizeof(out))) 2437cbaf9a3SMoshe Shemesh qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, 2447cbaf9a3SMoshe Shemesh out, out_of_buffer); 2457cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter && 2467cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0, 2477cbaf9a3SMoshe Shemesh out, sizeof(out))) 2487cbaf9a3SMoshe Shemesh qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out, 2497cbaf9a3SMoshe Shemesh out_of_buffer); 25019386177SKamal Heib } 25119386177SKamal Heib 2525c298143SMoshe Shemesh #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c) 2535c298143SMoshe Shemesh static const struct counter_desc vnic_env_stats_desc[] = { 2545c298143SMoshe Shemesh { "rx_steer_missed_packets", 2555c298143SMoshe Shemesh VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) }, 2565c298143SMoshe Shemesh }; 2575c298143SMoshe Shemesh 2585c298143SMoshe Shemesh #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc) 2595c298143SMoshe Shemesh 2605c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv) 2615c298143SMoshe Shemesh { 2625c298143SMoshe Shemesh return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ? 2635c298143SMoshe Shemesh NUM_VNIC_ENV_COUNTERS : 0; 2645c298143SMoshe Shemesh } 2655c298143SMoshe Shemesh 2665c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data, 2675c298143SMoshe Shemesh int idx) 2685c298143SMoshe Shemesh { 2695c298143SMoshe Shemesh int i; 2705c298143SMoshe Shemesh 2715c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 2725c298143SMoshe Shemesh return idx; 2735c298143SMoshe Shemesh 2745c298143SMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 2755c298143SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2765c298143SMoshe Shemesh vnic_env_stats_desc[i].format); 2775c298143SMoshe Shemesh return idx; 2785c298143SMoshe Shemesh } 2795c298143SMoshe Shemesh 2805c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data, 2815c298143SMoshe Shemesh int idx) 2825c298143SMoshe Shemesh { 2835c298143SMoshe Shemesh int i; 2845c298143SMoshe Shemesh 2855c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 2865c298143SMoshe Shemesh return idx; 2875c298143SMoshe Shemesh 2885c298143SMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 2895c298143SMoshe Shemesh data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out, 2905c298143SMoshe Shemesh vnic_env_stats_desc, i); 2915c298143SMoshe Shemesh return idx; 2925c298143SMoshe Shemesh } 2935c298143SMoshe Shemesh 2945c298143SMoshe Shemesh static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 2955c298143SMoshe Shemesh { 2965c298143SMoshe Shemesh u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out; 2975c298143SMoshe Shemesh int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out); 2985c298143SMoshe Shemesh u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; 2995c298143SMoshe Shemesh struct mlx5_core_dev *mdev = priv->mdev; 3005c298143SMoshe Shemesh 3015c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 3025c298143SMoshe Shemesh return; 3035c298143SMoshe Shemesh 3045c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, opcode, 3055c298143SMoshe Shemesh MLX5_CMD_OP_QUERY_VNIC_ENV); 3065c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, op_mod, 0); 3075c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, other_vport, 0); 3085c298143SMoshe Shemesh mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 3095c298143SMoshe Shemesh } 3105c298143SMoshe Shemesh 31140cab9f1SKamal Heib #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) 31240cab9f1SKamal Heib static const struct counter_desc vport_stats_desc[] = { 31340cab9f1SKamal Heib { "rx_vport_unicast_packets", 31440cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.packets) }, 31540cab9f1SKamal Heib { "rx_vport_unicast_bytes", 31640cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.octets) }, 31740cab9f1SKamal Heib { "tx_vport_unicast_packets", 31840cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) }, 31940cab9f1SKamal Heib { "tx_vport_unicast_bytes", 32040cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) }, 32140cab9f1SKamal Heib { "rx_vport_multicast_packets", 32240cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.packets) }, 32340cab9f1SKamal Heib { "rx_vport_multicast_bytes", 32440cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.octets) }, 32540cab9f1SKamal Heib { "tx_vport_multicast_packets", 32640cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) }, 32740cab9f1SKamal Heib { "tx_vport_multicast_bytes", 32840cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) }, 32940cab9f1SKamal Heib { "rx_vport_broadcast_packets", 33040cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.packets) }, 33140cab9f1SKamal Heib { "rx_vport_broadcast_bytes", 33240cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.octets) }, 33340cab9f1SKamal Heib { "tx_vport_broadcast_packets", 33440cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) }, 33540cab9f1SKamal Heib { "tx_vport_broadcast_bytes", 33640cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) }, 33740cab9f1SKamal Heib { "rx_vport_rdma_unicast_packets", 33840cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.packets) }, 33940cab9f1SKamal Heib { "rx_vport_rdma_unicast_bytes", 34040cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.octets) }, 34140cab9f1SKamal Heib { "tx_vport_rdma_unicast_packets", 34240cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) }, 34340cab9f1SKamal Heib { "tx_vport_rdma_unicast_bytes", 34440cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) }, 34540cab9f1SKamal Heib { "rx_vport_rdma_multicast_packets", 34640cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.packets) }, 34740cab9f1SKamal Heib { "rx_vport_rdma_multicast_bytes", 34840cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.octets) }, 34940cab9f1SKamal Heib { "tx_vport_rdma_multicast_packets", 35040cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) }, 35140cab9f1SKamal Heib { "tx_vport_rdma_multicast_bytes", 35240cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) }, 35340cab9f1SKamal Heib }; 35440cab9f1SKamal Heib 35540cab9f1SKamal Heib #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc) 35640cab9f1SKamal Heib 35740cab9f1SKamal Heib static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv) 35840cab9f1SKamal Heib { 35940cab9f1SKamal Heib return NUM_VPORT_COUNTERS; 36040cab9f1SKamal Heib } 36140cab9f1SKamal Heib 36240cab9f1SKamal Heib static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data, 36340cab9f1SKamal Heib int idx) 36440cab9f1SKamal Heib { 36540cab9f1SKamal Heib int i; 36640cab9f1SKamal Heib 36740cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 36840cab9f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format); 36940cab9f1SKamal Heib return idx; 37040cab9f1SKamal Heib } 37140cab9f1SKamal Heib 37240cab9f1SKamal Heib static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data, 37340cab9f1SKamal Heib int idx) 37440cab9f1SKamal Heib { 37540cab9f1SKamal Heib int i; 37640cab9f1SKamal Heib 37740cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 37840cab9f1SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out, 37940cab9f1SKamal Heib vport_stats_desc, i); 38040cab9f1SKamal Heib return idx; 38140cab9f1SKamal Heib } 38240cab9f1SKamal Heib 38319386177SKamal Heib static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv) 38419386177SKamal Heib { 38519386177SKamal Heib int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 38619386177SKamal Heib u32 *out = (u32 *)priv->stats.vport.query_vport_out; 38719386177SKamal Heib u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; 38819386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 38919386177SKamal Heib 39019386177SKamal Heib MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER); 39119386177SKamal Heib MLX5_SET(query_vport_counter_in, in, op_mod, 0); 39219386177SKamal Heib MLX5_SET(query_vport_counter_in, in, other_vport, 0); 39319386177SKamal Heib mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 39419386177SKamal Heib } 39519386177SKamal Heib 3966e6ef814SKamal Heib #define PPORT_802_3_OFF(c) \ 3976e6ef814SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 3986e6ef814SKamal Heib counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 3996e6ef814SKamal Heib static const struct counter_desc pport_802_3_stats_desc[] = { 4006e6ef814SKamal Heib { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) }, 4016e6ef814SKamal Heib { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) }, 4026e6ef814SKamal Heib { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) }, 4036e6ef814SKamal Heib { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) }, 4046e6ef814SKamal Heib { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) }, 4056e6ef814SKamal Heib { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) }, 4066e6ef814SKamal Heib { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) }, 4076e6ef814SKamal Heib { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) }, 4086e6ef814SKamal Heib { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) }, 4096e6ef814SKamal Heib { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) }, 4106e6ef814SKamal Heib { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) }, 4116e6ef814SKamal Heib { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) }, 4126e6ef814SKamal Heib { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) }, 4136e6ef814SKamal Heib { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) }, 4146e6ef814SKamal Heib { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) }, 4156e6ef814SKamal Heib { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) }, 4166e6ef814SKamal Heib { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) }, 4176e6ef814SKamal Heib { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) }, 4186e6ef814SKamal Heib }; 4196e6ef814SKamal Heib 4206e6ef814SKamal Heib #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc) 4216e6ef814SKamal Heib 4226e6ef814SKamal Heib static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv) 4236e6ef814SKamal Heib { 4246e6ef814SKamal Heib return NUM_PPORT_802_3_COUNTERS; 4256e6ef814SKamal Heib } 4266e6ef814SKamal Heib 4276e6ef814SKamal Heib static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data, 4286e6ef814SKamal Heib int idx) 4296e6ef814SKamal Heib { 4306e6ef814SKamal Heib int i; 4316e6ef814SKamal Heib 4326e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 4336e6ef814SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format); 4346e6ef814SKamal Heib return idx; 4356e6ef814SKamal Heib } 4366e6ef814SKamal Heib 4376e6ef814SKamal Heib static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data, 4386e6ef814SKamal Heib int idx) 4396e6ef814SKamal Heib { 4406e6ef814SKamal Heib int i; 4416e6ef814SKamal Heib 4426e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 4436e6ef814SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters, 4446e6ef814SKamal Heib pport_802_3_stats_desc, i); 4456e6ef814SKamal Heib return idx; 4466e6ef814SKamal Heib } 4476e6ef814SKamal Heib 44819386177SKamal Heib static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv) 44919386177SKamal Heib { 45019386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 45119386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 45219386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 45319386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 45419386177SKamal Heib void *out; 45519386177SKamal Heib 45619386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 45719386177SKamal Heib out = pstats->IEEE_802_3_counters; 45819386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 45919386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 46019386177SKamal Heib } 46119386177SKamal Heib 462fc8e64a3SKamal Heib #define PPORT_2863_OFF(c) \ 463fc8e64a3SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 464fc8e64a3SKamal Heib counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 465fc8e64a3SKamal Heib static const struct counter_desc pport_2863_stats_desc[] = { 466fc8e64a3SKamal Heib { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) }, 467fc8e64a3SKamal Heib { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) }, 468fc8e64a3SKamal Heib { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) }, 469fc8e64a3SKamal Heib }; 470fc8e64a3SKamal Heib 471fc8e64a3SKamal Heib #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc) 472fc8e64a3SKamal Heib 473fc8e64a3SKamal Heib static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv) 474fc8e64a3SKamal Heib { 475fc8e64a3SKamal Heib return NUM_PPORT_2863_COUNTERS; 476fc8e64a3SKamal Heib } 477fc8e64a3SKamal Heib 478fc8e64a3SKamal Heib static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data, 479fc8e64a3SKamal Heib int idx) 480fc8e64a3SKamal Heib { 481fc8e64a3SKamal Heib int i; 482fc8e64a3SKamal Heib 483fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 484fc8e64a3SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format); 485fc8e64a3SKamal Heib return idx; 486fc8e64a3SKamal Heib } 487fc8e64a3SKamal Heib 488fc8e64a3SKamal Heib static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data, 489fc8e64a3SKamal Heib int idx) 490fc8e64a3SKamal Heib { 491fc8e64a3SKamal Heib int i; 492fc8e64a3SKamal Heib 493fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 494fc8e64a3SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters, 495fc8e64a3SKamal Heib pport_2863_stats_desc, i); 496fc8e64a3SKamal Heib return idx; 497fc8e64a3SKamal Heib } 498fc8e64a3SKamal Heib 49919386177SKamal Heib static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv) 50019386177SKamal Heib { 50119386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 50219386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 50319386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 50419386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 50519386177SKamal Heib void *out; 50619386177SKamal Heib 50719386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 50819386177SKamal Heib out = pstats->RFC_2863_counters; 50919386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 51019386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 51119386177SKamal Heib } 51219386177SKamal Heib 513e0e0def9SKamal Heib #define PPORT_2819_OFF(c) \ 514e0e0def9SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 515e0e0def9SKamal Heib counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 516e0e0def9SKamal Heib static const struct counter_desc pport_2819_stats_desc[] = { 517e0e0def9SKamal Heib { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) }, 518e0e0def9SKamal Heib { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) }, 519e0e0def9SKamal Heib { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) }, 520e0e0def9SKamal Heib { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) }, 521e0e0def9SKamal Heib { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) }, 522e0e0def9SKamal Heib { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) }, 523e0e0def9SKamal Heib { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) }, 524e0e0def9SKamal Heib { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) }, 525e0e0def9SKamal Heib { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) }, 526e0e0def9SKamal Heib { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) }, 527e0e0def9SKamal Heib { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) }, 528e0e0def9SKamal Heib { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) }, 529e0e0def9SKamal Heib { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) }, 530e0e0def9SKamal Heib }; 531e0e0def9SKamal Heib 532e0e0def9SKamal Heib #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc) 533e0e0def9SKamal Heib 534e0e0def9SKamal Heib static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv) 535e0e0def9SKamal Heib { 536e0e0def9SKamal Heib return NUM_PPORT_2819_COUNTERS; 537e0e0def9SKamal Heib } 538e0e0def9SKamal Heib 539e0e0def9SKamal Heib static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data, 540e0e0def9SKamal Heib int idx) 541e0e0def9SKamal Heib { 542e0e0def9SKamal Heib int i; 543e0e0def9SKamal Heib 544e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 545e0e0def9SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format); 546e0e0def9SKamal Heib return idx; 547e0e0def9SKamal Heib } 548e0e0def9SKamal Heib 549e0e0def9SKamal Heib static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data, 550e0e0def9SKamal Heib int idx) 551e0e0def9SKamal Heib { 552e0e0def9SKamal Heib int i; 553e0e0def9SKamal Heib 554e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 555e0e0def9SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters, 556e0e0def9SKamal Heib pport_2819_stats_desc, i); 557e0e0def9SKamal Heib return idx; 558e0e0def9SKamal Heib } 559e0e0def9SKamal Heib 56019386177SKamal Heib static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv) 56119386177SKamal Heib { 56219386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 56319386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 56419386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 56519386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 56619386177SKamal Heib void *out; 56719386177SKamal Heib 56819386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 56919386177SKamal Heib out = pstats->RFC_2819_counters; 57019386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 57119386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 57219386177SKamal Heib } 57319386177SKamal Heib 5742e4df0b2SKamal Heib #define PPORT_PHY_STATISTICAL_OFF(c) \ 5752e4df0b2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 5762e4df0b2SKamal Heib counter_set.phys_layer_statistical_cntrs.c##_high) 5772e4df0b2SKamal Heib static const struct counter_desc pport_phy_statistical_stats_desc[] = { 5782e4df0b2SKamal Heib { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) }, 5792e4df0b2SKamal Heib { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) }, 5802e4df0b2SKamal Heib }; 5812e4df0b2SKamal Heib 5822e4df0b2SKamal Heib #define NUM_PPORT_PHY_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc) 5832e4df0b2SKamal Heib 5842e4df0b2SKamal Heib static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv) 5852e4df0b2SKamal Heib { 5862e4df0b2SKamal Heib return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ? 5872e4df0b2SKamal Heib NUM_PPORT_PHY_COUNTERS : 0; 5882e4df0b2SKamal Heib } 5892e4df0b2SKamal Heib 5902e4df0b2SKamal Heib static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data, 5912e4df0b2SKamal Heib int idx) 5922e4df0b2SKamal Heib { 5932e4df0b2SKamal Heib int i; 5942e4df0b2SKamal Heib 5952e4df0b2SKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group)) 5962e4df0b2SKamal Heib for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++) 5972e4df0b2SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 5982e4df0b2SKamal Heib pport_phy_statistical_stats_desc[i].format); 5992e4df0b2SKamal Heib return idx; 6002e4df0b2SKamal Heib } 6012e4df0b2SKamal Heib 6022e4df0b2SKamal Heib static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 6032e4df0b2SKamal Heib { 6042e4df0b2SKamal Heib int i; 6052e4df0b2SKamal Heib 6062e4df0b2SKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group)) 6072e4df0b2SKamal Heib for (i = 0; i < NUM_PPORT_PHY_COUNTERS; i++) 6082e4df0b2SKamal Heib data[idx++] = 6092e4df0b2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 6102e4df0b2SKamal Heib pport_phy_statistical_stats_desc, i); 6112e4df0b2SKamal Heib return idx; 6122e4df0b2SKamal Heib } 6132e4df0b2SKamal Heib 61419386177SKamal Heib static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv) 61519386177SKamal Heib { 61619386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 61719386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 61819386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 61919386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 62019386177SKamal Heib void *out; 62119386177SKamal Heib 62219386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 62319386177SKamal Heib out = pstats->phy_counters; 62419386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 62519386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 62619386177SKamal Heib 62719386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 62819386177SKamal Heib return; 62919386177SKamal Heib 63019386177SKamal Heib out = pstats->phy_statistical_counters; 63119386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 63219386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 63319386177SKamal Heib } 63419386177SKamal Heib 6353488bd4cSKamal Heib #define PPORT_ETH_EXT_OFF(c) \ 6363488bd4cSKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 6373488bd4cSKamal Heib counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 6383488bd4cSKamal Heib static const struct counter_desc pport_eth_ext_stats_desc[] = { 6393488bd4cSKamal Heib { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) }, 6403488bd4cSKamal Heib }; 6413488bd4cSKamal Heib 6423488bd4cSKamal Heib #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc) 6433488bd4cSKamal Heib 6443488bd4cSKamal Heib static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv) 6453488bd4cSKamal Heib { 6463488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 6473488bd4cSKamal Heib return NUM_PPORT_ETH_EXT_COUNTERS; 6483488bd4cSKamal Heib 6493488bd4cSKamal Heib return 0; 6503488bd4cSKamal Heib } 6513488bd4cSKamal Heib 6523488bd4cSKamal Heib static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data, 6533488bd4cSKamal Heib int idx) 6543488bd4cSKamal Heib { 6553488bd4cSKamal Heib int i; 6563488bd4cSKamal Heib 6573488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 6583488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 6593488bd4cSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 6603488bd4cSKamal Heib pport_eth_ext_stats_desc[i].format); 6613488bd4cSKamal Heib return idx; 6623488bd4cSKamal Heib } 6633488bd4cSKamal Heib 6643488bd4cSKamal Heib static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data, 6653488bd4cSKamal Heib int idx) 6663488bd4cSKamal Heib { 6673488bd4cSKamal Heib int i; 6683488bd4cSKamal Heib 6693488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 6703488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 6713488bd4cSKamal Heib data[idx++] = 6723488bd4cSKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters, 6733488bd4cSKamal Heib pport_eth_ext_stats_desc, i); 6743488bd4cSKamal Heib return idx; 6753488bd4cSKamal Heib } 6763488bd4cSKamal Heib 67719386177SKamal Heib static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv) 67819386177SKamal Heib { 67919386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 68019386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 68119386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 68219386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 68319386177SKamal Heib void *out; 68419386177SKamal Heib 68519386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) 68619386177SKamal Heib return; 68719386177SKamal Heib 68819386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 68919386177SKamal Heib out = pstats->eth_ext_counters; 69019386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 69119386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 69219386177SKamal Heib } 69319386177SKamal Heib 6949fd2b5f1SKamal Heib #define PCIE_PERF_OFF(c) \ 6959fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c) 6969fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc[] = { 6979fd2b5f1SKamal Heib { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) }, 6989fd2b5f1SKamal Heib { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) }, 6999fd2b5f1SKamal Heib }; 7009fd2b5f1SKamal Heib 7019fd2b5f1SKamal Heib #define PCIE_PERF_OFF64(c) \ 7029fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 7039fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc64[] = { 7049fd2b5f1SKamal Heib { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) }, 7059fd2b5f1SKamal Heib }; 7069fd2b5f1SKamal Heib 7079fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stall_stats_desc[] = { 7089fd2b5f1SKamal Heib { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) }, 7099fd2b5f1SKamal Heib { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) }, 7109fd2b5f1SKamal Heib { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) }, 7119fd2b5f1SKamal Heib { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) }, 7129fd2b5f1SKamal Heib }; 7139fd2b5f1SKamal Heib 7149fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc) 7159fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64) 7169fd2b5f1SKamal Heib #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc) 7179fd2b5f1SKamal Heib 7189fd2b5f1SKamal Heib static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv) 7199fd2b5f1SKamal Heib { 7209fd2b5f1SKamal Heib int num_stats = 0; 7219fd2b5f1SKamal Heib 7229fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7239fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS; 7249fd2b5f1SKamal Heib 7259fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 7269fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS64; 7279fd2b5f1SKamal Heib 7289fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 7299fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_STALL_COUNTERS; 7309fd2b5f1SKamal Heib 7319fd2b5f1SKamal Heib return num_stats; 7329fd2b5f1SKamal Heib } 7339fd2b5f1SKamal Heib 7349fd2b5f1SKamal Heib static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data, 7359fd2b5f1SKamal Heib int idx) 7369fd2b5f1SKamal Heib { 7379fd2b5f1SKamal Heib int i; 7389fd2b5f1SKamal Heib 7399fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7409fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 7419fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7429fd2b5f1SKamal Heib pcie_perf_stats_desc[i].format); 7439fd2b5f1SKamal Heib 7449fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 7459fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 7469fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7479fd2b5f1SKamal Heib pcie_perf_stats_desc64[i].format); 7489fd2b5f1SKamal Heib 7499fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 7509fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 7519fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7529fd2b5f1SKamal Heib pcie_perf_stall_stats_desc[i].format); 7539fd2b5f1SKamal Heib return idx; 7549fd2b5f1SKamal Heib } 7559fd2b5f1SKamal Heib 7569fd2b5f1SKamal Heib static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data, 7579fd2b5f1SKamal Heib int idx) 7589fd2b5f1SKamal Heib { 7599fd2b5f1SKamal Heib int i; 7609fd2b5f1SKamal Heib 7619fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7629fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 7639fd2b5f1SKamal Heib data[idx++] = 7649fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 7659fd2b5f1SKamal Heib pcie_perf_stats_desc, i); 7669fd2b5f1SKamal Heib 7679fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 7689fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 7699fd2b5f1SKamal Heib data[idx++] = 7709fd2b5f1SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters, 7719fd2b5f1SKamal Heib pcie_perf_stats_desc64, i); 7729fd2b5f1SKamal Heib 7739fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 7749fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 7759fd2b5f1SKamal Heib data[idx++] = 7769fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 7779fd2b5f1SKamal Heib pcie_perf_stall_stats_desc, i); 7789fd2b5f1SKamal Heib return idx; 7799fd2b5f1SKamal Heib } 7809fd2b5f1SKamal Heib 78119386177SKamal Heib static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv) 78219386177SKamal Heib { 78319386177SKamal Heib struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; 78419386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 78519386177SKamal Heib u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; 78619386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 78719386177SKamal Heib void *out; 78819386177SKamal Heib 78919386177SKamal Heib if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) 79019386177SKamal Heib return; 79119386177SKamal Heib 79219386177SKamal Heib out = pcie_stats->pcie_perf_counters; 79319386177SKamal Heib MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 79419386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 79519386177SKamal Heib } 79619386177SKamal Heib 7974377bea2SKamal Heib #define PPORT_PER_PRIO_OFF(c) \ 7984377bea2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 7994377bea2SKamal Heib counter_set.eth_per_prio_grp_data_layout.c##_high) 800e6000651SKamal Heib static const struct counter_desc pport_per_prio_traffic_stats_desc[] = { 801e6000651SKamal Heib { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) }, 802e6000651SKamal Heib { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) }, 803e6000651SKamal Heib { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) }, 804e6000651SKamal Heib { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) }, 805e6000651SKamal Heib }; 806e6000651SKamal Heib 807e6000651SKamal Heib #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc) 808e6000651SKamal Heib 809e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv) 810e6000651SKamal Heib { 811e6000651SKamal Heib return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO; 812e6000651SKamal Heib } 813e6000651SKamal Heib 814e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv, 815e6000651SKamal Heib u8 *data, 816e6000651SKamal Heib int idx) 817e6000651SKamal Heib { 818e6000651SKamal Heib int i, prio; 819e6000651SKamal Heib 820e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 821e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 822e6000651SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 823e6000651SKamal Heib pport_per_prio_traffic_stats_desc[i].format, prio); 824e6000651SKamal Heib } 825e6000651SKamal Heib 826e6000651SKamal Heib return idx; 827e6000651SKamal Heib } 828e6000651SKamal Heib 829e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv, 830e6000651SKamal Heib u64 *data, 831e6000651SKamal Heib int idx) 832e6000651SKamal Heib { 833e6000651SKamal Heib int i, prio; 834e6000651SKamal Heib 835e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 836e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 837e6000651SKamal Heib data[idx++] = 838e6000651SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 839e6000651SKamal Heib pport_per_prio_traffic_stats_desc, i); 840e6000651SKamal Heib } 841e6000651SKamal Heib 842e6000651SKamal Heib return idx; 843e6000651SKamal Heib } 844e6000651SKamal Heib 8454377bea2SKamal Heib static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 8464377bea2SKamal Heib /* %s is "global" or "prio{i}" */ 8474377bea2SKamal Heib { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) }, 8484377bea2SKamal Heib { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) }, 8494377bea2SKamal Heib { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) }, 8504377bea2SKamal Heib { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) }, 8514377bea2SKamal Heib { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, 8524377bea2SKamal Heib }; 8534377bea2SKamal Heib 8542fcb12dfSInbar Karmy static const struct counter_desc pport_pfc_stall_stats_desc[] = { 8552fcb12dfSInbar Karmy { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) }, 8562fcb12dfSInbar Karmy { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) }, 8572fcb12dfSInbar Karmy }; 8582fcb12dfSInbar Karmy 8594377bea2SKamal Heib #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc) 8602fcb12dfSInbar Karmy #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \ 8612fcb12dfSInbar Karmy MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \ 8622fcb12dfSInbar Karmy MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 8634377bea2SKamal Heib 8644377bea2SKamal Heib static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) 8654377bea2SKamal Heib { 8664377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 8674377bea2SKamal Heib u8 pfc_en_tx; 8684377bea2SKamal Heib u8 pfc_en_rx; 8694377bea2SKamal Heib int err; 8704377bea2SKamal Heib 8714377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 8724377bea2SKamal Heib return 0; 8734377bea2SKamal Heib 8744377bea2SKamal Heib err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx); 8754377bea2SKamal Heib 8764377bea2SKamal Heib return err ? 0 : pfc_en_tx | pfc_en_rx; 8774377bea2SKamal Heib } 8784377bea2SKamal Heib 8794377bea2SKamal Heib static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv) 8804377bea2SKamal Heib { 8814377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 8824377bea2SKamal Heib u32 rx_pause; 8834377bea2SKamal Heib u32 tx_pause; 8844377bea2SKamal Heib int err; 8854377bea2SKamal Heib 8864377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 8874377bea2SKamal Heib return false; 8884377bea2SKamal Heib 8894377bea2SKamal Heib err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 8904377bea2SKamal Heib 8914377bea2SKamal Heib return err ? false : rx_pause | tx_pause; 8924377bea2SKamal Heib } 8934377bea2SKamal Heib 8944377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) 8954377bea2SKamal Heib { 8964377bea2SKamal Heib return (mlx5e_query_global_pause_combined(priv) + 8974377bea2SKamal Heib hweight8(mlx5e_query_pfc_combined(priv))) * 8982fcb12dfSInbar Karmy NUM_PPORT_PER_PRIO_PFC_COUNTERS + 8992fcb12dfSInbar Karmy NUM_PPORT_PFC_STALL_COUNTERS(priv); 9004377bea2SKamal Heib } 9014377bea2SKamal Heib 9024377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, 9034377bea2SKamal Heib u8 *data, 9044377bea2SKamal Heib int idx) 9054377bea2SKamal Heib { 9064377bea2SKamal Heib unsigned long pfc_combined; 9074377bea2SKamal Heib int i, prio; 9084377bea2SKamal Heib 9094377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 9104377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 9114377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9124377bea2SKamal Heib char pfc_string[ETH_GSTRING_LEN]; 9134377bea2SKamal Heib 9144377bea2SKamal Heib snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio); 9154377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 9164377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, pfc_string); 9174377bea2SKamal Heib } 9184377bea2SKamal Heib } 9194377bea2SKamal Heib 9204377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 9214377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9224377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 9234377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, "global"); 9244377bea2SKamal Heib } 9254377bea2SKamal Heib } 9264377bea2SKamal Heib 9272fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 9282fcb12dfSInbar Karmy strcpy(data + (idx++) * ETH_GSTRING_LEN, 9292fcb12dfSInbar Karmy pport_pfc_stall_stats_desc[i].format); 9302fcb12dfSInbar Karmy 9314377bea2SKamal Heib return idx; 9324377bea2SKamal Heib } 9334377bea2SKamal Heib 9344377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, 9354377bea2SKamal Heib u64 *data, 9364377bea2SKamal Heib int idx) 9374377bea2SKamal Heib { 9384377bea2SKamal Heib unsigned long pfc_combined; 9394377bea2SKamal Heib int i, prio; 9404377bea2SKamal Heib 9414377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 9424377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 9434377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9444377bea2SKamal Heib data[idx++] = 9454377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 9464377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 9474377bea2SKamal Heib } 9484377bea2SKamal Heib } 9494377bea2SKamal Heib 9504377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 9514377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9524377bea2SKamal Heib data[idx++] = 9534377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 9544377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 9554377bea2SKamal Heib } 9564377bea2SKamal Heib } 9574377bea2SKamal Heib 9582fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 9592fcb12dfSInbar Karmy data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 9602fcb12dfSInbar Karmy pport_pfc_stall_stats_desc, i); 9612fcb12dfSInbar Karmy 9624377bea2SKamal Heib return idx; 9634377bea2SKamal Heib } 9644377bea2SKamal Heib 965a8984281SKamal Heib static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv) 966a8984281SKamal Heib { 967a8984281SKamal Heib return mlx5e_grp_per_prio_traffic_get_num_stats(priv) + 968a8984281SKamal Heib mlx5e_grp_per_prio_pfc_get_num_stats(priv); 969a8984281SKamal Heib } 970a8984281SKamal Heib 971a8984281SKamal Heib static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data, 972a8984281SKamal Heib int idx) 973a8984281SKamal Heib { 974a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx); 975a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx); 976a8984281SKamal Heib return idx; 977a8984281SKamal Heib } 978a8984281SKamal Heib 979a8984281SKamal Heib static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data, 980a8984281SKamal Heib int idx) 981a8984281SKamal Heib { 982a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx); 983a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx); 984a8984281SKamal Heib return idx; 985a8984281SKamal Heib } 986a8984281SKamal Heib 98719386177SKamal Heib static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv) 98819386177SKamal Heib { 98919386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 99019386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 99119386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 99219386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 99319386177SKamal Heib int prio; 99419386177SKamal Heib void *out; 99519386177SKamal Heib 99619386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 99719386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 99819386177SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 99919386177SKamal Heib out = pstats->per_prio_counters[prio]; 100019386177SKamal Heib MLX5_SET(ppcnt_reg, in, prio_tc, prio); 100119386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, 100219386177SKamal Heib MLX5_REG_PPCNT, 0, 0); 100319386177SKamal Heib } 100419386177SKamal Heib } 100519386177SKamal Heib 10060e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_status_desc[] = { 10070e6f01a4SKamal Heib { "module_unplug", 8 }, 10080e6f01a4SKamal Heib }; 10090e6f01a4SKamal Heib 10100e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_error_desc[] = { 10110e6f01a4SKamal Heib { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */ 10120e6f01a4SKamal Heib { "module_high_temp", 48 }, /* high temperature */ 10130e6f01a4SKamal Heib { "module_bad_shorted", 56 }, /* bad or shorted cable/module */ 10140e6f01a4SKamal Heib }; 10150e6f01a4SKamal Heib 10160e6f01a4SKamal Heib #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc) 10170e6f01a4SKamal Heib #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc) 10180e6f01a4SKamal Heib 10190e6f01a4SKamal Heib static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv) 10200e6f01a4SKamal Heib { 10210e6f01a4SKamal Heib return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS; 10220e6f01a4SKamal Heib } 10230e6f01a4SKamal Heib 10240e6f01a4SKamal Heib static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data, 10250e6f01a4SKamal Heib int idx) 10260e6f01a4SKamal Heib { 10270e6f01a4SKamal Heib int i; 10280e6f01a4SKamal Heib 10290e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 10300e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format); 10310e6f01a4SKamal Heib 10320e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 10330e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format); 10340e6f01a4SKamal Heib 10350e6f01a4SKamal Heib return idx; 10360e6f01a4SKamal Heib } 10370e6f01a4SKamal Heib 10380e6f01a4SKamal Heib static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data, 10390e6f01a4SKamal Heib int idx) 10400e6f01a4SKamal Heib { 10410e6f01a4SKamal Heib struct mlx5_priv *mlx5_priv = &priv->mdev->priv; 10420e6f01a4SKamal Heib int i; 10430e6f01a4SKamal Heib 10440e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 10450e6f01a4SKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters, 10460e6f01a4SKamal Heib mlx5e_pme_status_desc, i); 10470e6f01a4SKamal Heib 10480e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 10490e6f01a4SKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters, 10500e6f01a4SKamal Heib mlx5e_pme_error_desc, i); 10510e6f01a4SKamal Heib 10520e6f01a4SKamal Heib return idx; 10530e6f01a4SKamal Heib } 10540e6f01a4SKamal Heib 1055e185d43fSKamal Heib static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv) 1056e185d43fSKamal Heib { 1057e185d43fSKamal Heib return mlx5e_ipsec_get_count(priv); 1058e185d43fSKamal Heib } 1059e185d43fSKamal Heib 1060e185d43fSKamal Heib static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data, 1061e185d43fSKamal Heib int idx) 1062e185d43fSKamal Heib { 1063e185d43fSKamal Heib return idx + mlx5e_ipsec_get_strings(priv, 1064e185d43fSKamal Heib data + idx * ETH_GSTRING_LEN); 1065e185d43fSKamal Heib } 1066e185d43fSKamal Heib 1067e185d43fSKamal Heib static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data, 1068e185d43fSKamal Heib int idx) 1069e185d43fSKamal Heib { 1070e185d43fSKamal Heib return idx + mlx5e_ipsec_get_stats(priv, data + idx); 1071e185d43fSKamal Heib } 1072e185d43fSKamal Heib 107319386177SKamal Heib static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv) 107419386177SKamal Heib { 107519386177SKamal Heib mlx5e_ipsec_update_stats(priv); 107619386177SKamal Heib } 107719386177SKamal Heib 10781fe85006SKamal Heib static const struct counter_desc rq_stats_desc[] = { 10791fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) }, 10801fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) }, 10811fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) }, 10821fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) }, 10831fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 10841fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) }, 10851fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) }, 10861fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) }, 10871fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) }, 10881fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) }, 10891fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) }, 1090f24686e8SGal Pressman { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) }, 10911fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) }, 10921fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) }, 10931fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 10941fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 10951fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 10961fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) }, 10971fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) }, 10981fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) }, 10991fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) }, 11001fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) }, 11011fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) }, 11021fe85006SKamal Heib }; 11031fe85006SKamal Heib 11041fe85006SKamal Heib static const struct counter_desc sq_stats_desc[] = { 11051fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) }, 11061fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) }, 11071fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) }, 11081fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) }, 11091fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) }, 11101fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) }, 11111fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) }, 11121fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) }, 1113f24686e8SGal Pressman { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) }, 11141fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) }, 11151fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) }, 11161fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) }, 11171fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) }, 11181fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) }, 11191fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) }, 112016cc14d8SEran Ben Elisha { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) }, 1121db75373cSEran Ben Elisha { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) }, 11221fe85006SKamal Heib }; 11231fe85006SKamal Heib 112457d689a8SEran Ben Elisha static const struct counter_desc ch_stats_desc[] = { 112557d689a8SEran Ben Elisha { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) }, 112657d689a8SEran Ben Elisha }; 112757d689a8SEran Ben Elisha 11281fe85006SKamal Heib #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc) 11291fe85006SKamal Heib #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc) 113057d689a8SEran Ben Elisha #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc) 11311fe85006SKamal Heib 11321fe85006SKamal Heib static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv) 11331fe85006SKamal Heib { 11341fe85006SKamal Heib return (NUM_RQ_STATS * priv->channels.num) + 113557d689a8SEran Ben Elisha (NUM_CH_STATS * priv->channels.num) + 11361fe85006SKamal Heib (NUM_SQ_STATS * priv->channels.num * priv->channels.params.num_tc); 11371fe85006SKamal Heib } 11381fe85006SKamal Heib 11391fe85006SKamal Heib static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data, 11401fe85006SKamal Heib int idx) 11411fe85006SKamal Heib { 11421fe85006SKamal Heib int i, j, tc; 11431fe85006SKamal Heib 11441fe85006SKamal Heib if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 11451fe85006SKamal Heib return idx; 11461fe85006SKamal Heib 11471fe85006SKamal Heib for (i = 0; i < priv->channels.num; i++) 114857d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 114957d689a8SEran Ben Elisha sprintf(data + (idx++) * ETH_GSTRING_LEN, 115057d689a8SEran Ben Elisha ch_stats_desc[j].format, i); 115157d689a8SEran Ben Elisha 115257d689a8SEran Ben Elisha for (i = 0; i < priv->channels.num; i++) 11531fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 11541fe85006SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i); 11551fe85006SKamal Heib 11561fe85006SKamal Heib for (tc = 0; tc < priv->channels.params.num_tc; tc++) 11571fe85006SKamal Heib for (i = 0; i < priv->channels.num; i++) 11581fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 11591fe85006SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 11601fe85006SKamal Heib sq_stats_desc[j].format, 11611fe85006SKamal Heib priv->channel_tc2txq[i][tc]); 11621fe85006SKamal Heib 11631fe85006SKamal Heib return idx; 11641fe85006SKamal Heib } 11651fe85006SKamal Heib 11661fe85006SKamal Heib static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data, 11671fe85006SKamal Heib int idx) 11681fe85006SKamal Heib { 11691fe85006SKamal Heib struct mlx5e_channels *channels = &priv->channels; 11701fe85006SKamal Heib int i, j, tc; 11711fe85006SKamal Heib 11721fe85006SKamal Heib if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 11731fe85006SKamal Heib return idx; 11741fe85006SKamal Heib 11751fe85006SKamal Heib for (i = 0; i < channels->num; i++) 117657d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 117757d689a8SEran Ben Elisha data[idx++] = 117857d689a8SEran Ben Elisha MLX5E_READ_CTR64_CPU(&channels->c[i]->stats, 117957d689a8SEran Ben Elisha ch_stats_desc, j); 118057d689a8SEran Ben Elisha 118157d689a8SEran Ben Elisha for (i = 0; i < channels->num; i++) 11821fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 11831fe85006SKamal Heib data[idx++] = 11841fe85006SKamal Heib MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats, 11851fe85006SKamal Heib rq_stats_desc, j); 11861fe85006SKamal Heib 11871fe85006SKamal Heib for (tc = 0; tc < priv->channels.params.num_tc; tc++) 11881fe85006SKamal Heib for (i = 0; i < channels->num; i++) 11891fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 11901fe85006SKamal Heib data[idx++] = 11911fe85006SKamal Heib MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats, 11921fe85006SKamal Heib sq_stats_desc, j); 11931fe85006SKamal Heib 11941fe85006SKamal Heib return idx; 11951fe85006SKamal Heib } 11961fe85006SKamal Heib 119719386177SKamal Heib /* The stats groups order is opposite to the update_stats() order calls */ 1198c0752f2bSKamal Heib const struct mlx5e_stats_grp mlx5e_stats_grps[] = { 1199c0752f2bSKamal Heib { 1200c0752f2bSKamal Heib .get_num_stats = mlx5e_grp_sw_get_num_stats, 1201c0752f2bSKamal Heib .fill_strings = mlx5e_grp_sw_fill_strings, 1202c0752f2bSKamal Heib .fill_stats = mlx5e_grp_sw_fill_stats, 120319386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 120419386177SKamal Heib .update_stats = mlx5e_grp_sw_update_stats, 1205fd8dcdb8SKamal Heib }, 1206fd8dcdb8SKamal Heib { 1207fd8dcdb8SKamal Heib .get_num_stats = mlx5e_grp_q_get_num_stats, 1208fd8dcdb8SKamal Heib .fill_strings = mlx5e_grp_q_fill_strings, 1209fd8dcdb8SKamal Heib .fill_stats = mlx5e_grp_q_fill_stats, 121019386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 121119386177SKamal Heib .update_stats = mlx5e_grp_q_update_stats, 1212fd8dcdb8SKamal Heib }, 121340cab9f1SKamal Heib { 12145c298143SMoshe Shemesh .get_num_stats = mlx5e_grp_vnic_env_get_num_stats, 12155c298143SMoshe Shemesh .fill_strings = mlx5e_grp_vnic_env_fill_strings, 12165c298143SMoshe Shemesh .fill_stats = mlx5e_grp_vnic_env_fill_stats, 12175c298143SMoshe Shemesh .update_stats = mlx5e_grp_vnic_env_update_stats, 12185c298143SMoshe Shemesh }, 12195c298143SMoshe Shemesh { 122040cab9f1SKamal Heib .get_num_stats = mlx5e_grp_vport_get_num_stats, 122140cab9f1SKamal Heib .fill_strings = mlx5e_grp_vport_fill_strings, 122240cab9f1SKamal Heib .fill_stats = mlx5e_grp_vport_fill_stats, 122319386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 122419386177SKamal Heib .update_stats = mlx5e_grp_vport_update_stats, 122540cab9f1SKamal Heib }, 12266e6ef814SKamal Heib { 12276e6ef814SKamal Heib .get_num_stats = mlx5e_grp_802_3_get_num_stats, 12286e6ef814SKamal Heib .fill_strings = mlx5e_grp_802_3_fill_strings, 12296e6ef814SKamal Heib .fill_stats = mlx5e_grp_802_3_fill_stats, 123019386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 123119386177SKamal Heib .update_stats = mlx5e_grp_802_3_update_stats, 12326e6ef814SKamal Heib }, 1233fc8e64a3SKamal Heib { 1234fc8e64a3SKamal Heib .get_num_stats = mlx5e_grp_2863_get_num_stats, 1235fc8e64a3SKamal Heib .fill_strings = mlx5e_grp_2863_fill_strings, 1236fc8e64a3SKamal Heib .fill_stats = mlx5e_grp_2863_fill_stats, 123719386177SKamal Heib .update_stats = mlx5e_grp_2863_update_stats, 1238fc8e64a3SKamal Heib }, 1239e0e0def9SKamal Heib { 1240e0e0def9SKamal Heib .get_num_stats = mlx5e_grp_2819_get_num_stats, 1241e0e0def9SKamal Heib .fill_strings = mlx5e_grp_2819_fill_strings, 1242e0e0def9SKamal Heib .fill_stats = mlx5e_grp_2819_fill_stats, 124319386177SKamal Heib .update_stats = mlx5e_grp_2819_update_stats, 1244e0e0def9SKamal Heib }, 12452e4df0b2SKamal Heib { 12462e4df0b2SKamal Heib .get_num_stats = mlx5e_grp_phy_get_num_stats, 12472e4df0b2SKamal Heib .fill_strings = mlx5e_grp_phy_fill_strings, 12482e4df0b2SKamal Heib .fill_stats = mlx5e_grp_phy_fill_stats, 124919386177SKamal Heib .update_stats = mlx5e_grp_phy_update_stats, 12502e4df0b2SKamal Heib }, 12513488bd4cSKamal Heib { 12523488bd4cSKamal Heib .get_num_stats = mlx5e_grp_eth_ext_get_num_stats, 12533488bd4cSKamal Heib .fill_strings = mlx5e_grp_eth_ext_fill_strings, 12543488bd4cSKamal Heib .fill_stats = mlx5e_grp_eth_ext_fill_stats, 125519386177SKamal Heib .update_stats = mlx5e_grp_eth_ext_update_stats, 12569fd2b5f1SKamal Heib }, 12579fd2b5f1SKamal Heib { 12589fd2b5f1SKamal Heib .get_num_stats = mlx5e_grp_pcie_get_num_stats, 12599fd2b5f1SKamal Heib .fill_strings = mlx5e_grp_pcie_fill_strings, 12609fd2b5f1SKamal Heib .fill_stats = mlx5e_grp_pcie_fill_stats, 126119386177SKamal Heib .update_stats = mlx5e_grp_pcie_update_stats, 12629fd2b5f1SKamal Heib }, 1263e6000651SKamal Heib { 1264a8984281SKamal Heib .get_num_stats = mlx5e_grp_per_prio_get_num_stats, 1265a8984281SKamal Heib .fill_strings = mlx5e_grp_per_prio_fill_strings, 1266a8984281SKamal Heib .fill_stats = mlx5e_grp_per_prio_fill_stats, 126719386177SKamal Heib .update_stats = mlx5e_grp_per_prio_update_stats, 12684377bea2SKamal Heib }, 12690e6f01a4SKamal Heib { 12700e6f01a4SKamal Heib .get_num_stats = mlx5e_grp_pme_get_num_stats, 12710e6f01a4SKamal Heib .fill_strings = mlx5e_grp_pme_fill_strings, 12720e6f01a4SKamal Heib .fill_stats = mlx5e_grp_pme_fill_stats, 12730e6f01a4SKamal Heib }, 1274e185d43fSKamal Heib { 1275e185d43fSKamal Heib .get_num_stats = mlx5e_grp_ipsec_get_num_stats, 1276e185d43fSKamal Heib .fill_strings = mlx5e_grp_ipsec_fill_strings, 1277e185d43fSKamal Heib .fill_stats = mlx5e_grp_ipsec_fill_stats, 127819386177SKamal Heib .update_stats = mlx5e_grp_ipsec_update_stats, 1279e185d43fSKamal Heib }, 12801fe85006SKamal Heib { 12811fe85006SKamal Heib .get_num_stats = mlx5e_grp_channels_get_num_stats, 12821fe85006SKamal Heib .fill_strings = mlx5e_grp_channels_fill_strings, 12831fe85006SKamal Heib .fill_stats = mlx5e_grp_channels_fill_stats, 12841fe85006SKamal Heib } 1285c0752f2bSKamal Heib }; 1286c0752f2bSKamal Heib 1287c0752f2bSKamal Heib const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps); 1288