1c0752f2bSKamal Heib /* 2c0752f2bSKamal Heib * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3c0752f2bSKamal Heib * 4c0752f2bSKamal Heib * This software is available to you under a choice of one of two 5c0752f2bSKamal Heib * licenses. You may choose to be licensed under the terms of the GNU 6c0752f2bSKamal Heib * General Public License (GPL) Version 2, available from the file 7c0752f2bSKamal Heib * COPYING in the main directory of this source tree, or the 8c0752f2bSKamal Heib * OpenIB.org BSD license below: 9c0752f2bSKamal Heib * 10c0752f2bSKamal Heib * Redistribution and use in source and binary forms, with or 11c0752f2bSKamal Heib * without modification, are permitted provided that the following 12c0752f2bSKamal Heib * conditions are met: 13c0752f2bSKamal Heib * 14c0752f2bSKamal Heib * - Redistributions of source code must retain the above 15c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 16c0752f2bSKamal Heib * disclaimer. 17c0752f2bSKamal Heib * 18c0752f2bSKamal Heib * - Redistributions in binary form must reproduce the above 19c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 20c0752f2bSKamal Heib * disclaimer in the documentation and/or other materials 21c0752f2bSKamal Heib * provided with the distribution. 22c0752f2bSKamal Heib * 23c0752f2bSKamal Heib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24c0752f2bSKamal Heib * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25c0752f2bSKamal Heib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26c0752f2bSKamal Heib * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27c0752f2bSKamal Heib * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28c0752f2bSKamal Heib * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29c0752f2bSKamal Heib * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30c0752f2bSKamal Heib * SOFTWARE. 31c0752f2bSKamal Heib */ 32c0752f2bSKamal Heib 33c0752f2bSKamal Heib #include "en.h" 34e185d43fSKamal Heib #include "en_accel/ipsec.h" 3543585a41SIlya Lesokhin #include "en_accel/tls.h" 36c0752f2bSKamal Heib 37c0752f2bSKamal Heib static const struct counter_desc sw_stats_desc[] = { 38c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) }, 39c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) }, 40c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) }, 41c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) }, 42c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) }, 43c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) }, 44c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) }, 45c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) }, 46f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) }, 472ad9ecdbSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) }, 48bf239741SIlya Lesokhin 49bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 50bf239741SIlya Lesokhin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) }, 51bf239741SIlya Lesokhin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) }, 52bf239741SIlya Lesokhin #endif 53bf239741SIlya Lesokhin 54c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) }, 55c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) }, 56f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) }, 57c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) }, 58c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) }, 59c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) }, 60c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) }, 61c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) }, 6286690b4bSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) }, 63890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) }, 64c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) }, 65890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) }, 66890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) }, 67c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) }, 68c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) }, 69c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) }, 70c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) }, 71c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) }, 72c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) }, 73db75373cSEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) }, 7486155656STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) }, 75f65a59ffSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) }, 76bc5a7ccdSBoris Pismenny { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_udp_seg_rem) }, 77f65a59ffSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) }, 78c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) }, 79b71ba6b4STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) }, 80b71ba6b4STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) }, 81c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) }, 82c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 83c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 84c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) }, 85c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) }, 86c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) }, 87c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) }, 88c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) }, 89c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) }, 90dc983f0eSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) }, 91a1bf74dcSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) }, 922d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) }, 932d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) }, 942d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) }, 9557d689a8SEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) }, 96c0752f2bSKamal Heib }; 97c0752f2bSKamal Heib 98c0752f2bSKamal Heib #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc) 99c0752f2bSKamal Heib 100c0752f2bSKamal Heib static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv) 101c0752f2bSKamal Heib { 102c0752f2bSKamal Heib return NUM_SW_COUNTERS; 103c0752f2bSKamal Heib } 104c0752f2bSKamal Heib 105c0752f2bSKamal Heib static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 106c0752f2bSKamal Heib { 107c0752f2bSKamal Heib int i; 108c0752f2bSKamal Heib 109c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 110c0752f2bSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format); 111c0752f2bSKamal Heib return idx; 112c0752f2bSKamal Heib } 113c0752f2bSKamal Heib 114c0752f2bSKamal Heib static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 115c0752f2bSKamal Heib { 116c0752f2bSKamal Heib int i; 117c0752f2bSKamal Heib 118c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 119c0752f2bSKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i); 120c0752f2bSKamal Heib return idx; 121c0752f2bSKamal Heib } 122c0752f2bSKamal Heib 123868a01a2SShalom Lagziel void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv) 12419386177SKamal Heib { 12519386177SKamal Heib struct mlx5e_sw_stats temp, *s = &temp; 12605909babSEran Ben Elisha int i; 12719386177SKamal Heib 12819386177SKamal Heib memset(s, 0, sizeof(*s)); 12919386177SKamal Heib 13005909babSEran Ben Elisha for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) { 13105909babSEran Ben Elisha struct mlx5e_channel_stats *channel_stats = 13205909babSEran Ben Elisha &priv->channel_stats[i]; 133890388adSTariq Toukan struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq; 13405909babSEran Ben Elisha struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 13505909babSEran Ben Elisha struct mlx5e_ch_stats *ch_stats = &channel_stats->ch; 13605909babSEran Ben Elisha int j; 13719386177SKamal Heib 13819386177SKamal Heib s->rx_packets += rq_stats->packets; 13919386177SKamal Heib s->rx_bytes += rq_stats->bytes; 14019386177SKamal Heib s->rx_lro_packets += rq_stats->lro_packets; 14119386177SKamal Heib s->rx_lro_bytes += rq_stats->lro_bytes; 14219386177SKamal Heib s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets; 14319386177SKamal Heib s->rx_csum_none += rq_stats->csum_none; 14419386177SKamal Heib s->rx_csum_complete += rq_stats->csum_complete; 14519386177SKamal Heib s->rx_csum_unnecessary += rq_stats->csum_unnecessary; 14619386177SKamal Heib s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; 14719386177SKamal Heib s->rx_xdp_drop += rq_stats->xdp_drop; 14886690b4bSTariq Toukan s->rx_xdp_redirect += rq_stats->xdp_redirect; 149890388adSTariq Toukan s->rx_xdp_tx_xmit += xdpsq_stats->xmit; 150890388adSTariq Toukan s->rx_xdp_tx_full += xdpsq_stats->full; 151890388adSTariq Toukan s->rx_xdp_tx_err += xdpsq_stats->err; 152890388adSTariq Toukan s->rx_xdp_tx_cqe += xdpsq_stats->cqes; 15319386177SKamal Heib s->rx_wqe_err += rq_stats->wqe_err; 154b71ba6b4STariq Toukan s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes; 155b71ba6b4STariq Toukan s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides; 15619386177SKamal Heib s->rx_buff_alloc_err += rq_stats->buff_alloc_err; 15719386177SKamal Heib s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; 15819386177SKamal Heib s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; 15919386177SKamal Heib s->rx_page_reuse += rq_stats->page_reuse; 16019386177SKamal Heib s->rx_cache_reuse += rq_stats->cache_reuse; 16119386177SKamal Heib s->rx_cache_full += rq_stats->cache_full; 16219386177SKamal Heib s->rx_cache_empty += rq_stats->cache_empty; 16319386177SKamal Heib s->rx_cache_busy += rq_stats->cache_busy; 16419386177SKamal Heib s->rx_cache_waive += rq_stats->cache_waive; 165dc983f0eSTariq Toukan s->rx_congst_umr += rq_stats->congst_umr; 166a1bf74dcSTariq Toukan s->ch_events += ch_stats->events; 1672d7103c8STariq Toukan s->ch_poll += ch_stats->poll; 1682d7103c8STariq Toukan s->ch_arm += ch_stats->arm; 1692d7103c8STariq Toukan s->ch_aff_change += ch_stats->aff_change; 17019386177SKamal Heib s->ch_eq_rearm += ch_stats->eq_rearm; 17119386177SKamal Heib 17205909babSEran Ben Elisha for (j = 0; j < priv->max_opened_tc; j++) { 17305909babSEran Ben Elisha struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 17419386177SKamal Heib 17519386177SKamal Heib s->tx_packets += sq_stats->packets; 17619386177SKamal Heib s->tx_bytes += sq_stats->bytes; 17719386177SKamal Heib s->tx_tso_packets += sq_stats->tso_packets; 17819386177SKamal Heib s->tx_tso_bytes += sq_stats->tso_bytes; 17919386177SKamal Heib s->tx_tso_inner_packets += sq_stats->tso_inner_packets; 18019386177SKamal Heib s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; 18119386177SKamal Heib s->tx_added_vlan_packets += sq_stats->added_vlan_packets; 1822ad9ecdbSTariq Toukan s->tx_nop += sq_stats->nop; 18319386177SKamal Heib s->tx_queue_stopped += sq_stats->stopped; 18419386177SKamal Heib s->tx_queue_wake += sq_stats->wake; 185bc5a7ccdSBoris Pismenny s->tx_udp_seg_rem += sq_stats->udp_seg_rem; 18619386177SKamal Heib s->tx_queue_dropped += sq_stats->dropped; 18716cc14d8SEran Ben Elisha s->tx_cqe_err += sq_stats->cqe_err; 188db75373cSEran Ben Elisha s->tx_recover += sq_stats->recover; 18919386177SKamal Heib s->tx_xmit_more += sq_stats->xmit_more; 19019386177SKamal Heib s->tx_csum_partial_inner += sq_stats->csum_partial_inner; 19119386177SKamal Heib s->tx_csum_none += sq_stats->csum_none; 19219386177SKamal Heib s->tx_csum_partial += sq_stats->csum_partial; 193bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 194bf239741SIlya Lesokhin s->tx_tls_ooo += sq_stats->tls_ooo; 195bf239741SIlya Lesokhin s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes; 196bf239741SIlya Lesokhin #endif 19786155656STariq Toukan s->tx_cqes += sq_stats->cqes; 19819386177SKamal Heib } 19919386177SKamal Heib } 20019386177SKamal Heib 20119386177SKamal Heib memcpy(&priv->stats.sw, s, sizeof(*s)); 20219386177SKamal Heib } 20319386177SKamal Heib 204fd8dcdb8SKamal Heib static const struct counter_desc q_stats_desc[] = { 205fd8dcdb8SKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) }, 206fd8dcdb8SKamal Heib }; 207fd8dcdb8SKamal Heib 2087cbaf9a3SMoshe Shemesh static const struct counter_desc drop_rq_stats_desc[] = { 2097cbaf9a3SMoshe Shemesh { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) }, 2107cbaf9a3SMoshe Shemesh }; 2117cbaf9a3SMoshe Shemesh 212fd8dcdb8SKamal Heib #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc) 2137cbaf9a3SMoshe Shemesh #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc) 214fd8dcdb8SKamal Heib 215fd8dcdb8SKamal Heib static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv) 216fd8dcdb8SKamal Heib { 2177cbaf9a3SMoshe Shemesh int num_stats = 0; 2187cbaf9a3SMoshe Shemesh 2197cbaf9a3SMoshe Shemesh if (priv->q_counter) 2207cbaf9a3SMoshe Shemesh num_stats += NUM_Q_COUNTERS; 2217cbaf9a3SMoshe Shemesh 2227cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter) 2237cbaf9a3SMoshe Shemesh num_stats += NUM_DROP_RQ_COUNTERS; 2247cbaf9a3SMoshe Shemesh 2257cbaf9a3SMoshe Shemesh return num_stats; 226fd8dcdb8SKamal Heib } 227fd8dcdb8SKamal Heib 228fd8dcdb8SKamal Heib static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 229fd8dcdb8SKamal Heib { 230fd8dcdb8SKamal Heib int i; 231fd8dcdb8SKamal Heib 232fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 2337cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2347cbaf9a3SMoshe Shemesh q_stats_desc[i].format); 2357cbaf9a3SMoshe Shemesh 2367cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 2377cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2387cbaf9a3SMoshe Shemesh drop_rq_stats_desc[i].format); 2397cbaf9a3SMoshe Shemesh 240fd8dcdb8SKamal Heib return idx; 241fd8dcdb8SKamal Heib } 242fd8dcdb8SKamal Heib 243fd8dcdb8SKamal Heib static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 244fd8dcdb8SKamal Heib { 245fd8dcdb8SKamal Heib int i; 246fd8dcdb8SKamal Heib 247fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 2487cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 2497cbaf9a3SMoshe Shemesh q_stats_desc, i); 2507cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 2517cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 2527cbaf9a3SMoshe Shemesh drop_rq_stats_desc, i); 253fd8dcdb8SKamal Heib return idx; 254fd8dcdb8SKamal Heib } 255fd8dcdb8SKamal Heib 25619386177SKamal Heib static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv) 25719386177SKamal Heib { 25819386177SKamal Heib struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; 25919386177SKamal Heib u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; 26019386177SKamal Heib 2617cbaf9a3SMoshe Shemesh if (priv->q_counter && 2627cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, 2637cbaf9a3SMoshe Shemesh sizeof(out))) 2647cbaf9a3SMoshe Shemesh qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, 2657cbaf9a3SMoshe Shemesh out, out_of_buffer); 2667cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter && 2677cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0, 2687cbaf9a3SMoshe Shemesh out, sizeof(out))) 2697cbaf9a3SMoshe Shemesh qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out, 2707cbaf9a3SMoshe Shemesh out_of_buffer); 27119386177SKamal Heib } 27219386177SKamal Heib 2735c298143SMoshe Shemesh #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c) 2745c298143SMoshe Shemesh static const struct counter_desc vnic_env_stats_desc[] = { 2755c298143SMoshe Shemesh { "rx_steer_missed_packets", 2765c298143SMoshe Shemesh VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) }, 2775c298143SMoshe Shemesh }; 2785c298143SMoshe Shemesh 2795c298143SMoshe Shemesh #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc) 2805c298143SMoshe Shemesh 2815c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv) 2825c298143SMoshe Shemesh { 2835c298143SMoshe Shemesh return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ? 2845c298143SMoshe Shemesh NUM_VNIC_ENV_COUNTERS : 0; 2855c298143SMoshe Shemesh } 2865c298143SMoshe Shemesh 2875c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data, 2885c298143SMoshe Shemesh int idx) 2895c298143SMoshe Shemesh { 2905c298143SMoshe Shemesh int i; 2915c298143SMoshe Shemesh 2925c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 2935c298143SMoshe Shemesh return idx; 2945c298143SMoshe Shemesh 2955c298143SMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 2965c298143SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 2975c298143SMoshe Shemesh vnic_env_stats_desc[i].format); 2985c298143SMoshe Shemesh return idx; 2995c298143SMoshe Shemesh } 3005c298143SMoshe Shemesh 3015c298143SMoshe Shemesh static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data, 3025c298143SMoshe Shemesh int idx) 3035c298143SMoshe Shemesh { 3045c298143SMoshe Shemesh int i; 3055c298143SMoshe Shemesh 3065c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 3075c298143SMoshe Shemesh return idx; 3085c298143SMoshe Shemesh 3095c298143SMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 3105c298143SMoshe Shemesh data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out, 3115c298143SMoshe Shemesh vnic_env_stats_desc, i); 3125c298143SMoshe Shemesh return idx; 3135c298143SMoshe Shemesh } 3145c298143SMoshe Shemesh 3155c298143SMoshe Shemesh static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 3165c298143SMoshe Shemesh { 3175c298143SMoshe Shemesh u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out; 3185c298143SMoshe Shemesh int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out); 3195c298143SMoshe Shemesh u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; 3205c298143SMoshe Shemesh struct mlx5_core_dev *mdev = priv->mdev; 3215c298143SMoshe Shemesh 3225c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 3235c298143SMoshe Shemesh return; 3245c298143SMoshe Shemesh 3255c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, opcode, 3265c298143SMoshe Shemesh MLX5_CMD_OP_QUERY_VNIC_ENV); 3275c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, op_mod, 0); 3285c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, other_vport, 0); 3295c298143SMoshe Shemesh mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 3305c298143SMoshe Shemesh } 3315c298143SMoshe Shemesh 33240cab9f1SKamal Heib #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) 33340cab9f1SKamal Heib static const struct counter_desc vport_stats_desc[] = { 33440cab9f1SKamal Heib { "rx_vport_unicast_packets", 33540cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.packets) }, 33640cab9f1SKamal Heib { "rx_vport_unicast_bytes", 33740cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.octets) }, 33840cab9f1SKamal Heib { "tx_vport_unicast_packets", 33940cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) }, 34040cab9f1SKamal Heib { "tx_vport_unicast_bytes", 34140cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) }, 34240cab9f1SKamal Heib { "rx_vport_multicast_packets", 34340cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.packets) }, 34440cab9f1SKamal Heib { "rx_vport_multicast_bytes", 34540cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.octets) }, 34640cab9f1SKamal Heib { "tx_vport_multicast_packets", 34740cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) }, 34840cab9f1SKamal Heib { "tx_vport_multicast_bytes", 34940cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) }, 35040cab9f1SKamal Heib { "rx_vport_broadcast_packets", 35140cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.packets) }, 35240cab9f1SKamal Heib { "rx_vport_broadcast_bytes", 35340cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.octets) }, 35440cab9f1SKamal Heib { "tx_vport_broadcast_packets", 35540cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) }, 35640cab9f1SKamal Heib { "tx_vport_broadcast_bytes", 35740cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) }, 35840cab9f1SKamal Heib { "rx_vport_rdma_unicast_packets", 35940cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.packets) }, 36040cab9f1SKamal Heib { "rx_vport_rdma_unicast_bytes", 36140cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.octets) }, 36240cab9f1SKamal Heib { "tx_vport_rdma_unicast_packets", 36340cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) }, 36440cab9f1SKamal Heib { "tx_vport_rdma_unicast_bytes", 36540cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) }, 36640cab9f1SKamal Heib { "rx_vport_rdma_multicast_packets", 36740cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.packets) }, 36840cab9f1SKamal Heib { "rx_vport_rdma_multicast_bytes", 36940cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.octets) }, 37040cab9f1SKamal Heib { "tx_vport_rdma_multicast_packets", 37140cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) }, 37240cab9f1SKamal Heib { "tx_vport_rdma_multicast_bytes", 37340cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) }, 37440cab9f1SKamal Heib }; 37540cab9f1SKamal Heib 37640cab9f1SKamal Heib #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc) 37740cab9f1SKamal Heib 37840cab9f1SKamal Heib static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv) 37940cab9f1SKamal Heib { 38040cab9f1SKamal Heib return NUM_VPORT_COUNTERS; 38140cab9f1SKamal Heib } 38240cab9f1SKamal Heib 38340cab9f1SKamal Heib static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data, 38440cab9f1SKamal Heib int idx) 38540cab9f1SKamal Heib { 38640cab9f1SKamal Heib int i; 38740cab9f1SKamal Heib 38840cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 38940cab9f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format); 39040cab9f1SKamal Heib return idx; 39140cab9f1SKamal Heib } 39240cab9f1SKamal Heib 39340cab9f1SKamal Heib static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data, 39440cab9f1SKamal Heib int idx) 39540cab9f1SKamal Heib { 39640cab9f1SKamal Heib int i; 39740cab9f1SKamal Heib 39840cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 39940cab9f1SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out, 40040cab9f1SKamal Heib vport_stats_desc, i); 40140cab9f1SKamal Heib return idx; 40240cab9f1SKamal Heib } 40340cab9f1SKamal Heib 40419386177SKamal Heib static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv) 40519386177SKamal Heib { 40619386177SKamal Heib int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 40719386177SKamal Heib u32 *out = (u32 *)priv->stats.vport.query_vport_out; 40819386177SKamal Heib u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; 40919386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 41019386177SKamal Heib 41119386177SKamal Heib MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER); 41219386177SKamal Heib MLX5_SET(query_vport_counter_in, in, op_mod, 0); 41319386177SKamal Heib MLX5_SET(query_vport_counter_in, in, other_vport, 0); 41419386177SKamal Heib mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 41519386177SKamal Heib } 41619386177SKamal Heib 4176e6ef814SKamal Heib #define PPORT_802_3_OFF(c) \ 4186e6ef814SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 4196e6ef814SKamal Heib counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 4206e6ef814SKamal Heib static const struct counter_desc pport_802_3_stats_desc[] = { 4216e6ef814SKamal Heib { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) }, 4226e6ef814SKamal Heib { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) }, 4236e6ef814SKamal Heib { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) }, 4246e6ef814SKamal Heib { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) }, 4256e6ef814SKamal Heib { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) }, 4266e6ef814SKamal Heib { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) }, 4276e6ef814SKamal Heib { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) }, 4286e6ef814SKamal Heib { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) }, 4296e6ef814SKamal Heib { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) }, 4306e6ef814SKamal Heib { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) }, 4316e6ef814SKamal Heib { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) }, 4326e6ef814SKamal Heib { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) }, 4336e6ef814SKamal Heib { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) }, 4346e6ef814SKamal Heib { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) }, 4356e6ef814SKamal Heib { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) }, 4366e6ef814SKamal Heib { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) }, 4376e6ef814SKamal Heib { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) }, 4386e6ef814SKamal Heib { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) }, 4396e6ef814SKamal Heib }; 4406e6ef814SKamal Heib 4416e6ef814SKamal Heib #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc) 4426e6ef814SKamal Heib 4436e6ef814SKamal Heib static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv) 4446e6ef814SKamal Heib { 4456e6ef814SKamal Heib return NUM_PPORT_802_3_COUNTERS; 4466e6ef814SKamal Heib } 4476e6ef814SKamal Heib 4486e6ef814SKamal Heib static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data, 4496e6ef814SKamal Heib int idx) 4506e6ef814SKamal Heib { 4516e6ef814SKamal Heib int i; 4526e6ef814SKamal Heib 4536e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 4546e6ef814SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format); 4556e6ef814SKamal Heib return idx; 4566e6ef814SKamal Heib } 4576e6ef814SKamal Heib 4586e6ef814SKamal Heib static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data, 4596e6ef814SKamal Heib int idx) 4606e6ef814SKamal Heib { 4616e6ef814SKamal Heib int i; 4626e6ef814SKamal Heib 4636e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 4646e6ef814SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters, 4656e6ef814SKamal Heib pport_802_3_stats_desc, i); 4666e6ef814SKamal Heib return idx; 4676e6ef814SKamal Heib } 4686e6ef814SKamal Heib 46919386177SKamal Heib static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv) 47019386177SKamal Heib { 47119386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 47219386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 47319386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 47419386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 47519386177SKamal Heib void *out; 47619386177SKamal Heib 47719386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 47819386177SKamal Heib out = pstats->IEEE_802_3_counters; 47919386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 48019386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 48119386177SKamal Heib } 48219386177SKamal Heib 483fc8e64a3SKamal Heib #define PPORT_2863_OFF(c) \ 484fc8e64a3SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 485fc8e64a3SKamal Heib counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 486fc8e64a3SKamal Heib static const struct counter_desc pport_2863_stats_desc[] = { 487fc8e64a3SKamal Heib { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) }, 488fc8e64a3SKamal Heib { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) }, 489fc8e64a3SKamal Heib { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) }, 490fc8e64a3SKamal Heib }; 491fc8e64a3SKamal Heib 492fc8e64a3SKamal Heib #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc) 493fc8e64a3SKamal Heib 494fc8e64a3SKamal Heib static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv) 495fc8e64a3SKamal Heib { 496fc8e64a3SKamal Heib return NUM_PPORT_2863_COUNTERS; 497fc8e64a3SKamal Heib } 498fc8e64a3SKamal Heib 499fc8e64a3SKamal Heib static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data, 500fc8e64a3SKamal Heib int idx) 501fc8e64a3SKamal Heib { 502fc8e64a3SKamal Heib int i; 503fc8e64a3SKamal Heib 504fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 505fc8e64a3SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format); 506fc8e64a3SKamal Heib return idx; 507fc8e64a3SKamal Heib } 508fc8e64a3SKamal Heib 509fc8e64a3SKamal Heib static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data, 510fc8e64a3SKamal Heib int idx) 511fc8e64a3SKamal Heib { 512fc8e64a3SKamal Heib int i; 513fc8e64a3SKamal Heib 514fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 515fc8e64a3SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters, 516fc8e64a3SKamal Heib pport_2863_stats_desc, i); 517fc8e64a3SKamal Heib return idx; 518fc8e64a3SKamal Heib } 519fc8e64a3SKamal Heib 52019386177SKamal Heib static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv) 52119386177SKamal Heib { 52219386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 52319386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 52419386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 52519386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 52619386177SKamal Heib void *out; 52719386177SKamal Heib 52819386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 52919386177SKamal Heib out = pstats->RFC_2863_counters; 53019386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 53119386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 53219386177SKamal Heib } 53319386177SKamal Heib 534e0e0def9SKamal Heib #define PPORT_2819_OFF(c) \ 535e0e0def9SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 536e0e0def9SKamal Heib counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 537e0e0def9SKamal Heib static const struct counter_desc pport_2819_stats_desc[] = { 538e0e0def9SKamal Heib { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) }, 539e0e0def9SKamal Heib { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) }, 540e0e0def9SKamal Heib { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) }, 541e0e0def9SKamal Heib { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) }, 542e0e0def9SKamal Heib { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) }, 543e0e0def9SKamal Heib { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) }, 544e0e0def9SKamal Heib { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) }, 545e0e0def9SKamal Heib { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) }, 546e0e0def9SKamal Heib { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) }, 547e0e0def9SKamal Heib { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) }, 548e0e0def9SKamal Heib { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) }, 549e0e0def9SKamal Heib { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) }, 550e0e0def9SKamal Heib { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) }, 551e0e0def9SKamal Heib }; 552e0e0def9SKamal Heib 553e0e0def9SKamal Heib #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc) 554e0e0def9SKamal Heib 555e0e0def9SKamal Heib static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv) 556e0e0def9SKamal Heib { 557e0e0def9SKamal Heib return NUM_PPORT_2819_COUNTERS; 558e0e0def9SKamal Heib } 559e0e0def9SKamal Heib 560e0e0def9SKamal Heib static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data, 561e0e0def9SKamal Heib int idx) 562e0e0def9SKamal Heib { 563e0e0def9SKamal Heib int i; 564e0e0def9SKamal Heib 565e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 566e0e0def9SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format); 567e0e0def9SKamal Heib return idx; 568e0e0def9SKamal Heib } 569e0e0def9SKamal Heib 570e0e0def9SKamal Heib static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data, 571e0e0def9SKamal Heib int idx) 572e0e0def9SKamal Heib { 573e0e0def9SKamal Heib int i; 574e0e0def9SKamal Heib 575e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 576e0e0def9SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters, 577e0e0def9SKamal Heib pport_2819_stats_desc, i); 578e0e0def9SKamal Heib return idx; 579e0e0def9SKamal Heib } 580e0e0def9SKamal Heib 58119386177SKamal Heib static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv) 58219386177SKamal Heib { 58319386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 58419386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 58519386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 58619386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 58719386177SKamal Heib void *out; 58819386177SKamal Heib 58919386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 59019386177SKamal Heib out = pstats->RFC_2819_counters; 59119386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 59219386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 59319386177SKamal Heib } 59419386177SKamal Heib 5952e4df0b2SKamal Heib #define PPORT_PHY_STATISTICAL_OFF(c) \ 5962e4df0b2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 5972e4df0b2SKamal Heib counter_set.phys_layer_statistical_cntrs.c##_high) 5982e4df0b2SKamal Heib static const struct counter_desc pport_phy_statistical_stats_desc[] = { 5992e4df0b2SKamal Heib { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) }, 6002e4df0b2SKamal Heib { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) }, 6012e4df0b2SKamal Heib }; 6022e4df0b2SKamal Heib 6036ab75516SSaeed Mahameed #define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc) 6042e4df0b2SKamal Heib 6052e4df0b2SKamal Heib static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv) 6062e4df0b2SKamal Heib { 6076ab75516SSaeed Mahameed /* "1" for link_down_events special counter */ 6082e4df0b2SKamal Heib return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ? 6096ab75516SSaeed Mahameed NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1; 6102e4df0b2SKamal Heib } 6112e4df0b2SKamal Heib 6122e4df0b2SKamal Heib static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data, 6132e4df0b2SKamal Heib int idx) 6142e4df0b2SKamal Heib { 6152e4df0b2SKamal Heib int i; 6162e4df0b2SKamal Heib 6176ab75516SSaeed Mahameed strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy"); 6186ab75516SSaeed Mahameed 6196ab75516SSaeed Mahameed if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group)) 6206ab75516SSaeed Mahameed return idx; 6216ab75516SSaeed Mahameed 6226ab75516SSaeed Mahameed for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 6232e4df0b2SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 6242e4df0b2SKamal Heib pport_phy_statistical_stats_desc[i].format); 6252e4df0b2SKamal Heib return idx; 6262e4df0b2SKamal Heib } 6272e4df0b2SKamal Heib 6282e4df0b2SKamal Heib static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 6292e4df0b2SKamal Heib { 6302e4df0b2SKamal Heib int i; 6312e4df0b2SKamal Heib 6326ab75516SSaeed Mahameed /* link_down_events_phy has special handling since it is not stored in __be64 format */ 6336ab75516SSaeed Mahameed data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, 6346ab75516SSaeed Mahameed counter_set.phys_layer_cntrs.link_down_events); 6356ab75516SSaeed Mahameed 6366ab75516SSaeed Mahameed if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group)) 6376ab75516SSaeed Mahameed return idx; 6386ab75516SSaeed Mahameed 6396ab75516SSaeed Mahameed for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 6402e4df0b2SKamal Heib data[idx++] = 6412e4df0b2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 6422e4df0b2SKamal Heib pport_phy_statistical_stats_desc, i); 6432e4df0b2SKamal Heib return idx; 6442e4df0b2SKamal Heib } 6452e4df0b2SKamal Heib 64619386177SKamal Heib static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv) 64719386177SKamal Heib { 64819386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 64919386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 65019386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 65119386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 65219386177SKamal Heib void *out; 65319386177SKamal Heib 65419386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 65519386177SKamal Heib out = pstats->phy_counters; 65619386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 65719386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 65819386177SKamal Heib 65919386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 66019386177SKamal Heib return; 66119386177SKamal Heib 66219386177SKamal Heib out = pstats->phy_statistical_counters; 66319386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 66419386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 66519386177SKamal Heib } 66619386177SKamal Heib 6673488bd4cSKamal Heib #define PPORT_ETH_EXT_OFF(c) \ 6683488bd4cSKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 6693488bd4cSKamal Heib counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 6703488bd4cSKamal Heib static const struct counter_desc pport_eth_ext_stats_desc[] = { 6713488bd4cSKamal Heib { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) }, 6723488bd4cSKamal Heib }; 6733488bd4cSKamal Heib 6743488bd4cSKamal Heib #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc) 6753488bd4cSKamal Heib 6763488bd4cSKamal Heib static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv) 6773488bd4cSKamal Heib { 6783488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 6793488bd4cSKamal Heib return NUM_PPORT_ETH_EXT_COUNTERS; 6803488bd4cSKamal Heib 6813488bd4cSKamal Heib return 0; 6823488bd4cSKamal Heib } 6833488bd4cSKamal Heib 6843488bd4cSKamal Heib static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data, 6853488bd4cSKamal Heib int idx) 6863488bd4cSKamal Heib { 6873488bd4cSKamal Heib int i; 6883488bd4cSKamal Heib 6893488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 6903488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 6913488bd4cSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 6923488bd4cSKamal Heib pport_eth_ext_stats_desc[i].format); 6933488bd4cSKamal Heib return idx; 6943488bd4cSKamal Heib } 6953488bd4cSKamal Heib 6963488bd4cSKamal Heib static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data, 6973488bd4cSKamal Heib int idx) 6983488bd4cSKamal Heib { 6993488bd4cSKamal Heib int i; 7003488bd4cSKamal Heib 7013488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 7023488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 7033488bd4cSKamal Heib data[idx++] = 7043488bd4cSKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters, 7053488bd4cSKamal Heib pport_eth_ext_stats_desc, i); 7063488bd4cSKamal Heib return idx; 7073488bd4cSKamal Heib } 7083488bd4cSKamal Heib 70919386177SKamal Heib static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv) 71019386177SKamal Heib { 71119386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 71219386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 71319386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 71419386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 71519386177SKamal Heib void *out; 71619386177SKamal Heib 71719386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) 71819386177SKamal Heib return; 71919386177SKamal Heib 72019386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 72119386177SKamal Heib out = pstats->eth_ext_counters; 72219386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 72319386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 72419386177SKamal Heib } 72519386177SKamal Heib 7269fd2b5f1SKamal Heib #define PCIE_PERF_OFF(c) \ 7279fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c) 7289fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc[] = { 7299fd2b5f1SKamal Heib { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) }, 7309fd2b5f1SKamal Heib { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) }, 7319fd2b5f1SKamal Heib }; 7329fd2b5f1SKamal Heib 7339fd2b5f1SKamal Heib #define PCIE_PERF_OFF64(c) \ 7349fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 7359fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc64[] = { 7369fd2b5f1SKamal Heib { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) }, 7379fd2b5f1SKamal Heib }; 7389fd2b5f1SKamal Heib 7399fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stall_stats_desc[] = { 7409fd2b5f1SKamal Heib { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) }, 7419fd2b5f1SKamal Heib { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) }, 7429fd2b5f1SKamal Heib { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) }, 7439fd2b5f1SKamal Heib { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) }, 7449fd2b5f1SKamal Heib }; 7459fd2b5f1SKamal Heib 7469fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc) 7479fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64) 7489fd2b5f1SKamal Heib #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc) 7499fd2b5f1SKamal Heib 7509fd2b5f1SKamal Heib static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv) 7519fd2b5f1SKamal Heib { 7529fd2b5f1SKamal Heib int num_stats = 0; 7539fd2b5f1SKamal Heib 7549fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7559fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS; 7569fd2b5f1SKamal Heib 7579fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 7589fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS64; 7599fd2b5f1SKamal Heib 7609fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 7619fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_STALL_COUNTERS; 7629fd2b5f1SKamal Heib 7639fd2b5f1SKamal Heib return num_stats; 7649fd2b5f1SKamal Heib } 7659fd2b5f1SKamal Heib 7669fd2b5f1SKamal Heib static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data, 7679fd2b5f1SKamal Heib int idx) 7689fd2b5f1SKamal Heib { 7699fd2b5f1SKamal Heib int i; 7709fd2b5f1SKamal Heib 7719fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7729fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 7739fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7749fd2b5f1SKamal Heib pcie_perf_stats_desc[i].format); 7759fd2b5f1SKamal Heib 7769fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 7779fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 7789fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7799fd2b5f1SKamal Heib pcie_perf_stats_desc64[i].format); 7809fd2b5f1SKamal Heib 7819fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 7829fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 7839fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 7849fd2b5f1SKamal Heib pcie_perf_stall_stats_desc[i].format); 7859fd2b5f1SKamal Heib return idx; 7869fd2b5f1SKamal Heib } 7879fd2b5f1SKamal Heib 7889fd2b5f1SKamal Heib static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data, 7899fd2b5f1SKamal Heib int idx) 7909fd2b5f1SKamal Heib { 7919fd2b5f1SKamal Heib int i; 7929fd2b5f1SKamal Heib 7939fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 7949fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 7959fd2b5f1SKamal Heib data[idx++] = 7969fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 7979fd2b5f1SKamal Heib pcie_perf_stats_desc, i); 7989fd2b5f1SKamal Heib 7999fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 8009fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 8019fd2b5f1SKamal Heib data[idx++] = 8029fd2b5f1SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters, 8039fd2b5f1SKamal Heib pcie_perf_stats_desc64, i); 8049fd2b5f1SKamal Heib 8059fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 8069fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 8079fd2b5f1SKamal Heib data[idx++] = 8089fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 8099fd2b5f1SKamal Heib pcie_perf_stall_stats_desc, i); 8109fd2b5f1SKamal Heib return idx; 8119fd2b5f1SKamal Heib } 8129fd2b5f1SKamal Heib 81319386177SKamal Heib static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv) 81419386177SKamal Heib { 81519386177SKamal Heib struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; 81619386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 81719386177SKamal Heib u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; 81819386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 81919386177SKamal Heib void *out; 82019386177SKamal Heib 82119386177SKamal Heib if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) 82219386177SKamal Heib return; 82319386177SKamal Heib 82419386177SKamal Heib out = pcie_stats->pcie_perf_counters; 82519386177SKamal Heib MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 82619386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 82719386177SKamal Heib } 82819386177SKamal Heib 8294377bea2SKamal Heib #define PPORT_PER_PRIO_OFF(c) \ 8304377bea2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 8314377bea2SKamal Heib counter_set.eth_per_prio_grp_data_layout.c##_high) 832e6000651SKamal Heib static const struct counter_desc pport_per_prio_traffic_stats_desc[] = { 833e6000651SKamal Heib { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) }, 834e6000651SKamal Heib { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) }, 835e6000651SKamal Heib { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) }, 836e6000651SKamal Heib { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) }, 837e6000651SKamal Heib }; 838e6000651SKamal Heib 839e6000651SKamal Heib #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc) 840e6000651SKamal Heib 841e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv) 842e6000651SKamal Heib { 843e6000651SKamal Heib return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO; 844e6000651SKamal Heib } 845e6000651SKamal Heib 846e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv, 847e6000651SKamal Heib u8 *data, 848e6000651SKamal Heib int idx) 849e6000651SKamal Heib { 850e6000651SKamal Heib int i, prio; 851e6000651SKamal Heib 852e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 853e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 854e6000651SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 855e6000651SKamal Heib pport_per_prio_traffic_stats_desc[i].format, prio); 856e6000651SKamal Heib } 857e6000651SKamal Heib 858e6000651SKamal Heib return idx; 859e6000651SKamal Heib } 860e6000651SKamal Heib 861e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv, 862e6000651SKamal Heib u64 *data, 863e6000651SKamal Heib int idx) 864e6000651SKamal Heib { 865e6000651SKamal Heib int i, prio; 866e6000651SKamal Heib 867e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 868e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 869e6000651SKamal Heib data[idx++] = 870e6000651SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 871e6000651SKamal Heib pport_per_prio_traffic_stats_desc, i); 872e6000651SKamal Heib } 873e6000651SKamal Heib 874e6000651SKamal Heib return idx; 875e6000651SKamal Heib } 876e6000651SKamal Heib 8774377bea2SKamal Heib static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 8784377bea2SKamal Heib /* %s is "global" or "prio{i}" */ 8794377bea2SKamal Heib { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) }, 8804377bea2SKamal Heib { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) }, 8814377bea2SKamal Heib { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) }, 8824377bea2SKamal Heib { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) }, 8834377bea2SKamal Heib { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, 8844377bea2SKamal Heib }; 8854377bea2SKamal Heib 8862fcb12dfSInbar Karmy static const struct counter_desc pport_pfc_stall_stats_desc[] = { 8872fcb12dfSInbar Karmy { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) }, 8882fcb12dfSInbar Karmy { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) }, 8892fcb12dfSInbar Karmy }; 8902fcb12dfSInbar Karmy 8914377bea2SKamal Heib #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc) 8922fcb12dfSInbar Karmy #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \ 8932fcb12dfSInbar Karmy MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \ 8942fcb12dfSInbar Karmy MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 8954377bea2SKamal Heib 8964377bea2SKamal Heib static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) 8974377bea2SKamal Heib { 8984377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 8994377bea2SKamal Heib u8 pfc_en_tx; 9004377bea2SKamal Heib u8 pfc_en_rx; 9014377bea2SKamal Heib int err; 9024377bea2SKamal Heib 9034377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 9044377bea2SKamal Heib return 0; 9054377bea2SKamal Heib 9064377bea2SKamal Heib err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx); 9074377bea2SKamal Heib 9084377bea2SKamal Heib return err ? 0 : pfc_en_tx | pfc_en_rx; 9094377bea2SKamal Heib } 9104377bea2SKamal Heib 9114377bea2SKamal Heib static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv) 9124377bea2SKamal Heib { 9134377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 9144377bea2SKamal Heib u32 rx_pause; 9154377bea2SKamal Heib u32 tx_pause; 9164377bea2SKamal Heib int err; 9174377bea2SKamal Heib 9184377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 9194377bea2SKamal Heib return false; 9204377bea2SKamal Heib 9214377bea2SKamal Heib err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 9224377bea2SKamal Heib 9234377bea2SKamal Heib return err ? false : rx_pause | tx_pause; 9244377bea2SKamal Heib } 9254377bea2SKamal Heib 9264377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) 9274377bea2SKamal Heib { 9284377bea2SKamal Heib return (mlx5e_query_global_pause_combined(priv) + 9294377bea2SKamal Heib hweight8(mlx5e_query_pfc_combined(priv))) * 9302fcb12dfSInbar Karmy NUM_PPORT_PER_PRIO_PFC_COUNTERS + 9312fcb12dfSInbar Karmy NUM_PPORT_PFC_STALL_COUNTERS(priv); 9324377bea2SKamal Heib } 9334377bea2SKamal Heib 9344377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, 9354377bea2SKamal Heib u8 *data, 9364377bea2SKamal Heib int idx) 9374377bea2SKamal Heib { 9384377bea2SKamal Heib unsigned long pfc_combined; 9394377bea2SKamal Heib int i, prio; 9404377bea2SKamal Heib 9414377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 9424377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 9434377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9444377bea2SKamal Heib char pfc_string[ETH_GSTRING_LEN]; 9454377bea2SKamal Heib 9464377bea2SKamal Heib snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio); 9474377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 9484377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, pfc_string); 9494377bea2SKamal Heib } 9504377bea2SKamal Heib } 9514377bea2SKamal Heib 9524377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 9534377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9544377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 9554377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, "global"); 9564377bea2SKamal Heib } 9574377bea2SKamal Heib } 9584377bea2SKamal Heib 9592fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 9602fcb12dfSInbar Karmy strcpy(data + (idx++) * ETH_GSTRING_LEN, 9612fcb12dfSInbar Karmy pport_pfc_stall_stats_desc[i].format); 9622fcb12dfSInbar Karmy 9634377bea2SKamal Heib return idx; 9644377bea2SKamal Heib } 9654377bea2SKamal Heib 9664377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, 9674377bea2SKamal Heib u64 *data, 9684377bea2SKamal Heib int idx) 9694377bea2SKamal Heib { 9704377bea2SKamal Heib unsigned long pfc_combined; 9714377bea2SKamal Heib int i, prio; 9724377bea2SKamal Heib 9734377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 9744377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 9754377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9764377bea2SKamal Heib data[idx++] = 9774377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 9784377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 9794377bea2SKamal Heib } 9804377bea2SKamal Heib } 9814377bea2SKamal Heib 9824377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 9834377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 9844377bea2SKamal Heib data[idx++] = 9854377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 9864377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 9874377bea2SKamal Heib } 9884377bea2SKamal Heib } 9894377bea2SKamal Heib 9902fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 9912fcb12dfSInbar Karmy data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 9922fcb12dfSInbar Karmy pport_pfc_stall_stats_desc, i); 9932fcb12dfSInbar Karmy 9944377bea2SKamal Heib return idx; 9954377bea2SKamal Heib } 9964377bea2SKamal Heib 997a8984281SKamal Heib static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv) 998a8984281SKamal Heib { 999a8984281SKamal Heib return mlx5e_grp_per_prio_traffic_get_num_stats(priv) + 1000a8984281SKamal Heib mlx5e_grp_per_prio_pfc_get_num_stats(priv); 1001a8984281SKamal Heib } 1002a8984281SKamal Heib 1003a8984281SKamal Heib static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data, 1004a8984281SKamal Heib int idx) 1005a8984281SKamal Heib { 1006a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx); 1007a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx); 1008a8984281SKamal Heib return idx; 1009a8984281SKamal Heib } 1010a8984281SKamal Heib 1011a8984281SKamal Heib static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data, 1012a8984281SKamal Heib int idx) 1013a8984281SKamal Heib { 1014a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx); 1015a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx); 1016a8984281SKamal Heib return idx; 1017a8984281SKamal Heib } 1018a8984281SKamal Heib 101919386177SKamal Heib static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv) 102019386177SKamal Heib { 102119386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 102219386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 102319386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 102419386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 102519386177SKamal Heib int prio; 102619386177SKamal Heib void *out; 102719386177SKamal Heib 102819386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 102919386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 103019386177SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 103119386177SKamal Heib out = pstats->per_prio_counters[prio]; 103219386177SKamal Heib MLX5_SET(ppcnt_reg, in, prio_tc, prio); 103319386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, 103419386177SKamal Heib MLX5_REG_PPCNT, 0, 0); 103519386177SKamal Heib } 103619386177SKamal Heib } 103719386177SKamal Heib 10380e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_status_desc[] = { 10390e6f01a4SKamal Heib { "module_unplug", 8 }, 10400e6f01a4SKamal Heib }; 10410e6f01a4SKamal Heib 10420e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_error_desc[] = { 10430e6f01a4SKamal Heib { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */ 10440e6f01a4SKamal Heib { "module_high_temp", 48 }, /* high temperature */ 10450e6f01a4SKamal Heib { "module_bad_shorted", 56 }, /* bad or shorted cable/module */ 10460e6f01a4SKamal Heib }; 10470e6f01a4SKamal Heib 10480e6f01a4SKamal Heib #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc) 10490e6f01a4SKamal Heib #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc) 10500e6f01a4SKamal Heib 10510e6f01a4SKamal Heib static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv) 10520e6f01a4SKamal Heib { 10530e6f01a4SKamal Heib return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS; 10540e6f01a4SKamal Heib } 10550e6f01a4SKamal Heib 10560e6f01a4SKamal Heib static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data, 10570e6f01a4SKamal Heib int idx) 10580e6f01a4SKamal Heib { 10590e6f01a4SKamal Heib int i; 10600e6f01a4SKamal Heib 10610e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 10620e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format); 10630e6f01a4SKamal Heib 10640e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 10650e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format); 10660e6f01a4SKamal Heib 10670e6f01a4SKamal Heib return idx; 10680e6f01a4SKamal Heib } 10690e6f01a4SKamal Heib 10700e6f01a4SKamal Heib static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data, 10710e6f01a4SKamal Heib int idx) 10720e6f01a4SKamal Heib { 10730e6f01a4SKamal Heib struct mlx5_priv *mlx5_priv = &priv->mdev->priv; 10740e6f01a4SKamal Heib int i; 10750e6f01a4SKamal Heib 10760e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 10770e6f01a4SKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters, 10780e6f01a4SKamal Heib mlx5e_pme_status_desc, i); 10790e6f01a4SKamal Heib 10800e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 10810e6f01a4SKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters, 10820e6f01a4SKamal Heib mlx5e_pme_error_desc, i); 10830e6f01a4SKamal Heib 10840e6f01a4SKamal Heib return idx; 10850e6f01a4SKamal Heib } 10860e6f01a4SKamal Heib 1087e185d43fSKamal Heib static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv) 1088e185d43fSKamal Heib { 1089e185d43fSKamal Heib return mlx5e_ipsec_get_count(priv); 1090e185d43fSKamal Heib } 1091e185d43fSKamal Heib 1092e185d43fSKamal Heib static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data, 1093e185d43fSKamal Heib int idx) 1094e185d43fSKamal Heib { 1095e185d43fSKamal Heib return idx + mlx5e_ipsec_get_strings(priv, 1096e185d43fSKamal Heib data + idx * ETH_GSTRING_LEN); 1097e185d43fSKamal Heib } 1098e185d43fSKamal Heib 1099e185d43fSKamal Heib static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data, 1100e185d43fSKamal Heib int idx) 1101e185d43fSKamal Heib { 1102e185d43fSKamal Heib return idx + mlx5e_ipsec_get_stats(priv, data + idx); 1103e185d43fSKamal Heib } 1104e185d43fSKamal Heib 110519386177SKamal Heib static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv) 110619386177SKamal Heib { 110719386177SKamal Heib mlx5e_ipsec_update_stats(priv); 110819386177SKamal Heib } 110919386177SKamal Heib 111043585a41SIlya Lesokhin static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv) 111143585a41SIlya Lesokhin { 111243585a41SIlya Lesokhin return mlx5e_tls_get_count(priv); 111343585a41SIlya Lesokhin } 111443585a41SIlya Lesokhin 111543585a41SIlya Lesokhin static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data, 111643585a41SIlya Lesokhin int idx) 111743585a41SIlya Lesokhin { 111843585a41SIlya Lesokhin return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN); 111943585a41SIlya Lesokhin } 112043585a41SIlya Lesokhin 112143585a41SIlya Lesokhin static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 112243585a41SIlya Lesokhin { 112343585a41SIlya Lesokhin return idx + mlx5e_tls_get_stats(priv, data + idx); 112443585a41SIlya Lesokhin } 112543585a41SIlya Lesokhin 11261fe85006SKamal Heib static const struct counter_desc rq_stats_desc[] = { 11271fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) }, 11281fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) }, 11291fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) }, 11301fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) }, 11311fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 11321fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) }, 11331fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) }, 113486690b4bSTariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) }, 11351fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) }, 11361fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) }, 1137f24686e8SGal Pressman { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) }, 11381fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) }, 1139b71ba6b4STariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) }, 1140b71ba6b4STariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) }, 11411fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 11421fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 11431fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 11441fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) }, 11451fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) }, 11461fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) }, 11471fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) }, 11481fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) }, 11491fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) }, 1150dc983f0eSTariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) }, 11511fe85006SKamal Heib }; 11521fe85006SKamal Heib 11531fe85006SKamal Heib static const struct counter_desc sq_stats_desc[] = { 11541fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) }, 11551fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) }, 11561fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) }, 11571fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) }, 11581fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) }, 11591fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) }, 11601fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) }, 11611fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) }, 1162f24686e8SGal Pressman { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) }, 11631fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) }, 11641fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) }, 11651fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) }, 11661fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) }, 11671fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) }, 1168db75373cSEran Ben Elisha { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) }, 116986155656STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) }, 1170f65a59ffSTariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) }, 1171f65a59ffSTariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) }, 11721fe85006SKamal Heib }; 11731fe85006SKamal Heib 1174890388adSTariq Toukan static const struct counter_desc rq_xdpsq_stats_desc[] = { 1175890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 1176890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 1177890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 1178890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 1179890388adSTariq Toukan }; 1180890388adSTariq Toukan 118157d689a8SEran Ben Elisha static const struct counter_desc ch_stats_desc[] = { 1182a1bf74dcSTariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) }, 11832d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) }, 11842d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) }, 11852d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) }, 118657d689a8SEran Ben Elisha { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) }, 118757d689a8SEran Ben Elisha }; 118857d689a8SEran Ben Elisha 11891fe85006SKamal Heib #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc) 11901fe85006SKamal Heib #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc) 1191890388adSTariq Toukan #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc) 119257d689a8SEran Ben Elisha #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc) 11931fe85006SKamal Heib 11941fe85006SKamal Heib static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv) 11951fe85006SKamal Heib { 119605909babSEran Ben Elisha int max_nch = priv->profile->max_nch(priv->mdev); 119705909babSEran Ben Elisha 119805909babSEran Ben Elisha return (NUM_RQ_STATS * max_nch) + 119905909babSEran Ben Elisha (NUM_CH_STATS * max_nch) + 1200890388adSTariq Toukan (NUM_SQ_STATS * max_nch * priv->max_opened_tc) + 1201890388adSTariq Toukan (NUM_RQ_XDPSQ_STATS * max_nch); 12021fe85006SKamal Heib } 12031fe85006SKamal Heib 12041fe85006SKamal Heib static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data, 12051fe85006SKamal Heib int idx) 12061fe85006SKamal Heib { 120705909babSEran Ben Elisha int max_nch = priv->profile->max_nch(priv->mdev); 12081fe85006SKamal Heib int i, j, tc; 12091fe85006SKamal Heib 121005909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 121157d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 121257d689a8SEran Ben Elisha sprintf(data + (idx++) * ETH_GSTRING_LEN, 121357d689a8SEran Ben Elisha ch_stats_desc[j].format, i); 121457d689a8SEran Ben Elisha 1215890388adSTariq Toukan for (i = 0; i < max_nch; i++) { 12161fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 1217890388adSTariq Toukan sprintf(data + (idx++) * ETH_GSTRING_LEN, 1218890388adSTariq Toukan rq_stats_desc[j].format, i); 1219890388adSTariq Toukan for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1220890388adSTariq Toukan sprintf(data + (idx++) * ETH_GSTRING_LEN, 1221890388adSTariq Toukan rq_xdpsq_stats_desc[j].format, i); 1222890388adSTariq Toukan } 12231fe85006SKamal Heib 122405909babSEran Ben Elisha for (tc = 0; tc < priv->max_opened_tc; tc++) 122505909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 12261fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 12271fe85006SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 12281fe85006SKamal Heib sq_stats_desc[j].format, 12291fe85006SKamal Heib priv->channel_tc2txq[i][tc]); 12301fe85006SKamal Heib 12311fe85006SKamal Heib return idx; 12321fe85006SKamal Heib } 12331fe85006SKamal Heib 12341fe85006SKamal Heib static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data, 12351fe85006SKamal Heib int idx) 12361fe85006SKamal Heib { 123705909babSEran Ben Elisha int max_nch = priv->profile->max_nch(priv->mdev); 12381fe85006SKamal Heib int i, j, tc; 12391fe85006SKamal Heib 124005909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 124157d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 124257d689a8SEran Ben Elisha data[idx++] = 124305909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch, 124457d689a8SEran Ben Elisha ch_stats_desc, j); 124557d689a8SEran Ben Elisha 1246890388adSTariq Toukan for (i = 0; i < max_nch; i++) { 12471fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 12481fe85006SKamal Heib data[idx++] = 124905909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq, 12501fe85006SKamal Heib rq_stats_desc, j); 1251890388adSTariq Toukan for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1252890388adSTariq Toukan data[idx++] = 1253890388adSTariq Toukan MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq, 1254890388adSTariq Toukan rq_xdpsq_stats_desc, j); 1255890388adSTariq Toukan } 12561fe85006SKamal Heib 125705909babSEran Ben Elisha for (tc = 0; tc < priv->max_opened_tc; tc++) 125805909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 12591fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 12601fe85006SKamal Heib data[idx++] = 126105909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc], 12621fe85006SKamal Heib sq_stats_desc, j); 12631fe85006SKamal Heib 12641fe85006SKamal Heib return idx; 12651fe85006SKamal Heib } 12661fe85006SKamal Heib 126719386177SKamal Heib /* The stats groups order is opposite to the update_stats() order calls */ 1268c0752f2bSKamal Heib const struct mlx5e_stats_grp mlx5e_stats_grps[] = { 1269c0752f2bSKamal Heib { 1270c0752f2bSKamal Heib .get_num_stats = mlx5e_grp_sw_get_num_stats, 1271c0752f2bSKamal Heib .fill_strings = mlx5e_grp_sw_fill_strings, 1272c0752f2bSKamal Heib .fill_stats = mlx5e_grp_sw_fill_stats, 127319386177SKamal Heib .update_stats = mlx5e_grp_sw_update_stats, 1274fd8dcdb8SKamal Heib }, 1275fd8dcdb8SKamal Heib { 1276fd8dcdb8SKamal Heib .get_num_stats = mlx5e_grp_q_get_num_stats, 1277fd8dcdb8SKamal Heib .fill_strings = mlx5e_grp_q_fill_strings, 1278fd8dcdb8SKamal Heib .fill_stats = mlx5e_grp_q_fill_stats, 127919386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 128019386177SKamal Heib .update_stats = mlx5e_grp_q_update_stats, 1281fd8dcdb8SKamal Heib }, 128240cab9f1SKamal Heib { 12835c298143SMoshe Shemesh .get_num_stats = mlx5e_grp_vnic_env_get_num_stats, 12845c298143SMoshe Shemesh .fill_strings = mlx5e_grp_vnic_env_fill_strings, 12855c298143SMoshe Shemesh .fill_stats = mlx5e_grp_vnic_env_fill_stats, 12865c298143SMoshe Shemesh .update_stats = mlx5e_grp_vnic_env_update_stats, 12875c298143SMoshe Shemesh }, 12885c298143SMoshe Shemesh { 128940cab9f1SKamal Heib .get_num_stats = mlx5e_grp_vport_get_num_stats, 129040cab9f1SKamal Heib .fill_strings = mlx5e_grp_vport_fill_strings, 129140cab9f1SKamal Heib .fill_stats = mlx5e_grp_vport_fill_stats, 129219386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 129319386177SKamal Heib .update_stats = mlx5e_grp_vport_update_stats, 129440cab9f1SKamal Heib }, 12956e6ef814SKamal Heib { 12966e6ef814SKamal Heib .get_num_stats = mlx5e_grp_802_3_get_num_stats, 12976e6ef814SKamal Heib .fill_strings = mlx5e_grp_802_3_fill_strings, 12986e6ef814SKamal Heib .fill_stats = mlx5e_grp_802_3_fill_stats, 129919386177SKamal Heib .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 130019386177SKamal Heib .update_stats = mlx5e_grp_802_3_update_stats, 13016e6ef814SKamal Heib }, 1302fc8e64a3SKamal Heib { 1303fc8e64a3SKamal Heib .get_num_stats = mlx5e_grp_2863_get_num_stats, 1304fc8e64a3SKamal Heib .fill_strings = mlx5e_grp_2863_fill_strings, 1305fc8e64a3SKamal Heib .fill_stats = mlx5e_grp_2863_fill_stats, 130619386177SKamal Heib .update_stats = mlx5e_grp_2863_update_stats, 1307fc8e64a3SKamal Heib }, 1308e0e0def9SKamal Heib { 1309e0e0def9SKamal Heib .get_num_stats = mlx5e_grp_2819_get_num_stats, 1310e0e0def9SKamal Heib .fill_strings = mlx5e_grp_2819_fill_strings, 1311e0e0def9SKamal Heib .fill_stats = mlx5e_grp_2819_fill_stats, 131219386177SKamal Heib .update_stats = mlx5e_grp_2819_update_stats, 1313e0e0def9SKamal Heib }, 13142e4df0b2SKamal Heib { 13152e4df0b2SKamal Heib .get_num_stats = mlx5e_grp_phy_get_num_stats, 13162e4df0b2SKamal Heib .fill_strings = mlx5e_grp_phy_fill_strings, 13172e4df0b2SKamal Heib .fill_stats = mlx5e_grp_phy_fill_stats, 131819386177SKamal Heib .update_stats = mlx5e_grp_phy_update_stats, 13192e4df0b2SKamal Heib }, 13203488bd4cSKamal Heib { 13213488bd4cSKamal Heib .get_num_stats = mlx5e_grp_eth_ext_get_num_stats, 13223488bd4cSKamal Heib .fill_strings = mlx5e_grp_eth_ext_fill_strings, 13233488bd4cSKamal Heib .fill_stats = mlx5e_grp_eth_ext_fill_stats, 132419386177SKamal Heib .update_stats = mlx5e_grp_eth_ext_update_stats, 13259fd2b5f1SKamal Heib }, 13269fd2b5f1SKamal Heib { 13279fd2b5f1SKamal Heib .get_num_stats = mlx5e_grp_pcie_get_num_stats, 13289fd2b5f1SKamal Heib .fill_strings = mlx5e_grp_pcie_fill_strings, 13299fd2b5f1SKamal Heib .fill_stats = mlx5e_grp_pcie_fill_stats, 133019386177SKamal Heib .update_stats = mlx5e_grp_pcie_update_stats, 13319fd2b5f1SKamal Heib }, 1332e6000651SKamal Heib { 1333a8984281SKamal Heib .get_num_stats = mlx5e_grp_per_prio_get_num_stats, 1334a8984281SKamal Heib .fill_strings = mlx5e_grp_per_prio_fill_strings, 1335a8984281SKamal Heib .fill_stats = mlx5e_grp_per_prio_fill_stats, 133619386177SKamal Heib .update_stats = mlx5e_grp_per_prio_update_stats, 13374377bea2SKamal Heib }, 13380e6f01a4SKamal Heib { 13390e6f01a4SKamal Heib .get_num_stats = mlx5e_grp_pme_get_num_stats, 13400e6f01a4SKamal Heib .fill_strings = mlx5e_grp_pme_fill_strings, 13410e6f01a4SKamal Heib .fill_stats = mlx5e_grp_pme_fill_stats, 13420e6f01a4SKamal Heib }, 1343e185d43fSKamal Heib { 1344e185d43fSKamal Heib .get_num_stats = mlx5e_grp_ipsec_get_num_stats, 1345e185d43fSKamal Heib .fill_strings = mlx5e_grp_ipsec_fill_strings, 1346e185d43fSKamal Heib .fill_stats = mlx5e_grp_ipsec_fill_stats, 134719386177SKamal Heib .update_stats = mlx5e_grp_ipsec_update_stats, 1348e185d43fSKamal Heib }, 13491fe85006SKamal Heib { 135043585a41SIlya Lesokhin .get_num_stats = mlx5e_grp_tls_get_num_stats, 135143585a41SIlya Lesokhin .fill_strings = mlx5e_grp_tls_fill_strings, 135243585a41SIlya Lesokhin .fill_stats = mlx5e_grp_tls_fill_stats, 135343585a41SIlya Lesokhin }, 135443585a41SIlya Lesokhin { 13551fe85006SKamal Heib .get_num_stats = mlx5e_grp_channels_get_num_stats, 13561fe85006SKamal Heib .fill_strings = mlx5e_grp_channels_fill_strings, 13571fe85006SKamal Heib .fill_stats = mlx5e_grp_channels_fill_stats, 13581fe85006SKamal Heib } 1359c0752f2bSKamal Heib }; 1360c0752f2bSKamal Heib 1361c0752f2bSKamal Heib const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps); 1362