1c0752f2bSKamal Heib /* 2c0752f2bSKamal Heib * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3c0752f2bSKamal Heib * 4c0752f2bSKamal Heib * This software is available to you under a choice of one of two 5c0752f2bSKamal Heib * licenses. You may choose to be licensed under the terms of the GNU 6c0752f2bSKamal Heib * General Public License (GPL) Version 2, available from the file 7c0752f2bSKamal Heib * COPYING in the main directory of this source tree, or the 8c0752f2bSKamal Heib * OpenIB.org BSD license below: 9c0752f2bSKamal Heib * 10c0752f2bSKamal Heib * Redistribution and use in source and binary forms, with or 11c0752f2bSKamal Heib * without modification, are permitted provided that the following 12c0752f2bSKamal Heib * conditions are met: 13c0752f2bSKamal Heib * 14c0752f2bSKamal Heib * - Redistributions of source code must retain the above 15c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 16c0752f2bSKamal Heib * disclaimer. 17c0752f2bSKamal Heib * 18c0752f2bSKamal Heib * - Redistributions in binary form must reproduce the above 19c0752f2bSKamal Heib * copyright notice, this list of conditions and the following 20c0752f2bSKamal Heib * disclaimer in the documentation and/or other materials 21c0752f2bSKamal Heib * provided with the distribution. 22c0752f2bSKamal Heib * 23c0752f2bSKamal Heib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24c0752f2bSKamal Heib * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25c0752f2bSKamal Heib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26c0752f2bSKamal Heib * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27c0752f2bSKamal Heib * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28c0752f2bSKamal Heib * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29c0752f2bSKamal Heib * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30c0752f2bSKamal Heib * SOFTWARE. 31c0752f2bSKamal Heib */ 32c0752f2bSKamal Heib 3369c1280bSSaeed Mahameed #include "lib/mlx5.h" 34c0752f2bSKamal Heib #include "en.h" 3543585a41SIlya Lesokhin #include "en_accel/tls.h" 360aab3e1bSRaed Salem #include "en_accel/en_accel.h" 37c0752f2bSKamal Heib 383460c184SSaeed Mahameed static unsigned int stats_grps_num(struct mlx5e_priv *priv) 393460c184SSaeed Mahameed { 403460c184SSaeed Mahameed return !priv->profile->stats_grps_num ? 0 : 413460c184SSaeed Mahameed priv->profile->stats_grps_num(priv); 423460c184SSaeed Mahameed } 433460c184SSaeed Mahameed 443460c184SSaeed Mahameed unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv) 453460c184SSaeed Mahameed { 46f0ff8e8cSSaeed Mahameed mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps; 473460c184SSaeed Mahameed const unsigned int num_stats_grps = stats_grps_num(priv); 483460c184SSaeed Mahameed unsigned int total = 0; 493460c184SSaeed Mahameed int i; 503460c184SSaeed Mahameed 513460c184SSaeed Mahameed for (i = 0; i < num_stats_grps; i++) 52f0ff8e8cSSaeed Mahameed total += stats_grps[i]->get_num_stats(priv); 533460c184SSaeed Mahameed 543460c184SSaeed Mahameed return total; 553460c184SSaeed Mahameed } 563460c184SSaeed Mahameed 573460c184SSaeed Mahameed void mlx5e_stats_update(struct mlx5e_priv *priv) 583460c184SSaeed Mahameed { 59f0ff8e8cSSaeed Mahameed mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps; 603460c184SSaeed Mahameed const unsigned int num_stats_grps = stats_grps_num(priv); 613460c184SSaeed Mahameed int i; 623460c184SSaeed Mahameed 633460c184SSaeed Mahameed for (i = num_stats_grps - 1; i >= 0; i--) 64f0ff8e8cSSaeed Mahameed if (stats_grps[i]->update_stats) 65f0ff8e8cSSaeed Mahameed stats_grps[i]->update_stats(priv); 663460c184SSaeed Mahameed } 673460c184SSaeed Mahameed 683460c184SSaeed Mahameed void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx) 693460c184SSaeed Mahameed { 70f0ff8e8cSSaeed Mahameed mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps; 713460c184SSaeed Mahameed const unsigned int num_stats_grps = stats_grps_num(priv); 723460c184SSaeed Mahameed int i; 733460c184SSaeed Mahameed 743460c184SSaeed Mahameed for (i = 0; i < num_stats_grps; i++) 75f0ff8e8cSSaeed Mahameed idx = stats_grps[i]->fill_stats(priv, data, idx); 763460c184SSaeed Mahameed } 773460c184SSaeed Mahameed 783460c184SSaeed Mahameed void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data) 793460c184SSaeed Mahameed { 80f0ff8e8cSSaeed Mahameed mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps; 813460c184SSaeed Mahameed const unsigned int num_stats_grps = stats_grps_num(priv); 823460c184SSaeed Mahameed int i, idx = 0; 833460c184SSaeed Mahameed 843460c184SSaeed Mahameed for (i = 0; i < num_stats_grps; i++) 85f0ff8e8cSSaeed Mahameed idx = stats_grps[i]->fill_strings(priv, data, idx); 863460c184SSaeed Mahameed } 873460c184SSaeed Mahameed 883460c184SSaeed Mahameed /* Concrete NIC Stats */ 893460c184SSaeed Mahameed 90c0752f2bSKamal Heib static const struct counter_desc sw_stats_desc[] = { 91c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) }, 92c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) }, 93c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) }, 94c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) }, 95c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) }, 96c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) }, 97c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) }, 98c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) }, 99f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) }, 1002ad9ecdbSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) }, 101bf239741SIlya Lesokhin 102bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 103d2ead1f3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_packets) }, 104d2ead1f3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_bytes) }, 105d2ead1f3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ctx) }, 106bf239741SIlya Lesokhin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) }, 107d2ead1f3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_packets) }, 108d2ead1f3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_bytes) }, 10946a3ea98STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) }, 11046a3ea98STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_skip_no_sync_data) }, 11146a3ea98STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_no_sync_data) }, 11246a3ea98STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_bypass_req) }, 113bf239741SIlya Lesokhin #endif 114bf239741SIlya Lesokhin 115c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) }, 116c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) }, 117f007c13dSNatali Shechtman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) }, 118f24686e8SGal Pressman { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) }, 119c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) }, 120c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) }, 121c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) }, 1220aa1d186SSaeed Mahameed { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) }, 1230aa1d186SSaeed Mahameed { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) }, 124c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) }, 125c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) }, 12686690b4bSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) }, 127890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) }, 12873cab880SShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_mpwqe) }, 129c2273219SShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_inlnw) }, 1306c085a8aSShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_nops) }, 131c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) }, 132890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) }, 133890388adSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) }, 134c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) }, 135c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) }, 136c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) }, 137c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) }, 138c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) }, 139c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) }, 140db75373cSEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) }, 14186155656STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) }, 142f65a59ffSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) }, 143f65a59ffSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) }, 14458b99ee3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) }, 14573cab880SShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_mpwqe) }, 146c2273219SShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_inlnw) }, 1476c085a8aSShay Agroskin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_nops) }, 14858b99ee3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) }, 14958b99ee3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) }, 15058b99ee3STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) }, 151c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) }, 152b71ba6b4STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) }, 153b71ba6b4STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) }, 1540073c8f7SMoshe Shemesh { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) }, 155c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) }, 156c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 157c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 158c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) }, 159c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) }, 160c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) }, 161c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) }, 162c0752f2bSKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) }, 163dc983f0eSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) }, 16494563847SEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) }, 165be5323c8SAya Levin { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) }, 166a1bf74dcSTariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) }, 1672d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) }, 1682d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) }, 1692d7103c8STariq Toukan { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) }, 170db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_force_irq) }, 17157d689a8SEran Ben Elisha { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) }, 172db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_packets) }, 173db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_bytes) }, 174db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_complete) }, 175db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary) }, 176db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary_inner) }, 177db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_none) }, 178db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_ecn_mark) }, 179db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_removed_vlan_packets) }, 180db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_drop) }, 181db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_redirect) }, 182db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_wqe_err) }, 183db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_cqes) }, 184db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_strides) }, 185db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_oversize_pkts_sw_drop) }, 186db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_buff_alloc_err) }, 187db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) }, 188db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) }, 189db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) }, 190db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_arfs_err) }, 191db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) }, 192db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) }, 193db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) }, 194db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_full) }, 195db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_err) }, 196db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_cqes) }, 197c0752f2bSKamal Heib }; 198c0752f2bSKamal Heib 199c0752f2bSKamal Heib #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc) 200c0752f2bSKamal Heib 20196b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw) 202c0752f2bSKamal Heib { 203c0752f2bSKamal Heib return NUM_SW_COUNTERS; 204c0752f2bSKamal Heib } 205c0752f2bSKamal Heib 20696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(sw) 207c0752f2bSKamal Heib { 208c0752f2bSKamal Heib int i; 209c0752f2bSKamal Heib 210c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 211c0752f2bSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format); 212c0752f2bSKamal Heib return idx; 213c0752f2bSKamal Heib } 214c0752f2bSKamal Heib 21596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw) 216c0752f2bSKamal Heib { 217c0752f2bSKamal Heib int i; 218c0752f2bSKamal Heib 219c0752f2bSKamal Heib for (i = 0; i < NUM_SW_COUNTERS; i++) 220c0752f2bSKamal Heib data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i); 221c0752f2bSKamal Heib return idx; 222c0752f2bSKamal Heib } 223c0752f2bSKamal Heib 22496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw) 22519386177SKamal Heib { 2269659e49aSSaeed Mahameed struct mlx5e_sw_stats *s = &priv->stats.sw; 22705909babSEran Ben Elisha int i; 22819386177SKamal Heib 22919386177SKamal Heib memset(s, 0, sizeof(*s)); 23019386177SKamal Heib 231694826e3STariq Toukan for (i = 0; i < priv->max_nch; i++) { 23205909babSEran Ben Elisha struct mlx5e_channel_stats *channel_stats = 23305909babSEran Ben Elisha &priv->channel_stats[i]; 23458b99ee3STariq Toukan struct mlx5e_xdpsq_stats *xdpsq_red_stats = &channel_stats->xdpsq; 235890388adSTariq Toukan struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq; 236db05815bSMaxim Mikityanskiy struct mlx5e_xdpsq_stats *xsksq_stats = &channel_stats->xsksq; 237db05815bSMaxim Mikityanskiy struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; 23805909babSEran Ben Elisha struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 23905909babSEran Ben Elisha struct mlx5e_ch_stats *ch_stats = &channel_stats->ch; 24005909babSEran Ben Elisha int j; 24119386177SKamal Heib 24219386177SKamal Heib s->rx_packets += rq_stats->packets; 24319386177SKamal Heib s->rx_bytes += rq_stats->bytes; 24419386177SKamal Heib s->rx_lro_packets += rq_stats->lro_packets; 24519386177SKamal Heib s->rx_lro_bytes += rq_stats->lro_bytes; 246f007c13dSNatali Shechtman s->rx_ecn_mark += rq_stats->ecn_mark; 24719386177SKamal Heib s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets; 24819386177SKamal Heib s->rx_csum_none += rq_stats->csum_none; 24919386177SKamal Heib s->rx_csum_complete += rq_stats->csum_complete; 2500aa1d186SSaeed Mahameed s->rx_csum_complete_tail += rq_stats->csum_complete_tail; 2510aa1d186SSaeed Mahameed s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow; 25219386177SKamal Heib s->rx_csum_unnecessary += rq_stats->csum_unnecessary; 25319386177SKamal Heib s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; 25419386177SKamal Heib s->rx_xdp_drop += rq_stats->xdp_drop; 25586690b4bSTariq Toukan s->rx_xdp_redirect += rq_stats->xdp_redirect; 256890388adSTariq Toukan s->rx_xdp_tx_xmit += xdpsq_stats->xmit; 25773cab880SShay Agroskin s->rx_xdp_tx_mpwqe += xdpsq_stats->mpwqe; 258c2273219SShay Agroskin s->rx_xdp_tx_inlnw += xdpsq_stats->inlnw; 2596c085a8aSShay Agroskin s->rx_xdp_tx_nops += xdpsq_stats->nops; 260890388adSTariq Toukan s->rx_xdp_tx_full += xdpsq_stats->full; 261890388adSTariq Toukan s->rx_xdp_tx_err += xdpsq_stats->err; 262890388adSTariq Toukan s->rx_xdp_tx_cqe += xdpsq_stats->cqes; 26319386177SKamal Heib s->rx_wqe_err += rq_stats->wqe_err; 264b71ba6b4STariq Toukan s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes; 265b71ba6b4STariq Toukan s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides; 2660073c8f7SMoshe Shemesh s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop; 26719386177SKamal Heib s->rx_buff_alloc_err += rq_stats->buff_alloc_err; 26819386177SKamal Heib s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; 26919386177SKamal Heib s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; 27019386177SKamal Heib s->rx_cache_reuse += rq_stats->cache_reuse; 27119386177SKamal Heib s->rx_cache_full += rq_stats->cache_full; 27219386177SKamal Heib s->rx_cache_empty += rq_stats->cache_empty; 27319386177SKamal Heib s->rx_cache_busy += rq_stats->cache_busy; 27419386177SKamal Heib s->rx_cache_waive += rq_stats->cache_waive; 275dc983f0eSTariq Toukan s->rx_congst_umr += rq_stats->congst_umr; 27694563847SEran Ben Elisha s->rx_arfs_err += rq_stats->arfs_err; 277be5323c8SAya Levin s->rx_recover += rq_stats->recover; 278a1bf74dcSTariq Toukan s->ch_events += ch_stats->events; 2792d7103c8STariq Toukan s->ch_poll += ch_stats->poll; 2802d7103c8STariq Toukan s->ch_arm += ch_stats->arm; 2812d7103c8STariq Toukan s->ch_aff_change += ch_stats->aff_change; 282db05815bSMaxim Mikityanskiy s->ch_force_irq += ch_stats->force_irq; 28319386177SKamal Heib s->ch_eq_rearm += ch_stats->eq_rearm; 28458b99ee3STariq Toukan /* xdp redirect */ 28558b99ee3STariq Toukan s->tx_xdp_xmit += xdpsq_red_stats->xmit; 28673cab880SShay Agroskin s->tx_xdp_mpwqe += xdpsq_red_stats->mpwqe; 287c2273219SShay Agroskin s->tx_xdp_inlnw += xdpsq_red_stats->inlnw; 2886c085a8aSShay Agroskin s->tx_xdp_nops += xdpsq_red_stats->nops; 28958b99ee3STariq Toukan s->tx_xdp_full += xdpsq_red_stats->full; 29058b99ee3STariq Toukan s->tx_xdp_err += xdpsq_red_stats->err; 29158b99ee3STariq Toukan s->tx_xdp_cqes += xdpsq_red_stats->cqes; 292db05815bSMaxim Mikityanskiy /* AF_XDP zero-copy */ 293db05815bSMaxim Mikityanskiy s->rx_xsk_packets += xskrq_stats->packets; 294db05815bSMaxim Mikityanskiy s->rx_xsk_bytes += xskrq_stats->bytes; 295db05815bSMaxim Mikityanskiy s->rx_xsk_csum_complete += xskrq_stats->csum_complete; 296db05815bSMaxim Mikityanskiy s->rx_xsk_csum_unnecessary += xskrq_stats->csum_unnecessary; 297db05815bSMaxim Mikityanskiy s->rx_xsk_csum_unnecessary_inner += xskrq_stats->csum_unnecessary_inner; 298db05815bSMaxim Mikityanskiy s->rx_xsk_csum_none += xskrq_stats->csum_none; 299db05815bSMaxim Mikityanskiy s->rx_xsk_ecn_mark += xskrq_stats->ecn_mark; 300db05815bSMaxim Mikityanskiy s->rx_xsk_removed_vlan_packets += xskrq_stats->removed_vlan_packets; 301db05815bSMaxim Mikityanskiy s->rx_xsk_xdp_drop += xskrq_stats->xdp_drop; 302db05815bSMaxim Mikityanskiy s->rx_xsk_xdp_redirect += xskrq_stats->xdp_redirect; 303db05815bSMaxim Mikityanskiy s->rx_xsk_wqe_err += xskrq_stats->wqe_err; 304db05815bSMaxim Mikityanskiy s->rx_xsk_mpwqe_filler_cqes += xskrq_stats->mpwqe_filler_cqes; 305db05815bSMaxim Mikityanskiy s->rx_xsk_mpwqe_filler_strides += xskrq_stats->mpwqe_filler_strides; 306db05815bSMaxim Mikityanskiy s->rx_xsk_oversize_pkts_sw_drop += xskrq_stats->oversize_pkts_sw_drop; 307db05815bSMaxim Mikityanskiy s->rx_xsk_buff_alloc_err += xskrq_stats->buff_alloc_err; 308db05815bSMaxim Mikityanskiy s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks; 309db05815bSMaxim Mikityanskiy s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts; 310db05815bSMaxim Mikityanskiy s->rx_xsk_congst_umr += xskrq_stats->congst_umr; 311db05815bSMaxim Mikityanskiy s->rx_xsk_arfs_err += xskrq_stats->arfs_err; 312db05815bSMaxim Mikityanskiy s->tx_xsk_xmit += xsksq_stats->xmit; 313db05815bSMaxim Mikityanskiy s->tx_xsk_mpwqe += xsksq_stats->mpwqe; 314db05815bSMaxim Mikityanskiy s->tx_xsk_inlnw += xsksq_stats->inlnw; 315db05815bSMaxim Mikityanskiy s->tx_xsk_full += xsksq_stats->full; 316db05815bSMaxim Mikityanskiy s->tx_xsk_err += xsksq_stats->err; 317db05815bSMaxim Mikityanskiy s->tx_xsk_cqes += xsksq_stats->cqes; 31819386177SKamal Heib 31905909babSEran Ben Elisha for (j = 0; j < priv->max_opened_tc; j++) { 32005909babSEran Ben Elisha struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 32119386177SKamal Heib 32219386177SKamal Heib s->tx_packets += sq_stats->packets; 32319386177SKamal Heib s->tx_bytes += sq_stats->bytes; 32419386177SKamal Heib s->tx_tso_packets += sq_stats->tso_packets; 32519386177SKamal Heib s->tx_tso_bytes += sq_stats->tso_bytes; 32619386177SKamal Heib s->tx_tso_inner_packets += sq_stats->tso_inner_packets; 32719386177SKamal Heib s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; 32819386177SKamal Heib s->tx_added_vlan_packets += sq_stats->added_vlan_packets; 3292ad9ecdbSTariq Toukan s->tx_nop += sq_stats->nop; 33019386177SKamal Heib s->tx_queue_stopped += sq_stats->stopped; 33119386177SKamal Heib s->tx_queue_wake += sq_stats->wake; 33219386177SKamal Heib s->tx_queue_dropped += sq_stats->dropped; 33316cc14d8SEran Ben Elisha s->tx_cqe_err += sq_stats->cqe_err; 334db75373cSEran Ben Elisha s->tx_recover += sq_stats->recover; 33519386177SKamal Heib s->tx_xmit_more += sq_stats->xmit_more; 33619386177SKamal Heib s->tx_csum_partial_inner += sq_stats->csum_partial_inner; 33719386177SKamal Heib s->tx_csum_none += sq_stats->csum_none; 33819386177SKamal Heib s->tx_csum_partial += sq_stats->csum_partial; 339bf239741SIlya Lesokhin #ifdef CONFIG_MLX5_EN_TLS 340d2ead1f3STariq Toukan s->tx_tls_encrypted_packets += sq_stats->tls_encrypted_packets; 341d2ead1f3STariq Toukan s->tx_tls_encrypted_bytes += sq_stats->tls_encrypted_bytes; 342d2ead1f3STariq Toukan s->tx_tls_ctx += sq_stats->tls_ctx; 343bf239741SIlya Lesokhin s->tx_tls_ooo += sq_stats->tls_ooo; 344d2ead1f3STariq Toukan s->tx_tls_dump_bytes += sq_stats->tls_dump_bytes; 345d2ead1f3STariq Toukan s->tx_tls_dump_packets += sq_stats->tls_dump_packets; 34646a3ea98STariq Toukan s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes; 34746a3ea98STariq Toukan s->tx_tls_skip_no_sync_data += sq_stats->tls_skip_no_sync_data; 34846a3ea98STariq Toukan s->tx_tls_drop_no_sync_data += sq_stats->tls_drop_no_sync_data; 34946a3ea98STariq Toukan s->tx_tls_drop_bypass_req += sq_stats->tls_drop_bypass_req; 350bf239741SIlya Lesokhin #endif 35186155656STariq Toukan s->tx_cqes += sq_stats->cqes; 35242ae1a5cSArnd Bergmann 35342ae1a5cSArnd Bergmann /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */ 35442ae1a5cSArnd Bergmann barrier(); 35519386177SKamal Heib } 35619386177SKamal Heib } 35719386177SKamal Heib } 35819386177SKamal Heib 359fd8dcdb8SKamal Heib static const struct counter_desc q_stats_desc[] = { 360fd8dcdb8SKamal Heib { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) }, 361fd8dcdb8SKamal Heib }; 362fd8dcdb8SKamal Heib 3637cbaf9a3SMoshe Shemesh static const struct counter_desc drop_rq_stats_desc[] = { 3647cbaf9a3SMoshe Shemesh { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) }, 3657cbaf9a3SMoshe Shemesh }; 3667cbaf9a3SMoshe Shemesh 367fd8dcdb8SKamal Heib #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc) 3687cbaf9a3SMoshe Shemesh #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc) 369fd8dcdb8SKamal Heib 37096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qcnt) 371fd8dcdb8SKamal Heib { 3727cbaf9a3SMoshe Shemesh int num_stats = 0; 3737cbaf9a3SMoshe Shemesh 3747cbaf9a3SMoshe Shemesh if (priv->q_counter) 3757cbaf9a3SMoshe Shemesh num_stats += NUM_Q_COUNTERS; 3767cbaf9a3SMoshe Shemesh 3777cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter) 3787cbaf9a3SMoshe Shemesh num_stats += NUM_DROP_RQ_COUNTERS; 3797cbaf9a3SMoshe Shemesh 3807cbaf9a3SMoshe Shemesh return num_stats; 381fd8dcdb8SKamal Heib } 382fd8dcdb8SKamal Heib 38396b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qcnt) 384fd8dcdb8SKamal Heib { 385fd8dcdb8SKamal Heib int i; 386fd8dcdb8SKamal Heib 387fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 3887cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 3897cbaf9a3SMoshe Shemesh q_stats_desc[i].format); 3907cbaf9a3SMoshe Shemesh 3917cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 3927cbaf9a3SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 3937cbaf9a3SMoshe Shemesh drop_rq_stats_desc[i].format); 3947cbaf9a3SMoshe Shemesh 395fd8dcdb8SKamal Heib return idx; 396fd8dcdb8SKamal Heib } 397fd8dcdb8SKamal Heib 39896b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt) 399fd8dcdb8SKamal Heib { 400fd8dcdb8SKamal Heib int i; 401fd8dcdb8SKamal Heib 402fd8dcdb8SKamal Heib for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 4037cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 4047cbaf9a3SMoshe Shemesh q_stats_desc, i); 4057cbaf9a3SMoshe Shemesh for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 4067cbaf9a3SMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 4077cbaf9a3SMoshe Shemesh drop_rq_stats_desc, i); 408fd8dcdb8SKamal Heib return idx; 409fd8dcdb8SKamal Heib } 410fd8dcdb8SKamal Heib 41196b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt) 41219386177SKamal Heib { 41319386177SKamal Heib struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; 41419386177SKamal Heib u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; 41519386177SKamal Heib 4167cbaf9a3SMoshe Shemesh if (priv->q_counter && 4177cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, 4187cbaf9a3SMoshe Shemesh sizeof(out))) 4197cbaf9a3SMoshe Shemesh qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, 4207cbaf9a3SMoshe Shemesh out, out_of_buffer); 4217cbaf9a3SMoshe Shemesh if (priv->drop_rq_q_counter && 4227cbaf9a3SMoshe Shemesh !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0, 4237cbaf9a3SMoshe Shemesh out, sizeof(out))) 4247cbaf9a3SMoshe Shemesh qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out, 4257cbaf9a3SMoshe Shemesh out_of_buffer); 42619386177SKamal Heib } 42719386177SKamal Heib 4285c298143SMoshe Shemesh #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c) 4290cfafd4bSMoshe Shemesh static const struct counter_desc vnic_env_stats_steer_desc[] = { 4305c298143SMoshe Shemesh { "rx_steer_missed_packets", 4315c298143SMoshe Shemesh VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) }, 4325c298143SMoshe Shemesh }; 4335c298143SMoshe Shemesh 4340cfafd4bSMoshe Shemesh static const struct counter_desc vnic_env_stats_dev_oob_desc[] = { 4350cfafd4bSMoshe Shemesh { "dev_internal_queue_oob", 4360cfafd4bSMoshe Shemesh VNIC_ENV_OFF(vport_env.internal_rq_out_of_buffer) }, 4370cfafd4bSMoshe Shemesh }; 4380cfafd4bSMoshe Shemesh 4390cfafd4bSMoshe Shemesh #define NUM_VNIC_ENV_STEER_COUNTERS(dev) \ 4400cfafd4bSMoshe Shemesh (MLX5_CAP_GEN(dev, nic_receive_steering_discard) ? \ 4410cfafd4bSMoshe Shemesh ARRAY_SIZE(vnic_env_stats_steer_desc) : 0) 4420cfafd4bSMoshe Shemesh #define NUM_VNIC_ENV_DEV_OOB_COUNTERS(dev) \ 4430cfafd4bSMoshe Shemesh (MLX5_CAP_GEN(dev, vnic_env_int_rq_oob) ? \ 4440cfafd4bSMoshe Shemesh ARRAY_SIZE(vnic_env_stats_dev_oob_desc) : 0) 4455c298143SMoshe Shemesh 44696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vnic_env) 4475c298143SMoshe Shemesh { 4480cfafd4bSMoshe Shemesh return NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev) + 4490cfafd4bSMoshe Shemesh NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); 4505c298143SMoshe Shemesh } 4515c298143SMoshe Shemesh 45296b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vnic_env) 4535c298143SMoshe Shemesh { 4545c298143SMoshe Shemesh int i; 4555c298143SMoshe Shemesh 4560cfafd4bSMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++) 4575c298143SMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 4580cfafd4bSMoshe Shemesh vnic_env_stats_steer_desc[i].format); 4590cfafd4bSMoshe Shemesh 4600cfafd4bSMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++) 4610cfafd4bSMoshe Shemesh strcpy(data + (idx++) * ETH_GSTRING_LEN, 4620cfafd4bSMoshe Shemesh vnic_env_stats_dev_oob_desc[i].format); 4635c298143SMoshe Shemesh return idx; 4645c298143SMoshe Shemesh } 4655c298143SMoshe Shemesh 46696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env) 4675c298143SMoshe Shemesh { 4685c298143SMoshe Shemesh int i; 4695c298143SMoshe Shemesh 4700cfafd4bSMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++) 4715c298143SMoshe Shemesh data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out, 4720cfafd4bSMoshe Shemesh vnic_env_stats_steer_desc, i); 4730cfafd4bSMoshe Shemesh 4740cfafd4bSMoshe Shemesh for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++) 4750cfafd4bSMoshe Shemesh data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out, 4760cfafd4bSMoshe Shemesh vnic_env_stats_dev_oob_desc, i); 4775c298143SMoshe Shemesh return idx; 4785c298143SMoshe Shemesh } 4795c298143SMoshe Shemesh 48096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env) 4815c298143SMoshe Shemesh { 4825c298143SMoshe Shemesh u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out; 4835c298143SMoshe Shemesh int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out); 4845c298143SMoshe Shemesh u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; 4855c298143SMoshe Shemesh struct mlx5_core_dev *mdev = priv->mdev; 4865c298143SMoshe Shemesh 4875c298143SMoshe Shemesh if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 4885c298143SMoshe Shemesh return; 4895c298143SMoshe Shemesh 4905c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, opcode, 4915c298143SMoshe Shemesh MLX5_CMD_OP_QUERY_VNIC_ENV); 4925c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, op_mod, 0); 4935c298143SMoshe Shemesh MLX5_SET(query_vnic_env_in, in, other_vport, 0); 4945c298143SMoshe Shemesh mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 4955c298143SMoshe Shemesh } 4965c298143SMoshe Shemesh 49740cab9f1SKamal Heib #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) 49840cab9f1SKamal Heib static const struct counter_desc vport_stats_desc[] = { 49940cab9f1SKamal Heib { "rx_vport_unicast_packets", 50040cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.packets) }, 50140cab9f1SKamal Heib { "rx_vport_unicast_bytes", 50240cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_unicast.octets) }, 50340cab9f1SKamal Heib { "tx_vport_unicast_packets", 50440cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) }, 50540cab9f1SKamal Heib { "tx_vport_unicast_bytes", 50640cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) }, 50740cab9f1SKamal Heib { "rx_vport_multicast_packets", 50840cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.packets) }, 50940cab9f1SKamal Heib { "rx_vport_multicast_bytes", 51040cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_multicast.octets) }, 51140cab9f1SKamal Heib { "tx_vport_multicast_packets", 51240cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) }, 51340cab9f1SKamal Heib { "tx_vport_multicast_bytes", 51440cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) }, 51540cab9f1SKamal Heib { "rx_vport_broadcast_packets", 51640cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.packets) }, 51740cab9f1SKamal Heib { "rx_vport_broadcast_bytes", 51840cab9f1SKamal Heib VPORT_COUNTER_OFF(received_eth_broadcast.octets) }, 51940cab9f1SKamal Heib { "tx_vport_broadcast_packets", 52040cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) }, 52140cab9f1SKamal Heib { "tx_vport_broadcast_bytes", 52240cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) }, 52340cab9f1SKamal Heib { "rx_vport_rdma_unicast_packets", 52440cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.packets) }, 52540cab9f1SKamal Heib { "rx_vport_rdma_unicast_bytes", 52640cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_unicast.octets) }, 52740cab9f1SKamal Heib { "tx_vport_rdma_unicast_packets", 52840cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) }, 52940cab9f1SKamal Heib { "tx_vport_rdma_unicast_bytes", 53040cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) }, 53140cab9f1SKamal Heib { "rx_vport_rdma_multicast_packets", 53240cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.packets) }, 53340cab9f1SKamal Heib { "rx_vport_rdma_multicast_bytes", 53440cab9f1SKamal Heib VPORT_COUNTER_OFF(received_ib_multicast.octets) }, 53540cab9f1SKamal Heib { "tx_vport_rdma_multicast_packets", 53640cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) }, 53740cab9f1SKamal Heib { "tx_vport_rdma_multicast_bytes", 53840cab9f1SKamal Heib VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) }, 53940cab9f1SKamal Heib }; 54040cab9f1SKamal Heib 54140cab9f1SKamal Heib #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc) 54240cab9f1SKamal Heib 54396b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport) 54440cab9f1SKamal Heib { 54540cab9f1SKamal Heib return NUM_VPORT_COUNTERS; 54640cab9f1SKamal Heib } 54740cab9f1SKamal Heib 54896b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport) 54940cab9f1SKamal Heib { 55040cab9f1SKamal Heib int i; 55140cab9f1SKamal Heib 55240cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 55340cab9f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format); 55440cab9f1SKamal Heib return idx; 55540cab9f1SKamal Heib } 55640cab9f1SKamal Heib 55796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport) 55840cab9f1SKamal Heib { 55940cab9f1SKamal Heib int i; 56040cab9f1SKamal Heib 56140cab9f1SKamal Heib for (i = 0; i < NUM_VPORT_COUNTERS; i++) 56240cab9f1SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out, 56340cab9f1SKamal Heib vport_stats_desc, i); 56440cab9f1SKamal Heib return idx; 56540cab9f1SKamal Heib } 56640cab9f1SKamal Heib 56796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport) 56819386177SKamal Heib { 56919386177SKamal Heib int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 57019386177SKamal Heib u32 *out = (u32 *)priv->stats.vport.query_vport_out; 57119386177SKamal Heib u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; 57219386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 57319386177SKamal Heib 57419386177SKamal Heib MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER); 57519386177SKamal Heib MLX5_SET(query_vport_counter_in, in, op_mod, 0); 57619386177SKamal Heib MLX5_SET(query_vport_counter_in, in, other_vport, 0); 57719386177SKamal Heib mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 57819386177SKamal Heib } 57919386177SKamal Heib 5806e6ef814SKamal Heib #define PPORT_802_3_OFF(c) \ 5816e6ef814SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 5826e6ef814SKamal Heib counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 5836e6ef814SKamal Heib static const struct counter_desc pport_802_3_stats_desc[] = { 5846e6ef814SKamal Heib { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) }, 5856e6ef814SKamal Heib { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) }, 5866e6ef814SKamal Heib { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) }, 5876e6ef814SKamal Heib { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) }, 5886e6ef814SKamal Heib { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) }, 5896e6ef814SKamal Heib { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) }, 5906e6ef814SKamal Heib { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) }, 5916e6ef814SKamal Heib { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) }, 5926e6ef814SKamal Heib { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) }, 5936e6ef814SKamal Heib { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) }, 5946e6ef814SKamal Heib { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) }, 5956e6ef814SKamal Heib { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) }, 5966e6ef814SKamal Heib { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) }, 5976e6ef814SKamal Heib { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) }, 5986e6ef814SKamal Heib { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) }, 5996e6ef814SKamal Heib { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) }, 6006e6ef814SKamal Heib { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) }, 6016e6ef814SKamal Heib { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) }, 6026e6ef814SKamal Heib }; 6036e6ef814SKamal Heib 6046e6ef814SKamal Heib #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc) 6056e6ef814SKamal Heib 60696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(802_3) 6076e6ef814SKamal Heib { 6086e6ef814SKamal Heib return NUM_PPORT_802_3_COUNTERS; 6096e6ef814SKamal Heib } 6106e6ef814SKamal Heib 61196b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(802_3) 6126e6ef814SKamal Heib { 6136e6ef814SKamal Heib int i; 6146e6ef814SKamal Heib 6156e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 6166e6ef814SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format); 6176e6ef814SKamal Heib return idx; 6186e6ef814SKamal Heib } 6196e6ef814SKamal Heib 62096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3) 6216e6ef814SKamal Heib { 6226e6ef814SKamal Heib int i; 6236e6ef814SKamal Heib 6246e6ef814SKamal Heib for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 6256e6ef814SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters, 6266e6ef814SKamal Heib pport_802_3_stats_desc, i); 6276e6ef814SKamal Heib return idx; 6286e6ef814SKamal Heib } 6296e6ef814SKamal Heib 63075370eb0SEyal Davidovich #define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \ 63175370eb0SEyal Davidovich (MLX5_CAP_GEN(mdev, pcam_reg) ? MLX5_CAP_PCAM_REG(mdev, ppcnt) : 1) 63275370eb0SEyal Davidovich 6337c453526SVlad Buslov static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3) 63419386177SKamal Heib { 63519386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 63619386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 63719386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 63819386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 63919386177SKamal Heib void *out; 64019386177SKamal Heib 64175370eb0SEyal Davidovich if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 64275370eb0SEyal Davidovich return; 64375370eb0SEyal Davidovich 64419386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 64519386177SKamal Heib out = pstats->IEEE_802_3_counters; 64619386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 64719386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 64819386177SKamal Heib } 64919386177SKamal Heib 650fc8e64a3SKamal Heib #define PPORT_2863_OFF(c) \ 651fc8e64a3SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 652fc8e64a3SKamal Heib counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 653fc8e64a3SKamal Heib static const struct counter_desc pport_2863_stats_desc[] = { 654fc8e64a3SKamal Heib { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) }, 655fc8e64a3SKamal Heib { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) }, 656fc8e64a3SKamal Heib { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) }, 657fc8e64a3SKamal Heib }; 658fc8e64a3SKamal Heib 659fc8e64a3SKamal Heib #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc) 660fc8e64a3SKamal Heib 66196b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2863) 662fc8e64a3SKamal Heib { 663fc8e64a3SKamal Heib return NUM_PPORT_2863_COUNTERS; 664fc8e64a3SKamal Heib } 665fc8e64a3SKamal Heib 66696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2863) 667fc8e64a3SKamal Heib { 668fc8e64a3SKamal Heib int i; 669fc8e64a3SKamal Heib 670fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 671fc8e64a3SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format); 672fc8e64a3SKamal Heib return idx; 673fc8e64a3SKamal Heib } 674fc8e64a3SKamal Heib 67596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2863) 676fc8e64a3SKamal Heib { 677fc8e64a3SKamal Heib int i; 678fc8e64a3SKamal Heib 679fc8e64a3SKamal Heib for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 680fc8e64a3SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters, 681fc8e64a3SKamal Heib pport_2863_stats_desc, i); 682fc8e64a3SKamal Heib return idx; 683fc8e64a3SKamal Heib } 684fc8e64a3SKamal Heib 68596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2863) 68619386177SKamal Heib { 68719386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 68819386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 68919386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 69019386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 69119386177SKamal Heib void *out; 69219386177SKamal Heib 69319386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 69419386177SKamal Heib out = pstats->RFC_2863_counters; 69519386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 69619386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 69719386177SKamal Heib } 69819386177SKamal Heib 699e0e0def9SKamal Heib #define PPORT_2819_OFF(c) \ 700e0e0def9SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 701e0e0def9SKamal Heib counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 702e0e0def9SKamal Heib static const struct counter_desc pport_2819_stats_desc[] = { 703e0e0def9SKamal Heib { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) }, 704e0e0def9SKamal Heib { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) }, 705e0e0def9SKamal Heib { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) }, 706e0e0def9SKamal Heib { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) }, 707e0e0def9SKamal Heib { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) }, 708e0e0def9SKamal Heib { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) }, 709e0e0def9SKamal Heib { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) }, 710e0e0def9SKamal Heib { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) }, 711e0e0def9SKamal Heib { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) }, 712e0e0def9SKamal Heib { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) }, 713e0e0def9SKamal Heib { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) }, 714e0e0def9SKamal Heib { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) }, 715e0e0def9SKamal Heib { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) }, 716e0e0def9SKamal Heib }; 717e0e0def9SKamal Heib 718e0e0def9SKamal Heib #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc) 719e0e0def9SKamal Heib 72096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2819) 721e0e0def9SKamal Heib { 722e0e0def9SKamal Heib return NUM_PPORT_2819_COUNTERS; 723e0e0def9SKamal Heib } 724e0e0def9SKamal Heib 72596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2819) 726e0e0def9SKamal Heib { 727e0e0def9SKamal Heib int i; 728e0e0def9SKamal Heib 729e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 730e0e0def9SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format); 731e0e0def9SKamal Heib return idx; 732e0e0def9SKamal Heib } 733e0e0def9SKamal Heib 73496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2819) 735e0e0def9SKamal Heib { 736e0e0def9SKamal Heib int i; 737e0e0def9SKamal Heib 738e0e0def9SKamal Heib for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 739e0e0def9SKamal Heib data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters, 740e0e0def9SKamal Heib pport_2819_stats_desc, i); 741e0e0def9SKamal Heib return idx; 742e0e0def9SKamal Heib } 743e0e0def9SKamal Heib 74496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2819) 74519386177SKamal Heib { 74619386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 74719386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 74819386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 74919386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 75019386177SKamal Heib void *out; 75119386177SKamal Heib 75275370eb0SEyal Davidovich if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 75375370eb0SEyal Davidovich return; 75475370eb0SEyal Davidovich 75519386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 75619386177SKamal Heib out = pstats->RFC_2819_counters; 75719386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 75819386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 75919386177SKamal Heib } 76019386177SKamal Heib 7612e4df0b2SKamal Heib #define PPORT_PHY_STATISTICAL_OFF(c) \ 7622e4df0b2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 7632e4df0b2SKamal Heib counter_set.phys_layer_statistical_cntrs.c##_high) 7642e4df0b2SKamal Heib static const struct counter_desc pport_phy_statistical_stats_desc[] = { 7652e4df0b2SKamal Heib { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) }, 7662e4df0b2SKamal Heib { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) }, 7672e4df0b2SKamal Heib }; 7682e4df0b2SKamal Heib 7694cb4e98eSShay Agroskin static const struct counter_desc 7704cb4e98eSShay Agroskin pport_phy_statistical_err_lanes_stats_desc[] = { 7714cb4e98eSShay Agroskin { "rx_err_lane_0_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane0) }, 7724cb4e98eSShay Agroskin { "rx_err_lane_1_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane1) }, 7734cb4e98eSShay Agroskin { "rx_err_lane_2_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane2) }, 7744cb4e98eSShay Agroskin { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, 7754cb4e98eSShay Agroskin }; 7764cb4e98eSShay Agroskin 7774cb4e98eSShay Agroskin #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ 7784cb4e98eSShay Agroskin ARRAY_SIZE(pport_phy_statistical_stats_desc) 7794cb4e98eSShay Agroskin #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ 7804cb4e98eSShay Agroskin ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) 7812e4df0b2SKamal Heib 78296b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) 7832e4df0b2SKamal Heib { 7844cb4e98eSShay Agroskin struct mlx5_core_dev *mdev = priv->mdev; 7854cb4e98eSShay Agroskin int num_stats; 7864cb4e98eSShay Agroskin 7876ab75516SSaeed Mahameed /* "1" for link_down_events special counter */ 7884cb4e98eSShay Agroskin num_stats = 1; 7894cb4e98eSShay Agroskin 7904cb4e98eSShay Agroskin num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? 7914cb4e98eSShay Agroskin NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; 7924cb4e98eSShay Agroskin 7934cb4e98eSShay Agroskin num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ? 7944cb4e98eSShay Agroskin NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0; 7954cb4e98eSShay Agroskin 7964cb4e98eSShay Agroskin return num_stats; 7972e4df0b2SKamal Heib } 7982e4df0b2SKamal Heib 79996b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) 8002e4df0b2SKamal Heib { 8014cb4e98eSShay Agroskin struct mlx5_core_dev *mdev = priv->mdev; 8022e4df0b2SKamal Heib int i; 8032e4df0b2SKamal Heib 8046ab75516SSaeed Mahameed strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy"); 8056ab75516SSaeed Mahameed 8064cb4e98eSShay Agroskin if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 8076ab75516SSaeed Mahameed return idx; 8086ab75516SSaeed Mahameed 8096ab75516SSaeed Mahameed for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 8102e4df0b2SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 8112e4df0b2SKamal Heib pport_phy_statistical_stats_desc[i].format); 8124cb4e98eSShay Agroskin 8134cb4e98eSShay Agroskin if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) 8144cb4e98eSShay Agroskin for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) 8154cb4e98eSShay Agroskin strcpy(data + (idx++) * ETH_GSTRING_LEN, 8164cb4e98eSShay Agroskin pport_phy_statistical_err_lanes_stats_desc[i].format); 8174cb4e98eSShay Agroskin 8182e4df0b2SKamal Heib return idx; 8192e4df0b2SKamal Heib } 8202e4df0b2SKamal Heib 82196b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) 8222e4df0b2SKamal Heib { 8234cb4e98eSShay Agroskin struct mlx5_core_dev *mdev = priv->mdev; 8242e4df0b2SKamal Heib int i; 8252e4df0b2SKamal Heib 8266ab75516SSaeed Mahameed /* link_down_events_phy has special handling since it is not stored in __be64 format */ 8276ab75516SSaeed Mahameed data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, 8286ab75516SSaeed Mahameed counter_set.phys_layer_cntrs.link_down_events); 8296ab75516SSaeed Mahameed 8304cb4e98eSShay Agroskin if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 8316ab75516SSaeed Mahameed return idx; 8326ab75516SSaeed Mahameed 8336ab75516SSaeed Mahameed for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 8342e4df0b2SKamal Heib data[idx++] = 8352e4df0b2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 8362e4df0b2SKamal Heib pport_phy_statistical_stats_desc, i); 8374cb4e98eSShay Agroskin 8384cb4e98eSShay Agroskin if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) 8394cb4e98eSShay Agroskin for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) 8404cb4e98eSShay Agroskin data[idx++] = 8414cb4e98eSShay Agroskin MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 8424cb4e98eSShay Agroskin pport_phy_statistical_err_lanes_stats_desc, 8434cb4e98eSShay Agroskin i); 8442e4df0b2SKamal Heib return idx; 8452e4df0b2SKamal Heib } 8462e4df0b2SKamal Heib 84796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) 84819386177SKamal Heib { 84919386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 85019386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 85119386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 85219386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 85319386177SKamal Heib void *out; 85419386177SKamal Heib 85519386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 85619386177SKamal Heib out = pstats->phy_counters; 85719386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 85819386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 85919386177SKamal Heib 86019386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 86119386177SKamal Heib return; 86219386177SKamal Heib 86319386177SKamal Heib out = pstats->phy_statistical_counters; 86419386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 86519386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 86619386177SKamal Heib } 86719386177SKamal Heib 8683488bd4cSKamal Heib #define PPORT_ETH_EXT_OFF(c) \ 8693488bd4cSKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 8703488bd4cSKamal Heib counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 8713488bd4cSKamal Heib static const struct counter_desc pport_eth_ext_stats_desc[] = { 8723488bd4cSKamal Heib { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) }, 8733488bd4cSKamal Heib }; 8743488bd4cSKamal Heib 8753488bd4cSKamal Heib #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc) 8763488bd4cSKamal Heib 87796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(eth_ext) 8783488bd4cSKamal Heib { 8793488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 8803488bd4cSKamal Heib return NUM_PPORT_ETH_EXT_COUNTERS; 8813488bd4cSKamal Heib 8823488bd4cSKamal Heib return 0; 8833488bd4cSKamal Heib } 8843488bd4cSKamal Heib 88596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(eth_ext) 8863488bd4cSKamal Heib { 8873488bd4cSKamal Heib int i; 8883488bd4cSKamal Heib 8893488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 8903488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 8913488bd4cSKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 8923488bd4cSKamal Heib pport_eth_ext_stats_desc[i].format); 8933488bd4cSKamal Heib return idx; 8943488bd4cSKamal Heib } 8953488bd4cSKamal Heib 89696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext) 8973488bd4cSKamal Heib { 8983488bd4cSKamal Heib int i; 8993488bd4cSKamal Heib 9003488bd4cSKamal Heib if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 9013488bd4cSKamal Heib for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 9023488bd4cSKamal Heib data[idx++] = 9033488bd4cSKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters, 9043488bd4cSKamal Heib pport_eth_ext_stats_desc, i); 9053488bd4cSKamal Heib return idx; 9063488bd4cSKamal Heib } 9073488bd4cSKamal Heib 90896b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext) 90919386177SKamal Heib { 91019386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 91119386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 91219386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 91319386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 91419386177SKamal Heib void *out; 91519386177SKamal Heib 91619386177SKamal Heib if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) 91719386177SKamal Heib return; 91819386177SKamal Heib 91919386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 92019386177SKamal Heib out = pstats->eth_ext_counters; 92119386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 92219386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 92319386177SKamal Heib } 92419386177SKamal Heib 9259fd2b5f1SKamal Heib #define PCIE_PERF_OFF(c) \ 9269fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c) 9279fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc[] = { 9289fd2b5f1SKamal Heib { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) }, 9299fd2b5f1SKamal Heib { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) }, 9309fd2b5f1SKamal Heib }; 9319fd2b5f1SKamal Heib 9329fd2b5f1SKamal Heib #define PCIE_PERF_OFF64(c) \ 9339fd2b5f1SKamal Heib MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 9349fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stats_desc64[] = { 9359fd2b5f1SKamal Heib { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) }, 9369fd2b5f1SKamal Heib }; 9379fd2b5f1SKamal Heib 9389fd2b5f1SKamal Heib static const struct counter_desc pcie_perf_stall_stats_desc[] = { 9399fd2b5f1SKamal Heib { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) }, 9409fd2b5f1SKamal Heib { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) }, 9419fd2b5f1SKamal Heib { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) }, 9429fd2b5f1SKamal Heib { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) }, 9439fd2b5f1SKamal Heib }; 9449fd2b5f1SKamal Heib 9459fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc) 9469fd2b5f1SKamal Heib #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64) 9479fd2b5f1SKamal Heib #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc) 9489fd2b5f1SKamal Heib 94996b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie) 9509fd2b5f1SKamal Heib { 9519fd2b5f1SKamal Heib int num_stats = 0; 9529fd2b5f1SKamal Heib 9539fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 9549fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS; 9559fd2b5f1SKamal Heib 9569fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 9579fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_COUNTERS64; 9589fd2b5f1SKamal Heib 9599fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 9609fd2b5f1SKamal Heib num_stats += NUM_PCIE_PERF_STALL_COUNTERS; 9619fd2b5f1SKamal Heib 9629fd2b5f1SKamal Heib return num_stats; 9639fd2b5f1SKamal Heib } 9649fd2b5f1SKamal Heib 96596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie) 9669fd2b5f1SKamal Heib { 9679fd2b5f1SKamal Heib int i; 9689fd2b5f1SKamal Heib 9699fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 9709fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 9719fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 9729fd2b5f1SKamal Heib pcie_perf_stats_desc[i].format); 9739fd2b5f1SKamal Heib 9749fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 9759fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 9769fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 9779fd2b5f1SKamal Heib pcie_perf_stats_desc64[i].format); 9789fd2b5f1SKamal Heib 9799fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 9809fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 9819fd2b5f1SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, 9829fd2b5f1SKamal Heib pcie_perf_stall_stats_desc[i].format); 9839fd2b5f1SKamal Heib return idx; 9849fd2b5f1SKamal Heib } 9859fd2b5f1SKamal Heib 98696b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie) 9879fd2b5f1SKamal Heib { 9889fd2b5f1SKamal Heib int i; 9899fd2b5f1SKamal Heib 9909fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 9919fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 9929fd2b5f1SKamal Heib data[idx++] = 9939fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 9949fd2b5f1SKamal Heib pcie_perf_stats_desc, i); 9959fd2b5f1SKamal Heib 9969fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 9979fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 9989fd2b5f1SKamal Heib data[idx++] = 9999fd2b5f1SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters, 10009fd2b5f1SKamal Heib pcie_perf_stats_desc64, i); 10019fd2b5f1SKamal Heib 10029fd2b5f1SKamal Heib if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 10039fd2b5f1SKamal Heib for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 10049fd2b5f1SKamal Heib data[idx++] = 10059fd2b5f1SKamal Heib MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 10069fd2b5f1SKamal Heib pcie_perf_stall_stats_desc, i); 10079fd2b5f1SKamal Heib return idx; 10089fd2b5f1SKamal Heib } 10099fd2b5f1SKamal Heib 101096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie) 101119386177SKamal Heib { 101219386177SKamal Heib struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; 101319386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 101419386177SKamal Heib u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; 101519386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 101619386177SKamal Heib void *out; 101719386177SKamal Heib 101819386177SKamal Heib if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) 101919386177SKamal Heib return; 102019386177SKamal Heib 102119386177SKamal Heib out = pcie_stats->pcie_perf_counters; 102219386177SKamal Heib MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 102319386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 102419386177SKamal Heib } 102519386177SKamal Heib 10261297d97fSAya Levin #define PPORT_PER_TC_PRIO_OFF(c) \ 10271297d97fSAya Levin MLX5_BYTE_OFF(ppcnt_reg, \ 10281297d97fSAya Levin counter_set.eth_per_tc_prio_grp_data_layout.c##_high) 10291297d97fSAya Levin 10301297d97fSAya Levin static const struct counter_desc pport_per_tc_prio_stats_desc[] = { 10311297d97fSAya Levin { "rx_prio%d_buf_discard", PPORT_PER_TC_PRIO_OFF(no_buffer_discard_uc) }, 10321297d97fSAya Levin }; 10331297d97fSAya Levin 10341297d97fSAya Levin #define NUM_PPORT_PER_TC_PRIO_COUNTERS ARRAY_SIZE(pport_per_tc_prio_stats_desc) 10351297d97fSAya Levin 10361297d97fSAya Levin #define PPORT_PER_TC_CONGEST_PRIO_OFF(c) \ 10371297d97fSAya Levin MLX5_BYTE_OFF(ppcnt_reg, \ 10381297d97fSAya Levin counter_set.eth_per_tc_congest_prio_grp_data_layout.c##_high) 10391297d97fSAya Levin 10401297d97fSAya Levin static const struct counter_desc pport_per_tc_congest_prio_stats_desc[] = { 10411297d97fSAya Levin { "rx_prio%d_cong_discard", PPORT_PER_TC_CONGEST_PRIO_OFF(wred_discard) }, 10421297d97fSAya Levin { "rx_prio%d_marked", PPORT_PER_TC_CONGEST_PRIO_OFF(ecn_marked_tc) }, 10431297d97fSAya Levin }; 10441297d97fSAya Levin 10451297d97fSAya Levin #define NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS \ 10461297d97fSAya Levin ARRAY_SIZE(pport_per_tc_congest_prio_stats_desc) 10471297d97fSAya Levin 10481297d97fSAya Levin static int mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv *priv) 10491297d97fSAya Levin { 10501297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 10511297d97fSAya Levin 10521297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 10531297d97fSAya Levin return 0; 10541297d97fSAya Levin 10551297d97fSAya Levin return NUM_PPORT_PER_TC_PRIO_COUNTERS * NUM_PPORT_PRIO; 10561297d97fSAya Levin } 10571297d97fSAya Levin 105896b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_port_buff_congest) 10591297d97fSAya Levin { 10601297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 10611297d97fSAya Levin int i, prio; 10621297d97fSAya Levin 10631297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 10641297d97fSAya Levin return idx; 10651297d97fSAya Levin 10661297d97fSAya Levin for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 10671297d97fSAya Levin for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++) 10681297d97fSAya Levin sprintf(data + (idx++) * ETH_GSTRING_LEN, 10691297d97fSAya Levin pport_per_tc_prio_stats_desc[i].format, prio); 10701297d97fSAya Levin for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++) 10711297d97fSAya Levin sprintf(data + (idx++) * ETH_GSTRING_LEN, 10721297d97fSAya Levin pport_per_tc_congest_prio_stats_desc[i].format, prio); 10731297d97fSAya Levin } 10741297d97fSAya Levin 10751297d97fSAya Levin return idx; 10761297d97fSAya Levin } 10771297d97fSAya Levin 107896b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest) 10791297d97fSAya Levin { 10801297d97fSAya Levin struct mlx5e_pport_stats *pport = &priv->stats.pport; 10811297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 10821297d97fSAya Levin int i, prio; 10831297d97fSAya Levin 10841297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 10851297d97fSAya Levin return idx; 10861297d97fSAya Levin 10871297d97fSAya Levin for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 10881297d97fSAya Levin for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++) 10891297d97fSAya Levin data[idx++] = 10901297d97fSAya Levin MLX5E_READ_CTR64_BE(&pport->per_tc_prio_counters[prio], 10911297d97fSAya Levin pport_per_tc_prio_stats_desc, i); 10921297d97fSAya Levin for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++) 10931297d97fSAya Levin data[idx++] = 10941297d97fSAya Levin MLX5E_READ_CTR64_BE(&pport->per_tc_congest_prio_counters[prio], 10951297d97fSAya Levin pport_per_tc_congest_prio_stats_desc, i); 10961297d97fSAya Levin } 10971297d97fSAya Levin 10981297d97fSAya Levin return idx; 10991297d97fSAya Levin } 11001297d97fSAya Levin 11011297d97fSAya Levin static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv) 11021297d97fSAya Levin { 11031297d97fSAya Levin struct mlx5e_pport_stats *pstats = &priv->stats.pport; 11041297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 11051297d97fSAya Levin u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {}; 11061297d97fSAya Levin int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 11071297d97fSAya Levin void *out; 11081297d97fSAya Levin int prio; 11091297d97fSAya Levin 11101297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 11111297d97fSAya Levin return; 11121297d97fSAya Levin 11131297d97fSAya Levin MLX5_SET(ppcnt_reg, in, pnat, 2); 11141297d97fSAya Levin MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP); 11151297d97fSAya Levin for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 11161297d97fSAya Levin out = pstats->per_tc_prio_counters[prio]; 11171297d97fSAya Levin MLX5_SET(ppcnt_reg, in, prio_tc, prio); 11181297d97fSAya Levin mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 11191297d97fSAya Levin } 11201297d97fSAya Levin } 11211297d97fSAya Levin 11221297d97fSAya Levin static int mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv *priv) 11231297d97fSAya Levin { 11241297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 11251297d97fSAya Levin 11261297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 11271297d97fSAya Levin return 0; 11281297d97fSAya Levin 11291297d97fSAya Levin return NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS * NUM_PPORT_PRIO; 11301297d97fSAya Levin } 11311297d97fSAya Levin 11321297d97fSAya Levin static void mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv *priv) 11331297d97fSAya Levin { 11341297d97fSAya Levin struct mlx5e_pport_stats *pstats = &priv->stats.pport; 11351297d97fSAya Levin struct mlx5_core_dev *mdev = priv->mdev; 11361297d97fSAya Levin u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {}; 11371297d97fSAya Levin int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 11381297d97fSAya Levin void *out; 11391297d97fSAya Levin int prio; 11401297d97fSAya Levin 11411297d97fSAya Levin if (!MLX5_CAP_GEN(mdev, sbcam_reg)) 11421297d97fSAya Levin return; 11431297d97fSAya Levin 11441297d97fSAya Levin MLX5_SET(ppcnt_reg, in, pnat, 2); 11451297d97fSAya Levin MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP); 11461297d97fSAya Levin for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 11471297d97fSAya Levin out = pstats->per_tc_congest_prio_counters[prio]; 11481297d97fSAya Levin MLX5_SET(ppcnt_reg, in, prio_tc, prio); 11491297d97fSAya Levin mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 11501297d97fSAya Levin } 11511297d97fSAya Levin } 11521297d97fSAya Levin 115396b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_port_buff_congest) 11541297d97fSAya Levin { 11551297d97fSAya Levin return mlx5e_grp_per_tc_prio_get_num_stats(priv) + 11561297d97fSAya Levin mlx5e_grp_per_tc_congest_prio_get_num_stats(priv); 11571297d97fSAya Levin } 11581297d97fSAya Levin 115996b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_port_buff_congest) 11601297d97fSAya Levin { 11611297d97fSAya Levin mlx5e_grp_per_tc_prio_update_stats(priv); 11621297d97fSAya Levin mlx5e_grp_per_tc_congest_prio_update_stats(priv); 11631297d97fSAya Levin } 11641297d97fSAya Levin 11654377bea2SKamal Heib #define PPORT_PER_PRIO_OFF(c) \ 11664377bea2SKamal Heib MLX5_BYTE_OFF(ppcnt_reg, \ 11674377bea2SKamal Heib counter_set.eth_per_prio_grp_data_layout.c##_high) 1168e6000651SKamal Heib static const struct counter_desc pport_per_prio_traffic_stats_desc[] = { 1169e6000651SKamal Heib { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) }, 1170e6000651SKamal Heib { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) }, 1171827a8cb2SAharon Landau { "rx_prio%d_discards", PPORT_PER_PRIO_OFF(rx_discards) }, 1172e6000651SKamal Heib { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) }, 1173e6000651SKamal Heib { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) }, 1174e6000651SKamal Heib }; 1175e6000651SKamal Heib 1176e6000651SKamal Heib #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc) 1177e6000651SKamal Heib 117854c73f86SYuval Shaia static int mlx5e_grp_per_prio_traffic_get_num_stats(void) 1179e6000651SKamal Heib { 1180e6000651SKamal Heib return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO; 1181e6000651SKamal Heib } 1182e6000651SKamal Heib 1183e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv, 1184e6000651SKamal Heib u8 *data, 1185e6000651SKamal Heib int idx) 1186e6000651SKamal Heib { 1187e6000651SKamal Heib int i, prio; 1188e6000651SKamal Heib 1189e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 1190e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 1191e6000651SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 1192e6000651SKamal Heib pport_per_prio_traffic_stats_desc[i].format, prio); 1193e6000651SKamal Heib } 1194e6000651SKamal Heib 1195e6000651SKamal Heib return idx; 1196e6000651SKamal Heib } 1197e6000651SKamal Heib 1198e6000651SKamal Heib static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv, 1199e6000651SKamal Heib u64 *data, 1200e6000651SKamal Heib int idx) 1201e6000651SKamal Heib { 1202e6000651SKamal Heib int i, prio; 1203e6000651SKamal Heib 1204e6000651SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 1205e6000651SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 1206e6000651SKamal Heib data[idx++] = 1207e6000651SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 1208e6000651SKamal Heib pport_per_prio_traffic_stats_desc, i); 1209e6000651SKamal Heib } 1210e6000651SKamal Heib 1211e6000651SKamal Heib return idx; 1212e6000651SKamal Heib } 1213e6000651SKamal Heib 12144377bea2SKamal Heib static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 12154377bea2SKamal Heib /* %s is "global" or "prio{i}" */ 12164377bea2SKamal Heib { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) }, 12174377bea2SKamal Heib { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) }, 12184377bea2SKamal Heib { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) }, 12194377bea2SKamal Heib { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) }, 12204377bea2SKamal Heib { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, 12214377bea2SKamal Heib }; 12224377bea2SKamal Heib 12232fcb12dfSInbar Karmy static const struct counter_desc pport_pfc_stall_stats_desc[] = { 12242fcb12dfSInbar Karmy { "tx_pause_storm_warning_events", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) }, 12252fcb12dfSInbar Karmy { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) }, 12262fcb12dfSInbar Karmy }; 12272fcb12dfSInbar Karmy 12284377bea2SKamal Heib #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc) 12292fcb12dfSInbar Karmy #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \ 12302fcb12dfSInbar Karmy MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \ 12312fcb12dfSInbar Karmy MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 12324377bea2SKamal Heib 12334377bea2SKamal Heib static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) 12344377bea2SKamal Heib { 12354377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 12364377bea2SKamal Heib u8 pfc_en_tx; 12374377bea2SKamal Heib u8 pfc_en_rx; 12384377bea2SKamal Heib int err; 12394377bea2SKamal Heib 12404377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 12414377bea2SKamal Heib return 0; 12424377bea2SKamal Heib 12434377bea2SKamal Heib err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx); 12444377bea2SKamal Heib 12454377bea2SKamal Heib return err ? 0 : pfc_en_tx | pfc_en_rx; 12464377bea2SKamal Heib } 12474377bea2SKamal Heib 12484377bea2SKamal Heib static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv) 12494377bea2SKamal Heib { 12504377bea2SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 12514377bea2SKamal Heib u32 rx_pause; 12524377bea2SKamal Heib u32 tx_pause; 12534377bea2SKamal Heib int err; 12544377bea2SKamal Heib 12554377bea2SKamal Heib if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 12564377bea2SKamal Heib return false; 12574377bea2SKamal Heib 12584377bea2SKamal Heib err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 12594377bea2SKamal Heib 12604377bea2SKamal Heib return err ? false : rx_pause | tx_pause; 12614377bea2SKamal Heib } 12624377bea2SKamal Heib 12634377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) 12644377bea2SKamal Heib { 12654377bea2SKamal Heib return (mlx5e_query_global_pause_combined(priv) + 12664377bea2SKamal Heib hweight8(mlx5e_query_pfc_combined(priv))) * 12672fcb12dfSInbar Karmy NUM_PPORT_PER_PRIO_PFC_COUNTERS + 12682fcb12dfSInbar Karmy NUM_PPORT_PFC_STALL_COUNTERS(priv); 12694377bea2SKamal Heib } 12704377bea2SKamal Heib 12714377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, 12724377bea2SKamal Heib u8 *data, 12734377bea2SKamal Heib int idx) 12744377bea2SKamal Heib { 12754377bea2SKamal Heib unsigned long pfc_combined; 12764377bea2SKamal Heib int i, prio; 12774377bea2SKamal Heib 12784377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 12794377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 12804377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 12814377bea2SKamal Heib char pfc_string[ETH_GSTRING_LEN]; 12824377bea2SKamal Heib 12834377bea2SKamal Heib snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio); 12844377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 12854377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, pfc_string); 12864377bea2SKamal Heib } 12874377bea2SKamal Heib } 12884377bea2SKamal Heib 12894377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 12904377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 12914377bea2SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 12924377bea2SKamal Heib pport_per_prio_pfc_stats_desc[i].format, "global"); 12934377bea2SKamal Heib } 12944377bea2SKamal Heib } 12954377bea2SKamal Heib 12962fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 12972fcb12dfSInbar Karmy strcpy(data + (idx++) * ETH_GSTRING_LEN, 12982fcb12dfSInbar Karmy pport_pfc_stall_stats_desc[i].format); 12992fcb12dfSInbar Karmy 13004377bea2SKamal Heib return idx; 13014377bea2SKamal Heib } 13024377bea2SKamal Heib 13034377bea2SKamal Heib static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, 13044377bea2SKamal Heib u64 *data, 13054377bea2SKamal Heib int idx) 13064377bea2SKamal Heib { 13074377bea2SKamal Heib unsigned long pfc_combined; 13084377bea2SKamal Heib int i, prio; 13094377bea2SKamal Heib 13104377bea2SKamal Heib pfc_combined = mlx5e_query_pfc_combined(priv); 13114377bea2SKamal Heib for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 13124377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 13134377bea2SKamal Heib data[idx++] = 13144377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 13154377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 13164377bea2SKamal Heib } 13174377bea2SKamal Heib } 13184377bea2SKamal Heib 13194377bea2SKamal Heib if (mlx5e_query_global_pause_combined(priv)) { 13204377bea2SKamal Heib for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 13214377bea2SKamal Heib data[idx++] = 13224377bea2SKamal Heib MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 13234377bea2SKamal Heib pport_per_prio_pfc_stats_desc, i); 13244377bea2SKamal Heib } 13254377bea2SKamal Heib } 13264377bea2SKamal Heib 13272fcb12dfSInbar Karmy for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 13282fcb12dfSInbar Karmy data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 13292fcb12dfSInbar Karmy pport_pfc_stall_stats_desc, i); 13302fcb12dfSInbar Karmy 13314377bea2SKamal Heib return idx; 13324377bea2SKamal Heib } 13334377bea2SKamal Heib 133496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio) 1335a8984281SKamal Heib { 133654c73f86SYuval Shaia return mlx5e_grp_per_prio_traffic_get_num_stats() + 1337a8984281SKamal Heib mlx5e_grp_per_prio_pfc_get_num_stats(priv); 1338a8984281SKamal Heib } 1339a8984281SKamal Heib 134096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio) 1341a8984281SKamal Heib { 1342a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx); 1343a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx); 1344a8984281SKamal Heib return idx; 1345a8984281SKamal Heib } 1346a8984281SKamal Heib 134796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio) 1348a8984281SKamal Heib { 1349a8984281SKamal Heib idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx); 1350a8984281SKamal Heib idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx); 1351a8984281SKamal Heib return idx; 1352a8984281SKamal Heib } 1353a8984281SKamal Heib 135496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio) 135519386177SKamal Heib { 135619386177SKamal Heib struct mlx5e_pport_stats *pstats = &priv->stats.pport; 135719386177SKamal Heib struct mlx5_core_dev *mdev = priv->mdev; 135819386177SKamal Heib u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 135919386177SKamal Heib int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 136019386177SKamal Heib int prio; 136119386177SKamal Heib void *out; 136219386177SKamal Heib 136375370eb0SEyal Davidovich if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 136475370eb0SEyal Davidovich return; 136575370eb0SEyal Davidovich 136619386177SKamal Heib MLX5_SET(ppcnt_reg, in, local_port, 1); 136719386177SKamal Heib MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 136819386177SKamal Heib for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 136919386177SKamal Heib out = pstats->per_prio_counters[prio]; 137019386177SKamal Heib MLX5_SET(ppcnt_reg, in, prio_tc, prio); 137119386177SKamal Heib mlx5_core_access_reg(mdev, in, sz, out, sz, 137219386177SKamal Heib MLX5_REG_PPCNT, 0, 0); 137319386177SKamal Heib } 137419386177SKamal Heib } 137519386177SKamal Heib 13760e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_status_desc[] = { 1377c2fb3db2SMikhael Goikhman { "module_unplug", sizeof(u64) * MLX5_MODULE_STATUS_UNPLUGGED }, 13780e6f01a4SKamal Heib }; 13790e6f01a4SKamal Heib 13800e6f01a4SKamal Heib static const struct counter_desc mlx5e_pme_error_desc[] = { 1381c2fb3db2SMikhael Goikhman { "module_bus_stuck", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BUS_STUCK }, 1382c2fb3db2SMikhael Goikhman { "module_high_temp", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE }, 1383c2fb3db2SMikhael Goikhman { "module_bad_shorted", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BAD_CABLE }, 13840e6f01a4SKamal Heib }; 13850e6f01a4SKamal Heib 13860e6f01a4SKamal Heib #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc) 13870e6f01a4SKamal Heib #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc) 13880e6f01a4SKamal Heib 138996b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pme) 13900e6f01a4SKamal Heib { 13910e6f01a4SKamal Heib return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS; 13920e6f01a4SKamal Heib } 13930e6f01a4SKamal Heib 139496b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pme) 13950e6f01a4SKamal Heib { 13960e6f01a4SKamal Heib int i; 13970e6f01a4SKamal Heib 13980e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 13990e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format); 14000e6f01a4SKamal Heib 14010e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 14020e6f01a4SKamal Heib strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format); 14030e6f01a4SKamal Heib 14040e6f01a4SKamal Heib return idx; 14050e6f01a4SKamal Heib } 14060e6f01a4SKamal Heib 140796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme) 14080e6f01a4SKamal Heib { 140969c1280bSSaeed Mahameed struct mlx5_pme_stats pme_stats; 14100e6f01a4SKamal Heib int i; 14110e6f01a4SKamal Heib 141269c1280bSSaeed Mahameed mlx5_get_pme_stats(priv->mdev, &pme_stats); 141369c1280bSSaeed Mahameed 14140e6f01a4SKamal Heib for (i = 0; i < NUM_PME_STATUS_STATS; i++) 141569c1280bSSaeed Mahameed data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.status_counters, 14160e6f01a4SKamal Heib mlx5e_pme_status_desc, i); 14170e6f01a4SKamal Heib 14180e6f01a4SKamal Heib for (i = 0; i < NUM_PME_ERR_STATS; i++) 141969c1280bSSaeed Mahameed data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.error_counters, 14200e6f01a4SKamal Heib mlx5e_pme_error_desc, i); 14210e6f01a4SKamal Heib 14220e6f01a4SKamal Heib return idx; 14230e6f01a4SKamal Heib } 14240e6f01a4SKamal Heib 142596b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme) { return; } 142696b12796SSaeed Mahameed 142796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(tls) 142843585a41SIlya Lesokhin { 142943585a41SIlya Lesokhin return mlx5e_tls_get_count(priv); 143043585a41SIlya Lesokhin } 143143585a41SIlya Lesokhin 143296b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls) 143343585a41SIlya Lesokhin { 143443585a41SIlya Lesokhin return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN); 143543585a41SIlya Lesokhin } 143643585a41SIlya Lesokhin 143796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls) 143843585a41SIlya Lesokhin { 143943585a41SIlya Lesokhin return idx + mlx5e_tls_get_stats(priv, data + idx); 144043585a41SIlya Lesokhin } 144143585a41SIlya Lesokhin 144296b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls) { return; } 144396b12796SSaeed Mahameed 14441fe85006SKamal Heib static const struct counter_desc rq_stats_desc[] = { 14451fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) }, 14461fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) }, 14471fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) }, 14480aa1d186SSaeed Mahameed { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) }, 14490aa1d186SSaeed Mahameed { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) }, 14501fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) }, 14511fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 14521fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) }, 14531fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) }, 145486690b4bSTariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) }, 14551fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) }, 14561fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) }, 1457f007c13dSNatali Shechtman { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) }, 1458f24686e8SGal Pressman { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) }, 14591fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) }, 1460b71ba6b4STariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) }, 1461b71ba6b4STariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) }, 14620073c8f7SMoshe Shemesh { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) }, 14631fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 14641fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 14651fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 14661fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) }, 14671fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) }, 14681fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) }, 14691fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) }, 14701fe85006SKamal Heib { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) }, 1471dc983f0eSTariq Toukan { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) }, 147294563847SEran Ben Elisha { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) }, 1473be5323c8SAya Levin { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) }, 14741fe85006SKamal Heib }; 14751fe85006SKamal Heib 14761fe85006SKamal Heib static const struct counter_desc sq_stats_desc[] = { 14771fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) }, 14781fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) }, 14791fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) }, 14801fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) }, 14811fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) }, 14821fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) }, 14831fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) }, 14841fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) }, 1485f24686e8SGal Pressman { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) }, 14861fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) }, 1487d2ead1f3STariq Toukan #ifdef CONFIG_MLX5_EN_TLS 1488d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) }, 1489d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) }, 1490d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ctx) }, 1491d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ooo) }, 1492d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) }, 1493d2ead1f3STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) }, 149446a3ea98STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) }, 149546a3ea98STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) }, 149646a3ea98STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) }, 149746a3ea98STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) }, 1498d2ead1f3STariq Toukan #endif 14991fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) }, 15001fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) }, 15011fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) }, 15021fe85006SKamal Heib { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) }, 1503db75373cSEran Ben Elisha { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) }, 150486155656STariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) }, 1505f65a59ffSTariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) }, 1506f65a59ffSTariq Toukan { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) }, 15071fe85006SKamal Heib }; 15081fe85006SKamal Heib 1509890388adSTariq Toukan static const struct counter_desc rq_xdpsq_stats_desc[] = { 1510890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 151173cab880SShay Agroskin { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) }, 1512c2273219SShay Agroskin { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) }, 15136c085a8aSShay Agroskin { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) }, 1514890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 1515890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 1516890388adSTariq Toukan { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 1517890388adSTariq Toukan }; 1518890388adSTariq Toukan 151958b99ee3STariq Toukan static const struct counter_desc xdpsq_stats_desc[] = { 152058b99ee3STariq Toukan { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 152173cab880SShay Agroskin { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) }, 1522c2273219SShay Agroskin { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) }, 15236c085a8aSShay Agroskin { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) }, 152458b99ee3STariq Toukan { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 152558b99ee3STariq Toukan { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 152658b99ee3STariq Toukan { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 152758b99ee3STariq Toukan }; 152858b99ee3STariq Toukan 1529db05815bSMaxim Mikityanskiy static const struct counter_desc xskrq_stats_desc[] = { 1530db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, packets) }, 1531db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, bytes) }, 1532db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_complete) }, 1533db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) }, 1534db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 1535db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_none) }, 1536db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, ecn_mark) }, 1537db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) }, 1538db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_drop) }, 1539db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_redirect) }, 1540db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, wqe_err) }, 1541db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) }, 1542db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) }, 1543db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) }, 1544db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 1545db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 1546db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 1547db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) }, 1548db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, arfs_err) }, 1549db05815bSMaxim Mikityanskiy }; 1550db05815bSMaxim Mikityanskiy 1551db05815bSMaxim Mikityanskiy static const struct counter_desc xsksq_stats_desc[] = { 1552db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 1553db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) }, 1554db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) }, 1555db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 1556db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 1557db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 1558db05815bSMaxim Mikityanskiy }; 1559db05815bSMaxim Mikityanskiy 156057d689a8SEran Ben Elisha static const struct counter_desc ch_stats_desc[] = { 1561a1bf74dcSTariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) }, 15622d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) }, 15632d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) }, 15642d7103c8STariq Toukan { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) }, 1565db05815bSMaxim Mikityanskiy { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, force_irq) }, 156657d689a8SEran Ben Elisha { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) }, 156757d689a8SEran Ben Elisha }; 156857d689a8SEran Ben Elisha 15691fe85006SKamal Heib #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc) 15701fe85006SKamal Heib #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc) 157158b99ee3STariq Toukan #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc) 1572890388adSTariq Toukan #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc) 1573db05815bSMaxim Mikityanskiy #define NUM_XSKRQ_STATS ARRAY_SIZE(xskrq_stats_desc) 1574db05815bSMaxim Mikityanskiy #define NUM_XSKSQ_STATS ARRAY_SIZE(xsksq_stats_desc) 157557d689a8SEran Ben Elisha #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc) 15761fe85006SKamal Heib 157796b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(channels) 15781fe85006SKamal Heib { 1579694826e3STariq Toukan int max_nch = priv->max_nch; 158005909babSEran Ben Elisha 158105909babSEran Ben Elisha return (NUM_RQ_STATS * max_nch) + 158205909babSEran Ben Elisha (NUM_CH_STATS * max_nch) + 1583890388adSTariq Toukan (NUM_SQ_STATS * max_nch * priv->max_opened_tc) + 158458b99ee3STariq Toukan (NUM_RQ_XDPSQ_STATS * max_nch) + 1585db05815bSMaxim Mikityanskiy (NUM_XDPSQ_STATS * max_nch) + 1586db05815bSMaxim Mikityanskiy (NUM_XSKRQ_STATS * max_nch * priv->xsk.ever_used) + 1587db05815bSMaxim Mikityanskiy (NUM_XSKSQ_STATS * max_nch * priv->xsk.ever_used); 15881fe85006SKamal Heib } 15891fe85006SKamal Heib 159096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(channels) 15911fe85006SKamal Heib { 1592db05815bSMaxim Mikityanskiy bool is_xsk = priv->xsk.ever_used; 1593694826e3STariq Toukan int max_nch = priv->max_nch; 15941fe85006SKamal Heib int i, j, tc; 15951fe85006SKamal Heib 159605909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 159757d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 159857d689a8SEran Ben Elisha sprintf(data + (idx++) * ETH_GSTRING_LEN, 159957d689a8SEran Ben Elisha ch_stats_desc[j].format, i); 160057d689a8SEran Ben Elisha 1601890388adSTariq Toukan for (i = 0; i < max_nch; i++) { 16021fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 1603890388adSTariq Toukan sprintf(data + (idx++) * ETH_GSTRING_LEN, 1604890388adSTariq Toukan rq_stats_desc[j].format, i); 1605db05815bSMaxim Mikityanskiy for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++) 1606db05815bSMaxim Mikityanskiy sprintf(data + (idx++) * ETH_GSTRING_LEN, 1607db05815bSMaxim Mikityanskiy xskrq_stats_desc[j].format, i); 1608890388adSTariq Toukan for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1609890388adSTariq Toukan sprintf(data + (idx++) * ETH_GSTRING_LEN, 1610890388adSTariq Toukan rq_xdpsq_stats_desc[j].format, i); 1611890388adSTariq Toukan } 16121fe85006SKamal Heib 161305909babSEran Ben Elisha for (tc = 0; tc < priv->max_opened_tc; tc++) 161405909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 16151fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 16161fe85006SKamal Heib sprintf(data + (idx++) * ETH_GSTRING_LEN, 16171fe85006SKamal Heib sq_stats_desc[j].format, 1618c55d8b10SEran Ben Elisha i + tc * max_nch); 16191fe85006SKamal Heib 1620db05815bSMaxim Mikityanskiy for (i = 0; i < max_nch; i++) { 1621db05815bSMaxim Mikityanskiy for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++) 1622db05815bSMaxim Mikityanskiy sprintf(data + (idx++) * ETH_GSTRING_LEN, 1623db05815bSMaxim Mikityanskiy xsksq_stats_desc[j].format, i); 162458b99ee3STariq Toukan for (j = 0; j < NUM_XDPSQ_STATS; j++) 162558b99ee3STariq Toukan sprintf(data + (idx++) * ETH_GSTRING_LEN, 162658b99ee3STariq Toukan xdpsq_stats_desc[j].format, i); 1627db05815bSMaxim Mikityanskiy } 162858b99ee3STariq Toukan 16291fe85006SKamal Heib return idx; 16301fe85006SKamal Heib } 16311fe85006SKamal Heib 163296b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels) 16331fe85006SKamal Heib { 1634db05815bSMaxim Mikityanskiy bool is_xsk = priv->xsk.ever_used; 1635694826e3STariq Toukan int max_nch = priv->max_nch; 16361fe85006SKamal Heib int i, j, tc; 16371fe85006SKamal Heib 163805909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 163957d689a8SEran Ben Elisha for (j = 0; j < NUM_CH_STATS; j++) 164057d689a8SEran Ben Elisha data[idx++] = 164105909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch, 164257d689a8SEran Ben Elisha ch_stats_desc, j); 164357d689a8SEran Ben Elisha 1644890388adSTariq Toukan for (i = 0; i < max_nch; i++) { 16451fe85006SKamal Heib for (j = 0; j < NUM_RQ_STATS; j++) 16461fe85006SKamal Heib data[idx++] = 164705909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq, 16481fe85006SKamal Heib rq_stats_desc, j); 1649db05815bSMaxim Mikityanskiy for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++) 1650db05815bSMaxim Mikityanskiy data[idx++] = 1651db05815bSMaxim Mikityanskiy MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xskrq, 1652db05815bSMaxim Mikityanskiy xskrq_stats_desc, j); 1653890388adSTariq Toukan for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1654890388adSTariq Toukan data[idx++] = 1655890388adSTariq Toukan MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq, 1656890388adSTariq Toukan rq_xdpsq_stats_desc, j); 1657890388adSTariq Toukan } 16581fe85006SKamal Heib 165905909babSEran Ben Elisha for (tc = 0; tc < priv->max_opened_tc; tc++) 166005909babSEran Ben Elisha for (i = 0; i < max_nch; i++) 16611fe85006SKamal Heib for (j = 0; j < NUM_SQ_STATS; j++) 16621fe85006SKamal Heib data[idx++] = 166305909babSEran Ben Elisha MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc], 16641fe85006SKamal Heib sq_stats_desc, j); 16651fe85006SKamal Heib 1666db05815bSMaxim Mikityanskiy for (i = 0; i < max_nch; i++) { 1667db05815bSMaxim Mikityanskiy for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++) 1668db05815bSMaxim Mikityanskiy data[idx++] = 1669db05815bSMaxim Mikityanskiy MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xsksq, 1670db05815bSMaxim Mikityanskiy xsksq_stats_desc, j); 167158b99ee3STariq Toukan for (j = 0; j < NUM_XDPSQ_STATS; j++) 167258b99ee3STariq Toukan data[idx++] = 167358b99ee3STariq Toukan MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xdpsq, 167458b99ee3STariq Toukan xdpsq_stats_desc, j); 1675db05815bSMaxim Mikityanskiy } 167658b99ee3STariq Toukan 16771fe85006SKamal Heib return idx; 16781fe85006SKamal Heib } 16791fe85006SKamal Heib 168096b12796SSaeed Mahameed static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels) { return; } 168196b12796SSaeed Mahameed 16822a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(sw, 0); 16832a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(qcnt, MLX5E_NDO_UPDATE_STATS); 16842a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(vnic_env, 0); 16852a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(vport, MLX5E_NDO_UPDATE_STATS); 16862a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(802_3, MLX5E_NDO_UPDATE_STATS); 16872a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(2863, 0); 16882a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(2819, 0); 16892a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(phy, 0); 16902a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(pcie, 0); 16912a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(per_prio, 0); 16922a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(pme, 0); 16932a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(channels, 0); 16942a303f13SSaeed Mahameed MLX5E_DEFINE_STATS_GRP(per_port_buff_congest, 0); 16957c453526SVlad Buslov MLX5E_DEFINE_STATS_GRP(eth_ext, 0); 1696f0ff8e8cSSaeed Mahameed static MLX5E_DEFINE_STATS_GRP(tls, 0); 1697f0ff8e8cSSaeed Mahameed 169819386177SKamal Heib /* The stats groups order is opposite to the update_stats() order calls */ 1699f0ff8e8cSSaeed Mahameed mlx5e_stats_grp_t mlx5e_nic_stats_grps[] = { 1700f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(sw), 1701f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(qcnt), 1702f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(vnic_env), 1703f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(vport), 1704f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(802_3), 1705f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(2863), 1706f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(2819), 1707f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(phy), 1708f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(eth_ext), 1709f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(pcie), 1710f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(per_prio), 1711f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(pme), 17120aab3e1bSRaed Salem #ifdef CONFIG_MLX5_EN_IPSEC 17130aab3e1bSRaed Salem &MLX5E_STATS_GRP(ipsec_sw), 17140aab3e1bSRaed Salem &MLX5E_STATS_GRP(ipsec_hw), 17150aab3e1bSRaed Salem #endif 1716f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(tls), 1717f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(channels), 1718f0ff8e8cSSaeed Mahameed &MLX5E_STATS_GRP(per_port_buff_congest), 1719c0752f2bSKamal Heib }; 1720c0752f2bSKamal Heib 17213460c184SSaeed Mahameed unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv) 17223460c184SSaeed Mahameed { 17233460c184SSaeed Mahameed return ARRAY_SIZE(mlx5e_nic_stats_grps); 17243460c184SSaeed Mahameed } 1725