1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 #include "lib/clock.h" 46 47 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 48 { 49 return config->rx_filter == HWTSTAMP_FILTER_ALL; 50 } 51 52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 53 void *data) 54 { 55 u32 ci = cqcc & cq->wq.sz_m1; 56 57 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 58 } 59 60 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 61 struct mlx5e_cq *cq, u32 cqcc) 62 { 63 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 64 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 65 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 66 rq->stats.cqe_compress_blks++; 67 } 68 69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 70 { 71 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 72 cq->mini_arr_idx = 0; 73 } 74 75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 76 { 77 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 78 u32 wq_sz = 1 << cq->wq.log_sz; 79 u32 ci = cqcc & cq->wq.sz_m1; 80 u32 ci_top = min_t(u32, wq_sz, ci + n); 81 82 for (; ci < ci_top; ci++, n--) { 83 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 84 85 cqe->op_own = op_own; 86 } 87 88 if (unlikely(ci == wq_sz)) { 89 op_own = !op_own; 90 for (ci = 0; ci < n; ci++) { 91 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 92 93 cqe->op_own = op_own; 94 } 95 } 96 } 97 98 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 99 struct mlx5e_cq *cq, u32 cqcc) 100 { 101 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 102 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 103 cq->title.op_own &= 0xf0; 104 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 105 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 106 107 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 108 cq->decmprs_wqe_counter += 109 mpwrq_get_cqe_consumed_strides(&cq->title); 110 else 111 cq->decmprs_wqe_counter = 112 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 113 } 114 115 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 116 struct mlx5e_cq *cq, u32 cqcc) 117 { 118 mlx5e_decompress_cqe(rq, cq, cqcc); 119 cq->title.rss_hash_type = 0; 120 cq->title.rss_hash_result = 0; 121 } 122 123 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 124 struct mlx5e_cq *cq, 125 int update_owner_only, 126 int budget_rem) 127 { 128 u32 cqcc = cq->wq.cc + update_owner_only; 129 u32 cqe_count; 130 u32 i; 131 132 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 133 134 for (i = update_owner_only; i < cqe_count; 135 i++, cq->mini_arr_idx++, cqcc++) { 136 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 137 mlx5e_read_mini_arr_slot(cq, cqcc); 138 139 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 140 rq->handle_rx_cqe(rq, &cq->title); 141 } 142 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 143 cq->wq.cc = cqcc; 144 cq->decmprs_left -= cqe_count; 145 rq->stats.cqe_compress_pkts += cqe_count; 146 147 return cqe_count; 148 } 149 150 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 151 struct mlx5e_cq *cq, 152 int budget_rem) 153 { 154 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 155 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 156 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 157 rq->handle_rx_cqe(rq, &cq->title); 158 cq->mini_arr_idx++; 159 160 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 161 } 162 163 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 164 165 static inline bool mlx5e_page_is_reserved(struct page *page) 166 { 167 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 168 } 169 170 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 171 struct mlx5e_dma_info *dma_info) 172 { 173 struct mlx5e_page_cache *cache = &rq->page_cache; 174 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 175 176 if (tail_next == cache->head) { 177 rq->stats.cache_full++; 178 return false; 179 } 180 181 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 182 rq->stats.cache_waive++; 183 return false; 184 } 185 186 cache->page_cache[cache->tail] = *dma_info; 187 cache->tail = tail_next; 188 return true; 189 } 190 191 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 192 struct mlx5e_dma_info *dma_info) 193 { 194 struct mlx5e_page_cache *cache = &rq->page_cache; 195 196 if (unlikely(cache->head == cache->tail)) { 197 rq->stats.cache_empty++; 198 return false; 199 } 200 201 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 202 rq->stats.cache_busy++; 203 return false; 204 } 205 206 *dma_info = cache->page_cache[cache->head]; 207 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 208 rq->stats.cache_reuse++; 209 210 dma_sync_single_for_device(rq->pdev, dma_info->addr, 211 RQ_PAGE_SIZE(rq), 212 DMA_FROM_DEVICE); 213 return true; 214 } 215 216 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 217 struct mlx5e_dma_info *dma_info) 218 { 219 struct page *page; 220 221 if (mlx5e_rx_cache_get(rq, dma_info)) 222 return 0; 223 224 page = dev_alloc_pages(rq->buff.page_order); 225 if (unlikely(!page)) 226 return -ENOMEM; 227 228 dma_info->addr = dma_map_page(rq->pdev, page, 0, 229 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 230 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 231 put_page(page); 232 return -ENOMEM; 233 } 234 dma_info->page = page; 235 236 return 0; 237 } 238 239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 240 bool recycle) 241 { 242 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 243 return; 244 245 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 246 rq->buff.map_dir); 247 put_page(dma_info->page); 248 } 249 250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 251 struct mlx5e_wqe_frag_info *wi) 252 { 253 return rq->wqe.page_reuse && wi->di.page && 254 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 255 !mlx5e_page_is_reserved(wi->di.page); 256 } 257 258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 259 { 260 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 261 262 /* check if page exists, hence can be reused */ 263 if (!wi->di.page) { 264 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 265 return -ENOMEM; 266 wi->offset = 0; 267 } 268 269 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 270 return 0; 271 } 272 273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 274 struct mlx5e_wqe_frag_info *wi) 275 { 276 mlx5e_page_release(rq, &wi->di, true); 277 wi->di.page = NULL; 278 } 279 280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 281 struct mlx5e_wqe_frag_info *wi) 282 { 283 if (mlx5e_page_reuse(rq, wi)) { 284 rq->stats.page_reuse++; 285 return; 286 } 287 288 mlx5e_free_rx_wqe(rq, wi); 289 } 290 291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 292 { 293 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 294 295 if (wi->di.page) 296 mlx5e_free_rx_wqe(rq, wi); 297 } 298 299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 300 { 301 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 302 } 303 304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 305 struct sk_buff *skb, 306 struct mlx5e_mpw_info *wi, 307 u32 page_idx, u32 frag_offset, 308 u32 len) 309 { 310 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 311 312 dma_sync_single_for_cpu(rq->pdev, 313 wi->umr.dma_info[page_idx].addr + frag_offset, 314 len, DMA_FROM_DEVICE); 315 wi->skbs_frags[page_idx]++; 316 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 317 wi->umr.dma_info[page_idx].page, frag_offset, 318 len, truesize); 319 } 320 321 static inline void 322 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 323 struct sk_buff *skb, 324 struct mlx5e_mpw_info *wi, 325 u32 page_idx, u32 offset, 326 u32 headlen) 327 { 328 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 329 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 330 unsigned int len; 331 332 /* Aligning len to sizeof(long) optimizes memcpy performance */ 333 len = ALIGN(headlen_pg, sizeof(long)); 334 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 335 DMA_FROM_DEVICE); 336 skb_copy_to_linear_data_offset(skb, 0, 337 page_address(dma_info->page) + offset, 338 len); 339 if (unlikely(offset + headlen > PAGE_SIZE)) { 340 dma_info++; 341 headlen_pg = len; 342 len = ALIGN(headlen - headlen_pg, sizeof(long)); 343 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 344 DMA_FROM_DEVICE); 345 skb_copy_to_linear_data_offset(skb, headlen_pg, 346 page_address(dma_info->page), 347 len); 348 } 349 } 350 351 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 352 { 353 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 354 struct mlx5e_icosq *sq = &rq->channel->icosq; 355 struct mlx5_wq_cyc *wq = &sq->wq; 356 struct mlx5e_umr_wqe *wqe; 357 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 358 u16 pi; 359 360 /* fill sq edge with nops to avoid wqe wrap around */ 361 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 362 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 363 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 364 } 365 366 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 367 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 368 wqe->ctrl.opmod_idx_opcode = 369 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 370 MLX5_OPCODE_UMR); 371 372 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 373 sq->pc += num_wqebbs; 374 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 375 } 376 377 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 378 u16 ix) 379 { 380 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 381 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 382 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 383 int err; 384 int i; 385 386 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 387 err = mlx5e_page_alloc_mapped(rq, dma_info); 388 if (unlikely(err)) 389 goto err_unmap; 390 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 391 page_ref_add(dma_info->page, pg_strides); 392 } 393 394 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 395 wi->consumed_strides = 0; 396 397 return 0; 398 399 err_unmap: 400 while (--i >= 0) { 401 dma_info--; 402 page_ref_sub(dma_info->page, pg_strides); 403 mlx5e_page_release(rq, dma_info, true); 404 } 405 406 return err; 407 } 408 409 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 410 { 411 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 412 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 413 int i; 414 415 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 416 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 417 mlx5e_page_release(rq, dma_info, true); 418 } 419 } 420 421 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 422 { 423 struct mlx5_wq_ll *wq = &rq->wq; 424 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 425 426 rq->mpwqe.umr_in_progress = false; 427 428 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 429 430 /* ensure wqes are visible to device before updating doorbell record */ 431 dma_wmb(); 432 433 mlx5_wq_ll_update_db_record(wq); 434 } 435 436 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 437 { 438 int err; 439 440 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 441 if (unlikely(err)) { 442 rq->stats.buff_alloc_err++; 443 return err; 444 } 445 rq->mpwqe.umr_in_progress = true; 446 mlx5e_post_umr_wqe(rq, ix); 447 return 0; 448 } 449 450 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 451 { 452 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 453 454 mlx5e_free_rx_mpwqe(rq, wi); 455 } 456 457 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 458 { 459 struct mlx5_wq_ll *wq = &rq->wq; 460 int err; 461 462 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 463 return false; 464 465 if (mlx5_wq_ll_is_full(wq)) 466 return false; 467 468 do { 469 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 470 471 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 472 if (unlikely(err)) { 473 rq->stats.buff_alloc_err++; 474 break; 475 } 476 477 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 478 } while (!mlx5_wq_ll_is_full(wq)); 479 480 /* ensure wqes are visible to device before updating doorbell record */ 481 dma_wmb(); 482 483 mlx5_wq_ll_update_db_record(wq); 484 485 return !!err; 486 } 487 488 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 489 struct mlx5e_icosq *sq, 490 struct mlx5e_rq *rq, 491 struct mlx5_cqe64 *cqe) 492 { 493 struct mlx5_wq_cyc *wq = &sq->wq; 494 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 495 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 496 497 mlx5_cqwq_pop(&cq->wq); 498 499 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 500 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 501 cqe->op_own); 502 return; 503 } 504 505 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 506 mlx5e_post_rx_mpwqe(rq); 507 return; 508 } 509 510 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 511 WARN_ONCE(true, 512 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 513 icowi->opcode); 514 } 515 516 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 517 { 518 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 519 struct mlx5_cqe64 *cqe; 520 521 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 522 return; 523 524 cqe = mlx5_cqwq_get_cqe(&cq->wq); 525 if (likely(!cqe)) 526 return; 527 528 /* by design, there's only a single cqe */ 529 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 530 531 mlx5_cqwq_update_db_record(&cq->wq); 532 } 533 534 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 535 { 536 struct mlx5_wq_ll *wq = &rq->wq; 537 538 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 539 return false; 540 541 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 542 543 if (mlx5_wq_ll_is_full(wq)) 544 return false; 545 546 if (!rq->mpwqe.umr_in_progress) 547 mlx5e_alloc_rx_mpwqe(rq, wq->head); 548 549 return true; 550 } 551 552 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 553 u32 cqe_bcnt) 554 { 555 struct ethhdr *eth = (struct ethhdr *)(skb->data); 556 struct tcphdr *tcp; 557 int network_depth = 0; 558 __be16 proto; 559 u16 tot_len; 560 void *ip_p; 561 562 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 563 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 564 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 565 566 skb->mac_len = ETH_HLEN; 567 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 568 569 tot_len = cqe_bcnt - network_depth; 570 ip_p = skb->data + network_depth; 571 572 if (proto == htons(ETH_P_IP)) { 573 struct iphdr *ipv4 = ip_p; 574 575 tcp = ip_p + sizeof(struct iphdr); 576 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 577 578 ipv4->ttl = cqe->lro_min_ttl; 579 ipv4->tot_len = cpu_to_be16(tot_len); 580 ipv4->check = 0; 581 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 582 ipv4->ihl); 583 } else { 584 struct ipv6hdr *ipv6 = ip_p; 585 586 tcp = ip_p + sizeof(struct ipv6hdr); 587 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 588 589 ipv6->hop_limit = cqe->lro_min_ttl; 590 ipv6->payload_len = cpu_to_be16(tot_len - 591 sizeof(struct ipv6hdr)); 592 } 593 594 tcp->psh = get_cqe_lro_tcppsh(cqe); 595 596 if (tcp_ack) { 597 tcp->ack = 1; 598 tcp->ack_seq = cqe->lro_ack_seq_num; 599 tcp->window = cqe->lro_tcp_win; 600 } 601 } 602 603 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 604 struct sk_buff *skb) 605 { 606 u8 cht = cqe->rss_hash_type; 607 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 608 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 609 PKT_HASH_TYPE_NONE; 610 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 611 } 612 613 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 614 { 615 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 616 617 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 618 } 619 620 static inline void mlx5e_handle_csum(struct net_device *netdev, 621 struct mlx5_cqe64 *cqe, 622 struct mlx5e_rq *rq, 623 struct sk_buff *skb, 624 bool lro) 625 { 626 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 627 goto csum_none; 628 629 if (lro) { 630 skb->ip_summed = CHECKSUM_UNNECESSARY; 631 rq->stats.csum_unnecessary++; 632 return; 633 } 634 635 if (is_first_ethertype_ip(skb)) { 636 skb->ip_summed = CHECKSUM_COMPLETE; 637 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 638 rq->stats.csum_complete++; 639 return; 640 } 641 642 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 643 (cqe->hds_ip_ext & CQE_L4_OK))) { 644 skb->ip_summed = CHECKSUM_UNNECESSARY; 645 if (cqe_is_tunneled(cqe)) { 646 skb->csum_level = 1; 647 skb->encapsulation = 1; 648 rq->stats.csum_unnecessary_inner++; 649 return; 650 } 651 rq->stats.csum_unnecessary++; 652 return; 653 } 654 csum_none: 655 skb->ip_summed = CHECKSUM_NONE; 656 rq->stats.csum_none++; 657 } 658 659 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 660 u32 cqe_bcnt, 661 struct mlx5e_rq *rq, 662 struct sk_buff *skb) 663 { 664 struct net_device *netdev = rq->netdev; 665 int lro_num_seg; 666 667 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 668 if (lro_num_seg > 1) { 669 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 670 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 671 /* Subtract one since we already counted this as one 672 * "regular" packet in mlx5e_complete_rx_cqe() 673 */ 674 rq->stats.packets += lro_num_seg - 1; 675 rq->stats.lro_packets++; 676 rq->stats.lro_bytes += cqe_bcnt; 677 } 678 679 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 680 skb_hwtstamps(skb)->hwtstamp = 681 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 682 683 skb_record_rx_queue(skb, rq->ix); 684 685 if (likely(netdev->features & NETIF_F_RXHASH)) 686 mlx5e_skb_set_hash(cqe, skb); 687 688 if (cqe_has_vlan(cqe)) { 689 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 690 be16_to_cpu(cqe->vlan_info)); 691 rq->stats.removed_vlan_packets++; 692 } 693 694 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 695 696 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 697 skb->protocol = eth_type_trans(skb, netdev); 698 } 699 700 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 701 struct mlx5_cqe64 *cqe, 702 u32 cqe_bcnt, 703 struct sk_buff *skb) 704 { 705 rq->stats.packets++; 706 rq->stats.bytes += cqe_bcnt; 707 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 708 } 709 710 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 711 { 712 struct mlx5_wq_cyc *wq = &sq->wq; 713 struct mlx5e_tx_wqe *wqe; 714 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 715 716 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 717 718 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 719 } 720 721 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 722 struct mlx5e_dma_info *di, 723 const struct xdp_buff *xdp) 724 { 725 struct mlx5e_xdpsq *sq = &rq->xdpsq; 726 struct mlx5_wq_cyc *wq = &sq->wq; 727 u16 pi = sq->pc & wq->sz_m1; 728 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 729 730 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 731 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 732 struct mlx5_wqe_data_seg *dseg; 733 734 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 735 dma_addr_t dma_addr = di->addr + data_offset; 736 unsigned int dma_len = xdp->data_end - xdp->data; 737 738 prefetchw(wqe); 739 740 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 741 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 742 rq->stats.xdp_drop++; 743 return false; 744 } 745 746 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 747 if (sq->db.doorbell) { 748 /* SQ is full, ring doorbell */ 749 mlx5e_xmit_xdp_doorbell(sq); 750 sq->db.doorbell = false; 751 } 752 rq->stats.xdp_tx_full++; 753 return false; 754 } 755 756 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 757 758 cseg->fm_ce_se = 0; 759 760 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 761 762 /* copy the inline part if required */ 763 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 764 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 765 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 766 dma_len -= MLX5E_XDP_MIN_INLINE; 767 dma_addr += MLX5E_XDP_MIN_INLINE; 768 dseg++; 769 } 770 771 /* write the dma part */ 772 dseg->addr = cpu_to_be64(dma_addr); 773 dseg->byte_count = cpu_to_be32(dma_len); 774 775 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 776 777 /* move page to reference to sq responsibility, 778 * and mark so it's not put back in page-cache. 779 */ 780 rq->wqe.xdp_xmit = true; 781 sq->db.di[pi] = *di; 782 sq->pc++; 783 784 sq->db.doorbell = true; 785 786 rq->stats.xdp_tx++; 787 return true; 788 } 789 790 /* returns true if packet was consumed by xdp */ 791 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 792 struct mlx5e_dma_info *di, 793 void *va, u16 *rx_headroom, u32 *len) 794 { 795 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 796 struct xdp_buff xdp; 797 u32 act; 798 799 if (!prog) 800 return false; 801 802 xdp.data = va + *rx_headroom; 803 xdp_set_data_meta_invalid(&xdp); 804 xdp.data_end = xdp.data + *len; 805 xdp.data_hard_start = va; 806 807 act = bpf_prog_run_xdp(prog, &xdp); 808 switch (act) { 809 case XDP_PASS: 810 *rx_headroom = xdp.data - xdp.data_hard_start; 811 *len = xdp.data_end - xdp.data; 812 return false; 813 case XDP_TX: 814 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 815 trace_xdp_exception(rq->netdev, prog, act); 816 return true; 817 default: 818 bpf_warn_invalid_xdp_action(act); 819 case XDP_ABORTED: 820 trace_xdp_exception(rq->netdev, prog, act); 821 case XDP_DROP: 822 rq->stats.xdp_drop++; 823 return true; 824 } 825 } 826 827 static inline 828 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 829 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 830 { 831 struct mlx5e_dma_info *di = &wi->di; 832 u16 rx_headroom = rq->buff.headroom; 833 struct sk_buff *skb; 834 void *va, *data; 835 bool consumed; 836 u32 frag_size; 837 838 va = page_address(di->page) + wi->offset; 839 data = va + rx_headroom; 840 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 841 842 dma_sync_single_range_for_cpu(rq->pdev, 843 di->addr + wi->offset, 844 0, frag_size, 845 DMA_FROM_DEVICE); 846 prefetch(data); 847 wi->offset += frag_size; 848 849 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 850 rq->stats.wqe_err++; 851 return NULL; 852 } 853 854 rcu_read_lock(); 855 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 856 rcu_read_unlock(); 857 if (consumed) 858 return NULL; /* page/packet was consumed by XDP */ 859 860 skb = build_skb(va, frag_size); 861 if (unlikely(!skb)) { 862 rq->stats.buff_alloc_err++; 863 return NULL; 864 } 865 866 /* queue up for recycling/reuse */ 867 page_ref_inc(di->page); 868 869 skb_reserve(skb, rx_headroom); 870 skb_put(skb, cqe_bcnt); 871 872 return skb; 873 } 874 875 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 876 { 877 struct mlx5e_wqe_frag_info *wi; 878 struct mlx5e_rx_wqe *wqe; 879 __be16 wqe_counter_be; 880 struct sk_buff *skb; 881 u16 wqe_counter; 882 u32 cqe_bcnt; 883 884 wqe_counter_be = cqe->wqe_counter; 885 wqe_counter = be16_to_cpu(wqe_counter_be); 886 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 887 wi = &rq->wqe.frag_info[wqe_counter]; 888 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 889 890 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 891 if (!skb) { 892 /* probably for XDP */ 893 if (rq->wqe.xdp_xmit) { 894 wi->di.page = NULL; 895 rq->wqe.xdp_xmit = false; 896 /* do not return page to cache, it will be returned on XDP_TX completion */ 897 goto wq_ll_pop; 898 } 899 /* probably an XDP_DROP, save the page-reuse checks */ 900 mlx5e_free_rx_wqe(rq, wi); 901 goto wq_ll_pop; 902 } 903 904 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 905 napi_gro_receive(rq->cq.napi, skb); 906 907 mlx5e_free_rx_wqe_reuse(rq, wi); 908 wq_ll_pop: 909 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 910 &wqe->next.next_wqe_index); 911 } 912 913 #ifdef CONFIG_MLX5_ESWITCH 914 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 915 { 916 struct net_device *netdev = rq->netdev; 917 struct mlx5e_priv *priv = netdev_priv(netdev); 918 struct mlx5e_rep_priv *rpriv = priv->ppriv; 919 struct mlx5_eswitch_rep *rep = rpriv->rep; 920 struct mlx5e_wqe_frag_info *wi; 921 struct mlx5e_rx_wqe *wqe; 922 struct sk_buff *skb; 923 __be16 wqe_counter_be; 924 u16 wqe_counter; 925 u32 cqe_bcnt; 926 927 wqe_counter_be = cqe->wqe_counter; 928 wqe_counter = be16_to_cpu(wqe_counter_be); 929 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 930 wi = &rq->wqe.frag_info[wqe_counter]; 931 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 932 933 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 934 if (!skb) { 935 if (rq->wqe.xdp_xmit) { 936 wi->di.page = NULL; 937 rq->wqe.xdp_xmit = false; 938 /* do not return page to cache, it will be returned on XDP_TX completion */ 939 goto wq_ll_pop; 940 } 941 /* probably an XDP_DROP, save the page-reuse checks */ 942 mlx5e_free_rx_wqe(rq, wi); 943 goto wq_ll_pop; 944 } 945 946 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 947 948 if (rep->vlan && skb_vlan_tag_present(skb)) 949 skb_vlan_pop(skb); 950 951 napi_gro_receive(rq->cq.napi, skb); 952 953 mlx5e_free_rx_wqe_reuse(rq, wi); 954 wq_ll_pop: 955 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 956 &wqe->next.next_wqe_index); 957 } 958 #endif 959 960 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 961 struct mlx5_cqe64 *cqe, 962 struct mlx5e_mpw_info *wi, 963 u32 cqe_bcnt, 964 struct sk_buff *skb) 965 { 966 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 967 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 968 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 969 u32 page_idx = wqe_offset >> PAGE_SHIFT; 970 u32 head_page_idx = page_idx; 971 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 972 u32 frag_offset = head_offset + headlen; 973 u16 byte_cnt = cqe_bcnt - headlen; 974 975 if (unlikely(frag_offset >= PAGE_SIZE)) { 976 page_idx++; 977 frag_offset -= PAGE_SIZE; 978 } 979 980 while (byte_cnt) { 981 u32 pg_consumed_bytes = 982 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 983 984 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 985 pg_consumed_bytes); 986 byte_cnt -= pg_consumed_bytes; 987 frag_offset = 0; 988 page_idx++; 989 } 990 /* copy header */ 991 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 992 head_offset, headlen); 993 /* skb linear part was allocated with headlen and aligned to long */ 994 skb->tail += headlen; 995 skb->len += headlen; 996 } 997 998 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 999 { 1000 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1001 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1002 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1003 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1004 struct sk_buff *skb; 1005 u16 cqe_bcnt; 1006 1007 wi->consumed_strides += cstrides; 1008 1009 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1010 rq->stats.wqe_err++; 1011 goto mpwrq_cqe_out; 1012 } 1013 1014 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1015 rq->stats.mpwqe_filler++; 1016 goto mpwrq_cqe_out; 1017 } 1018 1019 skb = napi_alloc_skb(rq->cq.napi, 1020 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1021 sizeof(long))); 1022 if (unlikely(!skb)) { 1023 rq->stats.buff_alloc_err++; 1024 goto mpwrq_cqe_out; 1025 } 1026 1027 prefetchw(skb->data); 1028 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1029 1030 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1031 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1032 napi_gro_receive(rq->cq.napi, skb); 1033 1034 mpwrq_cqe_out: 1035 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1036 return; 1037 1038 mlx5e_free_rx_mpwqe(rq, wi); 1039 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1040 } 1041 1042 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1043 { 1044 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1045 struct mlx5e_xdpsq *xdpsq; 1046 struct mlx5_cqe64 *cqe; 1047 int work_done = 0; 1048 1049 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1050 return 0; 1051 1052 if (cq->decmprs_left) 1053 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1054 1055 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1056 if (!cqe) 1057 return 0; 1058 1059 xdpsq = &rq->xdpsq; 1060 1061 do { 1062 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1063 work_done += 1064 mlx5e_decompress_cqes_start(rq, cq, 1065 budget - work_done); 1066 continue; 1067 } 1068 1069 mlx5_cqwq_pop(&cq->wq); 1070 1071 rq->handle_rx_cqe(rq, cqe); 1072 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1073 1074 if (xdpsq->db.doorbell) { 1075 mlx5e_xmit_xdp_doorbell(xdpsq); 1076 xdpsq->db.doorbell = false; 1077 } 1078 1079 mlx5_cqwq_update_db_record(&cq->wq); 1080 1081 /* ensure cq space is freed before enabling more cqes */ 1082 wmb(); 1083 1084 return work_done; 1085 } 1086 1087 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1088 { 1089 struct mlx5e_xdpsq *sq; 1090 struct mlx5_cqe64 *cqe; 1091 struct mlx5e_rq *rq; 1092 u16 sqcc; 1093 int i; 1094 1095 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1096 1097 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1098 return false; 1099 1100 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1101 if (!cqe) 1102 return false; 1103 1104 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1105 1106 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1107 * otherwise a cq overrun may occur 1108 */ 1109 sqcc = sq->cc; 1110 1111 i = 0; 1112 do { 1113 u16 wqe_counter; 1114 bool last_wqe; 1115 1116 mlx5_cqwq_pop(&cq->wq); 1117 1118 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1119 1120 do { 1121 struct mlx5e_dma_info *di; 1122 u16 ci; 1123 1124 last_wqe = (sqcc == wqe_counter); 1125 1126 ci = sqcc & sq->wq.sz_m1; 1127 di = &sq->db.di[ci]; 1128 1129 sqcc++; 1130 /* Recycle RX page */ 1131 mlx5e_page_release(rq, di, true); 1132 } while (!last_wqe); 1133 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1134 1135 mlx5_cqwq_update_db_record(&cq->wq); 1136 1137 /* ensure cq space is freed before enabling more cqes */ 1138 wmb(); 1139 1140 sq->cc = sqcc; 1141 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1142 } 1143 1144 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1145 { 1146 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1147 struct mlx5e_dma_info *di; 1148 u16 ci; 1149 1150 while (sq->cc != sq->pc) { 1151 ci = sq->cc & sq->wq.sz_m1; 1152 di = &sq->db.di[ci]; 1153 sq->cc++; 1154 1155 mlx5e_page_release(rq, di, false); 1156 } 1157 } 1158 1159 #ifdef CONFIG_MLX5_CORE_IPOIB 1160 1161 #define MLX5_IB_GRH_DGID_OFFSET 24 1162 #define MLX5_GID_SIZE 16 1163 1164 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1165 struct mlx5_cqe64 *cqe, 1166 u32 cqe_bcnt, 1167 struct sk_buff *skb) 1168 { 1169 struct net_device *netdev; 1170 char *pseudo_header; 1171 u32 qpn; 1172 u8 *dgid; 1173 u8 g; 1174 1175 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1176 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1177 1178 /* No mapping present, cannot process SKB. This might happen if a child 1179 * interface is going down while having unprocessed CQEs on parent RQ 1180 */ 1181 if (unlikely(!netdev)) { 1182 /* TODO: add drop counters support */ 1183 skb->dev = NULL; 1184 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1185 return; 1186 } 1187 1188 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1189 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1190 if ((!g) || dgid[0] != 0xff) 1191 skb->pkt_type = PACKET_HOST; 1192 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1193 skb->pkt_type = PACKET_BROADCAST; 1194 else 1195 skb->pkt_type = PACKET_MULTICAST; 1196 1197 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1198 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1199 */ 1200 1201 skb_pull(skb, MLX5_IB_GRH_BYTES); 1202 1203 skb->protocol = *((__be16 *)(skb->data)); 1204 1205 skb->ip_summed = CHECKSUM_COMPLETE; 1206 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1207 1208 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 1209 skb_hwtstamps(skb)->hwtstamp = 1210 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1211 1212 skb_record_rx_queue(skb, rq->ix); 1213 1214 if (likely(netdev->features & NETIF_F_RXHASH)) 1215 mlx5e_skb_set_hash(cqe, skb); 1216 1217 /* 20 bytes of ipoib header and 4 for encap existing */ 1218 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1219 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1220 skb_reset_mac_header(skb); 1221 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1222 1223 skb->dev = netdev; 1224 1225 rq->stats.csum_complete++; 1226 rq->stats.packets++; 1227 rq->stats.bytes += cqe_bcnt; 1228 } 1229 1230 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1231 { 1232 struct mlx5e_wqe_frag_info *wi; 1233 struct mlx5e_rx_wqe *wqe; 1234 __be16 wqe_counter_be; 1235 struct sk_buff *skb; 1236 u16 wqe_counter; 1237 u32 cqe_bcnt; 1238 1239 wqe_counter_be = cqe->wqe_counter; 1240 wqe_counter = be16_to_cpu(wqe_counter_be); 1241 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1242 wi = &rq->wqe.frag_info[wqe_counter]; 1243 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1244 1245 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1246 if (!skb) 1247 goto wq_free_wqe; 1248 1249 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1250 if (unlikely(!skb->dev)) { 1251 dev_kfree_skb_any(skb); 1252 goto wq_free_wqe; 1253 } 1254 napi_gro_receive(rq->cq.napi, skb); 1255 1256 wq_free_wqe: 1257 mlx5e_free_rx_wqe_reuse(rq, wi); 1258 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1259 &wqe->next.next_wqe_index); 1260 } 1261 1262 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1263 1264 #ifdef CONFIG_MLX5_EN_IPSEC 1265 1266 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1267 { 1268 struct mlx5e_wqe_frag_info *wi; 1269 struct mlx5e_rx_wqe *wqe; 1270 __be16 wqe_counter_be; 1271 struct sk_buff *skb; 1272 u16 wqe_counter; 1273 u32 cqe_bcnt; 1274 1275 wqe_counter_be = cqe->wqe_counter; 1276 wqe_counter = be16_to_cpu(wqe_counter_be); 1277 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1278 wi = &rq->wqe.frag_info[wqe_counter]; 1279 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1280 1281 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1282 if (unlikely(!skb)) { 1283 /* a DROP, save the page-reuse checks */ 1284 mlx5e_free_rx_wqe(rq, wi); 1285 goto wq_ll_pop; 1286 } 1287 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1288 if (unlikely(!skb)) { 1289 mlx5e_free_rx_wqe(rq, wi); 1290 goto wq_ll_pop; 1291 } 1292 1293 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1294 napi_gro_receive(rq->cq.napi, skb); 1295 1296 mlx5e_free_rx_wqe_reuse(rq, wi); 1297 wq_ll_pop: 1298 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1299 &wqe->next.next_wqe_index); 1300 } 1301 1302 #endif /* CONFIG_MLX5_EN_IPSEC */ 1303