1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/ip.h> 34 #include <linux/ipv6.h> 35 #include <linux/tcp.h> 36 #include <net/busy_poll.h> 37 #include "en.h" 38 #include "en_tc.h" 39 40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 41 { 42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 43 } 44 45 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 46 void *data) 47 { 48 u32 ci = cqcc & cq->wq.sz_m1; 49 50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 51 } 52 53 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 54 struct mlx5e_cq *cq, u32 cqcc) 55 { 56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 59 rq->stats.cqe_compress_blks++; 60 } 61 62 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 63 { 64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 65 cq->mini_arr_idx = 0; 66 } 67 68 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 69 { 70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 71 u32 wq_sz = 1 << cq->wq.log_sz; 72 u32 ci = cqcc & cq->wq.sz_m1; 73 u32 ci_top = min_t(u32, wq_sz, ci + n); 74 75 for (; ci < ci_top; ci++, n--) { 76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 77 78 cqe->op_own = op_own; 79 } 80 81 if (unlikely(ci == wq_sz)) { 82 op_own = !op_own; 83 for (ci = 0; ci < n; ci++) { 84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 85 86 cqe->op_own = op_own; 87 } 88 } 89 } 90 91 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 92 struct mlx5e_cq *cq, u32 cqcc) 93 { 94 u16 wqe_cnt_step; 95 96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 98 cq->title.op_own &= 0xf0; 99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 101 102 wqe_cnt_step = 103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1; 105 cq->decmprs_wqe_counter = 106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1; 107 } 108 109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 110 struct mlx5e_cq *cq, u32 cqcc) 111 { 112 mlx5e_decompress_cqe(rq, cq, cqcc); 113 cq->title.rss_hash_type = 0; 114 cq->title.rss_hash_result = 0; 115 } 116 117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 118 struct mlx5e_cq *cq, 119 int update_owner_only, 120 int budget_rem) 121 { 122 u32 cqcc = cq->wq.cc + update_owner_only; 123 u32 cqe_count; 124 u32 i; 125 126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 127 128 for (i = update_owner_only; i < cqe_count; 129 i++, cq->mini_arr_idx++, cqcc++) { 130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 131 mlx5e_read_mini_arr_slot(cq, cqcc); 132 133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 134 rq->handle_rx_cqe(rq, &cq->title); 135 } 136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 137 cq->wq.cc = cqcc; 138 cq->decmprs_left -= cqe_count; 139 rq->stats.cqe_compress_pkts += cqe_count; 140 141 return cqe_count; 142 } 143 144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 145 struct mlx5e_cq *cq, 146 int budget_rem) 147 { 148 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 151 rq->handle_rx_cqe(rq, &cq->title); 152 cq->mini_arr_idx++; 153 154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 155 } 156 157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val) 158 { 159 bool was_opened; 160 161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 162 return; 163 164 mutex_lock(&priv->state_lock); 165 166 if (priv->params.rx_cqe_compress == val) 167 goto unlock; 168 169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 170 if (was_opened) 171 mlx5e_close_locked(priv->netdev); 172 173 priv->params.rx_cqe_compress = val; 174 175 if (was_opened) 176 mlx5e_open_locked(priv->netdev); 177 178 unlock: 179 mutex_unlock(&priv->state_lock); 180 } 181 182 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 183 184 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 185 struct mlx5e_dma_info *dma_info) 186 { 187 struct mlx5e_page_cache *cache = &rq->page_cache; 188 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 189 190 if (tail_next == cache->head) { 191 rq->stats.cache_full++; 192 return false; 193 } 194 195 cache->page_cache[cache->tail] = *dma_info; 196 cache->tail = tail_next; 197 return true; 198 } 199 200 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 201 struct mlx5e_dma_info *dma_info) 202 { 203 struct mlx5e_page_cache *cache = &rq->page_cache; 204 205 if (unlikely(cache->head == cache->tail)) { 206 rq->stats.cache_empty++; 207 return false; 208 } 209 210 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 211 rq->stats.cache_busy++; 212 return false; 213 } 214 215 *dma_info = cache->page_cache[cache->head]; 216 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 217 rq->stats.cache_reuse++; 218 219 dma_sync_single_for_device(rq->pdev, dma_info->addr, 220 RQ_PAGE_SIZE(rq), 221 DMA_FROM_DEVICE); 222 return true; 223 } 224 225 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 226 struct mlx5e_dma_info *dma_info) 227 { 228 struct page *page; 229 230 if (mlx5e_rx_cache_get(rq, dma_info)) 231 return 0; 232 233 page = dev_alloc_pages(rq->buff.page_order); 234 if (unlikely(!page)) 235 return -ENOMEM; 236 237 dma_info->page = page; 238 dma_info->addr = dma_map_page(rq->pdev, page, 0, 239 RQ_PAGE_SIZE(rq), DMA_FROM_DEVICE); 240 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 241 put_page(page); 242 return -ENOMEM; 243 } 244 245 return 0; 246 } 247 248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 249 bool recycle) 250 { 251 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 252 return; 253 254 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 255 DMA_FROM_DEVICE); 256 put_page(dma_info->page); 257 } 258 259 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 260 { 261 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 262 263 if (unlikely(mlx5e_page_alloc_mapped(rq, di))) 264 return -ENOMEM; 265 266 wqe->data.addr = cpu_to_be64(di->addr + MLX5_RX_HEADROOM); 267 return 0; 268 } 269 270 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 271 { 272 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 273 274 mlx5e_page_release(rq, di, true); 275 } 276 277 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 278 { 279 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 280 } 281 282 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 283 struct sk_buff *skb, 284 struct mlx5e_mpw_info *wi, 285 u32 page_idx, u32 frag_offset, 286 u32 len) 287 { 288 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz); 289 290 dma_sync_single_for_cpu(rq->pdev, 291 wi->umr.dma_info[page_idx].addr + frag_offset, 292 len, DMA_FROM_DEVICE); 293 wi->skbs_frags[page_idx]++; 294 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 295 wi->umr.dma_info[page_idx].page, frag_offset, 296 len, truesize); 297 } 298 299 static inline void 300 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 301 struct sk_buff *skb, 302 struct mlx5e_mpw_info *wi, 303 u32 page_idx, u32 offset, 304 u32 headlen) 305 { 306 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 307 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 308 unsigned int len; 309 310 /* Aligning len to sizeof(long) optimizes memcpy performance */ 311 len = ALIGN(headlen_pg, sizeof(long)); 312 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 313 DMA_FROM_DEVICE); 314 skb_copy_to_linear_data_offset(skb, 0, 315 page_address(dma_info->page) + offset, 316 len); 317 if (unlikely(offset + headlen > PAGE_SIZE)) { 318 dma_info++; 319 headlen_pg = len; 320 len = ALIGN(headlen - headlen_pg, sizeof(long)); 321 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 322 DMA_FROM_DEVICE); 323 skb_copy_to_linear_data_offset(skb, headlen_pg, 324 page_address(dma_info->page), 325 len); 326 } 327 } 328 329 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 330 { 331 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 332 struct mlx5e_sq *sq = &rq->channel->icosq; 333 struct mlx5_wq_cyc *wq = &sq->wq; 334 struct mlx5e_umr_wqe *wqe; 335 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 336 u16 pi; 337 338 /* fill sq edge with nops to avoid wqe wrap around */ 339 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 340 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 341 sq->db.ico_wqe[pi].num_wqebbs = 1; 342 mlx5e_send_nop(sq, true); 343 } 344 345 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 346 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 347 wqe->ctrl.opmod_idx_opcode = 348 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 349 MLX5_OPCODE_UMR); 350 351 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 352 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs; 353 sq->pc += num_wqebbs; 354 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0); 355 } 356 357 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 358 struct mlx5e_rx_wqe *wqe, 359 u16 ix) 360 { 361 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 362 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT; 363 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 364 int err; 365 int i; 366 367 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 368 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 369 370 err = mlx5e_page_alloc_mapped(rq, dma_info); 371 if (unlikely(err)) 372 goto err_unmap; 373 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 374 page_ref_add(dma_info->page, pg_strides); 375 wi->skbs_frags[i] = 0; 376 } 377 378 wi->consumed_strides = 0; 379 wqe->data.addr = cpu_to_be64(dma_offset); 380 381 return 0; 382 383 err_unmap: 384 while (--i >= 0) { 385 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 386 387 page_ref_sub(dma_info->page, pg_strides); 388 mlx5e_page_release(rq, dma_info, true); 389 } 390 391 return err; 392 } 393 394 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 395 { 396 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 397 int i; 398 399 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 400 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 401 402 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 403 mlx5e_page_release(rq, dma_info, true); 404 } 405 } 406 407 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 408 { 409 struct mlx5_wq_ll *wq = &rq->wq; 410 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 411 412 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 413 414 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) { 415 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); 416 return; 417 } 418 419 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 420 421 /* ensure wqes are visible to device before updating doorbell record */ 422 dma_wmb(); 423 424 mlx5_wq_ll_update_db_record(wq); 425 } 426 427 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 428 { 429 int err; 430 431 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix); 432 if (unlikely(err)) 433 return err; 434 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 435 mlx5e_post_umr_wqe(rq, ix); 436 return -EBUSY; 437 } 438 439 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 440 { 441 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 442 443 mlx5e_free_rx_mpwqe(rq, wi); 444 } 445 446 #define RQ_CANNOT_POST(rq) \ 447 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \ 448 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) 449 450 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 451 { 452 struct mlx5_wq_ll *wq = &rq->wq; 453 454 if (unlikely(RQ_CANNOT_POST(rq))) 455 return false; 456 457 while (!mlx5_wq_ll_is_full(wq)) { 458 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 459 int err; 460 461 err = rq->alloc_wqe(rq, wqe, wq->head); 462 if (err == -EBUSY) 463 return true; 464 if (unlikely(err)) { 465 rq->stats.buff_alloc_err++; 466 break; 467 } 468 469 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 470 } 471 472 /* ensure wqes are visible to device before updating doorbell record */ 473 dma_wmb(); 474 475 mlx5_wq_ll_update_db_record(wq); 476 477 return !mlx5_wq_ll_is_full(wq); 478 } 479 480 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 481 u32 cqe_bcnt) 482 { 483 struct ethhdr *eth = (struct ethhdr *)(skb->data); 484 struct iphdr *ipv4; 485 struct ipv6hdr *ipv6; 486 struct tcphdr *tcp; 487 int network_depth = 0; 488 __be16 proto; 489 u16 tot_len; 490 491 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 492 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 493 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 494 495 skb->mac_len = ETH_HLEN; 496 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 497 498 ipv4 = (struct iphdr *)(skb->data + network_depth); 499 ipv6 = (struct ipv6hdr *)(skb->data + network_depth); 500 tot_len = cqe_bcnt - network_depth; 501 502 if (proto == htons(ETH_P_IP)) { 503 tcp = (struct tcphdr *)(skb->data + network_depth + 504 sizeof(struct iphdr)); 505 ipv6 = NULL; 506 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 507 } else { 508 tcp = (struct tcphdr *)(skb->data + network_depth + 509 sizeof(struct ipv6hdr)); 510 ipv4 = NULL; 511 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 512 } 513 514 if (get_cqe_lro_tcppsh(cqe)) 515 tcp->psh = 1; 516 517 if (tcp_ack) { 518 tcp->ack = 1; 519 tcp->ack_seq = cqe->lro_ack_seq_num; 520 tcp->window = cqe->lro_tcp_win; 521 } 522 523 if (ipv4) { 524 ipv4->ttl = cqe->lro_min_ttl; 525 ipv4->tot_len = cpu_to_be16(tot_len); 526 ipv4->check = 0; 527 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 528 ipv4->ihl); 529 } else { 530 ipv6->hop_limit = cqe->lro_min_ttl; 531 ipv6->payload_len = cpu_to_be16(tot_len - 532 sizeof(struct ipv6hdr)); 533 } 534 } 535 536 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 537 struct sk_buff *skb) 538 { 539 u8 cht = cqe->rss_hash_type; 540 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 541 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 542 PKT_HASH_TYPE_NONE; 543 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 544 } 545 546 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 547 { 548 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 549 550 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 551 } 552 553 static inline void mlx5e_handle_csum(struct net_device *netdev, 554 struct mlx5_cqe64 *cqe, 555 struct mlx5e_rq *rq, 556 struct sk_buff *skb, 557 bool lro) 558 { 559 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 560 goto csum_none; 561 562 if (lro) { 563 skb->ip_summed = CHECKSUM_UNNECESSARY; 564 return; 565 } 566 567 if (is_first_ethertype_ip(skb)) { 568 skb->ip_summed = CHECKSUM_COMPLETE; 569 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 570 rq->stats.csum_complete++; 571 return; 572 } 573 574 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 575 (cqe->hds_ip_ext & CQE_L4_OK))) { 576 skb->ip_summed = CHECKSUM_UNNECESSARY; 577 if (cqe_is_tunneled(cqe)) { 578 skb->csum_level = 1; 579 skb->encapsulation = 1; 580 rq->stats.csum_unnecessary_inner++; 581 } 582 return; 583 } 584 csum_none: 585 skb->ip_summed = CHECKSUM_NONE; 586 rq->stats.csum_none++; 587 } 588 589 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 590 u32 cqe_bcnt, 591 struct mlx5e_rq *rq, 592 struct sk_buff *skb) 593 { 594 struct net_device *netdev = rq->netdev; 595 struct mlx5e_tstamp *tstamp = rq->tstamp; 596 int lro_num_seg; 597 598 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 599 if (lro_num_seg > 1) { 600 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 601 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 602 rq->stats.lro_packets++; 603 rq->stats.lro_bytes += cqe_bcnt; 604 } 605 606 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 607 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 608 609 skb_record_rx_queue(skb, rq->ix); 610 611 if (likely(netdev->features & NETIF_F_RXHASH)) 612 mlx5e_skb_set_hash(cqe, skb); 613 614 if (cqe_has_vlan(cqe)) 615 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 616 be16_to_cpu(cqe->vlan_info)); 617 618 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 619 620 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 621 skb->protocol = eth_type_trans(skb, netdev); 622 } 623 624 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 625 struct mlx5_cqe64 *cqe, 626 u32 cqe_bcnt, 627 struct sk_buff *skb) 628 { 629 rq->stats.packets++; 630 rq->stats.bytes += cqe_bcnt; 631 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 632 napi_gro_receive(rq->cq.napi, skb); 633 } 634 635 static inline enum xdp_action mlx5e_xdp_handle(struct mlx5e_rq *rq, 636 const struct bpf_prog *prog, 637 void *data, u32 len) 638 { 639 struct xdp_buff xdp; 640 641 xdp.data = data; 642 xdp.data_end = xdp.data + len; 643 return bpf_prog_run_xdp(prog, &xdp); 644 } 645 646 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 647 { 648 struct bpf_prog *xdp_prog = READ_ONCE(rq->xdp_prog); 649 struct mlx5e_dma_info *di; 650 struct mlx5e_rx_wqe *wqe; 651 __be16 wqe_counter_be; 652 struct sk_buff *skb; 653 u16 wqe_counter; 654 u32 cqe_bcnt; 655 void *va; 656 657 wqe_counter_be = cqe->wqe_counter; 658 wqe_counter = be16_to_cpu(wqe_counter_be); 659 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 660 di = &rq->dma_info[wqe_counter]; 661 va = page_address(di->page); 662 663 dma_sync_single_range_for_cpu(rq->pdev, 664 di->addr, 665 MLX5_RX_HEADROOM, 666 rq->buff.wqe_sz, 667 DMA_FROM_DEVICE); 668 prefetch(va + MLX5_RX_HEADROOM); 669 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 670 671 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 672 rq->stats.wqe_err++; 673 mlx5e_page_release(rq, di, true); 674 goto wq_ll_pop; 675 } 676 677 if (xdp_prog) { 678 enum xdp_action act = 679 mlx5e_xdp_handle(rq, xdp_prog, va + MLX5_RX_HEADROOM, 680 cqe_bcnt); 681 682 if (act != XDP_PASS) { 683 rq->stats.xdp_drop++; 684 mlx5e_page_release(rq, di, true); 685 goto wq_ll_pop; 686 } 687 } 688 689 skb = build_skb(va, RQ_PAGE_SIZE(rq)); 690 if (unlikely(!skb)) { 691 rq->stats.buff_alloc_err++; 692 mlx5e_page_release(rq, di, true); 693 goto wq_ll_pop; 694 } 695 696 /* queue up for recycling ..*/ 697 page_ref_inc(di->page); 698 mlx5e_page_release(rq, di, true); 699 700 skb_reserve(skb, MLX5_RX_HEADROOM); 701 skb_put(skb, cqe_bcnt); 702 703 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 704 705 wq_ll_pop: 706 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 707 &wqe->next.next_wqe_index); 708 } 709 710 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 711 struct mlx5_cqe64 *cqe, 712 struct mlx5e_mpw_info *wi, 713 u32 cqe_bcnt, 714 struct sk_buff *skb) 715 { 716 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 717 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz; 718 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 719 u32 page_idx = wqe_offset >> PAGE_SHIFT; 720 u32 head_page_idx = page_idx; 721 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 722 u32 frag_offset = head_offset + headlen; 723 u16 byte_cnt = cqe_bcnt - headlen; 724 725 if (unlikely(frag_offset >= PAGE_SIZE)) { 726 page_idx++; 727 frag_offset -= PAGE_SIZE; 728 } 729 730 while (byte_cnt) { 731 u32 pg_consumed_bytes = 732 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 733 734 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 735 pg_consumed_bytes); 736 byte_cnt -= pg_consumed_bytes; 737 frag_offset = 0; 738 page_idx++; 739 } 740 /* copy header */ 741 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 742 head_offset, headlen); 743 /* skb linear part was allocated with headlen and aligned to long */ 744 skb->tail += headlen; 745 skb->len += headlen; 746 } 747 748 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 749 { 750 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 751 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 752 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 753 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 754 struct sk_buff *skb; 755 u16 cqe_bcnt; 756 757 wi->consumed_strides += cstrides; 758 759 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 760 rq->stats.wqe_err++; 761 goto mpwrq_cqe_out; 762 } 763 764 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 765 rq->stats.mpwqe_filler++; 766 goto mpwrq_cqe_out; 767 } 768 769 skb = napi_alloc_skb(rq->cq.napi, 770 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 771 sizeof(long))); 772 if (unlikely(!skb)) { 773 rq->stats.buff_alloc_err++; 774 goto mpwrq_cqe_out; 775 } 776 777 prefetch(skb->data); 778 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 779 780 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 781 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 782 783 mpwrq_cqe_out: 784 if (likely(wi->consumed_strides < rq->mpwqe_num_strides)) 785 return; 786 787 mlx5e_free_rx_mpwqe(rq, wi); 788 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 789 } 790 791 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 792 { 793 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 794 int work_done = 0; 795 796 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) 797 return 0; 798 799 if (cq->decmprs_left) 800 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 801 802 for (; work_done < budget; work_done++) { 803 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); 804 805 if (!cqe) 806 break; 807 808 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 809 work_done += 810 mlx5e_decompress_cqes_start(rq, cq, 811 budget - work_done); 812 continue; 813 } 814 815 mlx5_cqwq_pop(&cq->wq); 816 817 rq->handle_rx_cqe(rq, cqe); 818 } 819 820 mlx5_cqwq_update_db_record(&cq->wq); 821 822 /* ensure cq space is freed before enabling more cqes */ 823 wmb(); 824 825 return work_done; 826 } 827