1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 47 { 48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 49 } 50 51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 52 void *data) 53 { 54 u32 ci = cqcc & cq->wq.sz_m1; 55 56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 57 } 58 59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 60 struct mlx5e_cq *cq, u32 cqcc) 61 { 62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 65 rq->stats.cqe_compress_blks++; 66 } 67 68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 69 { 70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 71 cq->mini_arr_idx = 0; 72 } 73 74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 75 { 76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 77 u32 wq_sz = 1 << cq->wq.log_sz; 78 u32 ci = cqcc & cq->wq.sz_m1; 79 u32 ci_top = min_t(u32, wq_sz, ci + n); 80 81 for (; ci < ci_top; ci++, n--) { 82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 83 84 cqe->op_own = op_own; 85 } 86 87 if (unlikely(ci == wq_sz)) { 88 op_own = !op_own; 89 for (ci = 0; ci < n; ci++) { 90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 91 92 cqe->op_own = op_own; 93 } 94 } 95 } 96 97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 98 struct mlx5e_cq *cq, u32 cqcc) 99 { 100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 102 cq->title.op_own &= 0xf0; 103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 105 106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 107 cq->decmprs_wqe_counter += 108 mpwrq_get_cqe_consumed_strides(&cq->title); 109 else 110 cq->decmprs_wqe_counter = 111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 112 } 113 114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 115 struct mlx5e_cq *cq, u32 cqcc) 116 { 117 mlx5e_decompress_cqe(rq, cq, cqcc); 118 cq->title.rss_hash_type = 0; 119 cq->title.rss_hash_result = 0; 120 } 121 122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 123 struct mlx5e_cq *cq, 124 int update_owner_only, 125 int budget_rem) 126 { 127 u32 cqcc = cq->wq.cc + update_owner_only; 128 u32 cqe_count; 129 u32 i; 130 131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 132 133 for (i = update_owner_only; i < cqe_count; 134 i++, cq->mini_arr_idx++, cqcc++) { 135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 136 mlx5e_read_mini_arr_slot(cq, cqcc); 137 138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 139 rq->handle_rx_cqe(rq, &cq->title); 140 } 141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 142 cq->wq.cc = cqcc; 143 cq->decmprs_left -= cqe_count; 144 rq->stats.cqe_compress_pkts += cqe_count; 145 146 return cqe_count; 147 } 148 149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 150 struct mlx5e_cq *cq, 151 int budget_rem) 152 { 153 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 156 rq->handle_rx_cqe(rq, &cq->title); 157 cq->mini_arr_idx++; 158 159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 160 } 161 162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 163 164 static inline bool mlx5e_page_is_reserved(struct page *page) 165 { 166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 167 } 168 169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 170 struct mlx5e_dma_info *dma_info) 171 { 172 struct mlx5e_page_cache *cache = &rq->page_cache; 173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 174 175 if (tail_next == cache->head) { 176 rq->stats.cache_full++; 177 return false; 178 } 179 180 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 181 rq->stats.cache_waive++; 182 return false; 183 } 184 185 cache->page_cache[cache->tail] = *dma_info; 186 cache->tail = tail_next; 187 return true; 188 } 189 190 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 191 struct mlx5e_dma_info *dma_info) 192 { 193 struct mlx5e_page_cache *cache = &rq->page_cache; 194 195 if (unlikely(cache->head == cache->tail)) { 196 rq->stats.cache_empty++; 197 return false; 198 } 199 200 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 201 rq->stats.cache_busy++; 202 return false; 203 } 204 205 *dma_info = cache->page_cache[cache->head]; 206 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 207 rq->stats.cache_reuse++; 208 209 dma_sync_single_for_device(rq->pdev, dma_info->addr, 210 RQ_PAGE_SIZE(rq), 211 DMA_FROM_DEVICE); 212 return true; 213 } 214 215 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 216 struct mlx5e_dma_info *dma_info) 217 { 218 struct page *page; 219 220 if (mlx5e_rx_cache_get(rq, dma_info)) 221 return 0; 222 223 page = dev_alloc_pages(rq->buff.page_order); 224 if (unlikely(!page)) 225 return -ENOMEM; 226 227 dma_info->addr = dma_map_page(rq->pdev, page, 0, 228 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 229 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 230 put_page(page); 231 return -ENOMEM; 232 } 233 dma_info->page = page; 234 235 return 0; 236 } 237 238 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 239 bool recycle) 240 { 241 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 242 return; 243 244 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 245 rq->buff.map_dir); 246 put_page(dma_info->page); 247 } 248 249 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 250 struct mlx5e_wqe_frag_info *wi) 251 { 252 return rq->wqe.page_reuse && wi->di.page && 253 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 254 !mlx5e_page_is_reserved(wi->di.page); 255 } 256 257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 258 { 259 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 260 261 /* check if page exists, hence can be reused */ 262 if (!wi->di.page) { 263 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 264 return -ENOMEM; 265 wi->offset = 0; 266 } 267 268 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 269 return 0; 270 } 271 272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 273 struct mlx5e_wqe_frag_info *wi) 274 { 275 mlx5e_page_release(rq, &wi->di, true); 276 wi->di.page = NULL; 277 } 278 279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 280 struct mlx5e_wqe_frag_info *wi) 281 { 282 if (mlx5e_page_reuse(rq, wi)) { 283 rq->stats.page_reuse++; 284 return; 285 } 286 287 mlx5e_free_rx_wqe(rq, wi); 288 } 289 290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 291 { 292 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 293 294 if (wi->di.page) 295 mlx5e_free_rx_wqe(rq, wi); 296 } 297 298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 299 { 300 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 301 } 302 303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 304 struct sk_buff *skb, 305 struct mlx5e_mpw_info *wi, 306 u32 page_idx, u32 frag_offset, 307 u32 len) 308 { 309 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 310 311 dma_sync_single_for_cpu(rq->pdev, 312 wi->umr.dma_info[page_idx].addr + frag_offset, 313 len, DMA_FROM_DEVICE); 314 wi->skbs_frags[page_idx]++; 315 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 316 wi->umr.dma_info[page_idx].page, frag_offset, 317 len, truesize); 318 } 319 320 static inline void 321 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 322 struct sk_buff *skb, 323 struct mlx5e_mpw_info *wi, 324 u32 page_idx, u32 offset, 325 u32 headlen) 326 { 327 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 328 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 329 unsigned int len; 330 331 /* Aligning len to sizeof(long) optimizes memcpy performance */ 332 len = ALIGN(headlen_pg, sizeof(long)); 333 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 334 DMA_FROM_DEVICE); 335 skb_copy_to_linear_data_offset(skb, 0, 336 page_address(dma_info->page) + offset, 337 len); 338 if (unlikely(offset + headlen > PAGE_SIZE)) { 339 dma_info++; 340 headlen_pg = len; 341 len = ALIGN(headlen - headlen_pg, sizeof(long)); 342 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 343 DMA_FROM_DEVICE); 344 skb_copy_to_linear_data_offset(skb, headlen_pg, 345 page_address(dma_info->page), 346 len); 347 } 348 } 349 350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 351 { 352 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 353 struct mlx5e_icosq *sq = &rq->channel->icosq; 354 struct mlx5_wq_cyc *wq = &sq->wq; 355 struct mlx5e_umr_wqe *wqe; 356 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 357 u16 pi; 358 359 /* fill sq edge with nops to avoid wqe wrap around */ 360 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 361 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 362 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 363 } 364 365 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 366 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 367 wqe->ctrl.opmod_idx_opcode = 368 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 369 MLX5_OPCODE_UMR); 370 371 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 372 sq->pc += num_wqebbs; 373 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 374 } 375 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 377 u16 ix) 378 { 379 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 380 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 381 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 382 int err; 383 int i; 384 385 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 386 err = mlx5e_page_alloc_mapped(rq, dma_info); 387 if (unlikely(err)) 388 goto err_unmap; 389 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 390 page_ref_add(dma_info->page, pg_strides); 391 } 392 393 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 394 wi->consumed_strides = 0; 395 396 return 0; 397 398 err_unmap: 399 while (--i >= 0) { 400 dma_info--; 401 page_ref_sub(dma_info->page, pg_strides); 402 mlx5e_page_release(rq, dma_info, true); 403 } 404 405 return err; 406 } 407 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 409 { 410 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 411 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 412 int i; 413 414 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 415 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 416 mlx5e_page_release(rq, dma_info, true); 417 } 418 } 419 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 421 { 422 struct mlx5_wq_ll *wq = &rq->wq; 423 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 424 425 rq->mpwqe.umr_in_progress = false; 426 427 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 428 429 /* ensure wqes are visible to device before updating doorbell record */ 430 dma_wmb(); 431 432 mlx5_wq_ll_update_db_record(wq); 433 } 434 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 436 { 437 int err; 438 439 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 440 if (unlikely(err)) { 441 rq->stats.buff_alloc_err++; 442 return err; 443 } 444 rq->mpwqe.umr_in_progress = true; 445 mlx5e_post_umr_wqe(rq, ix); 446 return 0; 447 } 448 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 450 { 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 452 453 mlx5e_free_rx_mpwqe(rq, wi); 454 } 455 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 457 { 458 struct mlx5_wq_ll *wq = &rq->wq; 459 int err; 460 461 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 462 return false; 463 464 if (mlx5_wq_ll_is_full(wq)) 465 return false; 466 467 do { 468 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 469 470 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 471 if (unlikely(err)) { 472 rq->stats.buff_alloc_err++; 473 break; 474 } 475 476 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 477 } while (!mlx5_wq_ll_is_full(wq)); 478 479 /* ensure wqes are visible to device before updating doorbell record */ 480 dma_wmb(); 481 482 mlx5_wq_ll_update_db_record(wq); 483 484 return !!err; 485 } 486 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 488 struct mlx5e_icosq *sq, 489 struct mlx5e_rq *rq, 490 struct mlx5_cqe64 *cqe) 491 { 492 struct mlx5_wq_cyc *wq = &sq->wq; 493 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 494 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 495 496 mlx5_cqwq_pop(&cq->wq); 497 498 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 499 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 500 cqe->op_own); 501 return; 502 } 503 504 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 505 mlx5e_post_rx_mpwqe(rq); 506 return; 507 } 508 509 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 510 WARN_ONCE(true, 511 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 512 icowi->opcode); 513 } 514 515 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 516 { 517 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 518 struct mlx5_cqe64 *cqe; 519 520 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 521 return; 522 523 cqe = mlx5_cqwq_get_cqe(&cq->wq); 524 if (likely(!cqe)) 525 return; 526 527 /* by design, there's only a single cqe */ 528 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 529 530 mlx5_cqwq_update_db_record(&cq->wq); 531 } 532 533 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 534 { 535 struct mlx5_wq_ll *wq = &rq->wq; 536 537 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 538 return false; 539 540 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 541 542 if (mlx5_wq_ll_is_full(wq)) 543 return false; 544 545 if (!rq->mpwqe.umr_in_progress) 546 mlx5e_alloc_rx_mpwqe(rq, wq->head); 547 548 return true; 549 } 550 551 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 552 u32 cqe_bcnt) 553 { 554 struct ethhdr *eth = (struct ethhdr *)(skb->data); 555 struct tcphdr *tcp; 556 int network_depth = 0; 557 __be16 proto; 558 u16 tot_len; 559 void *ip_p; 560 561 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 562 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 563 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 564 565 skb->mac_len = ETH_HLEN; 566 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 567 568 tot_len = cqe_bcnt - network_depth; 569 ip_p = skb->data + network_depth; 570 571 if (proto == htons(ETH_P_IP)) { 572 struct iphdr *ipv4 = ip_p; 573 574 tcp = ip_p + sizeof(struct iphdr); 575 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 576 577 ipv4->ttl = cqe->lro_min_ttl; 578 ipv4->tot_len = cpu_to_be16(tot_len); 579 ipv4->check = 0; 580 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 581 ipv4->ihl); 582 } else { 583 struct ipv6hdr *ipv6 = ip_p; 584 585 tcp = ip_p + sizeof(struct ipv6hdr); 586 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 587 588 ipv6->hop_limit = cqe->lro_min_ttl; 589 ipv6->payload_len = cpu_to_be16(tot_len - 590 sizeof(struct ipv6hdr)); 591 } 592 593 tcp->psh = get_cqe_lro_tcppsh(cqe); 594 595 if (tcp_ack) { 596 tcp->ack = 1; 597 tcp->ack_seq = cqe->lro_ack_seq_num; 598 tcp->window = cqe->lro_tcp_win; 599 } 600 } 601 602 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 603 struct sk_buff *skb) 604 { 605 u8 cht = cqe->rss_hash_type; 606 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 607 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 608 PKT_HASH_TYPE_NONE; 609 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 610 } 611 612 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 613 { 614 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 615 616 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 617 } 618 619 static inline void mlx5e_handle_csum(struct net_device *netdev, 620 struct mlx5_cqe64 *cqe, 621 struct mlx5e_rq *rq, 622 struct sk_buff *skb, 623 bool lro) 624 { 625 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 626 goto csum_none; 627 628 if (lro) { 629 skb->ip_summed = CHECKSUM_UNNECESSARY; 630 return; 631 } 632 633 if (is_first_ethertype_ip(skb)) { 634 skb->ip_summed = CHECKSUM_COMPLETE; 635 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 636 rq->stats.csum_complete++; 637 return; 638 } 639 640 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 641 (cqe->hds_ip_ext & CQE_L4_OK))) { 642 skb->ip_summed = CHECKSUM_UNNECESSARY; 643 if (cqe_is_tunneled(cqe)) { 644 skb->csum_level = 1; 645 skb->encapsulation = 1; 646 rq->stats.csum_unnecessary_inner++; 647 } 648 return; 649 } 650 csum_none: 651 skb->ip_summed = CHECKSUM_NONE; 652 rq->stats.csum_none++; 653 } 654 655 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 656 u32 cqe_bcnt, 657 struct mlx5e_rq *rq, 658 struct sk_buff *skb) 659 { 660 struct net_device *netdev = rq->netdev; 661 struct mlx5e_tstamp *tstamp = rq->tstamp; 662 int lro_num_seg; 663 664 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 665 if (lro_num_seg > 1) { 666 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 667 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 668 /* Subtract one since we already counted this as one 669 * "regular" packet in mlx5e_complete_rx_cqe() 670 */ 671 rq->stats.packets += lro_num_seg - 1; 672 rq->stats.lro_packets++; 673 rq->stats.lro_bytes += cqe_bcnt; 674 } 675 676 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 677 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 678 679 skb_record_rx_queue(skb, rq->ix); 680 681 if (likely(netdev->features & NETIF_F_RXHASH)) 682 mlx5e_skb_set_hash(cqe, skb); 683 684 if (cqe_has_vlan(cqe)) 685 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 686 be16_to_cpu(cqe->vlan_info)); 687 688 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 689 690 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 691 skb->protocol = eth_type_trans(skb, netdev); 692 } 693 694 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 695 struct mlx5_cqe64 *cqe, 696 u32 cqe_bcnt, 697 struct sk_buff *skb) 698 { 699 rq->stats.packets++; 700 rq->stats.bytes += cqe_bcnt; 701 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 702 } 703 704 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 705 { 706 struct mlx5_wq_cyc *wq = &sq->wq; 707 struct mlx5e_tx_wqe *wqe; 708 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 709 710 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 711 712 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 713 } 714 715 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 716 struct mlx5e_dma_info *di, 717 const struct xdp_buff *xdp) 718 { 719 struct mlx5e_xdpsq *sq = &rq->xdpsq; 720 struct mlx5_wq_cyc *wq = &sq->wq; 721 u16 pi = sq->pc & wq->sz_m1; 722 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 723 724 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 725 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 726 struct mlx5_wqe_data_seg *dseg; 727 728 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 729 dma_addr_t dma_addr = di->addr + data_offset; 730 unsigned int dma_len = xdp->data_end - xdp->data; 731 732 prefetchw(wqe); 733 734 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 735 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 736 rq->stats.xdp_drop++; 737 return false; 738 } 739 740 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 741 if (sq->db.doorbell) { 742 /* SQ is full, ring doorbell */ 743 mlx5e_xmit_xdp_doorbell(sq); 744 sq->db.doorbell = false; 745 } 746 rq->stats.xdp_tx_full++; 747 return false; 748 } 749 750 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 751 752 cseg->fm_ce_se = 0; 753 754 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 755 756 /* copy the inline part if required */ 757 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 758 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 759 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 760 dma_len -= MLX5E_XDP_MIN_INLINE; 761 dma_addr += MLX5E_XDP_MIN_INLINE; 762 dseg++; 763 } 764 765 /* write the dma part */ 766 dseg->addr = cpu_to_be64(dma_addr); 767 dseg->byte_count = cpu_to_be32(dma_len); 768 769 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 770 771 /* move page to reference to sq responsibility, 772 * and mark so it's not put back in page-cache. 773 */ 774 rq->wqe.xdp_xmit = true; 775 sq->db.di[pi] = *di; 776 sq->pc++; 777 778 sq->db.doorbell = true; 779 780 rq->stats.xdp_tx++; 781 return true; 782 } 783 784 /* returns true if packet was consumed by xdp */ 785 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 786 struct mlx5e_dma_info *di, 787 void *va, u16 *rx_headroom, u32 *len) 788 { 789 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 790 struct xdp_buff xdp; 791 u32 act; 792 793 if (!prog) 794 return false; 795 796 xdp.data = va + *rx_headroom; 797 xdp_set_data_meta_invalid(&xdp); 798 xdp.data_end = xdp.data + *len; 799 xdp.data_hard_start = va; 800 801 act = bpf_prog_run_xdp(prog, &xdp); 802 switch (act) { 803 case XDP_PASS: 804 *rx_headroom = xdp.data - xdp.data_hard_start; 805 *len = xdp.data_end - xdp.data; 806 return false; 807 case XDP_TX: 808 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 809 trace_xdp_exception(rq->netdev, prog, act); 810 return true; 811 default: 812 bpf_warn_invalid_xdp_action(act); 813 case XDP_ABORTED: 814 trace_xdp_exception(rq->netdev, prog, act); 815 case XDP_DROP: 816 rq->stats.xdp_drop++; 817 return true; 818 } 819 } 820 821 static inline 822 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 823 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 824 { 825 struct mlx5e_dma_info *di = &wi->di; 826 u16 rx_headroom = rq->buff.headroom; 827 struct sk_buff *skb; 828 void *va, *data; 829 bool consumed; 830 u32 frag_size; 831 832 va = page_address(di->page) + wi->offset; 833 data = va + rx_headroom; 834 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 835 836 dma_sync_single_range_for_cpu(rq->pdev, 837 di->addr + wi->offset, 838 0, frag_size, 839 DMA_FROM_DEVICE); 840 prefetch(data); 841 wi->offset += frag_size; 842 843 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 844 rq->stats.wqe_err++; 845 return NULL; 846 } 847 848 rcu_read_lock(); 849 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 850 rcu_read_unlock(); 851 if (consumed) 852 return NULL; /* page/packet was consumed by XDP */ 853 854 skb = build_skb(va, frag_size); 855 if (unlikely(!skb)) { 856 rq->stats.buff_alloc_err++; 857 return NULL; 858 } 859 860 /* queue up for recycling/reuse */ 861 page_ref_inc(di->page); 862 863 skb_reserve(skb, rx_headroom); 864 skb_put(skb, cqe_bcnt); 865 866 return skb; 867 } 868 869 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 870 { 871 struct mlx5e_wqe_frag_info *wi; 872 struct mlx5e_rx_wqe *wqe; 873 __be16 wqe_counter_be; 874 struct sk_buff *skb; 875 u16 wqe_counter; 876 u32 cqe_bcnt; 877 878 wqe_counter_be = cqe->wqe_counter; 879 wqe_counter = be16_to_cpu(wqe_counter_be); 880 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 881 wi = &rq->wqe.frag_info[wqe_counter]; 882 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 883 884 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 885 if (!skb) { 886 /* probably for XDP */ 887 if (rq->wqe.xdp_xmit) { 888 wi->di.page = NULL; 889 rq->wqe.xdp_xmit = false; 890 /* do not return page to cache, it will be returned on XDP_TX completion */ 891 goto wq_ll_pop; 892 } 893 /* probably an XDP_DROP, save the page-reuse checks */ 894 mlx5e_free_rx_wqe(rq, wi); 895 goto wq_ll_pop; 896 } 897 898 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 899 napi_gro_receive(rq->cq.napi, skb); 900 901 mlx5e_free_rx_wqe_reuse(rq, wi); 902 wq_ll_pop: 903 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 904 &wqe->next.next_wqe_index); 905 } 906 907 #ifdef CONFIG_MLX5_ESWITCH 908 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 909 { 910 struct net_device *netdev = rq->netdev; 911 struct mlx5e_priv *priv = netdev_priv(netdev); 912 struct mlx5e_rep_priv *rpriv = priv->ppriv; 913 struct mlx5_eswitch_rep *rep = rpriv->rep; 914 struct mlx5e_wqe_frag_info *wi; 915 struct mlx5e_rx_wqe *wqe; 916 struct sk_buff *skb; 917 __be16 wqe_counter_be; 918 u16 wqe_counter; 919 u32 cqe_bcnt; 920 921 wqe_counter_be = cqe->wqe_counter; 922 wqe_counter = be16_to_cpu(wqe_counter_be); 923 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 924 wi = &rq->wqe.frag_info[wqe_counter]; 925 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 926 927 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 928 if (!skb) { 929 if (rq->wqe.xdp_xmit) { 930 wi->di.page = NULL; 931 rq->wqe.xdp_xmit = false; 932 /* do not return page to cache, it will be returned on XDP_TX completion */ 933 goto wq_ll_pop; 934 } 935 /* probably an XDP_DROP, save the page-reuse checks */ 936 mlx5e_free_rx_wqe(rq, wi); 937 goto wq_ll_pop; 938 } 939 940 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 941 942 if (rep->vlan && skb_vlan_tag_present(skb)) 943 skb_vlan_pop(skb); 944 945 napi_gro_receive(rq->cq.napi, skb); 946 947 mlx5e_free_rx_wqe_reuse(rq, wi); 948 wq_ll_pop: 949 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 950 &wqe->next.next_wqe_index); 951 } 952 #endif 953 954 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 955 struct mlx5_cqe64 *cqe, 956 struct mlx5e_mpw_info *wi, 957 u32 cqe_bcnt, 958 struct sk_buff *skb) 959 { 960 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 961 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 962 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 963 u32 page_idx = wqe_offset >> PAGE_SHIFT; 964 u32 head_page_idx = page_idx; 965 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 966 u32 frag_offset = head_offset + headlen; 967 u16 byte_cnt = cqe_bcnt - headlen; 968 969 if (unlikely(frag_offset >= PAGE_SIZE)) { 970 page_idx++; 971 frag_offset -= PAGE_SIZE; 972 } 973 974 while (byte_cnt) { 975 u32 pg_consumed_bytes = 976 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 977 978 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 979 pg_consumed_bytes); 980 byte_cnt -= pg_consumed_bytes; 981 frag_offset = 0; 982 page_idx++; 983 } 984 /* copy header */ 985 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 986 head_offset, headlen); 987 /* skb linear part was allocated with headlen and aligned to long */ 988 skb->tail += headlen; 989 skb->len += headlen; 990 } 991 992 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 993 { 994 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 995 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 996 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 997 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 998 struct sk_buff *skb; 999 u16 cqe_bcnt; 1000 1001 wi->consumed_strides += cstrides; 1002 1003 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1004 rq->stats.wqe_err++; 1005 goto mpwrq_cqe_out; 1006 } 1007 1008 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1009 rq->stats.mpwqe_filler++; 1010 goto mpwrq_cqe_out; 1011 } 1012 1013 skb = napi_alloc_skb(rq->cq.napi, 1014 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1015 sizeof(long))); 1016 if (unlikely(!skb)) { 1017 rq->stats.buff_alloc_err++; 1018 goto mpwrq_cqe_out; 1019 } 1020 1021 prefetchw(skb->data); 1022 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1023 1024 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1025 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1026 napi_gro_receive(rq->cq.napi, skb); 1027 1028 mpwrq_cqe_out: 1029 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1030 return; 1031 1032 mlx5e_free_rx_mpwqe(rq, wi); 1033 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1034 } 1035 1036 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1037 { 1038 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1039 struct mlx5e_xdpsq *xdpsq; 1040 struct mlx5_cqe64 *cqe; 1041 int work_done = 0; 1042 1043 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1044 return 0; 1045 1046 if (cq->decmprs_left) 1047 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1048 1049 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1050 if (!cqe) 1051 return 0; 1052 1053 xdpsq = &rq->xdpsq; 1054 1055 do { 1056 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1057 work_done += 1058 mlx5e_decompress_cqes_start(rq, cq, 1059 budget - work_done); 1060 continue; 1061 } 1062 1063 mlx5_cqwq_pop(&cq->wq); 1064 1065 rq->handle_rx_cqe(rq, cqe); 1066 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1067 1068 if (xdpsq->db.doorbell) { 1069 mlx5e_xmit_xdp_doorbell(xdpsq); 1070 xdpsq->db.doorbell = false; 1071 } 1072 1073 mlx5_cqwq_update_db_record(&cq->wq); 1074 1075 /* ensure cq space is freed before enabling more cqes */ 1076 wmb(); 1077 1078 return work_done; 1079 } 1080 1081 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1082 { 1083 struct mlx5e_xdpsq *sq; 1084 struct mlx5_cqe64 *cqe; 1085 struct mlx5e_rq *rq; 1086 u16 sqcc; 1087 int i; 1088 1089 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1090 1091 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1092 return false; 1093 1094 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1095 if (!cqe) 1096 return false; 1097 1098 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1099 1100 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1101 * otherwise a cq overrun may occur 1102 */ 1103 sqcc = sq->cc; 1104 1105 i = 0; 1106 do { 1107 u16 wqe_counter; 1108 bool last_wqe; 1109 1110 mlx5_cqwq_pop(&cq->wq); 1111 1112 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1113 1114 do { 1115 struct mlx5e_dma_info *di; 1116 u16 ci; 1117 1118 last_wqe = (sqcc == wqe_counter); 1119 1120 ci = sqcc & sq->wq.sz_m1; 1121 di = &sq->db.di[ci]; 1122 1123 sqcc++; 1124 /* Recycle RX page */ 1125 mlx5e_page_release(rq, di, true); 1126 } while (!last_wqe); 1127 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1128 1129 mlx5_cqwq_update_db_record(&cq->wq); 1130 1131 /* ensure cq space is freed before enabling more cqes */ 1132 wmb(); 1133 1134 sq->cc = sqcc; 1135 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1136 } 1137 1138 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1139 { 1140 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1141 struct mlx5e_dma_info *di; 1142 u16 ci; 1143 1144 while (sq->cc != sq->pc) { 1145 ci = sq->cc & sq->wq.sz_m1; 1146 di = &sq->db.di[ci]; 1147 sq->cc++; 1148 1149 mlx5e_page_release(rq, di, false); 1150 } 1151 } 1152 1153 #ifdef CONFIG_MLX5_CORE_IPOIB 1154 1155 #define MLX5_IB_GRH_DGID_OFFSET 24 1156 #define MLX5_GID_SIZE 16 1157 1158 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1159 struct mlx5_cqe64 *cqe, 1160 u32 cqe_bcnt, 1161 struct sk_buff *skb) 1162 { 1163 struct net_device *netdev = rq->netdev; 1164 struct mlx5e_tstamp *tstamp = rq->tstamp; 1165 char *pseudo_header; 1166 u8 *dgid; 1167 u8 g; 1168 1169 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1170 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1171 if ((!g) || dgid[0] != 0xff) 1172 skb->pkt_type = PACKET_HOST; 1173 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1174 skb->pkt_type = PACKET_BROADCAST; 1175 else 1176 skb->pkt_type = PACKET_MULTICAST; 1177 1178 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1179 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1180 */ 1181 1182 skb_pull(skb, MLX5_IB_GRH_BYTES); 1183 1184 skb->protocol = *((__be16 *)(skb->data)); 1185 1186 skb->ip_summed = CHECKSUM_COMPLETE; 1187 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1188 1189 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1190 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 1191 1192 skb_record_rx_queue(skb, rq->ix); 1193 1194 if (likely(netdev->features & NETIF_F_RXHASH)) 1195 mlx5e_skb_set_hash(cqe, skb); 1196 1197 /* 20 bytes of ipoib header and 4 for encap existing */ 1198 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1199 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1200 skb_reset_mac_header(skb); 1201 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1202 1203 skb->dev = netdev; 1204 1205 rq->stats.csum_complete++; 1206 rq->stats.packets++; 1207 rq->stats.bytes += cqe_bcnt; 1208 } 1209 1210 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1211 { 1212 struct mlx5e_wqe_frag_info *wi; 1213 struct mlx5e_rx_wqe *wqe; 1214 __be16 wqe_counter_be; 1215 struct sk_buff *skb; 1216 u16 wqe_counter; 1217 u32 cqe_bcnt; 1218 1219 wqe_counter_be = cqe->wqe_counter; 1220 wqe_counter = be16_to_cpu(wqe_counter_be); 1221 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1222 wi = &rq->wqe.frag_info[wqe_counter]; 1223 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1224 1225 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1226 if (!skb) 1227 goto wq_free_wqe; 1228 1229 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1230 napi_gro_receive(rq->cq.napi, skb); 1231 1232 wq_free_wqe: 1233 mlx5e_free_rx_wqe_reuse(rq, wi); 1234 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1235 &wqe->next.next_wqe_index); 1236 } 1237 1238 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1239 1240 #ifdef CONFIG_MLX5_EN_IPSEC 1241 1242 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1243 { 1244 struct mlx5e_wqe_frag_info *wi; 1245 struct mlx5e_rx_wqe *wqe; 1246 __be16 wqe_counter_be; 1247 struct sk_buff *skb; 1248 u16 wqe_counter; 1249 u32 cqe_bcnt; 1250 1251 wqe_counter_be = cqe->wqe_counter; 1252 wqe_counter = be16_to_cpu(wqe_counter_be); 1253 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1254 wi = &rq->wqe.frag_info[wqe_counter]; 1255 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1256 1257 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1258 if (unlikely(!skb)) { 1259 /* a DROP, save the page-reuse checks */ 1260 mlx5e_free_rx_wqe(rq, wi); 1261 goto wq_ll_pop; 1262 } 1263 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1264 if (unlikely(!skb)) { 1265 mlx5e_free_rx_wqe(rq, wi); 1266 goto wq_ll_pop; 1267 } 1268 1269 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1270 napi_gro_receive(rq->cq.napi, skb); 1271 1272 mlx5e_free_rx_wqe_reuse(rq, wi); 1273 wq_ll_pop: 1274 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1275 &wqe->next.next_wqe_index); 1276 } 1277 1278 #endif /* CONFIG_MLX5_EN_IPSEC */ 1279