1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 43 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 44 { 45 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 46 } 47 48 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 49 void *data) 50 { 51 u32 ci = cqcc & cq->wq.sz_m1; 52 53 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 54 } 55 56 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 57 struct mlx5e_cq *cq, u32 cqcc) 58 { 59 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 60 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 61 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 62 rq->stats.cqe_compress_blks++; 63 } 64 65 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 66 { 67 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 68 cq->mini_arr_idx = 0; 69 } 70 71 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 72 { 73 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 74 u32 wq_sz = 1 << cq->wq.log_sz; 75 u32 ci = cqcc & cq->wq.sz_m1; 76 u32 ci_top = min_t(u32, wq_sz, ci + n); 77 78 for (; ci < ci_top; ci++, n--) { 79 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 80 81 cqe->op_own = op_own; 82 } 83 84 if (unlikely(ci == wq_sz)) { 85 op_own = !op_own; 86 for (ci = 0; ci < n; ci++) { 87 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 88 89 cqe->op_own = op_own; 90 } 91 } 92 } 93 94 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 95 struct mlx5e_cq *cq, u32 cqcc) 96 { 97 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 98 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 99 cq->title.op_own &= 0xf0; 100 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 101 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 102 103 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 104 cq->decmprs_wqe_counter += 105 mpwrq_get_cqe_consumed_strides(&cq->title); 106 else 107 cq->decmprs_wqe_counter = 108 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 109 } 110 111 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 112 struct mlx5e_cq *cq, u32 cqcc) 113 { 114 mlx5e_decompress_cqe(rq, cq, cqcc); 115 cq->title.rss_hash_type = 0; 116 cq->title.rss_hash_result = 0; 117 } 118 119 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 120 struct mlx5e_cq *cq, 121 int update_owner_only, 122 int budget_rem) 123 { 124 u32 cqcc = cq->wq.cc + update_owner_only; 125 u32 cqe_count; 126 u32 i; 127 128 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 129 130 for (i = update_owner_only; i < cqe_count; 131 i++, cq->mini_arr_idx++, cqcc++) { 132 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 133 mlx5e_read_mini_arr_slot(cq, cqcc); 134 135 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 136 rq->handle_rx_cqe(rq, &cq->title); 137 } 138 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 139 cq->wq.cc = cqcc; 140 cq->decmprs_left -= cqe_count; 141 rq->stats.cqe_compress_pkts += cqe_count; 142 143 return cqe_count; 144 } 145 146 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 147 struct mlx5e_cq *cq, 148 int budget_rem) 149 { 150 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 151 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 152 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 153 rq->handle_rx_cqe(rq, &cq->title); 154 cq->mini_arr_idx++; 155 156 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 157 } 158 159 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 160 161 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 162 struct mlx5e_dma_info *dma_info) 163 { 164 struct mlx5e_page_cache *cache = &rq->page_cache; 165 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 166 167 if (tail_next == cache->head) { 168 rq->stats.cache_full++; 169 return false; 170 } 171 172 if (unlikely(page_is_pfmemalloc(dma_info->page))) 173 return false; 174 175 cache->page_cache[cache->tail] = *dma_info; 176 cache->tail = tail_next; 177 return true; 178 } 179 180 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 181 struct mlx5e_dma_info *dma_info) 182 { 183 struct mlx5e_page_cache *cache = &rq->page_cache; 184 185 if (unlikely(cache->head == cache->tail)) { 186 rq->stats.cache_empty++; 187 return false; 188 } 189 190 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 191 rq->stats.cache_busy++; 192 return false; 193 } 194 195 *dma_info = cache->page_cache[cache->head]; 196 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 197 rq->stats.cache_reuse++; 198 199 dma_sync_single_for_device(rq->pdev, dma_info->addr, 200 RQ_PAGE_SIZE(rq), 201 DMA_FROM_DEVICE); 202 return true; 203 } 204 205 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 206 struct mlx5e_dma_info *dma_info) 207 { 208 struct page *page; 209 210 if (mlx5e_rx_cache_get(rq, dma_info)) 211 return 0; 212 213 page = dev_alloc_pages(rq->buff.page_order); 214 if (unlikely(!page)) 215 return -ENOMEM; 216 217 dma_info->page = page; 218 dma_info->addr = dma_map_page(rq->pdev, page, 0, 219 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 220 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 221 put_page(page); 222 return -ENOMEM; 223 } 224 225 return 0; 226 } 227 228 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 229 bool recycle) 230 { 231 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 232 return; 233 234 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 235 rq->buff.map_dir); 236 put_page(dma_info->page); 237 } 238 239 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 240 { 241 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 242 243 if (unlikely(mlx5e_page_alloc_mapped(rq, di))) 244 return -ENOMEM; 245 246 wqe->data.addr = cpu_to_be64(di->addr + rq->rx_headroom); 247 return 0; 248 } 249 250 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 251 { 252 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 253 254 mlx5e_page_release(rq, di, true); 255 } 256 257 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 258 { 259 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 260 } 261 262 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 263 struct sk_buff *skb, 264 struct mlx5e_mpw_info *wi, 265 u32 page_idx, u32 frag_offset, 266 u32 len) 267 { 268 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz); 269 270 dma_sync_single_for_cpu(rq->pdev, 271 wi->umr.dma_info[page_idx].addr + frag_offset, 272 len, DMA_FROM_DEVICE); 273 wi->skbs_frags[page_idx]++; 274 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 275 wi->umr.dma_info[page_idx].page, frag_offset, 276 len, truesize); 277 } 278 279 static inline void 280 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 281 struct sk_buff *skb, 282 struct mlx5e_mpw_info *wi, 283 u32 page_idx, u32 offset, 284 u32 headlen) 285 { 286 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 287 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 288 unsigned int len; 289 290 /* Aligning len to sizeof(long) optimizes memcpy performance */ 291 len = ALIGN(headlen_pg, sizeof(long)); 292 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 293 DMA_FROM_DEVICE); 294 skb_copy_to_linear_data_offset(skb, 0, 295 page_address(dma_info->page) + offset, 296 len); 297 if (unlikely(offset + headlen > PAGE_SIZE)) { 298 dma_info++; 299 headlen_pg = len; 300 len = ALIGN(headlen - headlen_pg, sizeof(long)); 301 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 302 DMA_FROM_DEVICE); 303 skb_copy_to_linear_data_offset(skb, headlen_pg, 304 page_address(dma_info->page), 305 len); 306 } 307 } 308 309 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 310 { 311 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 312 struct mlx5e_icosq *sq = &rq->channel->icosq; 313 struct mlx5_wq_cyc *wq = &sq->wq; 314 struct mlx5e_umr_wqe *wqe; 315 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 316 u16 pi; 317 318 /* fill sq edge with nops to avoid wqe wrap around */ 319 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 320 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 321 sq->db.ico_wqe[pi].num_wqebbs = 1; 322 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 323 } 324 325 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 326 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 327 wqe->ctrl.opmod_idx_opcode = 328 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 329 MLX5_OPCODE_UMR); 330 331 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 332 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs; 333 sq->pc += num_wqebbs; 334 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 335 } 336 337 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 338 struct mlx5e_rx_wqe *wqe, 339 u16 ix) 340 { 341 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 342 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT; 343 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 344 int err; 345 int i; 346 347 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 348 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 349 350 err = mlx5e_page_alloc_mapped(rq, dma_info); 351 if (unlikely(err)) 352 goto err_unmap; 353 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 354 page_ref_add(dma_info->page, pg_strides); 355 wi->skbs_frags[i] = 0; 356 } 357 358 wi->consumed_strides = 0; 359 wqe->data.addr = cpu_to_be64(dma_offset); 360 361 return 0; 362 363 err_unmap: 364 while (--i >= 0) { 365 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 366 367 page_ref_sub(dma_info->page, pg_strides); 368 mlx5e_page_release(rq, dma_info, true); 369 } 370 371 return err; 372 } 373 374 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 375 { 376 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 377 int i; 378 379 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 380 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 381 382 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 383 mlx5e_page_release(rq, dma_info, true); 384 } 385 } 386 387 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 388 { 389 struct mlx5_wq_ll *wq = &rq->wq; 390 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 391 392 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 393 394 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) { 395 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); 396 return; 397 } 398 399 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 400 401 /* ensure wqes are visible to device before updating doorbell record */ 402 dma_wmb(); 403 404 mlx5_wq_ll_update_db_record(wq); 405 } 406 407 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 408 { 409 int err; 410 411 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix); 412 if (unlikely(err)) 413 return err; 414 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 415 mlx5e_post_umr_wqe(rq, ix); 416 return -EBUSY; 417 } 418 419 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 420 { 421 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 422 423 mlx5e_free_rx_mpwqe(rq, wi); 424 } 425 426 #define RQ_CANNOT_POST(rq) \ 427 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \ 428 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) 429 430 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 431 { 432 struct mlx5_wq_ll *wq = &rq->wq; 433 434 if (unlikely(RQ_CANNOT_POST(rq))) 435 return false; 436 437 while (!mlx5_wq_ll_is_full(wq)) { 438 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 439 int err; 440 441 err = rq->alloc_wqe(rq, wqe, wq->head); 442 if (err == -EBUSY) 443 return true; 444 if (unlikely(err)) { 445 rq->stats.buff_alloc_err++; 446 break; 447 } 448 449 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 450 } 451 452 /* ensure wqes are visible to device before updating doorbell record */ 453 dma_wmb(); 454 455 mlx5_wq_ll_update_db_record(wq); 456 457 return !mlx5_wq_ll_is_full(wq); 458 } 459 460 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 461 u32 cqe_bcnt) 462 { 463 struct ethhdr *eth = (struct ethhdr *)(skb->data); 464 struct iphdr *ipv4; 465 struct ipv6hdr *ipv6; 466 struct tcphdr *tcp; 467 int network_depth = 0; 468 __be16 proto; 469 u16 tot_len; 470 471 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 472 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 473 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 474 475 skb->mac_len = ETH_HLEN; 476 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 477 478 ipv4 = (struct iphdr *)(skb->data + network_depth); 479 ipv6 = (struct ipv6hdr *)(skb->data + network_depth); 480 tot_len = cqe_bcnt - network_depth; 481 482 if (proto == htons(ETH_P_IP)) { 483 tcp = (struct tcphdr *)(skb->data + network_depth + 484 sizeof(struct iphdr)); 485 ipv6 = NULL; 486 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 487 } else { 488 tcp = (struct tcphdr *)(skb->data + network_depth + 489 sizeof(struct ipv6hdr)); 490 ipv4 = NULL; 491 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 492 } 493 494 if (get_cqe_lro_tcppsh(cqe)) 495 tcp->psh = 1; 496 497 if (tcp_ack) { 498 tcp->ack = 1; 499 tcp->ack_seq = cqe->lro_ack_seq_num; 500 tcp->window = cqe->lro_tcp_win; 501 } 502 503 if (ipv4) { 504 ipv4->ttl = cqe->lro_min_ttl; 505 ipv4->tot_len = cpu_to_be16(tot_len); 506 ipv4->check = 0; 507 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 508 ipv4->ihl); 509 } else { 510 ipv6->hop_limit = cqe->lro_min_ttl; 511 ipv6->payload_len = cpu_to_be16(tot_len - 512 sizeof(struct ipv6hdr)); 513 } 514 } 515 516 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 517 struct sk_buff *skb) 518 { 519 u8 cht = cqe->rss_hash_type; 520 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 521 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 522 PKT_HASH_TYPE_NONE; 523 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 524 } 525 526 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 527 { 528 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 529 530 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 531 } 532 533 static inline void mlx5e_handle_csum(struct net_device *netdev, 534 struct mlx5_cqe64 *cqe, 535 struct mlx5e_rq *rq, 536 struct sk_buff *skb, 537 bool lro) 538 { 539 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 540 goto csum_none; 541 542 if (lro) { 543 skb->ip_summed = CHECKSUM_UNNECESSARY; 544 return; 545 } 546 547 if (is_first_ethertype_ip(skb)) { 548 skb->ip_summed = CHECKSUM_COMPLETE; 549 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 550 rq->stats.csum_complete++; 551 return; 552 } 553 554 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 555 (cqe->hds_ip_ext & CQE_L4_OK))) { 556 skb->ip_summed = CHECKSUM_UNNECESSARY; 557 if (cqe_is_tunneled(cqe)) { 558 skb->csum_level = 1; 559 skb->encapsulation = 1; 560 rq->stats.csum_unnecessary_inner++; 561 } 562 return; 563 } 564 csum_none: 565 skb->ip_summed = CHECKSUM_NONE; 566 rq->stats.csum_none++; 567 } 568 569 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 570 u32 cqe_bcnt, 571 struct mlx5e_rq *rq, 572 struct sk_buff *skb) 573 { 574 struct net_device *netdev = rq->netdev; 575 struct mlx5e_tstamp *tstamp = rq->tstamp; 576 int lro_num_seg; 577 578 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 579 if (lro_num_seg > 1) { 580 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 581 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 582 /* Subtract one since we already counted this as one 583 * "regular" packet in mlx5e_complete_rx_cqe() 584 */ 585 rq->stats.packets += lro_num_seg - 1; 586 rq->stats.lro_packets++; 587 rq->stats.lro_bytes += cqe_bcnt; 588 } 589 590 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 591 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 592 593 skb_record_rx_queue(skb, rq->ix); 594 595 if (likely(netdev->features & NETIF_F_RXHASH)) 596 mlx5e_skb_set_hash(cqe, skb); 597 598 if (cqe_has_vlan(cqe)) 599 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 600 be16_to_cpu(cqe->vlan_info)); 601 602 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 603 604 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 605 skb->protocol = eth_type_trans(skb, netdev); 606 } 607 608 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 609 struct mlx5_cqe64 *cqe, 610 u32 cqe_bcnt, 611 struct sk_buff *skb) 612 { 613 rq->stats.packets++; 614 rq->stats.bytes += cqe_bcnt; 615 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 616 } 617 618 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 619 { 620 struct mlx5_wq_cyc *wq = &sq->wq; 621 struct mlx5e_tx_wqe *wqe; 622 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 623 624 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 625 626 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 627 } 628 629 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 630 struct mlx5e_dma_info *di, 631 const struct xdp_buff *xdp) 632 { 633 struct mlx5e_xdpsq *sq = &rq->xdpsq; 634 struct mlx5_wq_cyc *wq = &sq->wq; 635 u16 pi = sq->pc & wq->sz_m1; 636 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 637 638 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 639 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 640 struct mlx5_wqe_data_seg *dseg; 641 642 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 643 dma_addr_t dma_addr = di->addr + data_offset; 644 unsigned int dma_len = xdp->data_end - xdp->data; 645 646 prefetchw(wqe); 647 648 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 649 MLX5E_SW2HW_MTU(rq->netdev->mtu) < dma_len)) { 650 rq->stats.xdp_drop++; 651 mlx5e_page_release(rq, di, true); 652 return false; 653 } 654 655 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 656 if (sq->db.doorbell) { 657 /* SQ is full, ring doorbell */ 658 mlx5e_xmit_xdp_doorbell(sq); 659 sq->db.doorbell = false; 660 } 661 rq->stats.xdp_tx_full++; 662 mlx5e_page_release(rq, di, true); 663 return false; 664 } 665 666 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 667 668 cseg->fm_ce_se = 0; 669 670 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 671 672 /* copy the inline part if required */ 673 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 674 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 675 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 676 dma_len -= MLX5E_XDP_MIN_INLINE; 677 dma_addr += MLX5E_XDP_MIN_INLINE; 678 dseg++; 679 } 680 681 /* write the dma part */ 682 dseg->addr = cpu_to_be64(dma_addr); 683 dseg->byte_count = cpu_to_be32(dma_len); 684 685 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 686 687 sq->db.di[pi] = *di; 688 sq->pc++; 689 690 sq->db.doorbell = true; 691 rq->stats.xdp_tx++; 692 return true; 693 } 694 695 /* returns true if packet was consumed by xdp */ 696 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 697 struct mlx5e_dma_info *di, 698 void *va, u16 *rx_headroom, u32 *len) 699 { 700 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 701 struct xdp_buff xdp; 702 u32 act; 703 704 if (!prog) 705 return false; 706 707 xdp.data = va + *rx_headroom; 708 xdp.data_end = xdp.data + *len; 709 xdp.data_hard_start = va; 710 711 act = bpf_prog_run_xdp(prog, &xdp); 712 switch (act) { 713 case XDP_PASS: 714 *rx_headroom = xdp.data - xdp.data_hard_start; 715 *len = xdp.data_end - xdp.data; 716 return false; 717 case XDP_TX: 718 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 719 trace_xdp_exception(rq->netdev, prog, act); 720 return true; 721 default: 722 bpf_warn_invalid_xdp_action(act); 723 case XDP_ABORTED: 724 trace_xdp_exception(rq->netdev, prog, act); 725 case XDP_DROP: 726 rq->stats.xdp_drop++; 727 mlx5e_page_release(rq, di, true); 728 return true; 729 } 730 } 731 732 static inline 733 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 734 u16 wqe_counter, u32 cqe_bcnt) 735 { 736 struct mlx5e_dma_info *di; 737 struct sk_buff *skb; 738 void *va, *data; 739 u16 rx_headroom = rq->rx_headroom; 740 bool consumed; 741 742 di = &rq->dma_info[wqe_counter]; 743 va = page_address(di->page); 744 data = va + rx_headroom; 745 746 dma_sync_single_range_for_cpu(rq->pdev, 747 di->addr, 748 rx_headroom, 749 rq->buff.wqe_sz, 750 DMA_FROM_DEVICE); 751 prefetch(data); 752 753 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 754 rq->stats.wqe_err++; 755 mlx5e_page_release(rq, di, true); 756 return NULL; 757 } 758 759 rcu_read_lock(); 760 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 761 rcu_read_unlock(); 762 if (consumed) 763 return NULL; /* page/packet was consumed by XDP */ 764 765 skb = build_skb(va, RQ_PAGE_SIZE(rq)); 766 if (unlikely(!skb)) { 767 rq->stats.buff_alloc_err++; 768 mlx5e_page_release(rq, di, true); 769 return NULL; 770 } 771 772 /* queue up for recycling ..*/ 773 page_ref_inc(di->page); 774 mlx5e_page_release(rq, di, true); 775 776 skb_reserve(skb, rx_headroom); 777 skb_put(skb, cqe_bcnt); 778 779 return skb; 780 } 781 782 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 783 { 784 struct mlx5e_rx_wqe *wqe; 785 __be16 wqe_counter_be; 786 struct sk_buff *skb; 787 u16 wqe_counter; 788 u32 cqe_bcnt; 789 790 wqe_counter_be = cqe->wqe_counter; 791 wqe_counter = be16_to_cpu(wqe_counter_be); 792 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 793 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 794 795 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt); 796 if (!skb) 797 goto wq_ll_pop; 798 799 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 800 napi_gro_receive(rq->cq.napi, skb); 801 802 wq_ll_pop: 803 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 804 &wqe->next.next_wqe_index); 805 } 806 807 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 808 { 809 struct net_device *netdev = rq->netdev; 810 struct mlx5e_priv *priv = netdev_priv(netdev); 811 struct mlx5_eswitch_rep *rep = priv->ppriv; 812 struct mlx5e_rx_wqe *wqe; 813 struct sk_buff *skb; 814 __be16 wqe_counter_be; 815 u16 wqe_counter; 816 u32 cqe_bcnt; 817 818 wqe_counter_be = cqe->wqe_counter; 819 wqe_counter = be16_to_cpu(wqe_counter_be); 820 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 821 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 822 823 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt); 824 if (!skb) 825 goto wq_ll_pop; 826 827 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 828 829 if (rep->vlan && skb_vlan_tag_present(skb)) 830 skb_vlan_pop(skb); 831 832 napi_gro_receive(rq->cq.napi, skb); 833 834 wq_ll_pop: 835 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 836 &wqe->next.next_wqe_index); 837 } 838 839 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 840 struct mlx5_cqe64 *cqe, 841 struct mlx5e_mpw_info *wi, 842 u32 cqe_bcnt, 843 struct sk_buff *skb) 844 { 845 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 846 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz; 847 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 848 u32 page_idx = wqe_offset >> PAGE_SHIFT; 849 u32 head_page_idx = page_idx; 850 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 851 u32 frag_offset = head_offset + headlen; 852 u16 byte_cnt = cqe_bcnt - headlen; 853 854 if (unlikely(frag_offset >= PAGE_SIZE)) { 855 page_idx++; 856 frag_offset -= PAGE_SIZE; 857 } 858 859 while (byte_cnt) { 860 u32 pg_consumed_bytes = 861 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 862 863 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 864 pg_consumed_bytes); 865 byte_cnt -= pg_consumed_bytes; 866 frag_offset = 0; 867 page_idx++; 868 } 869 /* copy header */ 870 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 871 head_offset, headlen); 872 /* skb linear part was allocated with headlen and aligned to long */ 873 skb->tail += headlen; 874 skb->len += headlen; 875 } 876 877 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 878 { 879 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 880 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 881 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 882 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 883 struct sk_buff *skb; 884 u16 cqe_bcnt; 885 886 wi->consumed_strides += cstrides; 887 888 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 889 rq->stats.wqe_err++; 890 goto mpwrq_cqe_out; 891 } 892 893 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 894 rq->stats.mpwqe_filler++; 895 goto mpwrq_cqe_out; 896 } 897 898 skb = napi_alloc_skb(rq->cq.napi, 899 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 900 sizeof(long))); 901 if (unlikely(!skb)) { 902 rq->stats.buff_alloc_err++; 903 goto mpwrq_cqe_out; 904 } 905 906 prefetch(skb->data); 907 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 908 909 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 910 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 911 napi_gro_receive(rq->cq.napi, skb); 912 913 mpwrq_cqe_out: 914 if (likely(wi->consumed_strides < rq->mpwqe_num_strides)) 915 return; 916 917 mlx5e_free_rx_mpwqe(rq, wi); 918 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 919 } 920 921 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 922 { 923 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 924 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq; 925 int work_done = 0; 926 927 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 928 return 0; 929 930 if (cq->decmprs_left) 931 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 932 933 for (; work_done < budget; work_done++) { 934 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); 935 936 if (!cqe) 937 break; 938 939 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 940 work_done += 941 mlx5e_decompress_cqes_start(rq, cq, 942 budget - work_done); 943 continue; 944 } 945 946 mlx5_cqwq_pop(&cq->wq); 947 948 rq->handle_rx_cqe(rq, cqe); 949 } 950 951 if (xdpsq->db.doorbell) { 952 mlx5e_xmit_xdp_doorbell(xdpsq); 953 xdpsq->db.doorbell = false; 954 } 955 956 mlx5_cqwq_update_db_record(&cq->wq); 957 958 /* ensure cq space is freed before enabling more cqes */ 959 wmb(); 960 961 return work_done; 962 } 963 964 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 965 { 966 struct mlx5e_xdpsq *sq; 967 struct mlx5e_rq *rq; 968 u16 sqcc; 969 int i; 970 971 sq = container_of(cq, struct mlx5e_xdpsq, cq); 972 973 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) 974 return false; 975 976 rq = container_of(sq, struct mlx5e_rq, xdpsq); 977 978 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 979 * otherwise a cq overrun may occur 980 */ 981 sqcc = sq->cc; 982 983 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) { 984 struct mlx5_cqe64 *cqe; 985 u16 wqe_counter; 986 bool last_wqe; 987 988 cqe = mlx5e_get_cqe(cq); 989 if (!cqe) 990 break; 991 992 mlx5_cqwq_pop(&cq->wq); 993 994 wqe_counter = be16_to_cpu(cqe->wqe_counter); 995 996 do { 997 struct mlx5e_dma_info *di; 998 u16 ci; 999 1000 last_wqe = (sqcc == wqe_counter); 1001 1002 ci = sqcc & sq->wq.sz_m1; 1003 di = &sq->db.di[ci]; 1004 1005 sqcc++; 1006 /* Recycle RX page */ 1007 mlx5e_page_release(rq, di, true); 1008 } while (!last_wqe); 1009 } 1010 1011 mlx5_cqwq_update_db_record(&cq->wq); 1012 1013 /* ensure cq space is freed before enabling more cqes */ 1014 wmb(); 1015 1016 sq->cc = sqcc; 1017 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1018 } 1019 1020 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1021 { 1022 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1023 struct mlx5e_dma_info *di; 1024 u16 ci; 1025 1026 while (sq->cc != sq->pc) { 1027 ci = sq->cc & sq->wq.sz_m1; 1028 di = &sq->db.di[ci]; 1029 sq->cc++; 1030 1031 mlx5e_page_release(rq, di, false); 1032 } 1033 } 1034