1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include <net/ip6_checksum.h> 40 #include "en.h" 41 #include "en_tc.h" 42 #include "eswitch.h" 43 #include "en_rep.h" 44 #include "ipoib/ipoib.h" 45 #include "en_accel/ipsec_rxtx.h" 46 #include "lib/clock.h" 47 48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 49 { 50 return config->rx_filter == HWTSTAMP_FILTER_ALL; 51 } 52 53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 54 void *data) 55 { 56 u32 ci = cqcc & cq->wq.fbc.sz_m1; 57 58 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 59 } 60 61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 62 struct mlx5e_cq *cq, u32 cqcc) 63 { 64 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 65 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 66 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 67 rq->stats.cqe_compress_blks++; 68 } 69 70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 71 { 72 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 73 cq->mini_arr_idx = 0; 74 } 75 76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 77 { 78 struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc; 79 u8 op_own = (cqcc >> fbc->log_sz) & 1; 80 u32 wq_sz = 1 << fbc->log_sz; 81 u32 ci = cqcc & fbc->sz_m1; 82 u32 ci_top = min_t(u32, wq_sz, ci + n); 83 84 for (; ci < ci_top; ci++, n--) { 85 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 86 87 cqe->op_own = op_own; 88 } 89 90 if (unlikely(ci == wq_sz)) { 91 op_own = !op_own; 92 for (ci = 0; ci < n; ci++) { 93 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 94 95 cqe->op_own = op_own; 96 } 97 } 98 } 99 100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 101 struct mlx5e_cq *cq, u32 cqcc) 102 { 103 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 104 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 105 cq->title.op_own &= 0xf0; 106 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz); 107 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 108 109 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 110 cq->decmprs_wqe_counter += 111 mpwrq_get_cqe_consumed_strides(&cq->title); 112 else 113 cq->decmprs_wqe_counter = 114 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 115 } 116 117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 118 struct mlx5e_cq *cq, u32 cqcc) 119 { 120 mlx5e_decompress_cqe(rq, cq, cqcc); 121 cq->title.rss_hash_type = 0; 122 cq->title.rss_hash_result = 0; 123 } 124 125 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 126 struct mlx5e_cq *cq, 127 int update_owner_only, 128 int budget_rem) 129 { 130 u32 cqcc = cq->wq.cc + update_owner_only; 131 u32 cqe_count; 132 u32 i; 133 134 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 135 136 for (i = update_owner_only; i < cqe_count; 137 i++, cq->mini_arr_idx++, cqcc++) { 138 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 139 mlx5e_read_mini_arr_slot(cq, cqcc); 140 141 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 142 rq->handle_rx_cqe(rq, &cq->title); 143 } 144 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 145 cq->wq.cc = cqcc; 146 cq->decmprs_left -= cqe_count; 147 rq->stats.cqe_compress_pkts += cqe_count; 148 149 return cqe_count; 150 } 151 152 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 153 struct mlx5e_cq *cq, 154 int budget_rem) 155 { 156 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 157 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 158 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 159 rq->handle_rx_cqe(rq, &cq->title); 160 cq->mini_arr_idx++; 161 162 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 163 } 164 165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 166 167 static inline bool mlx5e_page_is_reserved(struct page *page) 168 { 169 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 170 } 171 172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 173 struct mlx5e_dma_info *dma_info) 174 { 175 struct mlx5e_page_cache *cache = &rq->page_cache; 176 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 177 178 if (tail_next == cache->head) { 179 rq->stats.cache_full++; 180 return false; 181 } 182 183 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 184 rq->stats.cache_waive++; 185 return false; 186 } 187 188 cache->page_cache[cache->tail] = *dma_info; 189 cache->tail = tail_next; 190 return true; 191 } 192 193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 194 struct mlx5e_dma_info *dma_info) 195 { 196 struct mlx5e_page_cache *cache = &rq->page_cache; 197 198 if (unlikely(cache->head == cache->tail)) { 199 rq->stats.cache_empty++; 200 return false; 201 } 202 203 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 204 rq->stats.cache_busy++; 205 return false; 206 } 207 208 *dma_info = cache->page_cache[cache->head]; 209 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 210 rq->stats.cache_reuse++; 211 212 dma_sync_single_for_device(rq->pdev, dma_info->addr, 213 RQ_PAGE_SIZE(rq), 214 DMA_FROM_DEVICE); 215 return true; 216 } 217 218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 219 struct mlx5e_dma_info *dma_info) 220 { 221 if (mlx5e_rx_cache_get(rq, dma_info)) 222 return 0; 223 224 dma_info->page = dev_alloc_pages(rq->buff.page_order); 225 if (unlikely(!dma_info->page)) 226 return -ENOMEM; 227 228 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, 229 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 230 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 231 put_page(dma_info->page); 232 dma_info->page = NULL; 233 return -ENOMEM; 234 } 235 236 return 0; 237 } 238 239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 240 bool recycle) 241 { 242 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 243 return; 244 245 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 246 rq->buff.map_dir); 247 put_page(dma_info->page); 248 } 249 250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 251 struct mlx5e_wqe_frag_info *wi) 252 { 253 return rq->wqe.page_reuse && wi->di.page && 254 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 255 !mlx5e_page_is_reserved(wi->di.page); 256 } 257 258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 259 { 260 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 261 262 /* check if page exists, hence can be reused */ 263 if (!wi->di.page) { 264 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 265 return -ENOMEM; 266 wi->offset = 0; 267 } 268 269 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 270 return 0; 271 } 272 273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 274 struct mlx5e_wqe_frag_info *wi) 275 { 276 mlx5e_page_release(rq, &wi->di, true); 277 wi->di.page = NULL; 278 } 279 280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 281 struct mlx5e_wqe_frag_info *wi) 282 { 283 if (mlx5e_page_reuse(rq, wi)) { 284 rq->stats.page_reuse++; 285 return; 286 } 287 288 mlx5e_free_rx_wqe(rq, wi); 289 } 290 291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 292 { 293 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 294 295 if (wi->di.page) 296 mlx5e_free_rx_wqe(rq, wi); 297 } 298 299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 300 { 301 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 302 } 303 304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 305 struct sk_buff *skb, 306 struct mlx5e_mpw_info *wi, 307 u32 page_idx, u32 frag_offset, 308 u32 len) 309 { 310 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 311 312 dma_sync_single_for_cpu(rq->pdev, 313 wi->umr.dma_info[page_idx].addr + frag_offset, 314 len, DMA_FROM_DEVICE); 315 wi->skbs_frags[page_idx]++; 316 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 317 wi->umr.dma_info[page_idx].page, frag_offset, 318 len, truesize); 319 } 320 321 static inline void 322 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 323 struct sk_buff *skb, 324 struct mlx5e_mpw_info *wi, 325 u32 page_idx, u32 offset, 326 u32 headlen) 327 { 328 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 329 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 330 unsigned int len; 331 332 /* Aligning len to sizeof(long) optimizes memcpy performance */ 333 len = ALIGN(headlen_pg, sizeof(long)); 334 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 335 DMA_FROM_DEVICE); 336 skb_copy_to_linear_data_offset(skb, 0, 337 page_address(dma_info->page) + offset, 338 len); 339 if (unlikely(offset + headlen > PAGE_SIZE)) { 340 dma_info++; 341 headlen_pg = len; 342 len = ALIGN(headlen - headlen_pg, sizeof(long)); 343 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 344 DMA_FROM_DEVICE); 345 skb_copy_to_linear_data_offset(skb, headlen_pg, 346 page_address(dma_info->page), 347 len); 348 } 349 } 350 351 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 352 { 353 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 354 struct mlx5e_icosq *sq = &rq->channel->icosq; 355 struct mlx5_wq_cyc *wq = &sq->wq; 356 struct mlx5e_umr_wqe *wqe; 357 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 358 u16 pi; 359 360 /* fill sq edge with nops to avoid wqe wrap around */ 361 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 362 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 363 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 364 } 365 366 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 367 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 368 wqe->ctrl.opmod_idx_opcode = 369 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 370 MLX5_OPCODE_UMR); 371 372 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 373 sq->pc += num_wqebbs; 374 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 375 } 376 377 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 378 u16 ix) 379 { 380 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 381 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 382 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 383 int err; 384 int i; 385 386 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 387 err = mlx5e_page_alloc_mapped(rq, dma_info); 388 if (unlikely(err)) 389 goto err_unmap; 390 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 391 page_ref_add(dma_info->page, pg_strides); 392 } 393 394 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 395 wi->consumed_strides = 0; 396 397 return 0; 398 399 err_unmap: 400 while (--i >= 0) { 401 dma_info--; 402 page_ref_sub(dma_info->page, pg_strides); 403 mlx5e_page_release(rq, dma_info, true); 404 } 405 406 return err; 407 } 408 409 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 410 { 411 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 412 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 413 int i; 414 415 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 416 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 417 mlx5e_page_release(rq, dma_info, true); 418 } 419 } 420 421 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 422 { 423 struct mlx5_wq_ll *wq = &rq->wq; 424 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 425 426 rq->mpwqe.umr_in_progress = false; 427 428 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 429 430 /* ensure wqes are visible to device before updating doorbell record */ 431 dma_wmb(); 432 433 mlx5_wq_ll_update_db_record(wq); 434 } 435 436 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 437 { 438 int err; 439 440 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 441 if (unlikely(err)) { 442 rq->stats.buff_alloc_err++; 443 return err; 444 } 445 rq->mpwqe.umr_in_progress = true; 446 mlx5e_post_umr_wqe(rq, ix); 447 return 0; 448 } 449 450 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 451 { 452 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 453 454 mlx5e_free_rx_mpwqe(rq, wi); 455 } 456 457 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 458 { 459 struct mlx5_wq_ll *wq = &rq->wq; 460 int err; 461 462 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 463 return false; 464 465 if (mlx5_wq_ll_is_full(wq)) 466 return false; 467 468 do { 469 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 470 471 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 472 if (unlikely(err)) { 473 rq->stats.buff_alloc_err++; 474 break; 475 } 476 477 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 478 } while (!mlx5_wq_ll_is_full(wq)); 479 480 /* ensure wqes are visible to device before updating doorbell record */ 481 dma_wmb(); 482 483 mlx5_wq_ll_update_db_record(wq); 484 485 return !!err; 486 } 487 488 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 489 struct mlx5e_icosq *sq, 490 struct mlx5e_rq *rq, 491 struct mlx5_cqe64 *cqe) 492 { 493 struct mlx5_wq_cyc *wq = &sq->wq; 494 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 495 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 496 497 mlx5_cqwq_pop(&cq->wq); 498 499 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 500 netdev_WARN_ONCE(cq->channel->netdev, 501 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own); 502 return; 503 } 504 505 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 506 mlx5e_post_rx_mpwqe(rq); 507 return; 508 } 509 510 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 511 netdev_WARN_ONCE(cq->channel->netdev, 512 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode); 513 } 514 515 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 516 { 517 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 518 struct mlx5_cqe64 *cqe; 519 520 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 521 return; 522 523 cqe = mlx5_cqwq_get_cqe(&cq->wq); 524 if (likely(!cqe)) 525 return; 526 527 /* by design, there's only a single cqe */ 528 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 529 530 mlx5_cqwq_update_db_record(&cq->wq); 531 } 532 533 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 534 { 535 struct mlx5_wq_ll *wq = &rq->wq; 536 537 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 538 return false; 539 540 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 541 542 if (mlx5_wq_ll_is_full(wq)) 543 return false; 544 545 if (!rq->mpwqe.umr_in_progress) 546 mlx5e_alloc_rx_mpwqe(rq, wq->head); 547 548 return true; 549 } 550 551 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) 552 { 553 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 554 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 555 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 556 557 tcp->check = 0; 558 tcp->psh = get_cqe_lro_tcppsh(cqe); 559 560 if (tcp_ack) { 561 tcp->ack = 1; 562 tcp->ack_seq = cqe->lro_ack_seq_num; 563 tcp->window = cqe->lro_tcp_win; 564 } 565 } 566 567 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 568 u32 cqe_bcnt) 569 { 570 struct ethhdr *eth = (struct ethhdr *)(skb->data); 571 struct tcphdr *tcp; 572 int network_depth = 0; 573 __wsum check; 574 __be16 proto; 575 u16 tot_len; 576 void *ip_p; 577 578 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 579 580 tot_len = cqe_bcnt - network_depth; 581 ip_p = skb->data + network_depth; 582 583 if (proto == htons(ETH_P_IP)) { 584 struct iphdr *ipv4 = ip_p; 585 586 tcp = ip_p + sizeof(struct iphdr); 587 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 588 589 ipv4->ttl = cqe->lro_min_ttl; 590 ipv4->tot_len = cpu_to_be16(tot_len); 591 ipv4->check = 0; 592 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 593 ipv4->ihl); 594 595 mlx5e_lro_update_tcp_hdr(cqe, tcp); 596 check = csum_partial(tcp, tcp->doff * 4, 597 csum_unfold((__force __sum16)cqe->check_sum)); 598 /* Almost done, don't forget the pseudo header */ 599 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, 600 tot_len - sizeof(struct iphdr), 601 IPPROTO_TCP, check); 602 } else { 603 u16 payload_len = tot_len - sizeof(struct ipv6hdr); 604 struct ipv6hdr *ipv6 = ip_p; 605 606 tcp = ip_p + sizeof(struct ipv6hdr); 607 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 608 609 ipv6->hop_limit = cqe->lro_min_ttl; 610 ipv6->payload_len = cpu_to_be16(payload_len); 611 612 mlx5e_lro_update_tcp_hdr(cqe, tcp); 613 check = csum_partial(tcp, tcp->doff * 4, 614 csum_unfold((__force __sum16)cqe->check_sum)); 615 /* Almost done, don't forget the pseudo header */ 616 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, 617 IPPROTO_TCP, check); 618 } 619 } 620 621 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 622 struct sk_buff *skb) 623 { 624 u8 cht = cqe->rss_hash_type; 625 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 626 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 627 PKT_HASH_TYPE_NONE; 628 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 629 } 630 631 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth) 632 { 633 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 634 635 ethertype = __vlan_get_protocol(skb, ethertype, network_depth); 636 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 637 } 638 639 static inline void mlx5e_handle_csum(struct net_device *netdev, 640 struct mlx5_cqe64 *cqe, 641 struct mlx5e_rq *rq, 642 struct sk_buff *skb, 643 bool lro) 644 { 645 int network_depth = 0; 646 647 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 648 goto csum_none; 649 650 if (lro) { 651 skb->ip_summed = CHECKSUM_UNNECESSARY; 652 rq->stats.csum_unnecessary++; 653 return; 654 } 655 656 if (likely(is_last_ethertype_ip(skb, &network_depth))) { 657 skb->ip_summed = CHECKSUM_COMPLETE; 658 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 659 if (network_depth > ETH_HLEN) 660 /* CQE csum is calculated from the IP header and does 661 * not cover VLAN headers (if present). This will add 662 * the checksum manually. 663 */ 664 skb->csum = csum_partial(skb->data + ETH_HLEN, 665 network_depth - ETH_HLEN, 666 skb->csum); 667 rq->stats.csum_complete++; 668 return; 669 } 670 671 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 672 (cqe->hds_ip_ext & CQE_L4_OK))) { 673 skb->ip_summed = CHECKSUM_UNNECESSARY; 674 if (cqe_is_tunneled(cqe)) { 675 skb->csum_level = 1; 676 skb->encapsulation = 1; 677 rq->stats.csum_unnecessary_inner++; 678 return; 679 } 680 rq->stats.csum_unnecessary++; 681 return; 682 } 683 csum_none: 684 skb->ip_summed = CHECKSUM_NONE; 685 rq->stats.csum_none++; 686 } 687 688 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 689 u32 cqe_bcnt, 690 struct mlx5e_rq *rq, 691 struct sk_buff *skb) 692 { 693 struct net_device *netdev = rq->netdev; 694 int lro_num_seg; 695 696 skb->mac_len = ETH_HLEN; 697 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 698 if (lro_num_seg > 1) { 699 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 700 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 701 /* Subtract one since we already counted this as one 702 * "regular" packet in mlx5e_complete_rx_cqe() 703 */ 704 rq->stats.packets += lro_num_seg - 1; 705 rq->stats.lro_packets++; 706 rq->stats.lro_bytes += cqe_bcnt; 707 } 708 709 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 710 skb_hwtstamps(skb)->hwtstamp = 711 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 712 713 skb_record_rx_queue(skb, rq->ix); 714 715 if (likely(netdev->features & NETIF_F_RXHASH)) 716 mlx5e_skb_set_hash(cqe, skb); 717 718 if (cqe_has_vlan(cqe)) { 719 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 720 be16_to_cpu(cqe->vlan_info)); 721 rq->stats.removed_vlan_packets++; 722 } 723 724 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 725 726 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 727 skb->protocol = eth_type_trans(skb, netdev); 728 } 729 730 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 731 struct mlx5_cqe64 *cqe, 732 u32 cqe_bcnt, 733 struct sk_buff *skb) 734 { 735 rq->stats.packets++; 736 rq->stats.bytes += cqe_bcnt; 737 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 738 } 739 740 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 741 { 742 struct mlx5_wq_cyc *wq = &sq->wq; 743 struct mlx5e_tx_wqe *wqe; 744 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 745 746 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 747 748 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 749 } 750 751 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 752 struct mlx5e_dma_info *di, 753 const struct xdp_buff *xdp) 754 { 755 struct mlx5e_xdpsq *sq = &rq->xdpsq; 756 struct mlx5_wq_cyc *wq = &sq->wq; 757 u16 pi = sq->pc & wq->sz_m1; 758 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 759 760 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 761 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 762 struct mlx5_wqe_data_seg *dseg; 763 764 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 765 dma_addr_t dma_addr = di->addr + data_offset; 766 unsigned int dma_len = xdp->data_end - xdp->data; 767 768 prefetchw(wqe); 769 770 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 771 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 772 rq->stats.xdp_drop++; 773 return false; 774 } 775 776 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 777 if (sq->db.doorbell) { 778 /* SQ is full, ring doorbell */ 779 mlx5e_xmit_xdp_doorbell(sq); 780 sq->db.doorbell = false; 781 } 782 rq->stats.xdp_tx_full++; 783 return false; 784 } 785 786 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 787 788 cseg->fm_ce_se = 0; 789 790 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 791 792 /* copy the inline part if required */ 793 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 794 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 795 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 796 dma_len -= MLX5E_XDP_MIN_INLINE; 797 dma_addr += MLX5E_XDP_MIN_INLINE; 798 dseg++; 799 } 800 801 /* write the dma part */ 802 dseg->addr = cpu_to_be64(dma_addr); 803 dseg->byte_count = cpu_to_be32(dma_len); 804 805 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 806 807 /* move page to reference to sq responsibility, 808 * and mark so it's not put back in page-cache. 809 */ 810 rq->wqe.xdp_xmit = true; 811 sq->db.di[pi] = *di; 812 sq->pc++; 813 814 sq->db.doorbell = true; 815 816 rq->stats.xdp_tx++; 817 return true; 818 } 819 820 /* returns true if packet was consumed by xdp */ 821 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 822 struct mlx5e_dma_info *di, 823 void *va, u16 *rx_headroom, u32 *len) 824 { 825 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 826 struct xdp_buff xdp; 827 u32 act; 828 829 if (!prog) 830 return false; 831 832 xdp.data = va + *rx_headroom; 833 xdp_set_data_meta_invalid(&xdp); 834 xdp.data_end = xdp.data + *len; 835 xdp.data_hard_start = va; 836 xdp.rxq = &rq->xdp_rxq; 837 838 act = bpf_prog_run_xdp(prog, &xdp); 839 switch (act) { 840 case XDP_PASS: 841 *rx_headroom = xdp.data - xdp.data_hard_start; 842 *len = xdp.data_end - xdp.data; 843 return false; 844 case XDP_TX: 845 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 846 trace_xdp_exception(rq->netdev, prog, act); 847 return true; 848 default: 849 bpf_warn_invalid_xdp_action(act); 850 case XDP_ABORTED: 851 trace_xdp_exception(rq->netdev, prog, act); 852 case XDP_DROP: 853 rq->stats.xdp_drop++; 854 return true; 855 } 856 } 857 858 static inline 859 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 860 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 861 { 862 struct mlx5e_dma_info *di = &wi->di; 863 u16 rx_headroom = rq->buff.headroom; 864 struct sk_buff *skb; 865 void *va, *data; 866 bool consumed; 867 u32 frag_size; 868 869 va = page_address(di->page) + wi->offset; 870 data = va + rx_headroom; 871 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 872 873 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, 874 frag_size, DMA_FROM_DEVICE); 875 prefetch(data); 876 wi->offset += frag_size; 877 878 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 879 rq->stats.wqe_err++; 880 return NULL; 881 } 882 883 rcu_read_lock(); 884 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 885 rcu_read_unlock(); 886 if (consumed) 887 return NULL; /* page/packet was consumed by XDP */ 888 889 skb = build_skb(va, frag_size); 890 if (unlikely(!skb)) { 891 rq->stats.buff_alloc_err++; 892 return NULL; 893 } 894 895 /* queue up for recycling/reuse */ 896 page_ref_inc(di->page); 897 898 skb_reserve(skb, rx_headroom); 899 skb_put(skb, cqe_bcnt); 900 901 return skb; 902 } 903 904 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 905 { 906 struct mlx5e_wqe_frag_info *wi; 907 struct mlx5e_rx_wqe *wqe; 908 __be16 wqe_counter_be; 909 struct sk_buff *skb; 910 u16 wqe_counter; 911 u32 cqe_bcnt; 912 913 wqe_counter_be = cqe->wqe_counter; 914 wqe_counter = be16_to_cpu(wqe_counter_be); 915 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 916 wi = &rq->wqe.frag_info[wqe_counter]; 917 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 918 919 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 920 if (!skb) { 921 /* probably for XDP */ 922 if (rq->wqe.xdp_xmit) { 923 wi->di.page = NULL; 924 rq->wqe.xdp_xmit = false; 925 /* do not return page to cache, it will be returned on XDP_TX completion */ 926 goto wq_ll_pop; 927 } 928 /* probably an XDP_DROP, save the page-reuse checks */ 929 mlx5e_free_rx_wqe(rq, wi); 930 goto wq_ll_pop; 931 } 932 933 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 934 napi_gro_receive(rq->cq.napi, skb); 935 936 mlx5e_free_rx_wqe_reuse(rq, wi); 937 wq_ll_pop: 938 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 939 &wqe->next.next_wqe_index); 940 } 941 942 #ifdef CONFIG_MLX5_ESWITCH 943 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 944 { 945 struct net_device *netdev = rq->netdev; 946 struct mlx5e_priv *priv = netdev_priv(netdev); 947 struct mlx5e_rep_priv *rpriv = priv->ppriv; 948 struct mlx5_eswitch_rep *rep = rpriv->rep; 949 struct mlx5e_wqe_frag_info *wi; 950 struct mlx5e_rx_wqe *wqe; 951 struct sk_buff *skb; 952 __be16 wqe_counter_be; 953 u16 wqe_counter; 954 u32 cqe_bcnt; 955 956 wqe_counter_be = cqe->wqe_counter; 957 wqe_counter = be16_to_cpu(wqe_counter_be); 958 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 959 wi = &rq->wqe.frag_info[wqe_counter]; 960 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 961 962 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 963 if (!skb) { 964 if (rq->wqe.xdp_xmit) { 965 wi->di.page = NULL; 966 rq->wqe.xdp_xmit = false; 967 /* do not return page to cache, it will be returned on XDP_TX completion */ 968 goto wq_ll_pop; 969 } 970 /* probably an XDP_DROP, save the page-reuse checks */ 971 mlx5e_free_rx_wqe(rq, wi); 972 goto wq_ll_pop; 973 } 974 975 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 976 977 if (rep->vlan && skb_vlan_tag_present(skb)) 978 skb_vlan_pop(skb); 979 980 napi_gro_receive(rq->cq.napi, skb); 981 982 mlx5e_free_rx_wqe_reuse(rq, wi); 983 wq_ll_pop: 984 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 985 &wqe->next.next_wqe_index); 986 } 987 #endif 988 989 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 990 struct mlx5_cqe64 *cqe, 991 struct mlx5e_mpw_info *wi, 992 u32 cqe_bcnt, 993 struct sk_buff *skb) 994 { 995 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 996 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 997 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 998 u32 page_idx = wqe_offset >> PAGE_SHIFT; 999 u32 head_page_idx = page_idx; 1000 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 1001 u32 frag_offset = head_offset + headlen; 1002 u16 byte_cnt = cqe_bcnt - headlen; 1003 1004 if (unlikely(frag_offset >= PAGE_SIZE)) { 1005 page_idx++; 1006 frag_offset -= PAGE_SIZE; 1007 } 1008 1009 while (byte_cnt) { 1010 u32 pg_consumed_bytes = 1011 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 1012 1013 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 1014 pg_consumed_bytes); 1015 byte_cnt -= pg_consumed_bytes; 1016 frag_offset = 0; 1017 page_idx++; 1018 } 1019 /* copy header */ 1020 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 1021 head_offset, headlen); 1022 /* skb linear part was allocated with headlen and aligned to long */ 1023 skb->tail += headlen; 1024 skb->len += headlen; 1025 } 1026 1027 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1028 { 1029 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1030 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1031 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1032 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1033 struct sk_buff *skb; 1034 u16 cqe_bcnt; 1035 1036 wi->consumed_strides += cstrides; 1037 1038 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1039 rq->stats.wqe_err++; 1040 goto mpwrq_cqe_out; 1041 } 1042 1043 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1044 rq->stats.mpwqe_filler++; 1045 goto mpwrq_cqe_out; 1046 } 1047 1048 skb = napi_alloc_skb(rq->cq.napi, 1049 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1050 sizeof(long))); 1051 if (unlikely(!skb)) { 1052 rq->stats.buff_alloc_err++; 1053 goto mpwrq_cqe_out; 1054 } 1055 1056 prefetchw(skb->data); 1057 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1058 1059 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1060 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1061 napi_gro_receive(rq->cq.napi, skb); 1062 1063 mpwrq_cqe_out: 1064 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1065 return; 1066 1067 mlx5e_free_rx_mpwqe(rq, wi); 1068 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1069 } 1070 1071 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1072 { 1073 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1074 struct mlx5e_xdpsq *xdpsq; 1075 struct mlx5_cqe64 *cqe; 1076 int work_done = 0; 1077 1078 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1079 return 0; 1080 1081 if (cq->decmprs_left) 1082 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1083 1084 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1085 if (!cqe) 1086 return 0; 1087 1088 xdpsq = &rq->xdpsq; 1089 1090 do { 1091 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1092 work_done += 1093 mlx5e_decompress_cqes_start(rq, cq, 1094 budget - work_done); 1095 continue; 1096 } 1097 1098 mlx5_cqwq_pop(&cq->wq); 1099 1100 rq->handle_rx_cqe(rq, cqe); 1101 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1102 1103 if (xdpsq->db.doorbell) { 1104 mlx5e_xmit_xdp_doorbell(xdpsq); 1105 xdpsq->db.doorbell = false; 1106 } 1107 1108 mlx5_cqwq_update_db_record(&cq->wq); 1109 1110 /* ensure cq space is freed before enabling more cqes */ 1111 wmb(); 1112 1113 return work_done; 1114 } 1115 1116 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1117 { 1118 struct mlx5e_xdpsq *sq; 1119 struct mlx5_cqe64 *cqe; 1120 struct mlx5e_rq *rq; 1121 u16 sqcc; 1122 int i; 1123 1124 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1125 1126 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1127 return false; 1128 1129 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1130 if (!cqe) 1131 return false; 1132 1133 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1134 1135 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1136 * otherwise a cq overrun may occur 1137 */ 1138 sqcc = sq->cc; 1139 1140 i = 0; 1141 do { 1142 u16 wqe_counter; 1143 bool last_wqe; 1144 1145 mlx5_cqwq_pop(&cq->wq); 1146 1147 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1148 1149 do { 1150 struct mlx5e_dma_info *di; 1151 u16 ci; 1152 1153 last_wqe = (sqcc == wqe_counter); 1154 1155 ci = sqcc & sq->wq.sz_m1; 1156 di = &sq->db.di[ci]; 1157 1158 sqcc++; 1159 /* Recycle RX page */ 1160 mlx5e_page_release(rq, di, true); 1161 } while (!last_wqe); 1162 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1163 1164 mlx5_cqwq_update_db_record(&cq->wq); 1165 1166 /* ensure cq space is freed before enabling more cqes */ 1167 wmb(); 1168 1169 sq->cc = sqcc; 1170 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1171 } 1172 1173 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1174 { 1175 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1176 struct mlx5e_dma_info *di; 1177 u16 ci; 1178 1179 while (sq->cc != sq->pc) { 1180 ci = sq->cc & sq->wq.sz_m1; 1181 di = &sq->db.di[ci]; 1182 sq->cc++; 1183 1184 mlx5e_page_release(rq, di, false); 1185 } 1186 } 1187 1188 #ifdef CONFIG_MLX5_CORE_IPOIB 1189 1190 #define MLX5_IB_GRH_DGID_OFFSET 24 1191 #define MLX5_GID_SIZE 16 1192 1193 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1194 struct mlx5_cqe64 *cqe, 1195 u32 cqe_bcnt, 1196 struct sk_buff *skb) 1197 { 1198 struct hwtstamp_config *tstamp; 1199 struct net_device *netdev; 1200 struct mlx5e_priv *priv; 1201 char *pseudo_header; 1202 u32 qpn; 1203 u8 *dgid; 1204 u8 g; 1205 1206 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1207 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1208 1209 /* No mapping present, cannot process SKB. This might happen if a child 1210 * interface is going down while having unprocessed CQEs on parent RQ 1211 */ 1212 if (unlikely(!netdev)) { 1213 /* TODO: add drop counters support */ 1214 skb->dev = NULL; 1215 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1216 return; 1217 } 1218 1219 priv = mlx5i_epriv(netdev); 1220 tstamp = &priv->tstamp; 1221 1222 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1223 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1224 if ((!g) || dgid[0] != 0xff) 1225 skb->pkt_type = PACKET_HOST; 1226 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1227 skb->pkt_type = PACKET_BROADCAST; 1228 else 1229 skb->pkt_type = PACKET_MULTICAST; 1230 1231 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1232 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1233 */ 1234 1235 skb_pull(skb, MLX5_IB_GRH_BYTES); 1236 1237 skb->protocol = *((__be16 *)(skb->data)); 1238 1239 skb->ip_summed = CHECKSUM_COMPLETE; 1240 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1241 1242 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1243 skb_hwtstamps(skb)->hwtstamp = 1244 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1245 1246 skb_record_rx_queue(skb, rq->ix); 1247 1248 if (likely(netdev->features & NETIF_F_RXHASH)) 1249 mlx5e_skb_set_hash(cqe, skb); 1250 1251 /* 20 bytes of ipoib header and 4 for encap existing */ 1252 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1253 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1254 skb_reset_mac_header(skb); 1255 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1256 1257 skb->dev = netdev; 1258 1259 rq->stats.csum_complete++; 1260 rq->stats.packets++; 1261 rq->stats.bytes += cqe_bcnt; 1262 } 1263 1264 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1265 { 1266 struct mlx5e_wqe_frag_info *wi; 1267 struct mlx5e_rx_wqe *wqe; 1268 __be16 wqe_counter_be; 1269 struct sk_buff *skb; 1270 u16 wqe_counter; 1271 u32 cqe_bcnt; 1272 1273 wqe_counter_be = cqe->wqe_counter; 1274 wqe_counter = be16_to_cpu(wqe_counter_be); 1275 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1276 wi = &rq->wqe.frag_info[wqe_counter]; 1277 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1278 1279 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1280 if (!skb) 1281 goto wq_free_wqe; 1282 1283 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1284 if (unlikely(!skb->dev)) { 1285 dev_kfree_skb_any(skb); 1286 goto wq_free_wqe; 1287 } 1288 napi_gro_receive(rq->cq.napi, skb); 1289 1290 wq_free_wqe: 1291 mlx5e_free_rx_wqe_reuse(rq, wi); 1292 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1293 &wqe->next.next_wqe_index); 1294 } 1295 1296 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1297 1298 #ifdef CONFIG_MLX5_EN_IPSEC 1299 1300 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1301 { 1302 struct mlx5e_wqe_frag_info *wi; 1303 struct mlx5e_rx_wqe *wqe; 1304 __be16 wqe_counter_be; 1305 struct sk_buff *skb; 1306 u16 wqe_counter; 1307 u32 cqe_bcnt; 1308 1309 wqe_counter_be = cqe->wqe_counter; 1310 wqe_counter = be16_to_cpu(wqe_counter_be); 1311 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1312 wi = &rq->wqe.frag_info[wqe_counter]; 1313 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1314 1315 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1316 if (unlikely(!skb)) { 1317 /* a DROP, save the page-reuse checks */ 1318 mlx5e_free_rx_wqe(rq, wi); 1319 goto wq_ll_pop; 1320 } 1321 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1322 if (unlikely(!skb)) { 1323 mlx5e_free_rx_wqe(rq, wi); 1324 goto wq_ll_pop; 1325 } 1326 1327 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1328 napi_gro_receive(rq->cq.napi, skb); 1329 1330 mlx5e_free_rx_wqe_reuse(rq, wi); 1331 wq_ll_pop: 1332 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1333 &wqe->next.next_wqe_index); 1334 } 1335 1336 #endif /* CONFIG_MLX5_EN_IPSEC */ 1337